74LVC1G58-Q100 Low-power configurable multiple function gate Rev. 1 — 10 June 2014 Product data sheet 1. General description The 74LVC1G58-Q100 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XOR, inverter and buffer. All inputs can be connected to VCC or GND. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. All inputs (A, B and C) are Schmitt trigger inputs. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V). ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options 74LVC1G58-Q100 NXP Semiconductors Low-power configurable multiple function gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LVC1G58GW-Q100 40 C to +125 C 74LVC1G58GV-Q100 40 C to +125 C Description Version SC-88 plastic surface-mounted package; 6 leads SOT363 TSOP6 plastic surface-mounted package (TSOP6); 6 leads SOT457 4. Marking Table 2. Marking Type number Marking code[1] 74LVC1G58GW-Q100 YK 74LVC1G58GV-Q100 V58 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram A 3 4 B C Fig 1. 1 Y 6 001aab687 Logic symbol 6. Pinning information 6.1 Pinning /9&*4 % & *1' 9&& $ < DDD Fig 2. Pin configuration SOT363 and SOT457 74LVC1G58_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 2 of 17 74LVC1G58-Q100 NXP Semiconductors Low-power configurable multiple function gate 6.2 Pin description Table 3. Pin description Symbol Pin Description B 1 data input GND 2 ground (0 V) A 3 data input Y 4 data output VCC 5 supply voltage C 6 data input 7. Functional description Table 4. Function table[1] Inputs Output C B A Y L L L L L L H H L H L L L H H H H L L H H L H H H H L L H H H L [1] H = HIGH voltage level; L = LOW voltage level 7.1 Logic configurations Table 5. Function selection table Logic function Figure 2-input NAND see Figure 3 2-input NAND with both inputs inverted see Figure 6 2-input AND with inverted input see Figure 4 and 5 2-input NOR with inverted input see Figure 4 and 5 2-input OR see Figure 6 2-input OR with both inputs inverted see Figure 3 2-input XOR see Figure 7 Buffer see Figure 8 Inverter see Figure 9 74LVC1G58_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 3 of 17 74LVC1G58-Q100 NXP Semiconductors Low-power configurable multiple function gate VCC B C B C Y B Y 1 6 2 5 3 4 VCC B C C Y Y B C B Y 1 6 2 5 3 4 Y 001aab689 001aab688 Fig 3. C 2-input NAND gate or 2-input OR with both inputs inverted Fig 4. 2-input AND gate with inverted B input or 2-input NOR gate with inverted C input VCC VCC A C A C Y A Y 1 6 2 5 3 4 A C C Y Y A C Y A 1 6 2 5 3 4 001aab690 Fig 5. C Y 001aab691 2-input AND gate with inverted C input or 2-input NOR gate with inverted A input Fig 6. 2-input OR gate or 2-input NAND gate with both inputs inverted VCC VCC B B C Y 1 6 2 5 3 4 C A Y Y A 6 5 3 4 Y 001aab693 001aab692 Fig 7. 1 2 2-input XOR gate Fig 8. Buffer VCC B B Y 1 6 2 5 3 4 Y 001aab694 Fig 9. Inverter 74LVC1G58_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 4 of 17 74LVC1G58-Q100 NXP Semiconductors Low-power configurable multiple function gate 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions VI < 0 V [1] Min Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V - 50 mA Active mode [1][2] 0.5 +6.5 V Power-down mode [1][2] 0.5 +6.5 V - 50 mA VO > VCC or VO < 0 V IO output current ICC supply current - 100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 250 mW [1] VO = 0 V to VCC Tamb = 40 C to +125 C [3] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For SC-88 and SC-74 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. 9. Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter VCC Min Typ Max Unit supply voltage 1.65 - 5.5 V VI input voltage 0 - 5.5 V VO output voltage Active mode 0 - VCC V Power-down mode; VCC = 0 V 0 - 5.5 V 40 - +125 C Tamb Conditions ambient temperature 74LVC1G58_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 5 of 17 74LVC1G58-Q100 NXP Semiconductors Low-power configurable multiple function gate 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Min Typ[1] Max Unit IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.45 V IO = 8 mA; VCC = 2.3 V - - 0.3 V Conditions Tamb = 40 C to +85 C VOL VOH LOW-level output voltage VI = VT+ or VT IO = 12 mA; VCC = 2.7 V - - 0.4 V IO = 24 mA; VCC = 3.0 V - - 0.55 V IO = 32 mA; VCC = 4.5 V - - 0.55 V HIGH-level output voltage VI = VT+ or VT IO = 100 A; VCC = 1.65 V to 5.5 V VCC 0.1 - - V IO = 4 mA; VCC = 1.65 V 1.2 - - V IO = 8 mA; VCC = 2.3 V 1.9 - - V IO = 12 mA; VCC = 2.7 V 2.2 - - V IO = 24 mA; VCC = 3.0 V 2.3 - - V IO = 32 mA; VCC = 4.5 V 3.8 - - V - 0.1 5 A II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - 0.1 10 A ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - 0.1 10 A ICC additional supply current VI = VCC 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - 5 500 A CI input capacitance - 2.5 - pF - - 0.1 V Tamb = 40 C to +125 C VOL LOW-level output voltage VI = VT+ or VT IO = 100 A; VCC = 1.65 V to 5.5 V VOH II IO = 4 mA; VCC = 1.65 V - - 0.7 V IO = 8 mA; VCC = 2.3 V - - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.8 V IO = 32 mA; VCC = 4.5 V - - 0.8 V HIGH-level output voltage VI = VT+ or VT input leakage current 74LVC1G58_Q100 Product data sheet IO = 100 A; VCC = 1.65 V to 5.5 V VCC 0.1 - - V IO = 4 mA; VCC = 1.65 V 0.95 - V - IO = 8 mA; VCC = 2.3 V 1.7 - - V IO = 12 mA; VCC = 2.7 V 1.9 - - V IO = 24 mA; VCC = 3.0 V 2.0 - - V IO = 32 mA; VCC = 4.5 V 3.4 - - V - - 100 A VI = 5.5 V or GND; VCC = 0 V to 5.5 V All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 6 of 17 74LVC1G58-Q100 NXP Semiconductors Low-power configurable multiple function gate Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Min Typ[1] Max Unit power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - 200 A ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - - 200 A ICC additional supply current VI = VCC 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - - 5000 A Symbol Parameter IOFF [1] Conditions Typical values are measured at maximum VCC and Tamb = 25 C. 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol Parameter tpd propagation delay 40 C to +85 C Conditions Min Max Min Max VCC = 1.65 V to 1.95 V 1.0 6.0 14.4 1.0 18.0 ns VCC = 2.3 V to 2.7 V 0.5 3.5 8.3 0.5 10.4 ns VCC = 2.7 V 0.5 4.2 8.5 0.5 10.6 ns VCC = 3.0 V to 3.6 V 0.5 3.8 6.3 0.5 7.9 ns 0.5 3.0 5.1 0.5 6.4 ns - 20 - - - pF A, B, C to Y; see Figure 10 [2] VCC = 4.5 V to 5.5 V CPD power dissipation capacitance VCC = 3.3 V; VI = GND to VCC [1] Typical values are measured at nominal VCC and at Tamb = 25 C. [2] tpd is the same as tPLH and tPHL [3] 40 C to +125 C Unit Typ[1] [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 74LVC1G58_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 7 of 17 74LVC1G58-Q100 NXP Semiconductors Low-power configurable multiple function gate 12. Waveforms VI A, B, C input VM VM GND t PHL t PLH VOH VM Y output VM VOL t PLH t PHL VOH Y output VM VOL VM 001aab593 Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load. Fig 10. Input A, B, C to output Y propagation delay times Table 10. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5 VCC 0.5 VCC 2.3 V to 2.7 V 0.5 VCC 0.5 VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5 VCC 0.5 VCC 74LVC1G58_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 8 of 17 74LVC1G58-Q100 NXP Semiconductors Low-power configurable multiple function gate VEXT VCC VI RL VO G DUT RT CL RL mna616 Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 11. Test circuit for measuring switching times Table 11. Test data Supply voltage Input Load VEXT VCC VI tr = tf CL RL tPLH, tPHL 1.65 V to 1.95 V VCC 2.0 ns 30 pF 1 k open 2.3 V to 2.7 V VCC 2.0 ns 30 pF 500 open 2.7 V 2.7 V 2.5 ns 50 pF 500 open 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 open 4.5 V to 5.5 V VCC 2.5 ns 50 pF 500 open 74LVC1G58_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 9 of 17 74LVC1G58-Q100 NXP Semiconductors Low-power configurable multiple function gate 13. Transfer characteristics Table 12. Transfer characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Typ[1] Min positive-going threshold voltage VT+ [1] Max VCC = 1.8 V 0.70 1.02 1.20 0.67 1.20 V VCC = 2.3 V 1.11 1.42 1.60 1.08 1.60 V VCC = 3.0 V 1.50 1.79 2.00 1.47 2.00 V VCC = 4.5 V 2.16 2.52 2.74 2.13 2.74 V VCC = 5.5 V 2.61 2.99 3.33 2.58 3.33 V VCC = 1.8 V 0.30 0.53 0.72 0.30 0.75 V VCC = 2.3 V 0.58 0.77 1.00 0.58 1.03 V VCC = 3.0 V 0.80 1.04 1.30 0.80 1.33 V VCC = 4.5 V 1.21 1.55 1.90 1.21 1.93 V VCC = 5.5 V 1.45 1.86 2.29 1.45 2.32 V VCC = 1.8 V 0.30 0.48 0.62 0.23 0.62 V VCC = 2.3 V 0.40 0.64 0.80 0.34 0.80 V VCC = 3.0 V 0.50 0.75 1.00 0.44 1.00 V VCC = 4.5 V 0.71 0.97 1.20 0.65 1.20 V VCC = 5.5 V 0.71 1.13 1.40 0.65 1.40 V see Figure 12, Figure 13, Figure 14 and Figure 15 hysteresis voltage VH Min see Figure 12, Figure 13, Figure 14 and Figure 15 negative-going threshold voltage VT Max 40 C to +125 C Unit (VT+ VT); see Figure 12, Figure 13, Figure 14 and Figure 15 Typical values are measured at Tamb = 25 C. 14. Waveforms transfer characteristics VT+ VO VI VH VT− VO VI VH VT− VT+ Fig 12. Transfer characteristics 74LVC1G58_Q100 Product data sheet mna207 mna208 VT+ and VT limits are at 70 % and 20 %. Fig 13. Definition of VT+, VT and VH All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 10 of 17 74LVC1G58-Q100 NXP Semiconductors Low-power configurable multiple function gate VI VO VT+ VH VT− VO VI VH VT− VT+ mnb155 001aab684 VT+ and VT limits are at 70 % and 20 %. Fig 14. Transfer characteristics Fig 15. Definition of VT+, VT and VH 001aab594 16 I CC (mA) 12 8 4 0 0 1 2 3 VI (V) Fig 16. Typical 74LVC1G58-Q100 transfer characteristics; VCC = 3.0 V 74LVC1G58_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 11 of 17 74LVC1G58-Q100 NXP Semiconductors Low-power configurable multiple function gate 15. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT363 JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 17. Package outline SOT363 (SC-88) 74LVC1G58_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 12 of 17 74LVC1G58-Q100 NXP Semiconductors Low-power configurable multiple function gate Plastic surface-mounted package (TSOP6); 6 leads D SOT457 E B y A HE 6 5 X v M A 4 Q pin 1 index A A1 c 1 2 3 Lp bp e w M B detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.1 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT457 JEITA SC-74 EUROPEAN PROJECTION ISSUE DATE 05-11-07 06-03-16 Fig 18. Package outline SOT457 (TSOP6) 74LVC1G58_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 13 of 17 74LVC1G58-Q100 NXP Semiconductors Low-power configurable multiple function gate 16. Abbreviations Table 13. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model TTL Transistor-Transistor Logic 17. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC1G58_Q100 v.1 20140610 Product data sheet - - 74LVC1G58_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 14 of 17 74LVC1G58-Q100 NXP Semiconductors Low-power configurable multiple function gate 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74LVC1G58_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 15 of 17 74LVC1G58-Q100 NXP Semiconductors Low-power configurable multiple function gate No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVC1G58_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 10 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 16 of 17 NXP Semiconductors 74LVC1G58-Q100 Low-power configurable multiple function gate 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Logic configurations . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Transfer characteristics . . . . . . . . . . . . . . . . . 10 Waveforms transfer characteristics. . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 10 June 2014 Document identifier: 74LVC1G58_Q100