MCP1726 Data Sheet

MCP1726
1A, Low-Voltage, Low Quiescent Current LDO Regulator
Features:
Description:
•
•
•
•
The MCP1726 is a 1A Low Dropout (LDO) linear
regulator that provides high current and low output
voltages in a very small package. The MCP1726
comes in fixed or adjustable output voltage versions,
with an output voltage range of 0.8V to 5.0V. The 1A
output current capability and low output voltage
capability make the MCP1726 a good choice for new
sub-1.8V output voltage LDO applications that have
high current demands.
•
•
•
•
•
•
•
•
•
1A Output Current Capability
Input Operating Voltage Range: 2.3V to 6.0V
Adjustable Output Voltage Range: 0.8V to 5.0V
Standard Fixed Output Voltages:
- 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V
Low Dropout Voltage: 220 mV typical at 1A
Typical Output Voltage Tolerance: ±0.5%
Stable with 1.0 µF Ceramic Output Capacitor
Fast Response to Load Transients
Low Supply Current: 140 µA (typical)
Low Shutdown Supply Current: 0.1 µA (typical)
Adjustable Delay on Power Good Output
Short-Circuit Current Limiting and
Overtemperature Protection
3x3 DFN-8 and SOIC-8 Package Options
Applications:
•
•
•
•
•
•
High-Speed Driver Chipset Power
Networking Backplane Cards
Notebook Computers
Network Interface Cards
Palmtop Computers
2.5V to 1.XV Regulators
The MCP1726 is stable using ceramic output
capacitors that inherently provide lower output noise
and reduce the size and cost of the entire regulator
solution. Only 1 µF of output capacitance is needed to
stabilize the LDO.
Using CMOS construction, the quiescent current
consumed by the MCP1726 is typically less than
140 µA over the entire input voltage range, making it
attractive for portable computing applications that
demand high output current. When the MCP1726 is
shut down, the quiescent current is reduced to less
than 0.1 µA.
The scaled-down output voltage is internally monitored
and a Power Good (PWRGD) output is provided when
the output is within 92% of regulation (typical). An
external capacitor can be used on the CDELAY pin to
adjust the delay from 1 ms to 300 ms.
The overtemperature and short-circuit current limiting
provide additional protection for the LDO during system
fault conditions.
Package Types
MCP1726-ADJ
SOIC
VIN 1
VIN 2
SHDN 3
GND 4
MCP1726-xx
SOIC
MCP1726-ADJ
3x3 DFN
MCP1726-xx
3x3 DFN
8 VOUT
VIN 1
8 VOUT
VIN 1
8 VOUT
VIN 1
7 ADJ
VIN 2
7 VOUT
VIN 2
7 ADJ
VIN 2
6 CDELAY SHDN 3
5 PWRGD GND 4
 2005-2014 Microchip Technology Inc.
6 CDELAY SHDN 3
5 PWRGD GND 4
EP
9
6 CDELAY SHDN 3
5 PWRGD
GND 4
8 VOUT
EP
9
7 VOUT
6 CDELAY
5 PWRGD
DS20001936D-page 1
MCP1726
Typical Application
MCP1726 Fixed Output Voltage
VIN = 2.3V to 2.8V
C1
4.7 µF
1 VIN
VOUT 8
2 VIN
VOUT 7
3 SHDN
4 GND
VOUT = 1.8V @ 1A
C2
1 µF
CDELAY 6
PWRGD 5
C3
1000 pF
On
R1
100 k
Off
PWRGD
MCP1726 Adjustable Output Voltage
VIN = 2.3V to 2.8V
C1
4.7 µF
1 VIN
VOUT 8
2 VIN
ADJ 7
3 SHDN
4 GND
On
Off
VOUT = 1.2V @ 1A
R1
40 k
CDELAY 6
C2
1 µF
R3
100 k
PWRGD 5
C3
1000 pF
R2
20 k
PWRGD
DS20001936D-page 2
 2005-2014 Microchip Technology Inc.
MCP1726
Functional Block Diagram
PMOS
VIN
VOUT
Undervoltage
Lockout
(UVLO)
ISNS
Cf
Rf
SHDN
ADJ
Overtemperature
Sensing
+
Driver w/ Limit
and SHDN
EA
–
SHDN
VREF
VIN
SHDN
Reference
Soft-Start
Comp
TDELAY
PWRGD
GND
92% of VREF
 2005-2014 Microchip Technology Inc.
CDELAY
DS20001936D-page 3
MCP1726
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VIN ....................................................................................6.5V
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
Maximum Voltage on Any Pin .. (GND – 0.3V) to (VDD + 0.3)V
Maximum Junction Temperature, TJ ........................... +150°C
Maximum Power Dissipation ......... Internally-Limited (Note 6)
Storage Temperature.....................................-65°C to +150°C
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, VIN = (VR + 0.5V) or 2.3V, whichever is greater, IOUT = 1 mA,
CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C. Boldface type applies for junction temperatures, TJ (Note 7), of -40°C to +125°C.
Parameters
Sym.
Min.
Typ.
Max.
Input Operating Voltage
VIN
2.3
Input Quiescent Current
Iq
Input Quiescent Current for
SHDN Mode
Maximum Output Current
6.0
V
Note 1
—
140
220
µA
IL = 0 mA, VIN = VR + 0.5V,
VOUT = 0.8V to 5.0V
ISHDN
—
0.1
3
µA
SHDN = GND
IOUT
1
—
—
A
VIN = 2.3V to 6.0V (Note 1)
Line Regulation
VOUT/
(VOUT x VIN)
—
0.05
0.3
%/V
Load Regulation
VOUT/VOUT
-1.5
±0.5
1.5
%
IOUT = 1 mA to 1A,
VIN = (VR + 0.6)V (Note 4)
IOUT_SC
—
1.7
—
A
VIN = (VR + 0.5)V,
RLOAD < 0.1, Peak Current
Adjust Pin Reference Voltage
VADJ
0.402
0.410
0.418
V
VIN = 2.3V to VIN = 6.0V,
IOUT = 1 mA
Adjust Pin Leakage Current
IADJ
-10
±0.01
+10
nA
VIN = 6.0V, VADJ = 0V to 6V
TCVOUT
—
40
—
ppm/°C
Note 3
V
Note 2
Output Short-Circuit Current
Units
Conditions
(VR + 0.5)V  VIN  6V
Adjust Pin Characteristics
Adjust Temperature Coefficient
Fixed-Output Characteristics
Voltage Regulation
VOUT
VR – 2.5% VR ± 0.5% VR + 2.5%
Dropout Characteristics
Dropout Voltage
Note 1:
2:
3:
4:
5:
6:
7:
VIN – VOUT
—
220
500
mV
IOUT = 1A, VIN(MIN) = 2.3V
(Note 5)
The minimum VIN must meet two conditions: VIN  2.3V and VIN  VR + 2.5%  VDROPOUT.
VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ x ((R1/R2) + 1). See Figure 4-1.
TCVOUT = (VOUT-HIGH – VOUT-LOW) x 106/(VR x Temperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VR + 0.5V.
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, JA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum 150°C rating. Sustained
junction temperatures above 125°C can impact device reliability.
The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
DS20001936D-page 4
 2005-2014 Microchip Technology Inc.
MCP1726
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = (VR + 0.5V) or 2.3V, whichever is greater, IOUT = 1 mA,
CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C. Boldface type applies for junction temperatures, TJ (Note 7), of -40°C to +125°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
VPWRGD_VIN
1.0
—
6.0
V
1.2
—
6.0
Conditions
Power Good Characteristics
Input Voltage Operating Range
for Valid PWRGD
TA = +25°C
TA = -40°C to +125°C
ISINK = 100 µA
PWRGD Threshold Voltage
(Referenced to VOUT)
PWRGD_THF
PWRGD_THR
88
92
96
%
VOUT < 2.5V, Falling Edge
89
92
95
%
VOUT > 2.5V, Falling Edge
89
94
98
%
VOUT < 2.5V, Rising Edge
90
93
96
%
VOUT > 2.5V, Rising Edge
PWRGD Output Voltage Low
VPWRGD_L
—
0.2
0.4
V
IPWRGD SINK = 1.2 mA
PWRGD Leakage
PWRGD_LK
—
0.1
—
µA
VPWRGD = VIN = 6.0V
PWRGD Time Delay
TPG
—
200
—
µs
CDELAY = OPEN
10
30
55
ms
CDELAY = 0.01 µF
CDELAY = 0.1 µF
—
300
—
ms
TVDET-PWRGD
—
170
—
µs
Logic-High Input
VSHDN-HIGH
45
—
—
%VIN
VIN = 2.3V to 6.0V
Logic-Low Input
VSHDN-LOW
—
—
15
%VIN
VIN = 2.3V to 6.0V
SHDNILK
-0.1
±0.001
+0.1
µA
VIN = 6V, SHDN = VIN,
SHDN = GND
µs
SHDN = GND to VIN
VOUT = GND to 95% VR
Detect Threshold to PWRGD
Active Time Delay
Shutdown Input
SHDN Input Leakage Current
AC Performance
Output Delay from SHDN
Output Noise
TOR
100
eN
—
2.0
—
µV/Hz
Power Supply Ripple Rejection
Ratio
PSRR
—
54
—
dB
f = 100 Hz, COUT = 10 µF,
IOUT = 100 mA,
VINAC = 30 mV pk-pk,
CIN = 0 µF
Thermal Shutdown Temperature
TSD
—
150
—
°C
IOUT = 100 µA,
VOUT = 1.8V, VIN = 2.8V
TSD
—
10
—
°C
IOUT = 100 µA,
VOUT = 1.8V, VIN = 2.8V
Thermal Shutdown Hysteresis
Note 1:
2:
3:
4:
5:
6:
7:
IOUT = 200 mA, f = 1 kHz,
COUT = 1 µF (X7R Ceramic),
VOUT = 2.5V
The minimum VIN must meet two conditions: VIN  2.3V and VIN  VR + 2.5%  VDROPOUT.
VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ x ((R1/R2) + 1). See Figure 4-1.
TCVOUT = (VOUT-HIGH – VOUT-LOW) x 106/(VR x Temperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VR + 0.5V.
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, JA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum 150°C rating. Sustained
junction temperatures above 125°C can impact device reliability.
The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
 2005-2014 Microchip Technology Inc.
DS20001936D-page 5
MCP1726
TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, all limits apply for VIN = 2.3V to 6.0V.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Operating Junction Temperature Range
TJ
-40
—
+125
°C
Steady State
Maximum Junction Temperature
TJ
—
—
+150
°C
Transient
Storage Temperature Range
TA
-65
—
+150
°C
JA
—
64
—
°C/W
4-Layer JC51-5
Standard Board with
Vias
JC
—
12
—
JA
—
163
—
°C/W
4-Layer JC51-7
Standard Board
JC
—
42
—
Temperature Ranges
Thermal Package Resistances
Thermal Resistance, 8L 3x3 DFN
Thermal Resistance, 8L SOIC
DS20001936D-page 6
 2005-2014 Microchip Technology Inc.
MCP1726
2.0
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Note: Unless otherwise indicated, VIN = VOUT + 0.5V, IOUT = 1 mA and TA = +25°C.
0.05
VR = 1.2V (Adj.)
IOUT = 0 mA
170
Line Regulation (%/V)
160
+125°C
150
140
+25°C
130
120
-40ºC
110
VR = 1.2V (Adj.)
VIN = 2.3V to 6.0V
0.04
IOUT = 1A
0.03
0.02
IOUT = 500 mA
0.01
0
IOUT = 1 mA
-0.01
IOUT = 100 mA
Input Voltage (V)
125
FIGURE 2-4:
Line Regulation vs.
Temperature (1.2V Adjustable).
300
0.70
VR = 1.2V (Adj.)
280
VR = 5.0V
Load Regulation (%)
260
240
220
VIN = 3.3V
200
VIN = 2.5V
180
160
140
120
0.60
0.50
VR = 3.3V
VR = 1.8V
0.40
VR = 0.8V
0.30
0.20
VIN = VR + 0.6V (or 2.3V)
IOUT = 1 mA to 1A
VIN = 3.3V
VIN = 2.5V
120
95
80
125
VIN = 5.0V
130
125
Adjust Pin Voltage (mV)
140
110
FIGURE 2-5:
Temperature.
411.00
VR = 1.2V (Adj.)
IOUT = 0 mA
150
65
Temperature (°C)
FIGURE 2-2:
Ground Current vs. Load
Current (1.2V Adjustable).
160
110
Load Current (mA)
50
1000
35
800
20
600
5
400
-10
200
-40
0.10
0
-25
110
100
Load Regulation vs.
IOUT = 1 mA
410.50
410.00
VIN = 6.0V
VIN = 2.3V
409.50
409.00
Temperature (°C)
FIGURE 2-3:
Quiescent Current vs.
Junction Temperature (1.2V Adjustable).
 2005-2014 Microchip Technology Inc.
95
80
65
50
35
20
-10
-25
-40
125
95
110
80
65
50
35
20
5
-10
-25
-40
408.50
5
Ground Current (µA)
95
Temperature (°C)
FIGURE 2-1:
Quiescent Current vs. Input
Voltage (1.2V Adjustable).
Quiescent Current (µA)
110
5.8
80
5.3
65
4.8
50
4.3
35
3.8
20
3.3
-10
2.8
-40
2.3
5
-0.02
100
-25
Quiescent Current (µA)
180
Temperature (°C)
FIGURE 2-6:
Temperature.
Adjust Pin Voltage vs.
DS20001936D-page 7
MCP1726
250
225
200
175
150
125
100
75
50
25
0
180
Adjustable Version
Quiescent Current (µA)
VOUT = 5.0V
VOUT = 2.5V
VOUT = 0.8V
IOUT = 0 mA
170
+125°C
160
150
140
+90°C
130
+25°C
120
-40°C
110
FIGURE 2-7:
Dropout Voltage vs. Output
Current (Adjustable Version).
Quiescent Current (µA)
Dropout Voltage (mV)
250
240
VOUT = 5.0V
230
VOUT = 3.3V
220
VOUT =2.5V
210
200
500
+25°C
200
100
-40°C
FIGURE 2-11:
Quiescent Current vs. Input
Voltage (3.3V Fixed).
Ground Current (µA)
VIN =2.3V
VIN =3.0V
28
VIN =5.5V
24
22
CDELAY = 10 nF
125
110
95
80
65
50
35
20
5
-10
20
-25
5.9
300
2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 5.6 5.9
32
-40
Power Good Time Delay (ms)
5.6
+125°C
400
Input Voltage (V)
FIGURE 2-8:
Dropout Voltage vs.
Temperature (Adjustable Version).
340
320
300
280
260
240
220
200
180
160
140
120
VIN = 2.3V for 0.8V device
VOUT =3.3V
VOUT =0.8V
0
FIGURE 2-9:
Power Good (PWRGD)
Time Delay vs. Temperature.
200
400
600
800
1000
Load Current (mA)
Temperature (°C)
DS20001936D-page 8
5.3
600
Temperature (°C)
26
5.0
VOUT =3.3V
IOUT = 0 mA
700
0
125
110
95
80
65
50
35
5
20
-10
-25
-40
190
30
4.7
FIGURE 2-10:
Quiescent Current vs. Input
Voltage (0.8V Fixed).
800
Adjustable Version
IOUT = 1A
260
4.4
Input Voltage (V)
Output Current (mA)
270
4.1
1000
3.8
800
3.5
600
3.2
400
2.9
200
2.6
100
0
2.3
Dropout Voltage (mV)
Note: Unless otherwise indicated, VIN = VOUT + 0.5V, IOUT = 1 mA and TA = +25°C.
FIGURE 2-12:
Current.
Ground Current vs. Load
 2005-2014 Microchip Technology Inc.
MCP1726
Note: Unless otherwise indicated, VIN = VOUT + 0.5V, IOUT = 1 mA and TA = +25°C.
0.025
IOUT =1 mA
Quiescent Current vs.
VOUT =0.8V
VOUT =1.2V
FIGURE 2-15:
Line Regulation vs.
Temperature (0.8V Fixed).
125
110
95
65
80
125
110
95
80
125
95
Temperature (°C)
110
80
65
50
35
20
5
-10
-25
-40
-0.025
IOUT = 1 mA to 1000 mA
VIN = VOUT + 0.6V
65
VOUT = 0.8V
50
IOUT =100 mA
-0.02
VOUT =2.5V
35
-0.01
VOUT =3.3V
VOUT =5.0V
5
IOUT =10 mA
-10
IOUT =500 mA
-0.005
-40
0.005
-0.20
-0.25
-0.30
-0.35
-0.40
-0.45
-0.50
-0.55
-0.60
-0.65
-0.70
-25
IOUT =1.0A
Load Regulation (%)
Line Regulation (%/V)
50
FIGURE 2-17:
Load Regulation vs.
Temperature (VOUT < 2.5V Fixed).
0.015
 2005-2014 Microchip Technology Inc.
35
Temperature (°C)
ISHDN vs. Temperature.
-0.015
20
5
-10
IOUT = 1 mA to 1000 mA
VIN = 2.3V
Temperature (°C)
0
125
VOUT =1.8V
-25
125
95
110
80
65
50
35
20
5
-10
-25
VIN =2.3V
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
-40
VIN =3.3V
0.01
95
FIGURE 2-16:
Line Regulation vs.
Temperature (3.3V Fixed).
VIN =6.0V
FIGURE 2-14:
110
Temperature (°C)
Load Regulation (%)
100
90
80
70
60
50
40
30
20
10
0
-40
ISHDN (nA)
FIGURE 2-13:
Temperature.
80
-40
Temperature (°C)
65
-0.01
125
95
110
80
65
50
35
20
5
-10
-25
-40
100
0
-0.005
50
110
IOUT =100 mA
35
VOUT =0.8V
120
0.01
0.005
5
130
IOUT =500 mA
20
VOUT =3.3V
140
IOUT =1A
0.015
20
150
VOUT = 3.3V
0.02
-10
160
-25
IOUT = 0 mA
VIN = 2.3V for 0.8V Device
Line Regulation (%/V)
Quiescent Current (µA)
170
Temperature (°C)
FIGURE 2-18:
Load Regulation vs.
Temperature (VOUT  2.5V Fixed).
DS20001936D-page 9
MCP1726
10
250
225
200
175
150
125
100
75
50
25
0
VOUT =2.5V (Adj)
IOUT = 200 mA
Noise (µV—Hz)
Dropout Voltage (mV)
Note: Unless otherwise indicated, VIN = VOUT + 0.5V, IOUT = 1 mA and TA = +25°C.
VOUT =5.0V
VOUT =2.5V
1
VOUT =0.8V (Fixed)
IOUT = 100 mA
0.1
COUT =1 µF
CIN = 10 µF
0
200
400
600
800
0.01
0.01
1000
0.1
Dropout Voltage vs. Load
80
1000
PSRR (dB)
60
VOUT =5.0V
VOUT =3.3V
50
40
30
20
COUT =10 µF
CIN = 0 µF
IOUT = 100 mA
0
0.01
125
110
95
80
65
50
35
5
10
20
-25
VOUT =2.5V
0.1
Temperature (°C)
FIGURE 2-20:
Temperature.
Dropout Voltage vs.
1
10
100
1000
Frequency (kHz)
FIGURE 2-23:
Power Supply Ripple
Rejection (PSRR) vs. Frequency (VOUT = 1.2V
Adjustable).
1.7
90
1.6
80
VOUT = 1.2V
VIN = 2.5V
70
1.5
PSRR (dB)
Short Circuit Current (A)
100
VOUT = 1.2V
VIN = 2.5V
70
250
240
230
220
210
200
190
180
1.4
1.3
1.2
60
50
40
30
20
1.1
10
FIGURE 2-22:
Output Noise Voltage
Density vs. Frequency.
IOUT = 1A
-10
270
260
-40
Dropout Voltage (mV)
FIGURE 2-19:
Current.
1
Frequency (kHz)
Load Current (mA)
VOUT =1.2V (Fixed)
1.0
2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 5.6 5.9
Input Voltage (V)
FIGURE 2-21:
Input Voltage.
DS20001936D-page 10
Short-Circuit Current vs.
10
COUT =22 µF
CIN = 0 µF
IOUT = 100 mA
0
0.01
0.1
1
10
100
1000
Frequency (kHz)
FIGURE 2-24:
Power Supply Ripple
Rejection (PSRR) vs. Frequency (VOUT = 1.2V
Adjustable).
 2005-2014 Microchip Technology Inc.
MCP1726
Note: Unless otherwise indicated, VIN = VOUT + 0.5V, IOUT = 1 mA and TA = +25°C.
80
VOUT = 2.5V
VIN = 3.3V
70
PSRR (dB)
60
VOUT
50
40
PWRGD
30
20
10
COUT =10 µF
CIN = 0 µF
IOUT = 100 mA
0
0.01
0.1
SHDN
1
10
100
1000
Frequency (kHz)
FIGURE 2-25:
Power Supply Ripple
Rejection (PSRR) vs. Frequency (VOUT = 2.5V
Fixed).
80
2.5V (Adjustable) Start-Up
VOUT = 2.5V
VIN = 3.3V
70
60
PSRR (dB)
FIGURE 2-28:
from Shutdown.
VOUT
50
40
PWRGD
30
20
10
COUT =22 µF
CIN = 0 µF
IOUT = 100 mA
0
0.01
0.1
VIN
1
10
100
1000
Frequency (kHz)
FIGURE 2-26:
Power Supply Ripple
Rejection (PSRR) vs. Frequency (VOUT = 2.5V
Fixed).
FIGURE 2-29:
Power Good (PWRGD)
Timing with CBYPASS of 1000 pF.
VOUT
VOUT
PWRGD
VIN
VIN
FIGURE 2-27:
from VIN.
PWRGD
2.5V (Adjustable) Start-Up
 2005-2014 Microchip Technology Inc.
FIGURE 2-30:
Power Good (PWRGD)
Timing with CBYPASS of 0.01 µF.
DS20001936D-page 11
MCP1726
Note: Unless otherwise indicated, VIN = VOUT + 0.5V, IOUT = 1 mA and TA = +25°C.
3.3V
VIN
2.3V
VOUT
CIN = 47 µF
COUT = 10 µF
VOUT
CIN = 1 µF
IOUT
VIN
COUT = 10 µF
IOUT = 100 mA
FIGURE 2-31:
(1.2V Fixed).
Dynamic Line Response
4.5V
3.5V
VIN
FIGURE 2-33:
Dynamic Load Response
(2.5V Fixed, 10 mA to 1000 mA).
VOUT
CIN = 47 µF
COUT = 10 µF
VOUT
CIN = 1 µF
IOUT
VIN
COUT = 10 µF
IOUT = 100 mA
FIGURE 2-32:
(2.5V Fixed).
DS20001936D-page 12
Dynamic Line Response
FIGURE 2-34:
Dynamic Load Response
(2.5V Fixed, 100 mA to 1000 mA).
 2005-2014 Microchip Technology Inc.
MCP1726
3.0
PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
Fixed Output
Adjustable Output
Name
3x3 DFN
SOIC
3x3 DFN
SOIC
1
1
1
1
2
2
2
3
3
3
4
4
4
3.1
Description
VIN
Input Voltage Supply
2
VIN
Input Voltage Supply
3
SHDN
4
GND
Shutdown Control Input (active-low)
Ground
5
5
5
5
PWRGD Power Good Output
6
6
6
6
CDELAY Power Good Delay Set-Point Input
—
—
7
7
ADJ
Output Voltage Sense Input (adjustable version)
7
7
—
—
VOUT
Regulated Output Voltage
8
8
8
8
VOUT
Regulated Output Voltage
9
—
9
—
EP
Exposed Pad
Input Voltage Supply (VIN)
Connect the unregulated or regulated input voltage
source to VIN. If the input voltage source is located
several inches away from the LDO or the input source
is a battery, it is recommended that an input capacitor
be used. A typical input capacitance value of 1 µF to
10 µF should be sufficient for most applications.
3.2
Shutdown Control Input (SHDN)
The SHDN input is used to turn the LDO output voltage
on and off. When the SHDN input is at a logic-high
level, the LDO output voltage is enabled. When the
SHDN input is pulled to a logic-low level, the LDO
output voltage is disabled. When the SHDN input is
pulled low, the PWRGD output also goes low and the
LDO enters a low quiescent current shutdown state
where the typical quiescent current is 0.1 µA.
3.3
Ground (GND)
3.5
Power Good Delay Set-Point Input
(CDELAY)
The CDELAY input sets the power-up delay time for the
PWRGD output. By connecting an external capacitor
from the CDELAY pin to ground, the delay times for the
PWRGD output can be adjusted from 200 µs (no
capacitance) to 300 ms (0.1 µF capacitor). This allows
for the optimal setting of the system reset time.
3.6
Output Voltage Sense Input (ADJ)
The output voltage adjust pin (ADJ) for the adjustable
output voltage version of the MCP1726 allows the user
to set the output voltage of the LDO by using two
external resistors. The adjust pin voltage is 0.41V
(typical).
3.7
Regulated Output Voltage (VOUT)
Connect the GND pin of the LDO to a quiet circuit
ground. This will help the LDO power supply rejection
ratio and noise performance. The ground pin of the
LDO only conducts the quiescent current of the LDO
(typically 140 µA), so a heavy trace is not required.
The VOUT pin(s) is the regulated output voltage of the
LDO. A minimum output capacitance of 1.0 µF is
required for LDO stability. The MCP1726 is stable with
ceramic,
tantalum
and
aluminum-electrolytic
capacitors. See Section 4.3 “Output Capacitor” for
output capacitor selection guidance.
3.4
3.8
Power Good Output (PWRGD)
The PWRGD output is an open-drain output used to
indicate when the LDO output voltage is within 92%
(typically) of its nominal regulation value. The PWRGD
output has a typical hysteresis value of 2% for the
adjustable voltage version and for voltage outputs less
than 2.5V. For fixed output voltage versions greater
than 2.5V, the hysteresis is 0.7%. The PWRGD output
is delayed on power-up by 200 µs (typical, no
capacitance on the CDELAY pin). This delay time is
controlled by the CDELAY pin.
 2005-2014 Microchip Technology Inc.
Exposed Pad (EP)
The 3x3 DFN package has an exposed pad on the
bottom of the package. This pad should be soldered to
the Printed Circuit Board (PCB) to aid in the removal of
heat from the package during operation. The exposed
pad is at the ground potential of the LDO.
DS20001936D-page 13
MCP1726
4.0
DEVICE OVERVIEW
4.2
The MCP1726 is a high output current, Low Dropout
(LDO) voltage regulator with an adjustable delay
power-good output and shutdown control input. The
low dropout voltage of 220 mV at 1A of current makes
it ideal for battery-powered applications. Unlike other
high output current LDOs, the MCP1726 only draws
220 µA of quiescent current at full load.
4.1
LDO Output Voltage
The MCP1726 LDO is available with either a fixed
output voltage or an adjustable output voltage. The
allowable output voltage range is 0.8V to 5.5V for both
versions.
4.1.1
ADJUSTABLE INPUT
The adjustable version of the MCP1726 uses the ADJ
pin (pin 7) to get the output voltage feedback for output
voltage regulation. This allows the user to set the
output voltage of the device with two external resistors.
The nominal voltage for ADJ is 0.41V.
Figure 4-1 shows the adjustable version of the
MCP1726. Resistors R1 and R2 form the resistor
divider network necessary to set the output voltage.
With this configuration, the equation for setting VOUT is:
EQUATION 4-1:
VOUT = LDO Output Voltage
VADJ = ADJ Pin Voltage (typically 0.41V)
MCP1726-ADJ
VIN
C1
4.7 µF
1 VIN
2 VIN
3 SHDN
On
4 GND
Off
VOUT 8
ADJ 7
VOUT
R1
CDELAY 6
C2
1 µF
PWRGD 5
C3
1000 pF
The MCP1726 LDO is tested and ensured to supply a
minimum of 1A of output current. The MCP1726 has no
minimum output load, so the output load current can go
to 0 mA and the LDO will continue to regulate the
output voltage to within tolerance.
The MCP1726 also incorporates an output current limit.
If the output voltage falls below 0.7V due to an overload
condition (usually represents a shorted load condition),
the output current is limited to 1.7A (typical). If the
overload condition is a soft overload, the MCP1726 will
supply higher load currents of up to 3A. The MCP1726
should not be operated in this condition continuously as
it may result in failure of the device. However, this does
allow for device usage in applications that have higher
pulsed load currents having an average output current
value of 1A or less.
Output overload conditions may also result in an
overtemperature shutdown of the device. If the junction
temperature rises above 150°C, the LDO will shut
down the output voltage. See Section 4.9
“Overtemperature Protection” for more information
on overtemperature shutdown.
4.3
Output Capacitor
The MCP1726 requires a minimum output capacitance
of 1 µF for output voltage stability. Ceramic capacitors
are recommended because of their size, cost and
environmental robustness qualities.
R1 + R 2
= V ADJ  -------------------
 R2 
V OUT
Output Current and Current
Limiting
R2
FIGURE 4-1:
Typical Adjustable Output
Voltage Application Circuit.
Aluminum-electrolytic and tantalum capacitors can be
used on the LDO output as well. The Equivalent Series
Resistance (ESR) of the electrolytic output capacitor
must be no greater than 2. The output capacitor
should be located as close to the LDO output as is
practical. Ceramic materials X7R and X5R have low
temperature coefficients and are well within the
acceptable ESR range required. A typical 1 µF X7R
0805 capacitor has an ESR of 50 m.
Larger LDO output capacitors can be used with the
MCP1726 to improve dynamic performance and power
supply ripple rejection performance. A maximum of
22 µF
is
recommended.
Aluminum-electrolytic
capacitors are not recommended for low-temperature
applications of < -25°C.
The range of allowable resistance values for resistor R2
is 10 kΩ to 200 kΩ. Solving the equation for R1 yields
the following equation:
EQUATION 4-2:
V OUT – V ADJ
R1 = R2  --------------------------------


V ADJ
VOUT = LDO Output Voltage
VADJ = ADJ Pin Voltage (typically 0.41V)
DS20001936D-page 14
 2005-2014 Microchip Technology Inc.
MCP1726
4.4
Input Capacitor
Low input source impedance is necessary for the LDO
output to operate properly. When operating from
batteries or in applications with long lead length (> 10
inches) between the input source and the LDO, some
input capacitance is recommended. A minimum of
1.0 µF to 4.7 µF is recommended for most applications.
For applications that have output step load
requirements, the input capacitance of the LDO is very
important. The input capacitance provides the LDO
with a good local low-impedance source to pull the
transient currents from in order to respond quickly to
the output load step. For good step response
performance, the input capacitor should be of
equivalent (or higher) value than the output capacitor.
The capacitor should be placed as close to the input of
the LDO as is practical. Larger input capacitors will also
help reduce any high-frequency noise on the input and
output of the LDO and reduce the effects of any
inductance that exists between the input source
voltage and the input capacitance of the LDO.
4.5
The power good output is an open-drain output that can
be pulled up to any voltage that is equal to or less than
the LDO input voltage. This output is capable of sinking
1.2 mA (VPWRGD < 0.4V maximum).
VPWRGD_TH
VOUT
TPG
VOH
TVDET_PWRGD
PWRGD
VOL
FIGURE 4-2:
Power Good Timing.
Power Good Output (PWRGD)
The PWRGD output is used to indicate when the output
voltage of the LDO is within 92% (typical value, see the
DC Characteristics table for Min/Max specs) of its
nominal regulation value.
As the output voltage of the LDO rises, the PWRGD
output will be held low until the output voltage has
exceeded the power good threshold plus the hysteresis
value. Once this threshold has been exceeded, the
power good time delay is started (shown as TPG in the
DC Characteristics table). The power good time delay
is adjustable via the CDELAY pin of the LDO (see
Section 4.6 “CDELAY Input”). By placing a capacitor
from the CDELAY pin to ground, the power good time
delay can be adjusted from 200 µs (no capacitance) to
300 ms (0.1 µF capacitor). After the time delay period,
the PWRGD output will go high, indicating that the
output voltage is stable and within regulation limits.
If the output voltage of the LDO falls below the power
good threshold, the power good output will transition
low. The power good circuitry has a 170 µs delay when
detecting a falling output voltage, which helps to
increase noise immunity of the power good output and
avoid false triggering of the power good output during
fast output transients. See Figure 4-2 for power good
timing characteristics.
When the LDO is put into Shutdown mode using the
SHDN input, the power good output is pulled low
immediately, indicating that the output voltage will be
out of regulation. The timing diagram for the power
good output when using the shutdown input is shown in
Figure 4-3.
 2005-2014 Microchip Technology Inc.
VIN
TOR
30 ms
70 ms
TPG
SHDN
VOUT
PWRGD
FIGURE 4-3:
Shutdown.
4.6
Power Good Timing from
CDELAY Input
The CDELAY input is used to provide the power-up delay
timing for the power good output, as discussed in the
previous section. By adding a capacitor from the
CDELAY pin to ground, the PWRGD power-up time
delay can be adjusted from 200 µs (no capacitance on
CDELAY) to 300 ms (0.1 µF of capacitance on CDELAY).
See the DC Characteristics table for CDELAY timing
tolerances.
DS20001936D-page 15
MCP1726
Once the power good threshold (rising) has been
reached, the CDELAY pin charges the external capacitor
to 1.5V (typical; this level can vary between 1.4V and
1.75V across the input voltage range of the part). The
PWRGD output will transition high when the CDELAY pin
voltage has charged to 0.42V. If the output falls below
the power good threshold limit during the charging time
between 0.0V and 0.42V on the CDELAY pin, the
CDELAY pin voltage will be pulled to ground, thus
resetting the timer. The CDELAY pin will be held low until
the output voltage of the LDO has once again risen
above the power good rising threshold. A timing
diagram showing CDELAY, PWRGD and VOUT is shown
in Figure 4-4.
VOUT
CDELAY
1.5V (typical)
CDELAY Threshold (0.42V)
0V
PWRGD
FIGURE 4-4:
Diagram.
4.7
CDELAY and PWRGD Timing
Shutdown Input (SHDN)
The SHDN input is an active-low input signal that turns
the LDO on and off. The SHDN threshold is a percentage
of the input voltage. The typical value of this shutdown
threshold is 30% of VIN, with minimum and maximum
limits over the entire operating temperature range of 45%
and 15%, respectively.
The SHDN input will ignore low-going pulses (pulses
meant to shut down the LDO) that are up to 400 ns in
pulse width. If the shutdown input is pulled low for more
than 400 ns, the LDO will enter Shutdown mode. This
small bit of filtering helps reject any system noise spikes
on the shutdown input signal.
On the rising edge of the SHDN input, the shutdown
circuitry has a 30 µs delay before allowing the LDO
output to turn on. This delay helps to reject any false
turn-on signals or noise on the SHDN input signal. After
the 30 µs delay, the LDO output enters its soft-start
period as it rises from 0V to its final regulation value. If the
SHDN input signal is pulled low during the 30 µs delay
period, the timer will be reset and the delay time will start
over again on the next rising edge of the SHDN input.
The total time from the SHDN input going high (turn-on)
to the LDO output being in regulation is typically 100 µs.
See Figure 4-5 for a timing diagram of the SHDN input.
DS20001936D-page 16
400 ns (typical)
30 µs
70 µs
SHDN
VOUT
FIGURE 4-5:
Diagram.
4.8
VPWRGD_TH
TPG
TOR
Shutdown Input Timing
Dropout Voltage and Undervoltage
Lockout
Dropout voltage is defined as the input-to-output
voltage differential at which the output voltage drops
2% below the nominal value that was measured with a
VR + 0.5V differential applied. The MCP1726 LDO has
a very low dropout voltage specification of 220 mV
(typical) at 1A of output current. See the DC
Characteristics table for maximum dropout voltage
specifications.
The MCP1726 LDO operates across an input voltage
range of 2.3V to 6.0V and incorporates input
Undervoltage Lockout (UVLO) circuitry that keeps the
LDO output voltage off until the input voltage reaches a
minimum of 2.18V (typical) on the rising edge of the
input voltage. As the input voltage falls, the LDO output
will remain on until the input voltage level reaches
2.04V (typical).
Since the MCP1726 LDO Undervoltage Lockout
activates at 2.04V as the input voltage is falling, the
dropout voltage specification does not apply for output
voltages that are less than 1.9V.
For high-current applications, voltage drops across the
PCB traces must be taken into account. The trace
resistances can cause significant voltage drops
between the input voltage source and the LDO. For
applications with input voltages near 2.3V, these PCB
trace voltage drops can sometimes lower the input
voltage enough to trigger a shutdown due to
undervoltage lockout.
 2005-2014 Microchip Technology Inc.
MCP1726
4.9
Overtemperature Protection
The MCP1726 LDO has temperature-sensing circuitry
to prevent the junction temperature from exceeding
approximately 150°C. If the LDO junction temperature
does reach 150°C, the LDO output will be turned off
until the junction temperature cools to approximately
140°C, at which point the LDO output will automatically
resume normal operation. If the internal power
dissipation continues to be excessive, the device will
shut off again. The junction temperature of the die is a
function of power dissipation, ambient temperature
and package thermal resistance. See Section 5.0
“Application Circuits/Issues” for more information
on LDO power dissipation and junction temperature.
 2005-2014 Microchip Technology Inc.
DS20001936D-page 17
MCP1726
5.0
APPLICATION CIRCUITS/
ISSUES
5.1
Typical Application
In addition to the LDO pass element power dissipation,
there is power dissipation within the MCP1726 as a
result of quiescent or ground current. The power
dissipation as a result of the ground current can be
calculated using the following equation:
The MCP1726 is used for applications that require high
LDO output current and a power good output.
EQUATION 5-2:
P I  GND  = V IN  MAX   I VIN
MCP1726-2.5
VIN = 3.3V
1 VIN
C1
10 µF
2 VIN
3 SHDN
4 GND
On
VOUT = 2.5V @ 1A
VOUT 8
VOUT 7
CDELAY 6
R1
10 k
C2
10 µF
PWRGD 5
Off
C3
1000 pF
PWRGD
FIGURE 5-1:
5.1.1
Typical Application Circuit.
APPLICATION CONDITIONS
Package Type = 8-Lead 3x3 DFN
Input Voltage Range = 3.3V ± 10%
VIN maximum = 3.63V
VIN minimum = 2.97V
VOUT typical = 2.5V
IOUT = 1.0A maximum
5.2
5.2.1
Power Calculations
POWER DISSIPATION
The internal power dissipation within the MCP1726 is a
function of input voltage, output voltage, output current
and quiescent current. The following equation can be
used to calculate the internal power dissipation for the
LDO.
EQUATION 5-1:
PI(GND) = Power dissipation due to the quiescent
current of the LDO
VIN(MAX) = Maximum input voltage
IVIN = Current flowing in the VIN pin with no
LDO output current (LDO quiescent
current)
The total power dissipated within the MCP1726 is the
sum of the power dissipated in the LDO pass device
and the PI(GND) term. Because of the CMOS
construction, the typical IGND for the MCP1726 is
140 µA. Operating at a maximum of 3.63V results in a
power dissipation of 0.51 mW. For most applications,
this is small compared to the LDO pass device power
dissipation and can be neglected.
The maximum continuous operating junction
temperature specified for the MCP1726 is +125°C. To
estimate the internal junction temperature of the
MCP1726, the total internal power dissipation is
multiplied by the thermal resistance from junction to
ambient (RJA) of the device. The thermal resistance
from junction to ambient for the 3x3 DFN package is
estimated at 64°C/W.
EQUATION 5-3:
T J  MAX  = PTOTAL  R  JA + T A  MAX 
TJ(MAX) = Maximum continuous junction
temperature
PTOTAL = Total device power dissipation
RJA = Thermal resistance from
junction-to-ambient
TA(MAX) = Maximum ambient temperature
PLDO =  V IN  MAX   – V OUT  MIN    I OUT  MAX  
PLDO = LDO Pass device internal power
dissipation
VIN(MAX) = Maximum input voltage
VOUT(MIN) = LDO minimum output voltage
DS20001936D-page 18
 2005-2014 Microchip Technology Inc.
MCP1726
The maximum power dissipation capability for a
package
can
be
calculated
given
the
junction-to-ambient thermal resistance and the
maximum ambient temperature for the application. The
following equation can be used to determine the
package maximum internal power dissipation.
5.3
EQUATION 5-4:
5.3.1
P D  MAX 
 T J  MAX  – T A  MAX  
= --------------------------------------------------R  JA
PD(MAX) = Maximum device power dissipation
TJ(MAX) = Maximum continuous junction
temperature
TA(MAX) = Maximum ambient temperature
RJA = Thermal resistance from
junction-to-ambient
Typical Application
Internal power dissipation, junction temperature rise,
junction temperature and maximum power dissipation
are calculated in the following example. The power
dissipation as a result of ground current is small
enough to be neglected.
POWER DISSIPATION EXAMPLE
Package
Package Type = 3x3 DFN
Input Voltage
VIN = 3.3V ± 10%
LDO Output Voltage and Current
VOUT = 2.5V
IOUT = 1.0A
Maximum Ambient Temperature
EQUATION 5-5:
T J  RISE  = P D  MAX   R  JA
TA(MAX) = 70°C
Internal Power Dissipation
PLDO(MAX) = [VIN(MAX) – VOUT(MIN)] x IOUT(MAX)
TJ(RISE) = Rise in device junction temperature
over the ambient temperature
PLDO = [(3.3V x 1.1) – (0.975 x 2.5V)]
x 1.0A
PD(MAX) = Maximum device power dissipation
PLDO = 1.192W
RJA = Thermal resistance from
junction-to-ambient
EQUATION 5-6:
T J = T J  RISE  + T A
TJ = Junction temperature
TJ(RISE) = Rise in device junction temperature
over the ambient temperature
TA = Ambient temperature
Device Junction Temperature Rise
The internal junction temperature rise is a function of
internal power dissipation and the thermal resistance
from junction to ambient for the application. The
thermal resistance from junction to ambient (RJA) is
derived from an EIA/JEDEC standard for measuring
thermal resistance for small surface-mount packages.
The EIA/JEDEC specification is JESD51-7 “High
Effective Thermal Conductivity Test Board for Leaded
Surface-Mount Packages”. The standard describes the
test method and board specifications for measuring the
thermal resistance from junction to ambient. The actual
thermal resistance for a particular application can vary
depending on many factors, such as copper area and
thickness. Refer to AN792, “A Method to Determine
How Much Power a SOT23 Can Dissipate in an
Application” (DS00792), for more information regarding
this subject.
TJ(RISE) = PTOTAL x RJA
TJ(RISE) = 1.192W x 64.0°C/W
TJ(RISE) = 76.3°C
 2005-2014 Microchip Technology Inc.
DS20001936D-page 19
MCP1726
Junction Temperature Estimate
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below.
TJ = TJRISE + TA(MAX)
TJ = 76.3°C + 70.0°C
TJ = 146.3°C
As can be seen from the result, this application will be
operating above the maximum operating junction
temperature of 125°C. The PCB layout for this
application is very important, as it has a significant
impact on the junction-to-ambient thermal resistance
(RJA) of the 3x3 DFN package, which is very important
in this application.
Maximum Package Power Dissipation at
70°C Ambient Temperature
3x3 DFN (64°C/W RJA)
PD(MAX) = (125°C – 70°C)/64°C/W
PD(MAX) = 0.86W
8LD SOIC (163°C/W RJA)
PD(MAX) = (125°C – 70°C)/163°C/W
PD(MAX) = 0.337W
From this table you can see the difference in maximum
allowable power dissipation between the 3x3 DFN
package and the 8-pin SOIC package. This difference
is due to the exposed metal tab on the bottom of the
DFN package. The exposed tab of the DFN package
provides a very good thermal path from the die of the
LDO to the PCB. The PCB then acts like a heat sink,
providing more area to distribute the heat generated by
the LDO. When the PCB heat sink area is used, the
RJA should be replaced by RJC plus RHS, where
RHS is the PCB copper area heat sink thermal
resistance. This will allow for higher maximum power
dissipation compared to the free-air power dissipation
calculated using RJA.
DS20001936D-page 20
 2005-2014 Microchip Technology Inc.
MCP1726
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
8-Lead DFN (3x3x0.9 mm)
8-Lead SOIC (3.90 mm)
Example
Voltage
Option
Code
0.8V
CAAA
1.2V
CAAB
1.8V
CAAC
2.5V
CAAD
3.0V
CAAE
3.3V
CAAF
5.0V
CAAG
Adj
AADJ
CAAA
E438
256
Example
1726ADJE
3
SN e^^1438
256
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2005-2014 Microchip Technology Inc.
DS20001936D-page 21
MCP1726
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001936D-page 22
 2005-2014 Microchip Technology Inc.
MCP1726
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2005-2014 Microchip Technology Inc.
DS20001936D-page 23
MCP1726
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001936D-page 24
 2005-2014 Microchip Technology Inc.
MCP1726
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2005-2014 Microchip Technology Inc.
DS20001936D-page 25
MCP1726
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001936D-page 26
 2005-2014 Microchip Technology Inc.
MCP1726
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!+$
 2005-2014 Microchip Technology Inc.
DS20001936D-page 27
MCP1726
NOTES:
DS20001936D-page 28
 2005-2014 Microchip Technology Inc.
MCP1726
APPENDIX A:
REVISION HISTORY
Revision D (September 2014)
The following is the list of modifications:
1.
2.
3.
Corrected the typical output voltage tolerance in
the Features section to match the stated value
in the DC Characteristics table.
Corrected illustrations of package markings in
Section 6.0, Packaging Information.
Minor typographical changes.
Revision C (August 2007)
The following is the list of modifications:
1.
2.
3.
Added 3.0V option to Section 6.1, Package
Marking Information.
Updated package outline drawings.
Added 3.0V option to Product Identification
System (PIS) section.
Revision B (March 2005)
The following is the list of modifications:
1.
2.
Replaced 3x3 DFN package diagram.
Emphasized (bolded) a few specifications of
Section 1.0, Electrical Characteristics in the
DC Characteristics table.
Revision A (February 2005)
• Original Release of this Document.
 2005-2014 Microchip Technology Inc.
DS20001936D-page 29
MCP1726
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
-XXX
Device
Tape &
Reel
Voltage
Output
Device:
X
X
XX
Tolerance Temperature Package
Range
Examples:
a)
b)
MCP1726: 1A, Low Quiescent Current LDO Regulator
c)
Tape & Reel Option: T
= Tape and Reel
Blank = Tube
Standard Output
Voltage*:
080
120
180
250
300
330
500
ADJ
=
=
=
=
=
=
=
=
0.80V
1.20V
1.80V
2.50V
3.00V
3.30V
5.00V
Adjustable Voltage Version
* Custom output voltages available upon request. Contact your
local Microchip sales office for more information.
Tolerance:
2
= 2.0%
Temperature
Range:
E
= -40 to +125C
Package*:
SN = Plastic Small Outline – Narrow, 3.90 mm Body, 8-Lead
(SOIC)
MF = Plastic Dual Flat, No Lead Package – 3x3x0.9 mm Body,
8-Lead (DFN)
*Both packages are Lead Free
DS20001936D-page 30
d)
e)
f)
g)
h)
MCP1726-0802E/MF: 0.80V, 1A LDO, 8LD
DFN Package
MCP1726T-1202E/MF: Tape
and
Reel,
1.20V, 1A LDO, 8LD
DFN Package
MCP1726-3002E/MF: 3.00V, 1A LDO, 8LD
DFN Package
MCP1726T-3302E/MF: Tape
and
Reel,
3.30V, 1A LDO, 8LD
DFN Package
MCP1726-1802E/SN: 1.80V, 1A LDO, 8LD
SOIC Package
MCP1726T-2502E/SN: Tape
and
Reel,
2.50V, 1A LDO, 8LD
SOIC Package
MCP1726-5002E/SN: 5.00V, 1A LDO, 8LD
SOIC Package
MCP1726T-ADJE/SN: Tape
and
Reel,
Adjustable, 1A LDO,
8LD SOIC Package
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This identifier is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
 2005-2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2005-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-576-5
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2005-2014 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS20001936D-page 31
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Austin, TX
Tel: 512-257-3370
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
DS20001936D-page 32
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Germany - Dusseldorf
Tel: 49-2129-3766400
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Germany - Pforzheim
Tel: 49-7231-424750
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Italy - Venice
Tel: 39-049-7625286
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Poland - Warsaw
Tel: 48-22-3325737
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
03/25/14
 2005-2014 Microchip Technology Inc.