Application Information LC5550LD Series PWM and Quasi-Resonant Off-Line Switching Regulator ICs General Description LC5550LD series is a PWM and quasi-resonant topology non-isolated buck LED driver IC. It incorporates separate controller and power MOSFET chips, and is designed for input capacitorless applications. The controller adapts the average current control method for realizing high power factors. The rich set of protection features helps to realize low component counts, and high performance-to-cost power supply. Features and Benefits Figure 1. The LC5550LD series package is a fully molded DIP8, with pin 7 removed for greater isolation. (Image not to scale.) • PWM and quasi-resonant topology • Integrated on-time control circuit (it realizes high power factor by average current control) • Integrated soft-start circuit (reduces power stress during start-up on the incorporated power MOSFET and output rectifier) • Integrated bias assist circuit (improves startup performance, suppresses VCC voltage droop during operation, and allows use of low-rated ceramic capacitor on VCC pin) • Integrated Leading Edge Blanking (LEB) circuit • Integrated maximum on-time limit circuit • Protection features: ▫ Overcurrent protection (OCP): pulse-by-pulse ▫ Overvoltage protection (OVP): latched shutdown ▫ Overload protection (OLP): latched shutdown ▫ Thermal shutdown (TSD): latched shutdown Applications • LED lighting fixtures • LED light bulbs The product lineup for the LC5550LD series provides the following options: POUT* (W) Part Number MOSFET VDSS(min) (V) RDS(on) (max) (Ω) PWM Operation Frequency, fOSC(typ) (kHz) On-Time tON(MAX)(typ) (μs) 230 VAC Universal LC5555LD 650 3.95 72 9.3 13 10 LC5556LD 650 1.9 60 11.2 20 16 *Based on the thermal rating; the allowable maximum output power can be up to 120% to 140% of this value. However, maximum output power may be limited in such an application with low output voltage or short duty cycle. LC5550LD-AN, Rev. 1.2 SANKEN ELECTRIC CO., LTD. Functional Block Diagram VCC ② Control Part ⑧ D/ST START UP TSD UVLO Reg Drv Bias OVP ① S/GND S RQ OCP/BD ③ ⑥ ISENSE Bottom Detection OCP OSC OLP OTA LEB Reg Feedback Control NF ⑤ ④ COMP Reg Pin List Table Number Name 1 S/GND 2 VCC 8 D/ST 3 OCP/BD 6 ISENSE 4 COMP 5 NF 6 ISENSE 7 – 8 D/ST Pin-out Diagram S/GND 1 VCC 2 OCP/BD 3 5 NF COMP 4 Function MOSFET source and GND pin for the Control Part Supply voltage input and Overvoltage Protection (OVP) signal input Overcurrent Protection (OCP), quasi-resonant signal input, and Overvoltage Protection (OVP) signal input Feedback phase-compensation input No function; must be externally connected to S/GND pin with as short a trace as possible, for stable operation of the IC Output current sensing voltage input Pin removed MOSFET drain pin and input of the startup current Table of Contents General Specifications 1 Package Diagram Electrical Characteristics Typical Application Circuits 3 4 6 Functional Description 7 Startup Operation Startup Period Undervoltage Lockout (UVLO) Circuit Bias Assist Function Soft Start Function Operational Mode at Startup Normal Operation On-Time Control Operation PWM Control 7 7 7 8 9 9 10 10 11 Quasi-Resonant Operation Bottom-On Timing Protection Functions Overvoltage Protection (OVP) VCC Pin Overvoltage Protection OCP/BD Pin Overvoltage Protection Overload Protection (OLP) Overcurrent Protection (OCP) Thermal Shutdown Protection Maximum On-Time Limiting Function Design Considerations LC5550LD-AN, Rev. 1.2 SANKEN ELECTRIC CO., LTD. 12 13 14 14 14 15 16 17 17 18 18 2 Package Diagram DIP8 package 9.4 ±0.3 5 1 4 6.5 ±0.2 8 1.0 +0.3 -0.05 +0.3 1.52 -0.05 3.3 ±0.2 7.5 ±0.5 4.2 ±0.3 3.4 ±0.1 (7.6 TYP) 0.2 5 + 0. - 0.01 5 ０～１５° ０～１５° 2.54 TYP 0.89 TYP 0.5 ±0.1 Unit： mm 8 LC555x SK YMD L Part Number Lot Number Y is the last digit of the year (0 to 9) M is the month (1 to 9, O, N, or D) D is a period of days (1 to 3): 1 – 1st to 10th 2 – 11th to 20th 3 – 21st to 31st Sanken Control Number 1 Pb-free. Device composition compliant with the RoHS directive. LC5550LD-AN, Rev. 1.2 SANKEN ELECTRIC CO., LTD. 3 Electrical Characteristics • This section provides electrical characteristic data for each product. • The polarity value for current specifies a sink as "+ ," and a source as “−,” referencing the IC. • Please refer to the datasheet of each product for additional details. Absolute Maximum Ratings Unless specifically noted, TA is 25°C Characteristic Drain Current Symbol IDPEAK Notes Pins Rating Unit A LC5555LD Single pulse 8–1 2.5 LC5556LD Single pulse 8–1 4.0 A LC5555LD ILPEAK = 2.0 A, VDD = 99 V, L = 20 mH 8–1 47 mJ LC5556LD ILPEAK = 2.7 A, VDD = 99 V, L = 20 mH Single Pulse Avalanche Energy EAS 8–1 86 mJ Input Voltage for Control Part (MIC) VCC 2–1 35 V OCP/BD Pin Voltage VOCP 3–1 −2.0 to 5.0 V COMP Pin Voltage VCOMP 4–1 −0.3 to 7.0 V ISENSE Pin Voltage VSEN 6–1 −0.3 to 5.0 V Allowable Power Dissipation of MOSFET PD1 8–1 0.97 W Operating Ambient Temperature TOP ― −55 to 125 °C Storage Temperature Tstg ― −55 to 125 °C Channel Temperature Tch ― 150 °C Mounted on a 15 mm × 15 mm PCB LC5550LD Electrical Characteristics of MOSFET Unless specifically noted, TA is 25°C Characteristic Symbol Test Conditions Pins Min. Typ. Max. Unit Drain-to-Source Breakdown Voltage VDSS 8–1 650 ― ― V Drain Leakage Current IDSS 8–1 ― ― 300 μA ― ― 3.95 Ω ― ― 1.9 Ω On-Resistance RDS(on) Switching Time tf Thermal Resistance* Rθch-c LC5555LD LC5556LD LC5555LD LC5556LD LC5555LD LC5556LD 8–1 8–1 ― ― ― 250 ns ― ― 400 ns ― ― 42 °C/W ― ― 35.5 °C/W *The thermal resistance between the channels of the MOSFET and the case. TC measured at the center of the case top surface. LC5550LD-AN, Rev. 1.2 SANKEN ELECTRIC CO., LTD. 4 Electrical Characteristics of Control Part (MIC) Unless specifically noted, TA is 25°C, VCC is 20 V Characteristic Symbol Test Conditions Pins Min. Typ. Max. Unit Power Supply Startup Operation Operation Start Voltage VCC(ON) 2–1 13.8 15.1 17.3 V Operation Stop Voltage* VCC(OFF) 2–1 8.4 9.4 10.7 V ICC(ON) 2–1 – – 4.7 mA VSTARTUP 8–1 18 21 24 V 2–1 −8.5 −4.0 −1.5 mA 2–1 9.5 11.0 12.5 V 60 72 84 kHz Circuit Current in Operation Startup Circuit Operation Voltage Startup Current Startup Current Threshold Biasing Voltage* ICC(STARTUP) VCC = 13 V VCC(BIAS) Normal Operation PWM Operation Frequency Maximum On-Time COMP Pin Control Minimum Voltage Error Amplifier Reference Voltage LC5555LD fOSC LC5556LD LC5555LD tON(MAX) LC5556LD 8–1 8–1 50 60 70 kHz 8.0 9.3 11.2 μs 9.0 11.2 13.4 μs VCOMP(MIN) 4–1 0.30 0.55 0.80 V VSEN(TH) 6–1 –0.21 –0.2 –0.19 V ISEN(SOURCE) 4–1 −36 −24 −12 μA Error Amplifier Sink Current ISEN(SINK) 4–1 12 24 36 μA Error Amplifier Source Current Leading Edge Blanking Time tON(LEB) 3–1 − 600 − ns Quasi-Resonant Operation Threshold Voltage-1 VBD(TH1) 3–1 0.14 0.24 0.34 V Quasi-Resonant Operation Threshold Voltage-2 VBD(TH2) 3–1 0.11 0.16 0.21 V VOCP(TH) 3–1 −0.92 −0.8 −0.68 V IOCP 3–1 −120 −40 −10 μA OCP/BD Pin Overvoltage Protection (OVP) Operation Voltage VBD(OVP) 3–1 2.2 2.6 3.0 V Overload Protection (OLP) Threshold Voltage VCOMP(OLP) 4–1 4.1 4.5 4.9 V VCC(OVP) 2–1 28.5 31.5 34.0 V TJ(TSD) – 135 – – °C Protected Operation OCP/BD Pin Overcurrent Protection (OCP) Threshold Voltage OCP/BD Pin Source Current VCC Pin OVP Threshold Voltage Thermal Shutdown Activating Temperature *VCC(BIAS) > VCC(OFF) always. LC5550LD-AN, Rev. 1.2 SANKEN ELECTRIC CO., LTD. 5 Typical Application Circuits The LC5550LD series is a non-isolated buck LED driver IC which can be used with both PWM control and quasi-resonant control. Figure 1 shows a circuit example with PWM control. Details are described in the PWM Operation section. D8, R7, and C8 in the figure) is added to PWM circuit. When the output voltage rises, the OCP/BD pin voltage will also rise, and when the quasi-resonant signal of the positive voltage on the OCP/BD pin reaches VBD(TH1) = 0.24 V or more, the quasiresonant operation will begin. Details are described in the QuasiResonant Operation section. Figure 2 shows a circuit example with quasi-resonant control. In a quasi-resonant circuit configuration, a delay circuit (D7, R1 D6 R2 U1 NF 5 LC5550LD Contro1 6 ISENSE D3 D4 D/ST 8 V AC COMP 4 3 OCP/BD 2 1 VCC C3 S/GND C4 C5 R5 C6 C2 R3 D2 D1 L1 R4 CV C1 C7 R6 LED D5 Figure 1. Typical application circuit 1, PWM control R1 D6 R2 U1 5 6 ISENSE D3 D4 D1 D2 LC5550LD Contro1 NF D/ST 8 V AC COMP 4 D7 3 OCP/BD 2 1 VCC C3 S/GND C4 C5 R5 C6 C8 C2 R3 C1 R7 D8 R4 L1 CV C7 R6 LED D5 Figure 2. Typical application circuit 2, Quasi-resonant control LC5550LD-AN, Rev. 1.2 SANKEN ELECTRIC CO., LTD. 6 Functional Description All of the parameter values used in these descriptions are typical values, according to the LC5555LD specification, unless they are specified as minimum or maximum. With regard to current direction, "+" indicates sink current (toward the IC) and "–" indicates source current (from the IC). Startup Operation Startup Period Figure 3 shows the VCC pin peripheral circuit. The VCC pin voltage can be supplied from VO in buck-converter configuration. The built-in startup circuit is connected to the D/ST pin, and it generates a constant current, ICC(STARTUP) = –4.0 mA to charge capacitor C2 connected to the VCC pin. During this process, when the VCC pin voltage reaches VCC(ON) = 15.1V, the Control Part (MIC) starts operation. After that, the startup circuit stops automatically, in order to eliminate its own power consumption. The startup time is determined by the C2 capacitance. A ceramic or film capacitor can be used for C2, and a value of 0.22 to 22 μF is generally recommended. The approximate value of the startup time can be calculated using the following formula: tSTART z C2 × VCC(ON) – VCC(INT) where: (1) |ICC(STARTUP)| Contro1 LC 5550LD D3 D4 D1 D2 D/ST V AC 2 R1 VCC D6 C2 8 1 S/GND R3 R4 L1 D5 C1 VO Figure 3. D/ST and VCC pin peripheral circuits ICC ICC(ON) (max) = 4.7mA Undervoltage Lockout (UVLO) Circuit Figure 4 shows the relation of the VCC pin voltage to the circuit current, ICC . When the VCC pin voltage reaches the Operation Start Voltage, VCC(ON) = 15.1 V, the Control Part (MIC) starts operation and the circuit current increases. In operation, when the VCC pin voltage decreases to VCC(OFF) = 9.4 V, the Control Part stops operation by UVLO circuit, and reverts to the state before startup. Stop VCC(INT) is the initial voltage of the VCC pin in V. Start tSTART is the startup time in s, and 9.4 V VCC(OFF) 15.1 V VCC pin voltage VCC(ON) Figure 4. VCC versus ICC LC5550LD-AN, Rev. 1.2 SANKEN ELECTRIC CO., LTD. 7 The VCC pin voltage must be set within the specifications of the input voltage range and the output load range of the power supply, according to the following formula. The optimal value is around 20 V. VCC(BIAS)(max) < VCC < VCC(OVP)(min) 12.5 (V) < VCC < 28.5 (V) (2) When the VO is in the range shown in the above formula, within the specifications of the input voltage range, and the output load range of the power supply, the VCC pin voltage can be supplied from VO ( figure 3 ). In the case where VCC is higher than VCC(OVP)(min) , the Zener diode D7 is inserted, to supply VCC pin voltage (figure 5). When the increasing power consumption of the Zener diode is not negligible (VCC is higher than VCC(OVP)(min)), or VCC is lower than VCC(BIAS)(max), the transformer (T1) is used to supply the VCC pin voltage (figure 6). Bias Assist Function Figure 7 shows the VCC pin voltage behavior during the startup period. If VCC pin voltage decreases enough to reach the Startup Current Threshold Biasing Voltage, VCC(BIAS) = 11.0 V, the Bias Assist function is activated before the voltage decreases to VCC(OFF) = 9.4 V. While the Bias Assist function is operating, any decrease of the VCC pin voltage is counteracted by a supplementary current from the Startup circuit, and thus VCC is kept almost constant. Because of the Bias Assist function, the use of a low-value capacitor for C2 (see figure 3) is allowed. Also, because the increase of VCC pin voltage becomes faster when the output runs with excess voltage, the response time of the OVP function can also be shortened. It is necessary to check and adjust the startup process in the application, so that poor starting conditions may be avoided. LC5550LD D/ST 8 D6 R1 VCC 2 D7 Contro1 Contro1 LC5550LD C2 1 D/ST S/GND R3 8 C2 1 S/GND R3 D5 L1 R4 D5 Figure 5. VCC pin peripheral circuits (VCC > VCC(OVP)(min)) VCC pin voltage D6 R1 VCC 2 R4 T1 Figure 6. VCC pin peripheral circuits (VCC > VCC(OVP)(min)) IC startup Startup success Target Operating Voltage Increasing by output voltage rising Bias Assist period VCC(ON) = 15.1 V VCC(BIAS) = 11.0 V VCC(OFF) = 9.4 V Startup failure Time Figure 7. VCC during startup period LC5550LD-AN, Rev. 1.2 SANKEN ELECTRIC CO., LTD. 8 Soft Start Function Operational Mode at Startup Figure 8 shows the operation mode at startup. After the startup period, when the COMP pin voltage reaches VCOMP(MIN) = 0.55 V, the switching operation begins in PWM operation at an operation frequency of fOSC = 72 kHz (for LC5555LD, 60 kHz for LC5556LD). Figure 8 shows the operation waveform at startup. The soft start operation begins when the COMP pin voltage reaches VCOMP(MIN) = 0.55 V, and lasts until the output current becomes constant. During this period, check the items below: • Ensure the VCC pin voltage does not drop to the Operation Stop Voltage, VCC(OFF). • Ensure the output current reaches the target value before the Overload Protection (OLP) function is activated by the COMP pin voltage reaching VCOMP(OLP) = 4.5 V. Then, when the output voltage rises, the auxiliary winding voltage will also rise, and when the quasi-resonant signal of the positive voltage on the OCP/BD pin reaches VBD(TH1) = 0.24 V or more, the quasi-resonant operation will begin. Figure 9 shows the OCP/BD pin voltage waveform expanded time scale at point A of figure 8. Soft-Start Period COMP Pin Voltage IC Startup VCOMP(MIN) = 0.55 V S/GND VCC Pin Voltage VCC(BIAS) = 11.0 V S/GND Constant Current Control Output (LED) Current, IOUT Target Current GND (IOUT) PWM operation Quasi-resonant (QR) operation Drain Current, ID S/GND A Time Figure 8. Soft-start operation waveforms at startup PWM operation Quasi-resonant (QR) operation VBD(TH1) OCP/BD Pin Voltage Drain Current, ID S/GND time GND(ID) time Figure 9. OCP/BD Pin Voltage (with time scale expanded at point A of figure 8) LC5550LD-AN, Rev. 1.2 SANKEN ELECTRIC CO., LTD. 9 Normal Operation On-Time Control Operation Figure 10 shows the peripheral circuit at the COMP pin, and figure 11 shows the on-time control. The output control is done by voltage mode control, which controls on-time depending on output load, and average current control. As shown in figure 11, in the average current control operation, the internal error amplifier reference voltage VSEN(TH) = –0.2 V is compared with the voltage drop of secondary side constant current detection resistance in the OTA circuit, and is equalized with the COMP pin. This averaged voltage at the COMP pin is compared with the internal oscillator (OSC) output by the internal FB comparator, and the on-time is controlled. Here, the internal OSC indicates the oscillator circuit, which controls the PWM operation frequency, quasi-resonant oscillation, and the maximum on-time limit. The recommended value of capacitor C4 linked to the COMP pin is approximately 1.0 to 4.7 μF. The value of R2 is 100 to 220 Ω. R2 and C5 are the filter for ISENSE pin. In the case where R2 value is large, ISENSE current (–40 μA) affects the accuracy of the LED current. Thus R2 and C5 values are recommended to be approximately 220 Ω and approximately 0.1 μF, respectively. The constant output current control of the output is done as below: LC5550LD COMP 4 C4 3 R5 S/GND ROCP 1 Figure 10. COMP pin peripheral circuit LC5550LD OSC - COMP voltage 4 FB + COMP C4 ISENSE 6 + OTA • When the output load current becomes less than the target value, the ISENSE pin voltage becomes low. This causes the averaged OTA circuit output voltage at the COMP pin to become high, and the on-time and the output current increase. • When the output current becomes greater than the target value, the circuits operate in the opposite way. The averaged voltage at the COMP pin becomes low, and the on-time and the output current decrease. Figure 12 shows the average input current waveform. The averaged COMP pin voltage becomes constant, and the duty cycle control becomes based on the EIN voltage (C1 voltage in figure 3). It makes an averaged input current sine waveform which realizes a high power factor. D7 OCP/BD - S/GND R2 C5 1 Constant current Detection resistor FB - LED OSC + COMP Voltage Gate on-time Drain current Figure 11. On-time control COMP pin voltage S/GND EIN Drain current Averaged input current Figure 12. Averaged input current waveform LC5550LD-AN, Rev. 1.2 SANKEN ELECTRIC CO., LTD. 10 PWM Control Figure 13 shows the waveforms and figure 14 shows the output current path in PWM operation, respectively. The basic current control of internal PWM is described in the following section, the on-time of the MOSFET is controlled using VISENSE . When VISENSE is equal to the internal PWM reference voltage, the internal power MOSFET turns off. PWM On-Time Period At startup, or during normal operation PWM Off-Time Period When the internal power MOSFET turns before the output current through the LED string reaches the target current level, the internal power MOSFET turns on and the output current flows through the ION path shown in figure 14. off, the current recirculation diode, D5, is forward biased by the back electromotive force (BEMF) in the inductor, L1, and D5 turns on. Then the energy stored in L1 during the PWM on-time flows through the recirculation path shown as IOFF in figure 14. Turing-Off Period The output current through the LED string is equivalent to the current through the detection resistors, R3 and R4. Thus the LED current is detected at the ISENSE pin as a voltage, VISENSE . As described in the On-Time Control Operation LED Current ILED Ԙ ԙ Ԛ ԛ I ON IOFF ION IOFF Turning-On Period After the PWM operation cycle (T = 1 / fOSC), the internal power MOSFET turns-on again, and the PWM on-time period repeats. LC5550LD Control V ISENSE R3 S/GND D/ST VISENSE ISENSE MOSFET D5 MOSFET L1 R4 ON OFF 1/f osc OFF ON IOFF V LED ION 1/f osc Figure 13. Constant current control operation in a buck configuration Figure 14. Output current flow in a buck configuration during PWM on-time and off-time periods LC5550LD-AN, Rev. 1.2 SANKEN ELECTRIC CO., LTD. 11 Quasi-Resonant Operation Figure 15 shows the circuit of quasi-resonant topology. The buck converter is a system which transfers the energy stored in the choke coil, L1, to the output when the power MOSFET is turned off. The MOSFET drain node begins free oscillation based on the inductance, L, of the choke coil, L1, and CV across the drain and source pins. The quasi-resonant operation is the VDS bottom-on operation that turns-on the MOSFET at the bottom point of VDS free oscillation. t ONDLY Ef VDS EIN Bottom Point I OFF Figure 16 shows an ideal VDS waveform during bottom-on operation. Using bottom-on operation, switching loss and switching noise are reduced and it is possible to obtain converters with high efficiency and low noise. ID tON Half cycle of free oscillation, tONDLY ≈ √ L P × CV Figure 16. Ideal bottom-on operation waveform (MOSFET turn-on at a bottom point of a VDS waveform) D6 R1 LC5550LD D7 OCP/BD 3 C6 VCC 2 R5 D8 R7 C8 C4 8 D/ST S/GND 1 R3 R4 D5 CV L1 R6 Figure 15. OCP/BD pin peripheral circuit LC5550LD-AN, Rev. 1.2 SANKEN ELECTRIC CO., LTD. 12 Bottom-On Timing During the turning-off of the power MOSFET, the output voltage is fed through the delay circuit (D7, D8, R7, and C8 of figure 15) to the OCP/BD pin, and a positive voltage quasi-resonant signal is provided to the OCP/BD pin (the quasi-resonant signal is VBD ). After the power MOSFET turns off, the quasi-resonant signal immediately goes up and it exceeds the Quasi-Resonant Operation Threshold Voltage 1, VBD(TH1) = 0.24 V. After this occurs, the power MOSFET remains off until the quasi-resonant signal comes down enough to cross the Quasi-Resonant Operation Threshold Voltage 2, VBD(TH2) = 0.16 V. Then the power MOSFET again turns on. In addition, at this point, the threshold voltage goes up to VBD(TH1) automatically, to prevent malfunction of the quasi-resonant operation from noise interference. Figure 17 defines the pulse width of the quasi-resonant signal. For initiating quasi-resonant operation, the quasi-resonant signal pulse width between the two points VBD(TH1) and VBD(TH2) , tQR , must be equal to 1.2 μs or more. This pulse width must be ensured, while at the same time the OCP/BD pin peak voltage, VBD(PK) , is recommended to be between 1.5 and 2.0 V. Both conditions should be satisfied throughout the power supply input and output ranges, and covering variations in R5 and R7 actual component values. R5 and C6 Setup R5 is recommended to be between 100 and 330 Ω, and C6 to be between 100 and 470 pF. R7 Setup R7 must set the range for the quasi-resonant signal: either greater than or equal to VBD(TH1) (under input and output conditions where VCC becomes lowest), or less than the OCP/BD Pin Overvoltage Protection (OVP) Threshold Voltage, VBD(OVP) = 2.6 V (under conditions where VCC becomes highest). The formula below is used to calculate R7, ignoring the value of ROCP assuming ROCP << R5: R3 × (VCC – VBD(PK) – 2 ×Vf ) (2) VBD(PK) given R5 = 220 Ω, VBD(PK) = 1.5 V, VCC = 16 V, and the Vf of D7 and D8 = 0.8 V. R7 is approximately 1.89 kΩ, and it is 1.8 kΩ in the E12 series. R7 = If the pulse width is not satisfied, increase R5 or decrease R7, in order to raise VBD(PK) . Alternatively, increasing the capacitance of resonant capacitor CV is also effective because it widens the free oscillation period. However, it causes an additional switching loss increase; therefore, ensure the IC temperature rise is acceptable. D7 and D8 Setup D7 and D8 are fast recovery and low coupling capacitance diodes. C8 Setup The delay time, tONDLY , after which the power MOSFET turns on, is adjusted by the value of C8 , so that the power MOSFET turns on at the bottom-on of VDS. To do so, observe the power MOSFET drain voltage, VDS, the drain currnet, ID, and the quasi-resonant signal, under the maximum input voltage and the maximum output power. The following show how to adjust the turn-on point: • If the turn-on point precedes the bottom of the VDS signal, it causes higher switching losses. In that situation, after confirming the initial turn-on point, delay the turn-on point by increasing the C8 value gradually, so that the turn-on will match the bottom point of VDS. • In the converse situation, if the turn-on point lags behind the VDS bottom point, it causes higher switching losses also. After confirming the initial turn-on point, advance the turn-on point by decreasing the C8 value gradually, so that the turn-on will match the bottom point of VDS . An initial reference value for C8 is about 1000 pF. VBD(PK), 1.5 to 2.0 V recommended, but less than 2.6 V V BD(TH1) = 0.34 V (max) V BD(TH2 ) = 0.21 V (max) S/GND Pulse width, t QR ≥ 1.2 μs Figure 17. Definition of the pulse width of the quasi-resonant signal LC5550LD-AN, Rev. 1.2 SANKEN ELECTRIC CO., LTD. 13 Protection Functions Overvoltage Protection (OVP) The IC has two OVP activation methods: linked to the VCC pin and to the OCP/BD pin. Both methods are latched. After the switching operation stops, the VCC pin voltage will begin to decrease, and when it falls to VCC(BIAS) = 11.0 V, the Bias Assist Function will be activated. When the Bias Assist Function is activated, the startup current is supplied to the VCC pin in order to prevent the VCC pin voltage from decreasing to VCC(OFF) = 9.4 V, and thus the latched state is maintained. Releasing the latched state is done by turning off the input voltage and allowing the VCC pin voltage to drop below VCC(OFF) . Vcc AC mains off V CC(OFF)= 9.4V Vo VO(MAX) = 0.7mA × R6 VOUT(OVP) COMP pin voltage VCOMP(MIN)= 0.55V Drain current In the cases represented by the typical application circuit (figures 1 and 2), the output voltage VOUT(OVP) is approximately 31.5 V. When the output voltage is higher than the VCC operation range, Zener diode D9 is necessary, as shown in figure 19. The output voltage is approximately 31.5 V + VZENER , in this configuration. ID Time Figure 18. Waveforms when VCC pin OVP function is being activated R1 D9 D6 LC5550LD D7 OCP/BD 3 C6 2 Latch release V CC(BIAS)= 11.0V VCC Pin Overvoltage Protection Figure 18 shows the waveforms of the OVP function on the VCC pin. When the VCC pin voltage with reference to the S/GND pin reaches VCC(OVP) = 31.5 V or more, VCC pin OVP is activated and the IC stops switching operation, in latch mode. Because VCC pin voltage is proportional to the output voltage, it can be used to detect an output overvoltage event. VCC Latched shutdown V CC(OVP)= 31.5V R5 D8 R7 C8 C4 D/ST S/GND 8 1 R3 CV R4 L1 D5 Figure 19. Circuit example in the case where the output voltage is higher than the VCC operation range LC5550LD-AN, Rev. 1.2 SANKEN ELECTRIC CO., LTD. 14 When the VCC pin OVP function is being activated, the VCC pin voltage is maintained by the current from the startup circuit of the IC. Thus the latch operation continues. The current charges the output capacitor. Thus the output voltage rises. When the D/ST pin voltage with reference to the S/GND pin drops below the Startup Circuit Operation Voltage, VSTARTUP , the VCC pin voltage decreases and the latched is released. In order to continue the latch operation, the D/ST pin voltage must be above VSTARTUP . The resistor (R6 in figures 1 and 2) is necessary, placed in parallel to the output capacitor. The maximum output voltage in latch operation is approximately VO(max) ≈ 0.7 mA × R6. The optimal value of R6 should be determined with consideration of the latch operation, the maximum output voltage, and the effect on LED current in normal operation. Releasing the latched state is done by turning off the input voltage and allowing the VCC pin voltage to drop below VCC(OFF) . OCP/BD Pin Overvoltage Protection Figure 20 shows the OCP/BD pin OVP circuit. The OCP/BD pin OVP function is activated when diode D10 is added between OCP/BD pin and VCC pin in a quasi-resonant circuit configuration. Figure 21 shows the waveform of the OCP/BD pin OVP function. When the OCP/BD pin voltage with reference to the S/GND pin reaches VBD(OVP) = 2.6 V or more, OCP/BD pin OVP is activated and the IC stops switching operation, in latch mode. This input voltage must be less than the absolute maximum rating, 5 V. Releasing the latched state is done by turning off the input voltage and allowing the VCC pin voltage to drop below VCC(OFF) . R1 LC5550LD D7 OCP/BD 3 VCC D9 D6 C6 2 R5 D8 R7 C8 C4 D/ST S/GND 8 1 R3 CV R4 L1 D5 Figure 20. OCP/BD pin OVP circuit VCC pin voltage AC mains off Latch release V CC(BIAS)= 11.0V OCP/BD pin voltage V CC(OFF)= 9.4V Latched shutdown VBD(OVP )= 2.6V Drain current ID Figure 21. Waveforms when OCP/BD pin OVP function is being activated LC5550LD-AN, Rev. 1.2 SANKEN ELECTRIC CO., LTD. 15 Overload Protection (OLP) In the overload protection (OLP) state, the peak drain current is limited by OCP operation under an overload condition. Figures 22 and 23 show the peripheral circuit of the COMP pin and waveforms when OLP function is being activated, respectively. In an overload condition, the VCC pin voltage drops because the output voltage drops. When the VCC pin voltage reaches the Startup Current Threshold Biasing Voltage, VCC(BIAS) = 11.0 V, the Bias Assist Function is activated to avoid the VCC pin voltage from decreasing. Simultaneously, the ISENSE pin voltage decreases. Because the OTA circuit output inside the IC will be lost if the ISENSE pin voltage falls to the error amplifier reference voltage, VSEN(TH) = –0.2 V, the C4 capacitor, connected to the COMP pin, is charged by the current generator inside the COMP pin. When the COMP pin voltage reaches the OLP Threshold Voltage, VCOMP(OLP) = 4.5 V, the overload protection circuit will operate and stop switching operation, in latch mode. Releasing the latched state is done by turning off the input voltage and allowing the VCC pin voltage to drop below VCC(OFF). If the OLP function is activated at transient conditions such as startup, it may cause startup failure. In order to avoid this, a C4 value of 1 to 4.7 μF is generally recommended. Too determine the optimal value, it is necessary to check and adjust in the application LC5550LD 7V Reg 3 6 D/ST 8 OTA 1 COMP C4 ISEN S/GND R3 L1 R4 D5 Figure 22. COMP pin peripheral circuit VCC pin voltage V CC(BIAS)1= 11.0V COMP pin voltage AC mains off Latch release V CC(OFF)= 9.4V Latched shutdown V COMP(OLP )= 4.5V Drain current ID Figure 23. Waveforms when OLP function is being activated LC5550LD-AN, Rev. 1.2 SANKEN ELECTRIC CO., LTD. 16 Overcurrent Protection (OCP) The Overcurrent Protection (OCP) feature monitors the power MOSFET drain current on a pulse-by-pulse basis, in order to limit output power. The drain current of the power MOSFET is detected by the current detection resistor, R3, placed between the OCP/BD pin and the S/GND pin, as shown in figure 24. The voltage across R3, VR3 , is fed through R5 to the OCP/BD pin, to be detected by it. The turn-off point for the power MOSFET can be determined as that point where VR3 reaches the value of the following equation: VR3 = – |VOCP | + R5 (3) |IOCP | where VOCP: OCP threshold voltage (−0.8 V), R5: R5 resistance, and IOCP: OCP/BD pin source current (−40 μA). • R5 setup. In order to minimize effects of variation in the internal resistor, R5 is recommended to have a value from 100 to 330 Ω. + 3 The surge current pulse width must be less than tON(LEB) as shown in figure 25. In case its width is longer than that, try these measures: Thermal Shutdown Protection Thermal Shutdown protection is activated when the temperature of the Control Part (MIC) in the IC reaches TJ(TSD) = 135°C(min), and then the IC stops switching operation, in latch mode. Releasing the latched state is done by turning off the input voltage and allowing the VCC pin voltage to drop below VCC(OFF). tON(LEB ) OCP/BD OCP detection period S/GND -0.6V Reg LOGIC DRIVE R5 C6 D/ST Because the OCP function detects a peak current, it can react to the surge voltage at the power MOSFET turn-on edge and thus the power MOSFET might turn off. In order to avoid this, the Leading Edge Blanking Time is built-in. The Leading Edge Blanking Time, tON(LEB), is set to 600 ns. • adjust the turn-on point to the VDS bottom point • reduce the voltage resonant capacitor CV capacitance A filter is inserted at the OCP/BD pin in order to prevent malfunction: LC5550LD • C6 setup. C6 is recommended to have a value from 100 to 470 pF, with good temperature characteristics. Selecting larger capacitances for C6 would cause OCP response to become slow, and then it would result in an increase in the peak drain current at transient conditions, such as startup. 8 1 VROCP S/GND R3 R4 L1 D5 Surge pulse voltage width at turning on CV Figure 24. OCP/BD pin peripheral circuit Figure 25. OCP/BD pin voltage (converted from MOSFET drain current by R3) LC5550LD-AN, Rev. 1.2 SANKEN ELECTRIC CO., LTD. 17 Maximum On-Time Limiting Function The maximum on-time, set at tON(MAX) = 9.3 μs (for the LC5555LD, 11.2 μs for LC5556LD), limits lower side operation frequency (see figure 26), at low AC input voltage on or off. Ensure that the actual on-time at the minimum AC input and the maximum load condition does not reach tON(MAX). Design Considerations Output Load (LEDs) The relation between the LED ratings and the output current ratings of the IC should be considered. In buck configuration, the total forward voltage drop, VLED , of the LEDs in series, should be less than the input voltage, VAC , because the LEDs would be turned off if VLED were more than VAC . Normally, a VLED of 9 to 60 V is assumed. ID Drain Current Free-Wheeling Diode (D5) This is a free-wheeling diode for recirculation of the output current. The energy stored during the PWM on-time period is provided to LEDs through this diode during the off-time period. The withstand voltage and recovery time, trr , should be considered. If a diode with a long recovery time, trr , is selected, surge current may flow through IC when the internal power MOSFET turns on. As a result, it would cause increased noise, potentially malfunction due to the noise, and decreased efficiency. Thus, it is recommended to select a diode which has a trr of approximately 30 ns, or a diode with a lower trr . Current Detection Resistor (R3) Choose a low equivalent series inductance and high surge tolerant type for the current detection resistor. If a high inductance type is used, it may cause malfunctioning because of the high frequency current running through it. Maximum On-Time time V DS Voltage between drain and source time Figure 26. Confirmation of Maximum On-Time LC5550LD-AN, Rev. 1.2 SANKEN ELECTRIC CO., LTD. 18 • The contents in this document are subject to changes, for improvement and other purposes, without notice. Make sure that this is the latest revision of the document before use. • Application and operation examples described in this document are quoted for the sole purpose of reference for the use of the products herein and Sanken can assume no responsibility for any infringement of industrial property rights, intellectual property rights or any other rights of Sanken or any third party which may result from its use. • Although Sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and defect of semiconductor products at a certain rate is inevitable. Users of Sanken products are requested to take, at their own risk, preventative measures including safety design of the equipment or systems against any possible injury, death, fires or damages to the society due to device failure or malfunction. • Sanken products listed in this document are designed and intended for the use as components in general purpose electronic equipment or apparatus (home appliances, office equipment, telecommunication equipment, measuring equipment, etc.). When considering the use of Sanken products in the applications where higher reliability is required (transportation equipment and its control systems, traffic signal control systems or equipment, fire/crime alarm systems, various safety devices, etc.), and whenever long life expectancy is required even in general purpose electronic equipment or apparatus, please contact your nearest Sanken sales representative to discuss, prior to the use of the products herein. The use of Sanken products without the written consent of Sanken in the applications where extremely high reliability is required (aerospace equipment, nuclear power control systems, life support systems, etc.) is strictly prohibited. • In the case that you use Sanken products or design your products by using Sanken products, the reliability largely depends on the degree of derating to be made to the rated values. Derating may be interpreted as a case that an operation range is set by derating the load from each rated value or surge voltage or noise is considered for derating in order to assure or improve the reliability. In general, derating factors include electric stresses such as electric voltage, electric current, electric power etc., environmental stresses such as ambient temperature, humidity etc. and thermal stress caused due to self-heating of semiconductor products. For these stresses, instantaneous values, maximum values and minimum values must be taken into consideration. In addition, it should be noted that since power devices or IC's including power devices have large self-heating value, the degree of derating of junction temperature affects the reliability significantly. • When using the products specified herein by either (i) combining other products or materials therewith or (ii) physically, chemically or otherwise processing or treating the products, please duly consider all possible risks that may result from all such uses in advance and proceed therewith at your own responsibility. • Anti radioactive ray design is not considered for the products listed herein. • Sanken assumes no responsibility for any troubles, such as dropping products caused during transportation out of Sanken's distribution network. • The contents in this document must not be transcribed or copied without Sanken's written consent. LC5550LD-AN, Rev. 1.2 SANKEN ELECTRIC CO., LTD. 19