LC5545LD, LC5546LD, LC5548LD, Application Note

Application Information
LC5540LD Series Single-Stage Power Factor Corrected
Off-Line Switching Regulator ICs
General Description
The LC5540LD series is the power IC for the isolated type
LED driver which has an incorporated power MOSFET,
designed for input capacitorless applications, and making it
possible for systems to comply with the harmonics standard
(IEC61000-3-2 class C) , even during light load condition.
The controller adapts the average current control method for
realizing high power factors, and the quasi-resonant topology contributes to high efficiency and low EMI noise. The
series is housed in DIP8 packages. The rich set of protection
features helps to realize low component counts, and high
performance-to-cost power supply.
Figure 1. The LC5540LD series package is a fully molded DIP8, with
pin 7 removed for greater isolation.
Features and Benefits
• DIP8 package
• Integrated on-time control circuit (it realizes high power
factor by average current control)
• Integrated startup circuit (no external startup
circuit necessary)
• Integrated soft-start circuit (reduces power stress during
start-up on the incorporated power MOSFET and output
rectifier)
• Integrated bias assist circuit (improves startup
performance, suppresses VCC voltage droop during
operation, and allows use of low-rated ceramic capacitor
on VCC pin)
• Integrated Leading Edge Blanking (LEB) circuit
• Integrated maximum on-time limit circuit
• Protection features:
▫ Overcurrent protection (OCP): pulse-by-pulse
▫ Overvoltage protection (OVP): latched shutdown
▫ Overload protection (OLP): latched shutdown
▫ Thermal shutdown (TSD): latched shutdown
Applications
• LED lighting fixtures
• LED light bulbs
The product lineup for the LC5540LD series provides the following options:
Part
Number
LC5545LD
LC5546LD
LC5548LD
MOSFET
VDSS(min)
(V)
650
800
RDS(on)
(max)
(Ω)
PWM
Operation
Frequency
fOSC(typ)
(kHz)
On-Time
tON(MAX)(typ)
(μs)
POUT*
(W)
230 VAC
85 to 265
VAC
3.95
72
9.3
13
10
1.9
60
11.2
20
16
3.5
72
9.3
13
10
*Based on the thermal rating; the allowable maximum output power can be up to 120%
to 140% of this value. However, maximum output power may be limited in such an
application with low output voltage or short duty cycle.
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
Functional Block Diagram
VCC
②
Control Part
⑧ D/ST
START UP
TSD
UVLO
Reg
Drv
Bias
OVP
OVP ⑥
① S/GND
S
RQ
OCP ③
Bottom
Detection
NF ⑤
OCP
OSC
OLP
LEB
Feedback
Control
④ FB
Reg
Pin List Table
Number
Name
1
S/GND
2
VCC
Supply voltage input and Overvoltage Protection (OVP) signal input
3
OCP
Overcurrent Protection (OCP), quasi-resonant signal input, and
Overvoltage Protection (OVP) signal input
4
FB
Feedback signal input and Overload Protection (OLP) signal input
5
NF
No function; must be externally connected to S/GND pin with as
short a trace as possible, for stable operation of the IC
6
OVP
7
–
8
D/ST
Function
MOSFET source and GND pin for the Control Part
Overvoltage Protection (OVP) signal input
Pin removed
MOSFET drain pin and input of the startup current
Table of Contents
General Specifications
1
3
4
10
Package Diagram
Electrical Characteristics
Typical Application Circuit
Functional Description
Startup Operation
Startup Period
Undervoltage Lockout (UVLO) Circuit
Bias Assist Function
Auxiliary Winding
Soft Start Function
Operational Mode at Startup
On-Time Control Operation
Quasi-Resonant Operation and Bottom-On Timing
Quasi-Resonant Operation
Bottom-On Timing
BD Pin Blanking Time
LC5540LD-AN, Rev. 1.7
11
11
11
11
12
12
14
14
15
16
16
17
19
Protection Functions
Latch Function
Overvoltage Protection (OVP)
Overload Protection (OLP)
Overcurrent Protection (OCP)
OCP Detection Method and Leading Edge Blanking
OCP Input Compensation Function
OCP Threshold Voltage with and without the OCP
Input Compensation Circuit
Determining OCP pin input compensation circuit
component values
AC input compensation circuit design example with
universal input
Thermal Shutdown Protection
Maximum On-Time Limiting Function
Design Notes
Peripheral Components
Transformer Design
Trace and Component Layout Design
SANKEN ELECTRIC CO., LTD.
20
20
20
22
22
22
24
26
27
27
28
28
28
28
29
30
2
Package Diagram
DIP8 package
9.4 ±0.3
8
5
LC
6.5 ±0.2
a
b
c
1.0 +0.3
-0.05
4
1
+0.3
1.52
-0.05
3.3 ±0.2
7.5 ±0.5
4.2 ±0.3
3.4 ±0.1
(7.6 TYP)
0.2 5 + 0.
- 0.01
5
０～１５° ０～１５°
2.54 TYP
0.89 TYP
0.5 ±0.1
Unit： mm
a: Part #: 554x
b: Lot number 3 digits, plus L
st
1 letter: Last digit of year
nd
2 letter: Month
Jan to September: Numeric
October: O
November: N
December: D
rd
3 letter: Week
Date 1 to 10: 1
Date 11 to 20: 2
Date 21 to 31: 3
c: Sanken control number
Pb-free. Device composition compliant
with the RoHS directive.
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
3
Electrical Characteristics
• This section provides separate sets of electrical characteristic data for each product.
• The polarity value for current specifies a sink as "+ ," and a source as “−,” referencing the IC.
• Please refer to the datasheet of each product for additional details.
LC5545LD Absolute Maximum Ratings Unless specifically noted, TA is 25°C
Characteristic
Drain Current
Symbol
IDPeak
Notes
Pins
Rating
Unit
Single pulse
8–1
2.5
A
ILPeak = 2.0 A, VDD = 99 V, L = 20 mH
8–1
47
mJ
Single Pulse Avalanche Energy
EAS
Control Part Input Voltage
VCC
2–1
35
V
OCP Pin Voltage
VOCP
3–1
−2.0 to 5.0
V
FB Pin Voltage
VFB
4–1
−0.3 to 7.0
V
OVP Pin Voltage
VOVP
6–1
−0.3 to 5.0
V
Allowable Power Dissipation of
MOSFET*
PD1
8–1
0.97
W
Operating Ambient Temperature
TOP
―
−55 to 125
°C
Storage Temperature
Tstg
―
−55 to 125
°C
Channel Temperature
Tch
―
150
°C
*Mounted on a 15 mm × 15 mm PCB.
LC5545LD Electrical Characteristics of MOSFET Unless specifically noted, TA is 25°C
Characteristic
Drain-to-Source Breakdown Voltage
Drain Leakage Current
On-Resistance
Switching Time
Thermal Resistance*
Symbol
Pins
Min.
Typ.
Max.
Unit
VDSS
Test Conditions
8–1
650
―
―
V
IDSS
8–1
―
―
300
μA
RDS(on)
8–1
―
―
3.95
Ω
tf
Rθch-c
Between channel and case
8–1
―
―
250
ns
―
―
―
42
°C/W
*The thermal resistance between the channels of the MOSFET and the case. TC measured at the center of the case top surface.
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
4
LC5545LD Electrical Characteristics of Control Part Unless specifically noted, TA is 25°C, VCC = 20 V
Characteristic
Symbol
Test Conditions
Pins
Min.
Typ.
Max.
Unit
Power Supply Startup Operation
Operation Start Voltage
VCC(ON)
2–1
13.8
15.1
17.3
V
Operation Stop Voltage*
VCC(OFF)
2–1
8.4
9.4
10.7
V
ICC(ON)
2–1
–
–
4.7
mA
VSTARTUP
8–1
18
21
24
V
2–1
−8.5
−4.0
−1.5
mA
VCC(BIAS)
2–1
9.5
11.0
12.5
V
fOSC
8–1
60
72
84
kHz
Maximum On-Time
tON(MAX)
8–1
8.0
9.3
11.2
μs
FB Pin Control Minimum Voltage
VFB(MIN)
4–1
0.50
0.85
1.20
V
Circuit Current in Operation
Startup Circuit Operation Voltage
Startup Current
Startup Current Threshold Biasing
Voltage*
ICC(STARTUP) VCC = 13 V
Normal Operation
PWM Operation Frequency
Maximum Feedback Current
IFB(MAX)
4–1
–40
–25
–10
μA
Leading Edge Blanking Time
tON(LEB)
3–1
−
600
−
ns
Quasi-Resonant Operation Threshold
Voltage-1
VBD(TH1)
3–1
0.14
0.24
0.34
V
Quasi-Resonant Operation Threshold
Voltage-2
VBD(TH2)
3–1
0.11
0.16
0.21
V
OCP Pin Overcurrent Protection
(OCP) Threshold Voltage
VOCP
3–1
−0.66
−0.60
−0.54
V
OCP Pin Source Current
Protection Operation
IOCP
3–1
−120
−40
−10
μA
OCP Pin Overvoltage Protection
(OVP) Operation Voltage
VBD(OVP)
3–1
2.2
2.6
3.0
V
Overload Protection (OLP) Threshold
Voltage
VFB(OLP)
4–1
4.1
4.5
4.9
V
OVP Pin OVP Threshold Voltage
VOVP(OVP)
6–1
1.6
2.0
2.4
V
VCC Pin OVP Threshold Voltage
VCC(OVP)
2–1
28.5
31.5
34.0
V
TJ(TSD)
–
135
–
–
°C
Thermal Shutdown Activating
Temperature
*VCC(BIAS) > VCC(OFF) always.
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
5
LC5546LD Absolute Maximum Ratings Unless specifically noted, TA is 25°C
Characteristic
Drain Current
Symbol
IDPeak
Notes
Single pulse
Pins
Rating
Unit
8–1
4.0
A
Single Pulse Avalanche Energy
EAS
8–1
86
mJ
Control Part Input Voltage
VCC
2–1
35
V
OCP Pin Voltage
ILPeak = 2.7 A, VDD = 99 V, L = 20 mH
VOCP
3–1
−2.0 to 5.0
V
FB Pin Voltage
VFB
4–1
−0.3 to 7.0
V
OVP Pin Voltage
VOVP
6–1
−0.3 to 5.0
V
Allowable Power Dissipation of
MOSFET*
PD1
8–1
0.97
W
Operating Ambient Temperature
TOP
―
−55 to 125
°C
Storage Temperature
Tstg
―
−55 to 125
°C
Channel Temperature
Tch
―
150
°C
*Mounted on a 15 mm × 15 mm PCB.
LC5546LD Electrical Characteristics of MOSFET Unless specifically noted, TA is 25°C
Pins
Min.
Typ.
Max.
Drain-to-Source Breakdown Voltage
Characteristic
VDSS
8–1
650
―
―
V
Drain Leakage Current
IDSS
8–1
―
―
300
μA
On-Resistance
RDS(on)
8–1
―
―
1.9
Ω
Switching Time
tf
8–1
―
―
400
ns
―
―
―
35.5
°C/W
Thermal Resistance*
Symbol
Rθch-c
Test Conditions
Between channel and case
Unit
*The thermal resistance between the channels of the MOSFET and the case. TC measured at the center of the case top surface.
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
6
LC5546LD Electrical Characteristics of Control Part Unless specifically noted, TA is 25°C, VCC = 20 V
Characteristic
Symbol
Test Conditions
Pins
Min.
Typ.
Max.
Unit
Power Supply Startup Operation
Operation Start Voltage
VCC(ON)
2–1
13.8
15.1
17.3
V
Operation Stop Voltage*
VCC(OFF)
2–1
8.4
9.4
10.7
V
ICC(ON)
2–1
–
–
4.7
mA
VSTARTUP
8–1
18
21
24
V
2–1
−8.5
−4.0
−1.5
mA
VCC(BIAS)
2–1
9.5
11.0
12.5
V
fOSC
8–1
50
60
70
kHz
Maximum On-Time
tON(MAX)
8–1
9.0
11.2
13.4
μs
FB Pin Control Minimum Voltage
VFB(MIN)
4–1
0.50
0.85
1.20
V
Circuit Current in Operation
Startup Circuit Operation Voltage
Startup Current
Startup Current Threshold Biasing
Voltage*
ICC(STARTUP) VCC = 13 V
Normal Operation
PWM Operation Frequency
Maximum Feedback Current
IFB(MAX)
4–1
–40
–25
–10
μA
Leading Edge Blanking Time
tON(LEB)
3–1
−
600
−
ns
Quasi-Resonant Operation Threshold
Voltage-1
VBD(TH1)
3–1
0.14
0.24
0.34
V
Quasi-Resonant Operation Threshold
Voltage-2
VBD(TH2)
3–1
0.11
0.16
0.21
V
OCP Pin Overcurrent Protection
(OCP) Threshold Voltage
VOCP
3–1
−0.66
−0.60
−0.54
V
OCP Pin Source Current
Protection Operation
IOCP
3–1
−120
−40
−10
μA
OCP Pin Overvoltage Protection
(OVP) Operation Voltage
VBD(OVP)
3–1
2.2
2.6
3.0
V
Overload Protection (OLP) Threshold
Voltage
VFB(OLP)
4–1
4.1
4.5
4.9
V
OVP Pin OVP Threshold Voltage
VOVP(OVP)
6–1
1.6
2.0
2.4
V
VCC Pin OVP Threshold Voltage
VCC(OVP)
2–1
28.5
31.5
34.0
V
TJ(TSD)
–
135
–
–
°C
Thermal Shutdown Activating
Temperature
*VCC(BIAS) > VCC(OFF) always.
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
7
LC5548LD Absolute Maximum Ratings Unless specifically noted, TA is 25°C
Characteristic
Drain Current
Symbol
IDPeak
Notes
Single pulse
Pins
Rating
Unit
8–1
2.6
A
Single Pulse Avalanche Energy
EAS
8–1
56
mJ
Control Part Input Voltage
VCC
2–1
35
V
OCP Pin Voltage
ILPeak = 2.3 A, VDD = 99 V, L = 20 mH
VOCP
3–1
−2.0 to 5.0
V
FB Pin Voltage
VFB
4–1
−0.3 to 7.0
V
OVP Pin Voltage
VOVP
6–1
−0.3 to 5.0
V
Allowable Power Dissipation of
MOSFET*
PD1
8–1
0.97
W
Operating Ambient Temperature
TOP
―
−55 to 125
°C
Storage Temperature
Tstg
―
−55 to 125
°C
Channel Temperature
Tch
―
150
°C
*Mounted on a 15 mm × 15 mm PCB.
LC5548LD Electrical Characteristics of MOSFET Unless specifically noted, TA is 25°C
Pins
Min.
Typ.
Max.
Drain-to-Source Breakdown Voltage
Characteristic
VDSS
8–1
800
―
―
V
Drain Leakage Current
IDSS
8–1
―
―
300
μA
On-Resistance
RDS(on)
8–1
―
―
3.5
Ω
Switching Time
tf
8–1
―
―
400
ns
―
―
―
40
°C/W
Thermal Resistance*
Symbol
Rθch-c
Test Conditions
Between channel and case
Unit
*The thermal resistance between the channels of the MOSFET and the case. TC measured at the center of the case top surface.
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
8
LC5548LD Electrical Characteristics of Control Part Unless specifically noted, TA is 25°C, VCC = 20 V
Characteristic
Symbol
Test Conditions
Pins
Min.
Typ.
Max.
Unit
Power Supply Startup Operation
Operation Start Voltage
VCC(ON)
2–1
13.8
15.1
17.3
V
Operation Stop Voltage*
VCC(OFF)
2–1
8.4
9.4
10.7
V
ICC(ON)
2–1
–
–
4.7
mA
VSTARTUP
8–1
18
21
24
V
2–1
−8.5
−4.0
−1.5
mA
VCC(BIAS)
2–1
9.5
11.0
12.5
V
fOSC
8–1
60
72
84
kHz
Maximum On-Time
tON(MAX)
8–1
8.0
9.3
11.2
μs
FB Pin Control Minimum Voltage
VFB(MIN)
4–1
0.50
0.85
1.20
V
Circuit Current in Operation
Startup Circuit Operation Voltage
Startup Current
Startup Current Threshold Biasing
Voltage*
ICC(STARTUP) VCC = 13 V
Normal Operation
PWM Operation Frequency
Maximum Feedback Current
IFB(MAX)
4–1
–40
–25
–10
μA
Leading Edge Blanking Time
tON(LEB)
3–1
−
600
−
ns
Quasi-Resonant Operation Threshold
Voltage-1
VBD(TH1)
3–1
0.14
0.24
0.34
V
Quasi-Resonant Operation Threshold
Voltage-2
VBD(TH2)
3–1
0.11
0.16
0.21
V
OCP Pin Overcurrent Protection
(OCP) Threshold Voltage
VOCP
3–1
−0.66
−0.60
−0.54
V
OCP Pin Source Current
Protection Operation
IOCP
3–1
−120
−40
−10
μA
OCP Pin Overvoltage Protection
(OVP) Operation Voltage
VBD(OVP)
3–1
2.2
2.6
3.0
V
Overload Protection (OLP) Threshold
Voltage
VFB(OLP)
4–1
4.1
4.5
4.9
V
OVP Pin OVP Threshold Voltage
VOVP(OVP)
6–1
1.6
2.0
2.4
V
VCC Pin OVP Threshold Voltage
VCC(OVP)
2–1
28.5
31.5
34.0
V
TJ(TSD)
–
135
–
–
°C
Thermal Shutdown Activating
Temperature
*VCC(BIAS) > VCC(OFF) always.
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
9
Typical Application Circuit
F1
VAC
L1
C11
D1
D2
D3
D4
T1
L2
C1
C8
D8
R5
R8 R10
PC2
C2
C9
Q1
C10
D5
U1
LC554xLD
8
S/GND
5
NC
6
D/ST
OVP
R1
R9
PC1
R11
R12
C13
C4
DZ2
PC2
C3
Controller
Chip
C17
D6
R14
R17
R15
R18
-
DZ1
C12
R6
LED
R13
D9
U2
+
C14
C15
R16
C16
R19 R20
S/GND VCC OCP FB
1
2
3
4
R7
C5
ROCP
R3
C6
R21
C18 DZ3
R4
PC1
D7
C7
Power supply circuit example for LED lighting
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
10
Functional Description
All of the parameter values used in these descriptions are typical
values, according to the LC5545LD specification, unless they are
specified as minimum or maximum.
With regard to current direction, "+" indicates sink current
(toward the IC) and "–" indicates source current (from the IC).
L2
T1
VAC
Startup Operation
C2
Startup Period
Figure 2 shows the VCC pin peripheral circuit. The integrated
startup circuit is connected to the D/ST pin. When the D/ST pin
voltage reaches VSTARTUP = 21 V, the startup circuit is activated,
and it generates a constant current, ICC(STARTUP) = –4.0 mA, to
charge capacitor C4 at the VCC pin. During this process, when
the VCC pin voltage reaches VCC(ON) = 15.1 V, the IC starts operation. After that, the startup circuit stops automatically, in order to
eliminate its own power consumption.
The startup time is determined by the C4 capacitance. A ceramic
or film capacitor can be used for C4, and a value of 0.22 to 22 μF
is generally recommended. The approximate value of the startup
time can be calculated using the following formula:
C4 ×
VCC(ON) – VCC(INT)
where:
VCC
2
LC554×LD
S/GND
D5
R1
C4
VD
1
D
Figure 2. D/ST and VCC pin peripheral circuits
(1)
|ICC(STARTUP)|
tSTART is the startup time in s, and
ICC
VCC(INT) is the initial voltage of the VCC pin in V.
ICC(ON) (max)
= 4.7mA
The voltage from the auxiliary winding (D in figure 2) becomes
a power source to the IC in steady-state operation. The auxiliary
winding voltage should be targeted to be about 20 V, determined
by the winding turns of the D winding, in order that the VCC pin
voltage should be set within the specifications of the input voltage
range and the output load range of the power supply, according to
the following formula:
Stop
Undervoltage Lockout (UVLO) Circuit
Figure 3 shows the relation of the VCC pin voltage to the circuit
current, ICC . When the VCC pin voltage reaches the Operation
Start Voltage, VCC(ON) = 15.1 V, the IC starts operation and the
circuit current increases. In operation, when the VCC pin voltage
decreases to VCC(OFF) = 9.4 V, the IC stops operation by UVLO
circuit, and reverts to the state before startup.
Start
z
tSTART
8
D/ST
P
9.4 V
VCC(OFF)
15.1 V VCC pin voltage
VCC(ON)
Figure 3. VCC versus ICC
VCC(BIAS)(max) < VCC < VCC(OVP)(min)
12.5 (V) < VCC < 28.5 (V)
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
11
Bias Assist Function
Figure 4 shows the VCC pin voltage behavior during the startup
period. If VCC pin voltage decreases enough to reach the Startup
Current Threshold Biasing Voltage, VCC(BIAS) = 11.0 V, the
Bias Assist function is activated before the voltage decreases to
VCC(OFF) = 9.4 V. While the Bias Assist function is operating, any
decrease of the VCC pin voltage is counteracted by a supplementary current from the Startup circuit, and thus VCC is kept almost
constant.
VCC
pin voltage
Startup success
IC startup
Target
Operating
Voltage
Increasing by
output voltage rising
Bias Assist period
VCC(ON) =
15.1 V
VCC(BIAS) =
11.0 V
VCC(OFF) =
9.4 V
Startup failure
While the output voltage rises, the VCC pin voltage increases to
the target voltage to counterbalance the voltage drop caused by
increasing IC current and the increase of the auxiliary winding
voltage, VD , proportional to the output voltage.
Because of the Bias Assist function, the use of a low-value
capacitor for C4 (see figure 6) is allowed. Also, because the
increase of VCC pin voltage becomes faster when the output runs
with excess voltage, the response time of the OVP function can
also be shortened.
It is necessary to check and adjust the startup process in the application, so that poor starting conditions may be avoided.
Time
Figure 4. VCC during startup period
Without R1
VCC
pin voltage
Auxiliary Winding
In actual power supply circuits, there are cases in which the VCC
pin voltage fluctuates in proportion to the output of the SMPS
(see figure 5). This happens because C4 is charged to a peak voltage on the auxiliary winding D, which is caused by the transient
surge voltage coupled from the primary winding when the power
MOSFET turns off.
For alleviating C4 peak charging, it is effective to add some value
R1, of several tenths of ohms to several ohms, in series with D5
(see figure 6). The optimal value of R1 should be determined
using a transformer matching what will be used in the actual
application, because the proportion of the VCC pin voltage versus
the transformer output voltage differs according to transformer
structural design.
With R1
IOUT
Figure 5. VCC versus IOUT with and without resistor R1
D5
2
VCC
LC554xLD
Added
R1
D
C4
S/GND
1
Figure 6. VCC pin peripheral circuit with R1
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
12
Fluctuation of VCC by IOUT worsens in the following cases,
requiring a transformer designer to pay close attention to the
placement of the auxiliary winding D:
• Poor coupling between the primary and secondary windings
(this causes high surge voltage and is seen in a design with low
output voltage and high output current).
• Poor coupling between the auxiliary winding D and the secondary stabilized output winding where the output line voltage
is controlled constant by the output voltage feedback (this is
susceptible to surge voltage)
Figure 7 shows two transformer design examples considered the
winding location of the auxiliary winding D to minimize impact
of VCC surge voltage. Triple insulation wires are used for either
the primary or secondary winding, and thus no margin-tape is
used:
• Separate the auxiliary winding D from the primary windings
P1 and P2 (figure 7 (A)); P1 and P2 are two separated primary
windings.
• Place the auxiliary winding D within the secondary winding S1 in order to improve the coupling of those windings
(figure 7 (B)); S1 is the secondary output winding.
Bobbin
Core
Bobbin
P1, P2: Primary Winding
S1: Secondary Winding
D: Auxiliary winding
P1 S1 P2 S1 D
Core
P1 S1 D S1 P2
(A)
P1, P2: Primary Winding
S1: Secondary Winding
D: Auxiliary winding
(B)
Figure 7. Transformer winding structures
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
13
Soft Start Function
Figure 8 shows the operation waveform at startup. The soft start
function reduces power stress on the incorporated MOSFET and
the secondary rectifier.
The soft start operation begins when the FB pin voltage reaches
VFB(min) = 0.85 V, and lasts until the output current becomes
constant. During that period, the operation is in PWM operation, at the internally set fOSC = 72 kHz (for LC5545LD and
LC5548LD, 60 kHz for LC5546LD), and the output power
gradually increases.
During this period, check the items below:
• Ensure the VCC pin voltage does not drop to the Operation Stop
Voltage, VCC(OFF).
• Ensure the output current reaches the target value before the
Overload Protection (OLP) function is activated by the FB pin
voltage reaching VFB(OLP) = 4.5 V.
Operational Mode at Startup
Figure 8 shows the operation mode at the startup. After the
startup, when the FB pin voltage reaches VFB(min) = 0.85 V, the
switching operation begins in PWM operation at an operation frequency of fOSC = 72 kHz ( for LC5545LD and LC5548LD, 60 kHz
for LC5546LD).
Then, when the output voltage rises, the auxiliary winding voltage will rise, and when the quasi-resonant signal of the positive
voltage on OCP pin reaches VBD(TH1) = 0.24 V or more, the quasiresonant operation will begin.
Figure 9 shows the OCP pin voltage waveform expanded time
scale at point A of figure 8.
Soft-Start Period
FB Pin
Voltage
IC Startup
VFB(MIN) = 0.85 V
S/GND
VCC Pin
Voltage
VCC(BIAS) = 11.0 V
S/GND
Constant Current Control
Output (LED)
Current, IOUT
Target
Current
GND (IOUT)
PWM operation
Quasi-resonant (QR) operation
Drain
Current, ID
S/GND
A
Time
Figure 8. Soft-start operation waveforms at startup
PWM operation Quasi-resonant (QR) operation
VBD(TH1)
OCP Pin
Voltage
S/GND
time
Drain
Current, ID
GND(ID)
time
Figure 9. OCP Pin Voltage (with time scale expanded at point A of figure 8)
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
14
On-Time Control Operation
LC554×LD
Figure 10 shows the peripheral circuit at the FB pin, and figure 11
shows the on-time control. The output control is done by voltage
mode control, which controls on-time depending on output load,
and average current control.
S/GND OCP
This averaged voltage at the FB pin is compared with the internal oscillator (OSC) output by the internal FB comparator, and
the on-time is controlled. Here, the internal OSC indicates the
oscillator circuit, which controls the PWM operation frequency,
quasi-resonant oscillation, and the maximum on-time limit.
The recommended value of capacitor C6 linked to the FB pin is
approximately 2.2 μF.
PC1
C6
ROCP
Figure 10. FB pin peripheral circuit
LC554×LD
-
FB voltage
OSC
+
• When the output load current becomes less than the target value,
the current detection resistor voltage in secondary side becomes
low, and the feedback current through the PC1 decreases.
Because the averaged voltage at the FB pin becomes high, the
on-time and the output current increase.
Figure 12 shows the average input current waveform. The averaged FB pin voltage becomes constant, and the duty cycle is
controlled according to the EIN voltage (C2 voltage in the Typical
Application Circuit drawing). It makes an averaged input current
sine waveform which realizes a high power factor.
R7
D7
R3
The constant output current control of the output is done as
below:
• When the output current becomes greater than the target value,
the circuits operate in the opposite way. The feedback current
through the PC1 increases. Because the averaged voltage at the
FB pin becomes low, the on-time and the output current decrease.
4
3
1
As shown in figure 11, in the average current control operation,
the current detection resistor voltage in secondary side is compared with the reference voltage by the secondary operational
amplifier circuit (U2 in the Typical Application Circuit drawing).
This output is run through the photo-coupler, PC1, to the FB pin,
and its output is averaged at the FB pin.
FB
4
FB
S/GND
C6
PC1
LED
1
+
Constant current
detection resistor
-
FB+
OSC
FB
voltage
Gate on-time
Drain current
Figure 11. On-time control
FB pin voltage
S/GND
EIN
Drain current
Averaged input current
Figure 12. Averaged input current waveform
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
15
Quasi-Resonant Operation and Bottom-On
Timing
t ONDLY
Quasi-Resonant Operation
Figure 13 shows the circuit of a flyback converter. A flyback
converter is a system which transfers the energy stored in the
transformer to the secondary side when the primary side power
MOSFET is turned off. After the energy is completely transferred to the secondary, when the MOSFET keeps turning off, the
MOSFET drain node begins free oscillation based on the LP of the
transformer and CV across the drain and source pins.
Ef
VDS
I OFF
The quasi-resonant operation is the VDS bottom-on operation that
turns-on the MOSFET at the bottom point of VDS free oscillation.
ID
Figure 14 shows an ideal VDS waveform during bottom-on
operation.
Using bottom-on operation, switching loss and switching noise
are reduced and it is possible to obtain converters with high efficiency and low noise.
Ef
EIN
ID
NP T1 NS
LP
P
S
VF
D4
IOFF
C2
CV
Figure 13. Basic flyback converter circuit
LC5540LD-AN, Rev. 1.7
VOUT
EIN
Bottom
Point
tON
Half cycle of free oscillation, tONDLY
≈ √ L P × CV
Figure 14. Ideal bottom-on operation waveform (MOSFET turn-on at a
bottom point of a VDS waveform)
EIN:
Ef:
Input voltage
Flyback voltage
C9
Ef =
NP
NS
(VOUT + Vf)
(2)
N P:
N S:
VOUT:
Vf:
ID:
IOFF:
Number of turns in the primary winding
Number of turns in the secondary winding
Output voltage
Forward voltage of the secondary rectifier
Drain current of the power MOSFET
Current running through the secondary rectifier during
the power MOSFET off-period
CV: Voltage resonant capacitor
LP: Primary inductance
SANKEN ELECTRIC CO., LTD.
16
Bottom-On Timing
Figure 15 shows the voltage waveform of the OCP pin peripheral
circuit and auxiliary winding, D.
R3 and R4 Setup
R3 is recommended to be between 100 and 330 Ω, and C5 to be
between 100 and 470 pF.
This delay time, tONLDLY , for bottom-on, from the start of VDS
free oscillation to the timing of turning-on the power MOSFET,
is created by exploiting the auxiliary winding voltage, which
synchronizes to the drain voltage VDS waveform.
R4 must set the range for the quasi-resonant signal: greater than
or equal to VBD(TH1) under input and output conditions where VCC
becomes lowest, but less than the OCP Pin Overvoltage Protection (OVP) Threshold Voltage, VBD(OVP) = 2.6 V, under conditions
where VCC becomes highest.
During turning off the power MOSFET, the auxiliary winding
voltage is fed through the delay circuit ( D6, R4, C7, and D7 of
figure 15) to the OCP pin, and the OCP pin is provided the quasiresonant signal of positive voltage.
After the power MOSFET turns off, the quasi-resonant signal
immediately goes up and it exceeds the Quasi-Resonant Operation Threshold Voltage 1, VBD(TH1) = 0.24 V. After this occurs,
the power MOSFET remains off until the quasi-resonant signal comes down enough to cross the Quasi-Resonant Operation Threshold Voltage 2, VBD(TH2) = 0.16 V. Then the power
MOSFET again turns on. In addition, at this point, the threshold
voltage goes up to VBD(TH1) automatically to prevent malfunction
of the quasi-resonant operation from noise interference.
Figure 16 defines the pulse width of the quasi-resonant signal.
For initiating quasi-resonant operation, the quasi-resonant signal
pulse width between the two points VBD(TH1) and VBD(TH2) ,
tQR, must be equal to 1.2 μs or more. This pulse width must
be ensured, while at the same time the OCP pin peak voltage,
VBD(PK) , is recommended to be between 1.5 and 2.0 V. Both conditions should be satisfied throughout the power supply input and
output ranges, over variations in R3 and R4 actual component
values.
Because ROCP is much less than R3, the formula below is used to
calculate R4:
R4 =
R3 × (VCC – VBD(PK) – 2 ×Vf )
VBD(PK)
(3)
Clamping snubber circuit
T1
EIN
P
C2
EIN
D5
C3
8
D/ST
2
C4
D6
Ef
R1
Erev1
D
Auxiliary
winding voltage
VD
Erev1
0
Efw1
Efw1
VCC
R4
LC554×LD
OCP 3
S/GND
1
Forward voltage
Flyback voltage
tON
D7
C7
R3
C5
ROCP
VBD
Quasi-resonant
signal
VBD(TH1)
VBD
0
VBD(TH2)
Figure 15. OCP pin peripheral circuit (left) and auxiliary winding voltage and quasi-resonant signal (right)
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
17
given R3 = 220 Ω, VBD(PK) = 1.5 V, VCC = 16 V, and the Vf of D6
and D7 = 0.8 V. R4 is approximately 1.89 kΩ, and it is 1.8 kΩ in
the E12 series.
If the pulse width is not satisfied, increase R3 or decrease R4, in
order to raise VBD(PK) . Alternatively, increasing the capacitance of
resonant capacitor C3 is also effective because it widens the free
oscillation period. However, it causes an additional switching loss
increase; therefore, ensure the IC temperature rise is acceptable.
C7 Setup
The delay time, tONDLY , after which the power MOSFET turns on,
is adjusted by the value of C7 , so that the power MOSFET turns
on at the bottom-on of VDS.
To do so, observe the power MOSFET drain voltage, VDS, the
drain currnet, ID, and the quasi-resonant signal, under the maximum input voltage and the maximum output power, as shown in
figure 14.
The following show how to adjust the turn-on point:
• If the turn-on point precedes the bottom of the VDS signal (see
figure 17, left panel), it causes higher switching losses. In that
situation, after confirming the initial turn-on point, delay the
turn-on point by increasing the C7 value gradually, so that the
turn-on will match the bottom point of VDS.
VBD(PK), 1.5 to 2.0 V recommended, but less than 2.6 V
V BD(TH1) = 0.34 V (max)
V BD(TH2 ) = 0.21 V (max)
• In the converse situation, if the turn-on point lags behind the
VDS bottom point (see figure 17, right panel), it causes higher
switching losses also. After confirming the initial turn-on point,
advance the turn-on point by decreasing the C7 value gradually,
so that the turn-on will match the bottom point of VDS .
S/GND
Pulse width, t QR ≥ 1.2 μs
An initial reference value for C7 is about 1000 pF.
Figure 16. Definition of the pulse width of the quasi-resonant signal
AC mains frequency (50 Hz / 60 Hz)
2 × AC mains frequency
VDS(peak)
VDS
EIN(max)
GND
Turn-on occurring before
the VDS bottom point
Early turn-on point
fR ≈
VDS
0
Turn-on occurring
after the VDS bottom point
Delayed turn-on point
1
2 √ LP × CV
VDS
Bottom point
Free oscillation, fR
0
IOFF
0
IOFF
0
ID
0
ID
0
OCP pin
voltage 0
Auxiliary
winding VD 0
voltage
tON
VBD(TH1)
VBD(TH2)
Bottom point
OCP pin
voltage 0
Free oscillation, fR
tON
VBD(TH1)
VBD(TH2)
Auxiliary
winding VD 0
voltage
Figure 17. Effects of failure to turn on precisely at the VDS bottom point: (left) turn-on before a bottom point, and (right) turn-on
after a bottom point
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
18
BD Pin Blanking Time
Figure 18 shows two different OCP pin waveforms, comparing
transformer coupling conditions between the primary and secondary winding. The poor coupling tends to happen in a low output
voltage transformer design with high NP/ NS turns ratio (NP
and NS indicate the number of turns of the primary winding and
secondary winding, respectively), and it results in high leakage
inductance. The poor coupling causes high surge voltage ringing at the power MOSFET drain pin when it turns off. That high
surge voltage ringing is coupled to the auxiliary winding and then
the inappropriate quasi-resonant signal occurs.
The OCP pin has a blanking period of 250 ns (max) to avoid
the IC reacting to it, but if the surge voltage continues longer
than that period, the IC responds to it and repeatedly turns the
power MOSFET on and off at high frequency. This results in an
increase of the MOSFET power dissipation and temperature, and
it can be damaged.
The following adjustments are required when such high frequency operation occurs:
• C5 must be connected near the OCP pin and the GND pin
• The circuit trace loop between the OCP pin and the GND pin
must be separated from any traces carrying high current
• The coupling of the primary winding and the auxiliary winding
must be loosened
• The clamping snubber circuit (refer to figure 15) must be adjusted properly.
In addition, the OCP pin waveform during operation should be
measured by connecting test probes as short to the OCP pin and
the GND pin as possible, in order to measure any surge voltage
correctly.
Normal Waveform
(Good coupling)
VBD(TH1)= 0.24 V
VBD(TH2)= 0.16 V
0V
Inappropriate Waveform
(Poor coupling)
V BD(TH1)= 0.24 V
VBD(TH2)= 0.16 V
0V
OCP pin blanking time
250 ns（max）
Figure 18. The difference of OCP pin voltage waveform by the coupling condition
of the transformer; good coupling (top) versus inappropriate coupling (bottom)
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
19
Protection Functions
Latch Function
Overvoltage protection (OVP), Overload protection (OLP),
and Thermal shutdown (TSD) protection are latched. After the
switching operation stops, the VCC pin voltage will begin to
decrease, and when it falls to VCC(BIAS) = 11.0 V, the Bias Assist
Function will be activated. When the Bias Assist Function is activated, the startup current is supplied to the VCC pin in order to
prevent the VCC pin voltage from decreasing to VCC(OFF) = 9.4 V,
and thus the latched state is maintained. Releasing the latched
state is done by turning off the input voltage and by dropping the
VCC pin voltage below VCC(OFF) .
Overvoltage Protection (OVP)
The IC has three OVP activation methods: linked to the VCC pin,
to the OCP pin, and to the OVP Pin.
• VCC Pin Overvoltage Protection. Figure 19 shows the waveforms of the OVP function on the VCC pin. When the VCC pin
voltage with reference to the S/GND pin reaches VCC(OVP) =
31.5 V or more, OVP is activated and the IC stops switching
operation in latch mode.
Because VCC pin voltage is proportional to the output voltage, it
can be used to detect an output overvoltage event, such as open
load condition. In this situation, the detecting voltage, VOUT(OVP) ,
is expressed by the formula below:
VOUT(OVP) =
VCC pin voltage
VOUT(normal operation)
VCC(normal operation)
31.5 (V)
(4)
Latched shutdown
VCC(OVP)= 31.5V
AC mains off
VCC(BIAS)= 11.0V
Latch release
VCC(OFF)= 9.4V
FB pin voltage
VFB(MIN)= 0.85V
Drain current
ID
Time
Figure 19. Waveforms when VCC pin OVP function is being activated
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
20
• OCP Pin Overvoltage Protection. Figure 20 shows the waveform of the OCP function on the OCP pin. When the OCP pin
voltage with reference to the S/GND pin reaches VBD(OVP) =
2.6 V or more, OVP is activated and the IC stops switching
operation in latch mode. This input voltage must be less than the
absolute maximum rating, 5 V.
• OVP Pin Overvoltage Protection. Figure 21 shows the waveform of the OVP function on the OVP pin. When the OVP Pin
voltage with reference to the S/GND pin reaches VOVP(OVP) =
2.0 V or more, OVP is activated, and the IC stops switching
operation in latch mode. This input voltage must be less than the
absolute maximum rating, 5 V.
This can be used as protection in the event that the quasi-resonant
signal setup is mistaken or excess load current happens in the use
of a poor coupling transformer between the primary and secondary winding.
This function can be used through a photocoupler (PC2 as shown
in the Typical Application Diagram) to detect an excess output
voltage, such as caused by an open load condition, and protect
the circuit.
Latched shutdown
VBD(OVP)
OCP
Figure 20. Waveforms when OCP pin OVP function is being activated
VCC pin voltage
VCC(BIAS)= 11.0V
OVP pin voltage
AC mains off
Latch release
VCC(OFF)= 9.4V
Latched shutdown
VOVP(OVP) = 2.0V
Drain current
ID
Time
Figure 21. Waveforms when OVP pin OVP function is being activated
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
21
Overload Protection (OLP)
voltage and by dropping the VCC pin voltage below VCC(OFF).
The overload protection (OLP) state is a state in which the peak
drain current is limited by OCP operation under an overload condition. Figure 22 shows the the waveform of the OLP function on
the FB pin. At the overload condition, the VCC pin voltage drops
because the output voltage drops. When the VCC pin voltage
reaches the Startup Current Threshold Biasing Voltage, VCC(BIAS)
= 11.0 V, the Bias Assist Function is activated to avoid the VCC
pin voltage from decreasing. Simultaneously, the output voltage
decreases so the error amplifier on the secondary side cuts off,
and a photo-coupler, PC1, is cut off.
Generally, the target value of capacitor C6 is about 1 to 4.7 μF.
If the C6 value is too small, the OLP function may be activated
after cycling power to the IC.
When the error amplifier cuts off, the capacitor C6 connected to
the FB pin is charged, and when the FB/OLP pin voltage reaches
the OLP Threshold Voltage, VFB(OLP) = 4.5 V, the overload protection circuit will operate and stop switching operation in latch
mode. Releasing the latched state is done by turning off the input
The C6 value should be adjusted based on actual operation in the
application.
Overcurrent Protection (OCP)
The Overcurrent Protection (OCP) feature monitors the power
MOSFET drain current on a pulse-by-pulse basis, in order to
limit output power.
OCP Detection Method and Leading Edge Blanking
The drain current of the power MOSFET is detected by the current detection resistor, ROCP , placed between the OCP pin and the
S/GND pin, as shown in figure 23.
Latched shutdown
Figure 22. Operation waveform at the time of OLP operation (left) and peripheral circuit (right)
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
22
The voltage across ROCP, VROCP , is fed through R3 to the
OCP pin to be detected by it. The turn-off point for the power
MOSFET can be determined as that where VROCP reaches the
value of the following equation:
VROCP = – |VOCP | + R3
larger capacitances for C5 would cause OCP response to become
slow, and then it would result in an increase in the peak drain current at transient conditions, such as startup.
(5)
|IOCP |
where
VOCP: OCP threshold voltage (−0.6 V) of the IC,
R3: R3 resistance, and
IOCP: OCP pin source current (−40 μA) of the IC.
A filter is inserted at the OCP pin in order to prevent malfunction:
• R3 setup. In order to minimize effects of variation in the
internal resistor, R3 is recommended to have a value
from 100 to 330 Ω.
• C5 setup. C5 is recommended to have a value from
100 to 470 pF, with good temperature characteristics. Selecting
Because the OCP function detects a peak current, it can react to
the surge voltage at the power MOSFET turn-on edge and thus
the power MOSFET might turn off. In order to avoid this, the
Leading Edge Blanking Time, tON(LEB), = 600 ns, is set.
The surge current pulse width must be less than tON(LEB) as shown
in figure 24. In case its width is longer than that, try these measures:
• adjust the turn-on point to the VDS bottom point
• reduce the voltage resonant capacitor CV (C3 in figure 23)
capacitance
• reduce the secondary rectifier snubber capacitor capacitance
P
D/ST 8
LC554×LD
LOGIC
C3
DRIVE
1
S/GND
OCP Comp.
3
-
OCP
+
-0.6V
Reg
C5
ROCP VROCP
R3
Surge pulse voltage width
at turning on
Filter
Figure 23. OCP circuit for negative side detect
LC5540LD-AN, Rev. 1.7
Figure 24. OCP pin voltage (converted from MOSFET drain
current by ROCP)
SANKEN ELECTRIC CO., LTD.
23
OCP Input Compensation Function
This Overcurrent Input Compensation function can compensate
the OCP threshold voltage according to the AC input voltage.
When using a quasi-resonant converter with universal input
(85 to 265 VAC), if the output power is set constant, then because
higher input voltages have higher frequency, the MOSFET peak
drain current becomes low.
Because ROCP is fixed, the OCP point in the higher input voltage
will shift further into the overload area, as shown by curve A in
figure 25. In order to suppress this phenomenon, this IC has the
Overcurrent Input Compensation function.
As for determining an input compensation value, it is necessary
to avoid excessive input compensation for the output current
specification, IOUT , as shown in figure 25. When excessive input
compensation is applied, IOUT(OCP) may be below IOUT in the situation where the input voltage is high. Therefore, it is necessary
to ensure that IOUT(OCP) remains more than IOUT across the input
voltage range.
Figure 26 shows an overcurrent input compensation circuit (DX1,
DZX1, RX1).
T1
EIN
P
C2
D5
R1
D
Output Current at OCP, IOUT(OCP) 㧔A㧕
C4
A IOUT without input
compensation
C3
8
D/ST
2
D6
B IOUT with appropriate
input compensation
R4
IOUT
IOUT target output level
C IOUT with excessive
input compensation
C7
LC554×LD
DZX1
RX1
D7
OCP 3
S/GND
R3
1
85 V
DX1
VCC
Input compensation
cricuit for OCP
C5
AC Input Voltage (V㧕 265 V
ROCP
Figure 25. OCP circuit input compensation
LC5540LD-AN, Rev. 1.7
Figure 26. External OCP input compensation circuit
SANKEN ELECTRIC CO., LTD.
24
The OCP compensation amount depends on values of the input
compensation current, RX1, R3, and ROCP (see figure 27). The
input compensation current, I, is expressed by the following
equation:
I =
Efw1 – VZX1 – VFX1
This input Compensation Current, I, creates the voltage of R3 × I,
and it lowers the absolute value of the compensated OCP threshold voltage to less than the original OCP threshold voltage, VOCP
= –0.6 V. This way, when EIN is high, the compensation amount
becomes high.
(6)
RX1 + R3 + ROCP
where
I: Input compensation current,
Efw1: Forward voltage of the auxiliary winding D proportional
to input voltage,
VFX1: DX1 forward voltage, and
VZX1: DZX1 Zener voltage.
Optimize the circuit in a way to minimize the difference between
the overcurrent points at low and high AC input voltage. Also
ensure that the output current meets its target over the entire AC
input voltage range, as the curve B in figure 25 (appropriate input
compensation). The OCP pin voltage, including surge voltage,
must not exceed its absolute maximum rating of –2.0 to 5.0 V at
the highest AC input voltage.
OCP threshold voltage after input compensation, V'ROCP , is
expressed by the following equation:
V 'ROCP = –
¨
©
©
ª
¨
The DZX1 Zener diode is used to set the voltage at which the
input compensation begins, so choose the Zener voltage value
that is equal to Efw1 at the time when input compensation begins.
(7)
|VOCP | + |R3 × IOCP | – R3 × I ©©
ª
T1
EIN
P
C2
D5
R1
D
Flyback voltage,
Erev1
100VAC
C4
230VAC
0
AC
VZX1
C3
8
D/ST
2
D6
LC554×LD
OCP
IOCP
R4
DZX1
D7
RX1
Input compensation
current, I
0
Efw2
3
R3
1
IDP(OCP)
OCP input voltage,
Efw2
C5
AC
OCP input compensation
starting point:
the point matching Efw1– VZX1 = 0
ROCP
Figure 27. OCP input compensation circuit
LC5540LD-AN, Rev. 1.7
Efw1
DX1
VCC
C7
S/GND
Forward voltage,
Efw1
Figure 28. Efw1 and Efw2 voltage relative to AC input voltage
SANKEN ELECTRIC CO., LTD.
25
OCP Threshold Voltage with and without the OCP Input
Compensation Circuit
OCP threshold voltage without OCP input compensation circuit,
VROCP , is expressed by equation 8. As shown in figure 29, when
VROCP with reference to the S/GND pin is equal to the sum of the
OCP threshold voltage, VOCP , and the voltage across R3 (= R3 ×
IOCP ), then OCP operations will start.
VROCP = – |ROCP × IDP(OCP)|
(8)
= – |VOCP | + R3 × |IOCP |
where
equal to the sum of the Overcurrent Protection Threshold Voltage
(VOCP), the voltage across R3 (= R3 × IOCP ), and –R3×I, then
OCP operations will start:
V 'ROCP = – |R'OCP × I'DP(OCP) |
¨
¨
(9)
= – ©© |VOCP | + |R3 × IOCP | – R3 × I ©©
ª
ª
where,
I'DP(OCP): The peak drain current during OCP operation with
OCP input compensation circuit,
VOCP: OCP threshold voltage (−0.60 V) of the IC,
IDP(OCP): Peak drain current during OCP operation,
VOCP: OCP threshold voltage (−0.6 V) of the IC, and
IOCP: OCP pin source current (−40 μA) of the IC.
In the converse situation, with the input compensation circuit,
as shown in the figure 30, the overcurrent detecting voltage is
IOCP: OCP pin source current (−40 μA), and
I: Input compensation current.
Thus, by adding OCP input compensation circuit, OCP threshold
voltage during OCP operation will be changed and the output
power is limited.
ROCP × IDP
Figure 29. Without OCP input compensation function
'
ROCP × I'DP
Figure 30. With OCP input compensation function
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
26
Determining OCP pin input compensation circuit
component values
Given:
IDP , Peak drain current of power MOSFET
VFX1, DX1 forward voltage
VZX1, DZX1 Zener voltage
VOCP, OCP threshold voltage: −0.6 V at the IC
IOCP , OCP pin source current; −40 μA at the IC
I, Input compensation current
Other component numbers, such as resistors, are as referred to in
figure 27.
1. The peak drain current during OCP operation without OCP
input compensation circuit, IDP(OCP) , is expressed by the following equation, derived from equation 8. IDP(OCP) is equal to
the drain current limited by OCP threshold voltage without
OCP input compensation function at the minimum AC input
voltage:
|VOCP| + R3 × |IOCP|
(10)
ROCP
2. The overcurrent detecting peak drain current with the input
compensation circuit, I'DP(OCP) , is expressed by the following equation, derived from equation 9. I'DP(OCP) is set to the
peak drain current where the output current is equal to that at
the maximum AC input voltage of the curve B in figure 25
(appropriate input compensation):
|IDP(OCP)| =
|VOCP| + R3 × (|IOCP| – I )
(11)
ROCP
3. The input compensation current, I, can be expressed by the
following equation, derived from equations 10 and 11:
R
I = ( |I DP(OCP) | – |I 'DP(OCP)| ) × OCP
(12)
R3
I 'DP(OCP) =
4. The forward voltage, Efw1 , at C2 peak voltage EIN(PK)MAX of
the maximum AC input voltage is expressed as follows:
N × EIN(PK)MAX
Efw1 = D
(13)
NP
5. To calculate component values for RXI so that the input
compensation circuit provides adequate input compensation
current, I, at the maximum AC input voltage, EIN(PK)MAX , the
following equation is used:
I =
Efw1 – VZX1 – VFX1
RX1 + R3 + ROCP
(14)
RX1 =
Efw1 – VZX1 – VFX1
I
(15)
and, from equations 13 and 15:
ND × EIN(PK)MAX
NP
RX1 =
–
(VZX1 + VFX1 )
(16)
I
AC input compensation circuit design example with
universal input
When the input voltage is universal specification (85 to
265 VAC), the OCP pin input voltage compensation circuit
(DZX1, RX1) rating is calculated as follows, but should also be
checked for functional operation in the actual application:
Given:
EIN , AC input voltage: 85 to 265 VAC
POUT , Output power: 40 W
NP , Transformer primary winding turns: 40 T
ND , Transformer auxiliary winding turns: 6 T
ROCP , OCP detection resistor: 0.2 Ω
R3, Filter resistor at the OCP pin: 220 Ω
VFX1 , DX1 forward voltage: 0.8 V
IDP(OCP) , Drain current during OCP operation, measured at
EIN(min) of 85 VAC: 3.0 A
I'DP(OCP), Drain current when the output current is equal to that
at the maximum AC input voltage of the curve B in figure 25
(appropriate input compensation): 1.9 A
The OCP input compensation startup voltage, VIN(OCP_ST) , should
be set in the range of 100 to 130 VAC. Tentatively, for this
example, VIN(OCP_ST) is set to 120 VAC.
1. Calculate DZX1 value. Efw1 at 120 VAC input:
ND
× EIN(PK)(max)
NP
N
= D × VIN(OCP_ST) × √2
NP
6 (T)
=
× 120 (VAC) × √2 = 25.5 V
40 (T)
Efw1 =
(17)
Thus, select 27 V as the Zener value for DZX1.
2. The compensation current, I, is calculated using equation 12:
0.2 (Ω)
I = (3.0 (A) – 1.9 (A)) ×
= 1 mA
220 (Ω)
assuming: R3 and ROCP << RX1, then:
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
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3. RX1 can be calculated using equation 16:
6 (T) × 265 (VAC)√2
– (27 (V) + 0.8 (V))
40 (T)
RX1 =
= 28.4 kΩ
1 (mA)
Thus, select RX1 = 27 kΩ out of the E12 series.
Finally, ensure that the output current limited by OCP operation
is similar to that of the curve B in figure 25 (appropriate input
compensation), in actual operation throughout AC input voltage
ranges. If necessary, re-adjust the rating of DZX1 and RX1 by
changing the compensation startup voltage VIN(OCP_ST) for OCP
pin input voltage.
Thermal Shutdown Protection
Thermal Shutdown protection is activated when the temperature
of the Control Part in the IC reaches TJ(TSD) = 135°C(min), and
then the IC stops switching operation in latch mode. Releasing
the latched state is done by turning off the input voltage and by
dropping the VCC pin voltage below VCC(OFF).
Maximum On-Time Limiting Function
The maximum on-time, set at tON(MAX) = 9.3 μs (for LC5545LD
and LC5548LD, 11.2 μs for LC5546LD), limits lower side operation frequency (see figure 31), and it minimizes audible noise
from the transformer, as well as power stress on the incorporated
MOSFET and secondary rectifier at low AC input or during transient periods such as at switching AC input voltage on or off.
Ensure that the actual on-time at the minimum AC input and the
maximum load condition does not reach tON(MAX). If that does
happen, redesign the transformer, such as by reducing the primary
inductance, LP , or reducing the duty cycle by lowering the turns
ratio of NP / NS .
Design Notes
Peripheral Components
Take care to use properly rated and proper type of components.
• Output smoothing capacitor. Consider design margins for ratings of ripple current, voltage, and temperature in selecting the
output capacitor. A low impedance capacitor, designed to be
tolerant against high ripple current, is recommended.
• Transformer. Consider design margins for temperature rise,
resulting from copper losses and core losses, in designing or
selecting a transformer.
Switching current contains a high frequency component that
causes the skin effect; therefore, consider a current density of
3 to 4 A/mm2 and select a wire gauge based on RMS current.
In the event further temperature measurement is necessary, try
the following measures to increase the surface area of the wire:
▫ Increase the quantity of parallel wires
▫ Use litz wire
▫ Increase the diameter of the wires
• Current detection resistor, ROCP . Choose a low equivalent series
inductance and high surge tolerant type for the current detection resistor. If a high inductance type is used, it may cause
malfunctioning because of the high frequency current running
through it.
ID
Drain current
time
VDS
Voltage between
drain and source
Maximum
On-Time
time
Figure 31. Confirmation of Maximum On-Time
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
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Transformer Design
Figure 32 shows an ideal waveform in average current control
relative to a sine wave of AC input voltage. The Average Current
Control function controls FB pin voltage at a fixed rate relative to
the sine wave of AC input voltage, VIN , at commercial frequencies. Therefore, the envelope curve of the peak drain current, IDP ,
and the input current, IIN (which is the averaged IDP), shows a
sine waveform which is similar to that of the AC input voltage.
To set the fixed FB pin voltage, the value of C6 (connected to the
FB pin) and the secondary side current detection resistor must be
be adjusted.
The transformer design is the same as for an RCC (ringing choke
converter, or self-oscillation flyback converter) transformer
design. However, a quasi-resonant operation includes a certain
delay to turn-on, so duty cycle must be compensated. Moreover,
for input capacitorless applications, the applied voltage of a transformer is the sine wave of the AC input voltage, VIN , at commercial frequencies.
Therefore, the duty cycle compensation for quasi-resonant delay
time is added to the basic equation of the RCC topology; moreover, the equation must be changed into the sine wave of the AC
input voltage, VIN.
In consideration of quasi-resonant delay time, the primary side
inductance, L'P , applied the sine wave of AC input voltage, is
expressed by the following equation:
( VINRMS(MIN) × DON )2
L'P =

 2×P
OUT × fS(MIN)

+ VINRMS(MIN) × DON× fS(MIN)× √ CV 
H


2
(18)
where
VINRMS(MIN): Effective value (rms) of the sine wave of the
minimum AC input voltage,
POUT: Maximum output power:
POUT = VOUT × IOUT
(19)
where VOUT is the output voltage, and IOUT is the maximum
output current,
fS(MIN): Operation frequency at the peak voltage of the sine
wave of AC input voltage (the minimum operation frequency in
quasi-resonant operation),
η: Efficiency rate: 80% to 90%,
CV: Voltage resonant capacitor (C3) rating: usually 47 to 470 pF
DON: Maximum duty cycle, not compensated for the quasiresonant delay time, at the minimum AC input voltage:
Ef
DON =
(20)
√2 × VINRMS(MIN) + Ef
VINRMS: Effective value (RMS) of sine wave of
AC input voltage
IIN
: Input current
IINP : Peak input current
ID
: Power MOSFET drain current
IDP
: Power MOSFET peak drain current
IS
: Forward current of a secondary side
rectifier
ISP
: Peak forward current of a secondary
side rectifier
Figure 32. Ideal current waveform
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
29
Ef : Flyback voltage:
Ef = (NP /NS) × (VOUT +Vf)
(21)
where NP is the number of turns of the primary winding, NS
is the number of turns of the secondary winding, and Vf is the
forward voltage of the secondary rectifier, D8, approximately
0.7 V.
Ef is determined by the power MOSFET breakdown voltage
and the surge voltage. Because the breakdown voltage of the
power MOSFET of this IC is 650 V, when it is used with the
specified universal input range, the target voltage of Ef is
100 to 150 V.
Quasi-resonant delay time, tONDLY:
(22)
tONDLY = √L'P × CV
When choosing a ferrite core to match the relationship of
NI-Limit (AT) versus AL-value, it is recommended to set the calculated NI-Limit value below about 30% from the NI-Limit curve
of ferrite core data, as shown in the hatched area containing the
design point in figure 33, to provide a design margin in consideration of temperature effects and other variations, as expressed by
the formulas below:
NI-Limit ≤ NP × IDP(DLY) × 130%
L'P
(27)
AL-Value
Then, the rest of the winding turns are determined by the formulas below.
NP =
NS =
Maximum duty cycle, compensated for quasi-resonant delay time
(tONDLY), D'ON:
D'ON = (1 – fS(MIN) × tONDLY) × DON
(23)
Input rms current of the sine wave of the minimum AC input
voltage, IINRMS(MAX):
POUT
(24)
η × VINRMS(MIN)
Peak drain current, compensated for quasi-resonant delay time
(tONDLY), IDP(DLY):
I INRMS(MAX) =
2√2 × POUT
I DP(DLY) =
(25)
η × D'ON × VIN(RMS(MIN)
In transformer design, the AL-value of the ferrite core should be
chosen so the transformer does not saturate, in consideration of
NI-Limit(AT) (= NP × IDP(DLY) ).
N I-Limit (AT)
Saturation
region lower
boundary
(26)
ND =
VOUT + Vf
× NP
Ef
VCC
× NS
VOUT + Vf
(28)
(29)
Trace and Component Layout Design
PCB circuit trace design and component layout affect IC functioning during operation. Unless they are proper, malfunction,
significant noise, and large power dissipation may occur.
Circuit loop traces flowing high frequency current, as shown in
figure 34, should be designed as wide and short as possible to
reduce trace impedance.
In addition, earth ground traces affect radiation noise, and thus
should be designed as wide and short as possible.
Switching mode power supplies consist of current traces with
high frequency and high voltage, and thus trace design and
component layout should be done in compliance with all safety
guidelines.
Furthermore, because an integrated power MOSFET is being
used as the switching device, take account of the positive thermal
coefficient of RDS(on) for thermal design.
Margin = 30% less
Design point
(example)
AL-Value (nH/T 2 )
Figure 33. Example of NI-Limit versus AL-Value characteristics
LC5540LD-AN, Rev. 1.7
Figure 34. High frequency current loops (hatched portion)
SANKEN ELECTRIC CO., LTD.
30
Figure 35 shows practical trace design examples and considerations. In addition, observe the following:
(3) Current Detection Resistor, ROCP:
• IC peripheral circuit
Place ROCP as close to the S/GND pin as possible. In addition,
in order to avoid interference of the switching current with the
control circuit, connect the trace of R3 to the base of ROCP at the
point A in figure 35.
(1) Traces among S/GND pin, ROCP , C2, T1(primary winding),
and D/ST pin
The traces carry the switching current; therefore, widen and
shorten them as much as possible.
• Secondary side, traces among T1(secondary winding), D8,
and C9
The input capacitor C2 must be placed close to the IC or the
transformer in order to reduce series inductances of the traces
against high frequency current.
The secondary-side switching current runs through this trace.
Widen and shorten the traces as much as possible.
(2) Traces among S/GND pin, C4(–), T1(auxiliary winding D),
R1, D5, C4(+), and VCC pin
This trace is for supplying voltage to the IC. Widen and shorten
the traces as much as possible. If the IC and the capacitor C4 are
apart, place a film or ceramic capacitor (0.1 to 1.0 μF) as close to
the VCC pin and the S/GND pin
as possible.
Thin and long traces cause the series inductance to be high and it
results in high surge voltage on the power MOSFET when it turns
off. Therefore, proper layout pattern design helps to increase the
voltage margin of the power MOSFET to its breakdown voltage
and to reduce power stress and losses in the clamping snubber
circuit.
Clamping snubber circuit
D8
T1
C8
P
R5
C2
C9
D9
6
8
D/ST
C3
D5
5
OVP
NC
S
NF
R1
PC2
D
C4
U1
Main circuit
LC554×LD
R6
S/GND VCC
OCP
1
3
2
C5
FB
GND circuit of control circuit
D6
4
Secondary rectification circuit
R7
R4
PC1 R21
C6
ROCP
D7
A
C7
C18 DZ3
C17
R3
Figure 35. An example schematic of a typical application circuit
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
31
• The contents in this document are subject to changes, for improvement and other purposes, without notice. Make sure that this is the
latest revision of the document before use.
• Application and operation examples described in this document are quoted for the sole purpose of reference for the use of the products herein and Sanken can assume no responsibility for any infringement of industrial property rights, intellectual property rights or
any other rights of Sanken or any third party which may result from its use.
• Although Sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and defect of semiconductor products at a certain rate is inevitable. Users of Sanken products are requested to take, at their own risk, preventative measures
including safety design of the equipment or systems against any possible injury, death, fires or damages to the society due to device
failure or malfunction.
• Sanken products listed in this document are designed and intended for the use as components in general purpose electronic equipment or apparatus (home appliances, office equipment, telecommunication equipment, measuring equipment, etc.).
When considering the use of Sanken products in the applications where higher reliability is required (transportation equipment and
its control systems, traffic signal control systems or equipment, fire/crime alarm systems, various safety devices, etc.), and whenever
long life expectancy is required even in general purpose electronic equipment or apparatus, please contact your nearest Sanken sales
representative to discuss, prior to the use of the products herein.
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(aerospace equipment, nuclear power control systems, life support systems, etc.) is strictly prohibited.
• In the case that you use Sanken products or design your products by using Sanken products, the reliability largely depends on the
degree of derating to be made to the rated values. Derating may be interpreted as a case that an operation range is set by derating the
load from each rated value or surge voltage or noise is considered for derating in order to assure or improve the reliability. In general,
derating factors include electric stresses such as electric voltage, electric current, electric power etc., environmental stresses such
as ambient temperature, humidity etc. and thermal stress caused due to self-heating of semiconductor products. For these stresses,
instantaneous values, maximum values and minimum values must be taken into consideration.
In addition, it should be noted that since power devices or IC's including power devices have large self-heating value, the degree of
derating of junction temperature affects the reliability significantly.
• When using the products specified herein by either (i) combining other products or materials therewith or (ii) physically, chemically
or otherwise processing or treating the products, please duly consider all possible risks that may result from all such uses in advance
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• The contents in this document must not be transcribed or copied without Sanken's written consent.
LC5540LD-AN, Rev. 1.7
SANKEN ELECTRIC CO., LTD.
32