SANKEN LC5513D

Application Information
LC5500 Series Single-Stage Power Factor Corrected
Off-Line Switching Regulators
Introduction
The LC5500 series is the power IC for the isolated type
LED driver which has an incorporated power MOSFET,
designed for input capacitorless applications, and making it
possible for systems to comply with the harmonics standard
(IEC61000-3-2 class C). The controller adapts the average
current control method for realizing high power factors, and
the quasi-resonant topology contributes to high efficiency
and low EMI noise. The series is housed in either DIP8 or
TO-220F-7L packages, depending on output power
capability. The rich set of protection features helps to realize low component counts, and high performance-to-cost
power supply.
Figure 1. The LC5500 series packages for lower wattage versions
are fully molded DIP8s, with pin 7 removed for greater isolation. For
higher wattages, the TO-220F-7L fully molded package is provided,
with three leadform options, all which provide a separation between
pins 1 and 2.
• DIP8 package (LC551xD/LC552xD) and TO-220F-7L
package (LC552xF)
• Integrated on-width control circuit (it realizes high power
factor by average current control)
• Integrated startup circuit (no external startup
circuit necessary)
• Integrated soft-start circuit (reduces power stress during
start-up on the incorporated power MOSFET and output
rectifier)
• Integrated bias assist circuit (improves the startup
performance, suppresses VCC voltage droop during
operation, allows reduction of VCC capacitor value as well
as use of a ceramic capacitor)
• Integrated Leading Edge Blanking (LEB) circuit
• Integrated maximum on-width limit circuit
• Dual-chip structure, with an avalanche-guaranteed power
MOSFET (allows simplified surge suppressing circuits)
• Protection features:
▫ Overcurrent protection (OCP): pulse-by-pulse
▫ Overvoltage protection (OVP): auto restart, OVPactivating pins vary by product series:
OVP-Activating Pins
Series
VCC
ISENSE
OVP
OCP
LC551xD
×
×
–
×
LC552xD
×
–
×
×
LC552xF
×
–
×
×
▫ Overload protection (OLP): auto restart
▫ Thermal shutdown (TSD): halts switching operation and
latches in the off-state
The product lineup for the LC5500 series provides the following options:
MOSFET
VDSS(min)
(V)
RDS(on)
(max)
(Ω)
LC5511D
3.95
LC5513D
1.9
LC5521D
LC5523D
650
LC5523F
LC5525F
Isolation
DIP8
3.95
1.9
1.1
Isolated
TO-220F7L
Part Number Assignment
POUT*
(W)
Package
Nonisolated
TO-220F-7L
(LF 3054)
TO-220F-7L
(LF 3052)
Features and Benefits
Part
Number
LC55nna
A
BC D
230 VAC
Universal
(Wide)
13
10
A
Product series name
20
16
B
13
10
Indicates non-isolated or isolated:
1 – Non-isolated, 2 – Isolated
20
16
C
On-resistance of the incorporated MOSFET:
1 – 3.95 Ω, 3 – 1.9 Ω, 5 – 1.1 Ω
60
40
80
55
D
Indicates the package:
D – DIP8, F – TO-220F-7L
*Based on the thermal rating; the allowable maximum output power can be up to
120% to 140% of this value. However, maximum output power may be limited in an
applications with low output voltage or short duty cycle.
LC5500-AN, Rev.1.2
TO-220F-7L
(LF 3051)
DIP8
SANKEN ELECTRIC CO., LTD.
Table of Contents
General Specifications
Block Diagrams and Pin Descriptions
Package Drawings
Electrical Characteristics
Application Circuit Examples
Operation Description
On-Width Control Operation
Startup Operation
Operation Modes at Startup
Soft-Start Function
Quasi-Resonant Operation and Bottom-On Timing
Latch Function
Overvoltage Protection (OVP)
Overload Protection (OLP)
Overcurrent Protection (OCP)
Input Compensation Function for Overcurrent Protection
OCP Threshold Voltage with and without the OCP Input
Compensation Circuit
Thermal Shutdown Protection
Maximum On-Width Limiting Function
Design Considerations
Peripheral Components
Transformer Design
Trace and Component Layout Design
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
1
3
5
9
15
17
17
19
21
21
22
25
26
30
32
33
33
35
35
35
35
35
37
2
Block Diagrams and Pin Descriptions
This section provides block diagrams and pin descriptions of:
• LC551xD for non-isolated DIP8 designs
• LC552xD for isolated DIP8 designs
• LC552xF for isolated TO-220-7L designs
VCC
②
Controller Chip
⑧ D/ST
START UP
TSD
UVLO
Reg
Drv
Bias
OVP
① S/GND
S
RQ
OCP ③
Bottom
Detection
NF ⑤
OCP
OSC
OLP
OTA
⑥ ISENSE
LEB
Feedback
Control
④ COMP
Reg
Figure 2. LC551xD series functional block diagram (for non-isolated DIP8 designs)
LC551xD Series Terminal List Table
Pin-out Diagram
(LC551xD)
S/GND 1
8 D/ST
VCC 2
OCP 3
COMP 4
LC5500-AN, Rev.1.2
6 ISENSE
5 NF
Number
Name
Function
1
S/GND
2
VCC
Supply voltage input and Overvoltage protection (OVP) signal input
3
OCP
Overcurrent Protection, quasi-resonant signal input terminal, and
Overvoltage Protection (OVP) signal input
4
COMP
5
NF
6
ISENSE
7
–
8
D/ST
MOSFET source and GND terminal for the Controller chip
Feedback phase-compensation input
No function; must be externally connected to S/GND pin with as short
a trace as possible, for stable operation of the IC
Output current sensing voltage input and Overvoltage Protection
(OVP) signal input
Pin removed
MOSFET drain terminal and input of the startup current
SANKEN ELECTRIC CO., LTD.
3
VCC
②
Controller Chip
STARTUP
TSD
UVLO
Drv
Bias
OVP
OVP ⑥
⑧ D/ST
Reg
① S/GND
S
RQ
OCP ③
Bottom
Detection
NF ⑤
OCP
OLP
OSC
LEB
Feedback
Control
④ FB
Reg
Figure 3. LC552xD series functional block diagram (for isolated DIP8 designs)
Pin-out Diagram
(LC552xD)
LC552xD Series Terminal List Table
8 D/ST
S/GND 1
VCC 2
7
OCP 3
6 OVP
5 NF
FB 4
Pin-out Diagrams
(LC552xF)
D/ST
2
NC
3
VCC
4
S/GND
2
VCC
Supply voltage input and Overvoltage protection (OVP) signal input
3
OCP
Overcurrent Protection, quasi-resonant signal input terminal, and
Overvoltage Protection (OVP) signal input
4
FB
Feedback signal input and Overload Protection (OLP) signal input
5
NF
No function; must be externally connected to S/GND pin with as short
a trace as possible, for stable operation of the IC
6
OVP
7
–
8
D/ST
MOSFET source and GND terminal for the Controller chip
Overvoltage Protection (OVP) signal input
Pin removed
MOSFET drain terminal and input of the startup current
VCC
④
Controller Chip
① D/ST
UVLO
Reg
Drv
Bias
OVP
OVP ⑦
② S/GND
S
RQ
5
6
OCP ⑤
7
D/ST
Bottom
Detection
OCP
1
3
(LF 3052)
5
6
OVP
LEB
⑥ FB
Reg
4
OCP
OLP
OSC
Feedback
Control
2
NC
FB
Function
STARTUP
(LF 3051)
OVP
VCC
1
TSD
OCP
S/GND
Name
1
S/GND
FB
Number
Figure 4. LC552xF series functional block diagram (for isolated TO-220F-7L designs)
LC552xF Series Terminal List Table
7
Number
Name
1
D/ST
2
S/GND
Function
MOSFET drain terminal and input of the startup current
1
D/ST
2
S/GND
3
NC
3
NC
4
VCC
Supply voltage input and Overvoltage protection (OVP) signal input
4
VCC
5
OCP
5
OCP
Overcurrent Protection, quasi-resonant signal input terminal, and
Overvoltage Protection (OVP) signal input
6
FB
7
OVP
6
FB
Feedback signal input and Overload Protection (OLP) signal input
7
OVP
LC5500-AN, Rev.1.2
(LF 3054)
MOSFET source and GND terminal for the Controller chip
No connection
Overvoltage Protection (OVP) signal input
SANKEN ELECTRIC CO., LTD.
4
Package Drawings
This section provides dimensioned drawings of the DIP8 and the
TO-220-7L packages.
9.4 ±0.3
8
5
LC
6.5 ±0.2
a
b
c
4
1
1.0 +0.3
-0.05
+0.3
1.52
-0.05
3.3 ±0.2
7.5 ±0.5
4.2 ±0.3
3.4 ±0.1
(7.6 TYP)
0.2 5 + 0.
- 0.01
5
０～１５° ０～１５°
2.54 TYP
0.89 TYP
0.5 ±0.1
Unit： mm
Leadframe Material： Cu
Pin treatment: Solder plating
Weight： Approximately 0.51g
Pb-free. Device composition compliant
with the RoHS directive.
a: Part #: 55xx
b: Lot number 3 digits, plus D
st
1 letter: Last digit of year
nd
2 letter: Month
Jan to September: Numeric
October: O
November: N
December: D
rd
3 letter: Week
Date 1 to 10: 1
Date 11 to 20: 2
Date 21 to 31: 3
c: Internal use control number
Figure 5. DIP8 package drawing
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
5
Leadform 3051
2.6 ±0.2
15 ±0.3
（5.6）
Gate burr
Ø3.2 ±0.2
4.2 ±0.2
2.8 +0.2
10 ±0.2
LC
（1.1）
a
2.6 ±0.1
（At base of pin）
10.4 ±0.5
7-0.62 ±0.15
+0.2
7-0.55 -0.1
R-end
R-end
+0.2
0.45 -0.1
5×P1.17±0.15
＝5.85±0.15
2 ±0.15
5±0.5
5±0.5
b
（At base of pin）
5.08±0.6
2.54±0.6
（At tip of pin）
（At tip of pin）
2
1
4
3
6
5
7
0.5
0.5
Front view
Unit: mm
Package: TO-220F-7L
Leadframe material: Cu
Pin treatment: Solder dip
Weight: Approximately 1.45 g
Note: "Gate Burr" shows area
where 0.3 mm (max) gate burr
may be present.
Pin treatment Pb-free. Device composition
compliant with the RoHS directive.
0.5
0.5
Side view
a: Part # 55xxF
b: Lot number
st
1 letter: Last digit of year
nd
2 letter: Month
Jan to September: Numeric
October: O
November: N
December: D
rd
th
3 and 4 letter: Date
01 to 31: Numeric
th
5 letter: Internal use control number
Figure 6. TO-220F-7L (Sanken leadform number 3051) package drawing
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
6
Leadform 3052
2.6 ±0.2
LC
15 ±0.3
（5.6）
Gate burr
Ø3.2 ±0.2
4.2 ±0.2
2.8 +0.2
10 ±0.2
a
（1.1）
2.6 ±0.1
（At base of pin）
5±0.5
b
10.4 ±0.5
7-0.62 ±0.15
+0.2
7-0.55 -0.1
0.45 +0.2
-0.1
5×P1.17±0.15
＝5.85±0.15
2 ±0.15
R-end
5.08±0.6
（At base of pin）
（At tip of pin）
0.5
0.5
Front View
1
0.5
0.5
Side View
2 3 4 5 6 7
Unit: mm
Package: TO-220F-7L
Leadframe material: Cu
Pin treatment: Solder dip
Weight: Approximately 1.45 g
Note: "Gate Burr" shows area
where 0.3 mm (max) gate burr
may be present.
a: Part # 55xxF
b: Lot number
st
1 letter: Last digit of year
nd
2 letter: Month
Jan to September: Numeric
October: O
November: N
December: D
rd
th
3 and 4 letter: Date
01 to 31: Numeric
th
5 letter: Internal use control number
Pin treatment Pb-free. Device composition
compliant with the RoHS directive.
Figure 7. TO-220F-7L (Sanken leadform number 3052) package drawing
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
7
2.8 ±0.2
Leadform 3054
2.6 ±0.2
a
b
2.8 ±0.5
（At tip of pin）
2.5 ±0.5
LC
15 ±0.3
(5.6)
Gate burr
4.2±0.2
Ø3.2 ±0.2
10 ±0.2
(1.1)
3-( R1)
2.6 ±0.1
（At base of pin）
（At base of pin）
0.5
（At tip of pin）
5×P 1.17 ±0.15
= 5.85 ±0.15
2 ±0.15
+0.2
0.45 -0.1
7-0.55 +0.2
-0.1
5 ±0.5
7-0.62 ±0.15
3.8±0.5
0.5
Plan View
1
0.5
0.5
Side View
2 3 4 5 6 7
Unit: mm
Package: TO-220F-7L
Leadframe material: Cu
Pin treatment: Solder dip
Weight: Approximately 1.45 g
Note: "Gate Burr" shows area
where 0.3 mm (max) gate burr
may be present.
a: Part # 55xxF
b: Lot number
st
1 letter: Last digit of year
nd
2 letter: Month
Jan to September: Numeric
October: O
November: N
December: D
rd
th
3 and 4 letter: Date
01 to 31: Numeric
th
5 letter: Internal use control number
Pin treatment Pb-free. Device composition
compliant with the RoHS directive.
Figure 8. TO-220F-7L (Sanken leadform number 3054) package drawing
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
8
Electrical Characteristics
This section provides separate sets of electrical characteristic
data, using representative examples (refer to individual datasheets for more details):
• LC551xD series (non-isolated): LC5513D is the example
• LC552xD series (isolated): LC5521D is the example
• LC552xF series (isolated): LC5523F is the example
Current direction is sink is positive (+) and source is negative (–) in reference to the IC.
LC5513D Absolute Maximum Ratings TA = 25°C, unless otherwise specified
Characteristic
Drain
Current1
Symbol
Notes
IDPeak
Pins
Rating
Unit
Single pulse
8–1
4.0
A
ILPeak = 2.7 A, VDD = 99 V, L = 20 mH
8–1
86
mJ
Single Pulse Avalanche Energy1
EAS
Supply Voltage for Controller Chip
VCC
2–1
35
V
OCP Pin Voltage
VOCP
3–1
−2.0 to 5.0
V
COMP Pin Voltage
VCOMP
4–1
−0.3 to 7.0
V
ISENSE Pin Voltage
VISEN
6–1
−0.3 to 5.0
V
Allowable Power Dissipation of
MOSFET2
PD1
8–1
0.97
W
Operating Ambient Temperature
TOP
―
−55 to 125
°C
Storage Temperature
Tstg
―
−55 to 125
°C
Channel Temperature
Tch
―
150
°C
1Refer
to each individual product datasheet for details.
on a 15 mm × 15 mm PCB.
2Mounted
LC5513D ELECTRICAL CHARACTERISTICS (MOSFET) TA = 25°C, unless otherwise specified
Characteristic
Drain-to-Source Breakdown Voltage1
Drain Leakage Current
On Resistance1
Switching
Time1
Thermal Resistance1,2
Symbol
Pins
Min.
Typ.
Max.
Unit
VDSS
Test Conditions
8–1
650
―
―
V
IDSS
8–1
―
―
300
μA
RDS(on)
8–1
―
―
1.9
Ω
tf
Rθch-c
Between channel and case
8–1
―
―
400
ns
―
―
―
35.5
°C/W
1Refer
2The
to each individual product datasheet for details.
thermal resistance between the channels of the MOSFET and the case. TC measured at the center of the case top surface.
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
9
LC5513D ELECTRICAL CHARACTERISTICS (Controller Chip) TA = 25°C, VCC = 20 V, unless otherwise specified
Characteristic
Symbol
Test Conditions
Pins
Min.
Typ.
Max.
Unit
Startup Operation
Operation Start Voltage
VCC(ON)
2–1
13.8
15.1
17.3
V
Operation Stop Voltage*
VCC(OFF)
2–1
8.4
9.4
10.7
V
ICC(ON)
2–1
–
–
3.7
mA
VSTARTUP
8–1
42
57
72
V
2–1
−5.5
−3.0
−1.0
mA
Operating Current
Startup Circuit Operation Voltage
Startup Current
ICC(STARTUP) VCC = 13 V
Startup Current Threshold Biasing
Voltage-1*
VCC(BIAS)1
2–1
9.5
11.0
12.5
V
Startup Current Threshold Biasing
Voltage-2
VCC(BIAS)2
2–1
14.4
16.6
18.8
V
fOSC
8–1
11.0
14.0
18.0
kHz
tON(MAX)
8–1
30.0
40.0
50.0
μs
VCOMP(MIN)
4–1
0.55
0.90
1.25
V
Normal Operation
PWM Operation Frequency
Maximum On-Width
COMP Pin Control Voltage
Lower Limit
Error Amplifier Reference Voltage
VSEN(th)
6–1
0.27
0.30
0.33
V
ISEN(SOURCE)
4–1
−11
−7
−3
μA
Error Amplifier Sink Current
ISEN(SINK)
4–1
3
7
11
μA
Leading Edge Blanking Time
tON(LEB)
3–1
−
500
−
ns
Quasi-Resonant Operation Threshold
Voltage-1
VBD(TH1)
3–1
0.14
0.24
0.34
V
Quasi-Resonant Operation Threshold
Voltage-2
VBD(TH2)
3–1
0.12
0.17
0.22
V
OCP Pin Overcurrent Protection
(OCP) Threshold Voltage
VOCP
3–1
−0.54
−0.60
−0.66
V
OCP Pin Source Current
IOCP
3–1
−120
−40
−10
μA
VBD(OVP)
3–1
2.2
2.6
3.0
V
Overload Protection (OLP) Threshold
Voltage-1
VCOMP(OLP)1
4–1
5.0
5.5
6.0
V
Overload Protection (OLP) Threshold
Voltage-2
VCOMP(OLP)2
4–1
4.1
4.5
4.9
V
ISENSE Pin OVP Threshold Voltage
VISEN(OVP)
6–1
1.6
2.0
2.4
V
VCC(OVP)
2–1
28.5
31.5
34.0
V
TJ(TSD)
–
135
–
–
°C
Error Amplifier Source Current
Protection Operation
OCP Pin Overvoltage Protection
(OVP) Threshold Voltage
VCC Pin OVP Threshold Voltage
Thermal Shutdown Activating
Temperature
*VCC(BIAS)1 > VCC(OFF) always.
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
10
LC5521D Absolute Maximum Ratings TA = 25°C, unless otherwise specified
Characteristic
Drain Current1
Single Pulse Avalanche
Symbol
Notes
IDPeak
Energy1
Single pulse
EAS
ILPeak = 2.0 A, VDD = 99 V, L = 20 mH
Pins
Rating
Unit
8–1
2.5
A
8–1
47
mJ
Supply Voltage for Controller Chip
VCC
2–1
35
V
OCP Pin Voltage
VOCP
3–1
−2.0 to 5.0
V
FB Pin Voltage
VFB
4–1
−0.3 to 7.0
V
OVP Pin Voltage
VOVP
6–1
−0.3 to 5.0
V
Allowable Power Dissipation of
MOSFET2
PD1
8–1
0.97
W
Operating Ambient Temperature
TOP
―
−55 to 125
°C
Storage Temperature
Tstg
―
−55 to 125
°C
Channel Temperature
Tch
―
150
°C
1Refer
to each individual product datasheet for details.
2Mounted on a 15 mm × 15 mm PCB.
LC5521D ELECTRICAL CHARACTERISTICS (MOSFET) TA = 25°C, unless otherwise specified
Pins
Min.
Typ.
Max.
Drain-to-Source Breakdown Voltage1
Characteristic
VDSS
8–1
650
―
―
V
Drain Leakage Current
IDSS
8–1
―
―
300
μA
On Resistance1
RDS(on)
8–1
―
―
3.95
Ω
Switching Time1
tf
8–1
―
―
250
ns
―
―
―
42
°C/W
Thermal Resistance1,2
Symbol
Rθch-c
Test Conditions
Between channel and case
Unit
1Refer
to each individual product datasheet for details.
2The thermal resistance between the channels of the MOSFET and the case. T measured at the center of the case top surface.
C
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
11
LC5521D ELECTRICAL CHARACTERISTICS (Controller Chip) TA = 25°C, VCC = 20 V, unless otherwise specified
Characteristic
Symbol
Test Conditions
Pins
Min.
Typ.
Max.
Unit
Startup Operation
Operation Start Voltage
VCC(ON)
2–1
13.8
15.1
17.3
V
Operation Stop Voltage*
VCC(OFF)
2–1
8.4
9.4
10.7
V
ICC(ON)
2–1
–
–
3.7
mA
VSTARTUP
8–1
42
57
72
V
2–1
−5.5
−3.0
−1.0
mA
Operating Current
Startup Circuit Operation Voltage
Startup Current
ICC(STARTUP) VCC= 13 V
Startup Current Threshold Biasing
Voltage-1*
VCC(BIAS)1
2–1
9.5
11.0
12.5
V
Startup Current Threshold Biasing
Voltage-2
VCC(BIAS)2
2–1
14.4
16.6
18.8
V
fOSC
8–1
11.0
14.0
18.0
kHz
Maximum On-Width
tON(MAX)
8–1
30.0
40.0
50.0
μs
FB Pin Voltage Minimum Limit
VFB(MIN)
4–1
0.55
0.90
1.25
V
Normal Operation
PWM Operation Frequency
Maximum Feedback Current
IFB(MAX)
4–1
−10
−25
−40
μA
Leading Edge Blanking Time
tON(LEB)
3–1
−
500
−
ns
Quasi-Resonant Operation Threshold
Voltage-1
VBD(TH1)
3–1
0.14
0.24
0.34
V
Quasi-Resonant Operation Threshold
Voltage-2
VBD(TH2)
3–1
0.12
0.17
0.22
V
OCP Pin Overcurrent Protection
(OCP) Threshold Voltage
VOCP
3–1
−0.54
−0.60
−0.66
V
OCP Pin Source Current
IOCP
3–1
−120
−40
−10
μA
OCP Pin Overvoltage Protection
(OVP) Threshold Voltage
VBD(OVP)
3–1
2.2
2.6
3.0
V
Overload Protection (OLP) Threshold
Voltage-1
VFB(OLP)1
4–1
5.0
5.5
6.0
V
Overload Protection (OLP) Threshold
Voltage-2
VFB(OLP)2
4–1
4.1
4.5
4.9
V
OVP Pin OVP Threshold Voltage
VOVP(OVP)
6–1
1.6
2.0
2.4
V
VCC Pin OVP Threshold Voltage
VCC(OVP)
2–1
28.5
31.5
34.0
V
TJ(TSD)
–
135
–
–
°C
Protection Operation
Thermal Shutdown Activating
Temperature
*V
CC(BIAS)1
> VCC(OFF) always.
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
12
LC5523F Absolute Maximum Ratings TA = 25°C, unless otherwise specified
Characteristic
Drain Current*
Symbol
Notes
IDPeak
Single pulse
Pins
Rating
Unit
1–2
9.2
A
Single Pulse Avalanche Energy*
EAS
1–2
99
mJ
Supply Voltage for Controller Chip
VCC
4–2
35
V
OCP Pin Voltage
ILPeak = 2.9 A, VDD = 99 V, L = 20 mH
VOCP
5–2
−2.0 to 5.0
V
FB Pin Voltage
VFB
6–2
−0.3 to 7.0
V
OVP Pin Voltage
VOVP
7–2
−0.3 to 5.0
V
With infinite heatsink
1–2
20.2
W
Without heatsink
1–2
1.8
W
TF
―
−20 to 115
°C
Operating Ambient Temperature
TOP
―
−55 to 115
°C
Storage Temperature
Tstg
―
−55 to 125
°C
Channel Temperature
Tch
―
150
°C
Allowable Power Dissipation of
MOSFET*
PD1
Internal Frame Temperature in
Operation
*Refer to each individual product datasheet for details.
LC5523F ELECTRICAL CHARACTERISTICS (MOSFET) TA = 25°C, unless otherwise specified
Pins
Min.
Typ.
Max.
Drain-to-Source Breakdown Voltage1
Characteristic
VDSS
1–2
650
―
―
V
Drain Leakage Current
IDSS
1–2
―
―
300
μA
On Resistance1
RDS(on)
1–2
―
―
1.9
Ω
Switching Time1
tf
1–2
―
―
400
ns
―
―
―
3.1
°C/W
Thermal Resistance1,2
Symbol
Rθch-F
Test Conditions
Between channel and internal frame
Unit
1Refer
to each individual product datasheet for details.
2The thermal resistance between the channels of the MOSFET and the case. T measured at the center of the case top surface.
C
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
13
LC5523F ELECTRICAL CHARACTERISTICS (Controller Chip) TA = 25°C, VCC = 20 V, unless otherwise specified
Characteristic
Symbol
Test Conditions
Pins
Min.
Typ.
Max.
Unit
Startup Operation
Operation Start Voltage
VCC(ON)
4–2
13.8
15.1
17.3
V
Operation Stop Voltage*
VCC(OFF)
4–2
8.4
9.4
10.7
V
ICC(ON)
4–2
–
–
3.7
mA
VSTARTUP
1–2
42
57
72
V
4–2
−5.5
−3.0
−1.0
mA
Operating Current
Startup Circuit Operation Voltage
Startup Current
ICC(STARTUP) VCC = 13 V
Startup Current Threshold Biasing
Voltage-1*
VCC(BIAS)1
4–2
9.5
11.0
12.5
V
Startup Current Threshold Biasing
Voltage-2
VCC(BIAS)2
4–2
14.4
16.6
18.8
V
fOSC
1–2
11.0
14.0
18.0
kHz
Maximum On-Width
tON(MAX)
1–2
30.0
40.0
50.0
μs
FB Pin Voltage Minimum Limit
VFB(MIN)
6–2
0.55
0.90
1.25
V
Normal Operation
PWM Operation Frequency
Maximum Feedback Current
IFB(MAX)
6–2
−10
−25
−40
μA
Leading Edge Blanking Time
tON(LEB)
5–2
–
500
–
ns
Quasi-Resonant Operation Threshold
Voltage-1
VBD(TH1)
5–2
0.14
0.24
0.34
V
Quasi-Resonant Operation Threshold
Voltage-2
VBD(TH2)
5–2
0.12
0.17
0.22
V
OCP Pin Overcurrent Protection
(OCP) Threshold Voltage
VOCP
5–2
−0.54
−0.60
−0.66
V
OCP Pin Source Current
Protection Operation
IOCP
5–2
−120
−40
−10
μA
OCP Pin Overvoltage Protection
(OVP) Threshold Voltage
VBD(OVP)
5–2
2.2
2.6
3.0
V
Overload Protection (OLP) Threshold
Voltage-1
VFB(OLP)1
6–2
5.0
5.5
6.0
V
Overload Protection (OLP) Threshold
Voltage-2
VFB(OLP)2
6–2
4.1
4.5
4.9
V
OVP Pin OVP Threshold Voltage
VOVP(OVP)
7–2
1.6
2.0
2.4
V
VCC Pin OVP Threshold Voltage
VCC(OVP)
4–2
28.5
31.5
34.0
V
TJ(TSD)
–
135
–
–
°C
Thermal Shutdown Activating
Temperature
*VCC(BIAS)1 > VCC(OFF) always.
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
14
Application Circuit Examples
This section provides typical application circuits, using representative examples (refer to individual datasheets for more details):
• LC551xD series (non-isolated)
• LC552xD series (isolated)
• LC552xF series (isolated)
F1
VAC
L1
D1
D2
D3
D4
C11
T1
L2
C1
C8
D8
R5
C2
D9
D5
U1
LC551x D
8
R6
C10
R7
R1
R8
C12
S/GND
4
COMP
D/ST
LED
DZ1
C9
5
NC
C4
C3
Controller
Chip
D6
S/GND VCC OCP ISENSE
1
2
3
6
R4
C6
C5
R2
(Rocp)
C7
D7
R3
Figure 9. Non-isolated application circuit example, with LC551xD series device
F1
VAC
L1
C11
D1
D2
D3
D4
T1
L2
C1
C8
D8
R5
R8 R10
PC2
C2
C9
Q1
C10
D5
U1
LC552xD
8
6
D/ST
R1
R9
S/GND
5
NC
OVP
PC1
R11
R12
C13
C4
DZ2
PC2
C3
Controller
Chip
D6
R14
R17
R15
R18
-
DZ1
C12
R6
LED
R13
D9
C17
U2
+
C14
C15
R16
C16
R19 R20
S/GND VCC OCP FB
1
2
3
4
R7
C5
R2
(Rocp)
R4
PC1
C6
D7
C7
R3
Figure 10. Isolated application circuit example, with LC552xD series device
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
15
F1
VA C
L1
D1
D2
D3
D4
C11
T1
L2
C1
C8
D8
R5
C2
C9
D9
U1
LC552xF
D5
Vcc
R10
PC2
C10
R1
R9
PC1
DZ1
D6
C17
LED
R13
R11
C13 R17
DZ2
PC2
R6
Q1
R12
C4
Controller
Chip
R8
C12 U2
+
C14
R14
R15
R18
C15
R19 R20
R16
C16
D/ST S/GND NC VCC OCP FB OVP
1
2
3 4
5
6
7
R7
C3
C5
R2
(Rocp)
R4
C6
PC1
D7
C7
R3
Figure 11. Isolated application circuit example, with LC552xF series device
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
16
Operation Description
All of the parameter values used in these descriptions are typical values, unless they are specified as minimum or maximum.
This section describes IC operations as it is used for LED lighting
power supply applications. About current direction, "+" indicates
sink current toward the IC and "–" indicates source current from
the IC. The pin numbers parenthesized represent LC552xF numbers.
LC551xD
ISE NSE
S/GND
1
COMP
OCP
3
R OCP
6
4
C6
D7
On-Width Control Operation
R3
LC551xD series (non-isolated designs) Figure 12 shows the
peripheral circuit at the COMP pin of the LC551xD, and figure 13
shows the on-width control. The output control is done by voltage
mode control, which controls on-width depending on output load,
and average current control.
As showed in figure 13, in the average current control operation,
the output current detection resistor voltage is compared against
the reference voltage by the OTA circuit, and its output is averaged at COMP pin. This voltage is compared against the internal
oscillator (OSC) by the FB comparator in order to control the
on-width for the average current control operation. Here, OSC
indicates the oscillator circuit, which controls the PWM operation
frequency, quasi-resonant oscillation, and the maximum on-width
limit.
For the LC551xD devices, the recommended value of C6, which
is connected to the COMP terminal, is approximately 2.2 μF.
Figure 12. COMP pin peripheral circuit
LC551xD
COMP pin
voltage
OSC
–
FB
4
+
COMP
Gate
on-width
S/GND
–
OTA
+
1
Current
detection
resistor
LED
ISENSE 6
The constant output current control of the output is done as
below:
• When the output load current becomes less than the target value,
the ISENSE pin voltage becomes low. This causes the averaged
OTA circuit output voltage at the COMP pin to become high,
which increases the on-width and the output current.
• When the output current becomes greater than the target value,
the circuits operate in the opposite way. The averaged voltage
at the COMP pin becomes low, and reductions result in the
on-width and the output current.
Figure 14 shows the average input current waveform. The averaged COMP pin voltage becomes constant, and the duty cycle
control becomes based on the EIN voltage (C2 voltage in figure 9).
It makes an averaged input current sine waveform which realizes
a high power factor.
OSC
VCOMP
Gate on-width
Drain current
Figure 13. On-width control, LC551xD series
LC552xD and LC552xF series (isolated designs) Figure 15
shows the peripheral circuit at the FB pin of the LC552xD/
LC552xF, and figure 16 shows the on-width control. The output
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
17
COMP pin voltage
S/GND
EIN
Drain current
Averaged input current
Figure 14. Averaged input current waveform, LC551xD series
control is done by voltage mode control, which controls on-width
depending on output load, and average current control.
As showed in figure 16, in the average current control operation,
the output current detection resistor voltage is compared by the
operational amplifier, and its output is sent to the FB pin in conjunction with the opto-coupler and averaged at the FB pin. The
FB pin voltage is compared against the internal oscillator (OSC)
by the FB comparator in order to control the on-width for averaged current control operation. Here, OSC indicates the oscillator
circuit, which controls the PWM operation frequency, quasiresonant oscillation, and the maximum on-width limit. For the
LC552xD and LC552xF series devices, the recommended value
of C6, which is connected to the FB pin, is approximately 2.2 μF.
FB
LC552xD
(LC552xF)
S/GND
1(2)
C6
D7
R3
Figure 15. FB pin peripheral circuit
LC552xD
(LC552xF)
FB pin
voltage
OSC
• When the output current becomes more than the target value, the
circuits operate in the opposite way The averaged voltage at the
FB pin becomes low, which reduces the on-width and the output
current.
Figure 17 shows the average input current waveform. The averaged FB pin voltage becomes constant, and the duty cycle control
becomes based on the EIN voltage (C2 voltage in figures 10 and
11). It makes an averaged input current sine waveform which
realizes a high power factor.
PC1
OCP
3(5)
R OCP
The constant output current control of the output is done as below.
• When the output load current becomes less than the target value,
the secondary current detection resistor voltage becomes low
and it results in low feedback current from the opto-coupler. It
causes the averaged voltage at the FB pin to become high, and
results in increases of the on-width and the output current.
4(6) R7
–
+
Gate
on-time
4(6)
FB
C6
S/GND
LED
R7
1(2)
PC
–
+
Current
detection
resistor
OSC
VFB
Gate on-time
Drain current
Figure 16. On-width control, LC552xD and LC552xF series
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
18
FB pin voltage
S/GND
Drain current
Averaged input current
EIN
Figure 17. Averaged input current waveform, LC552xD and LC552xF series
Startup Operation
Figure 18 shows the VCC pin peripheral circuit. The integrated
startup circuit is connected to the D/ST pin, and it generates a
constant current, ICC(STARTUP) = –3.0 mA, to charge capacitor C4
at the VCC pin. During this process, when VCC voltage reaches
VCC(ON) = 15.1 V, the IC starts operation, and when its voltage
exceeds VCC(BIAS)2 = 16.6 V, the startup circuit stops, in order to
eliminate its own power consumption.
L2
C2
P
The startup time is determined by the C4 capacitance and is
expressed by the formula below:
(1)
LC55xxD
(LC552xF)
where
tSTART is the startup time (s), and
VCC(INIT) is the VCC pin initial voltage (V).
A ceramic or film capacitor can be used for C4, and a value of
0.22 to 22 μF is generally recommended.
Figure 19 shows the relationship between VCC voltage and the
operating current, ICC . When VCC voltage reaches VCC(ON) =
15.1 V, the Controller circuit operation begins and the operating
current increases. After that, if VCC voltage decreases to VCC(OFF)
= 9.4 V, the Undervoltage Lockout (UVLO) circuit stops Controller circuit operation, and the operation state returns to the startup
phase.
VCC
D5
2(4)
R1
VD D
C4
S/GND 1(2)
Figure 18. VCC pin peripheral circuit
ICC
ICC(ON) (max)
= 3.7mA
After the control circuit starts up, the auxiliary winding (D in
figure 18) voltage, rectified by diode D5, powers the VCC pin.
Startup
|ICC(STARTUP)|
8(1)
D/ST
Stop
tSTART ≈ C4
VCC(ON) – VCC(INIT)
VCC voltage must satisfy these conditions:
VCC(BIAS)1(max) = 12.5 V < VCC < VCC(OVP)(min) = 28.5 V
Initially, target 20 V in a transformer design, and then optimize its
winding turns in a way that VCC voltage stays within that specified range over the conceivable input voltage range and output
load conditions.
LC5500-AN, Rev.1.2
9.4 V
VCC(OFF)
15.1 V
VCC(ON)
VCC pin
voltage
Figure 19. VCC versus operation current, ICC
SANKEN ELECTRIC CO., LTD.
19
Figure 20 shows the VCC voltage behavior at the startup phase.
Immediately after the controller circuit starts operation, the auxiliary winding voltage, VD , has not yet reached its design target
value, which is determined by the transformer auxiliary winding
turns. Therefore, as shown figure 20, VCC voltage starts decreasing after the startup circuit turns off at VCC(BIAS)2 = 16.6 V. After a
while, if the VCC voltage reaches the Startup Current Threshold
Biasing Voltage-1, VCC(BIAS)1 = 11.0 V, the bias assisting function
is activated in order to avoid further voltage drop and VCC voltage
becomes nearly constant. Thanks to this function, the C4 value can
be small, which results in shortening the startup period and improving the response time of the VCC pin overvoltage protection.
VCC pin
voltage
VCC(BIAS)2 = 16.6 V
VCC(ON) = 15.1 V
Startup
successful
VCC(BIAS)1 = 11.0 V
Bias assisting
VCC(OFF) = 9.4 V
Startup failure
Time
Figure 21 shows the positive dependency of VCC voltage on
output current. This is caused by the surge voltage, which occurs
on the D/ST pin at the turn-off edge of the incorporated power
MOSFET. The surge voltage is coupled to the auxiliary winding
and it charges-up C4 more than the design target. In order to avoid
this, insert R1 in series with D5 as shown in figure 22, and choose a
value for it between several ohms to several tenths of ohms.
Figure 20. VCC at startup period
VCC pin
voltage
In addition, the transformer winding structure has influence on
VCC fluctuation and the two items below are examples of worsening it:
• Poor coupling between the primary and secondary windings
(this causes high surge voltage and is seen in a design with low
output voltage and high output current).
• Poor coupling between the secondary winding and the auxiliary
winding D (this increases the effect of the surge voltage on the
auxiliary winding voltage).
Against those items, the two items below are commonly used
as techniques for improvement (its construction with triple
insulation wires as primary winding and/or secondary winding,
and without margin region):
• Separate the auxiliary winding D from the primary windings
P1 and P2 (figure 23(A)); P1 and P2 are two separated primary
windings.
• Place the auxiliary winding D within the secondary winding
S1 in order to improve the coupling of those windings (figure
23(B)); S1 is the secondary output winding.
Without R1
With R1
IOUT
Figure 21. VCC versus IOUT with and without resistor R1
D5
2(4)
Vcc
LC55xxD
(LC55xxF)
R1
Added
D
C4
S/GND
1(2)
Figure 22. VCC pin peripheral circuit with R1
Bobbin
Core
Operation start
Startup circuit off
Bobbin
P1, P2: Primary Winding
S1: Secondary Winding
D: Auxiliary winding
P1 S1 P2 S1 D
Core
P1 S1 D S1 P2
(A)
P1, P2: Primary Winding
S1: Secondary Winding
D: Auxiliary winding
(B)
Figure 23. Transformer winding structures: (A) auxiliary winding apart from
the primary windings, and (B) auxiliary winding within secondary winding
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
20
Operation Modes at Startup
Figure 24 shows the operation modes during the startup phase of
the LC551xD, and figure 25 shows those for the LC552xD and
LC552xF. Note that OCP pin voltage, which determines the timing of quasi-resonant operation, is in positive voltage on the OCP
pin, in reference to the S/GND pin.
During two periods below at startup, IC operation is set to PWM,
with fOSC = 14 kHz:
• While the COMP pin voltage (for LC551xD) and FB pin voltage (for LC552xD and LC552xF), in reference to S/GND, are
0 to 0.9 V (the control voltage lower limit for the COMP pin,
VCOMP(MIN), and FB pin, VFB(MIN) ): During this period, on-width
is fixed at the Leading Edge Blanking Time, tBW = 500 ns.
• Until the quasi-resonant signal (OCP pin voltage) reaches the
Quasi-Resonant Operation Threshold Voltage-1, VBD(TH1) =
0.24 V: During this period, the output voltage is low; therefore,
the auxiliary winding voltage, VD , is low. Thus the quasi-resonant signal is low.
After those startup operations the output voltage starts increasing,
when the OCP pin voltage reaches VBD(TH1) = 0.24 V, the IC is
switched to quasi-resonant operation (figure 26).
Soft-Start Function
The soft-start function reduces power stress on the incorporated
MOSFET and secondary rectifier during the startup phase.
LC551xD series (non-isolated designs) The soft-start operation
begins when the COMP pin voltage reaches VCOMP(MIN) = 0.9 V
and lasts until the output current becomes constant. During that
period, the output power gradually increases.
During this period, check the items below:
• VCC pin voltage does not drop to the Operation Stop Voltage,
VCC(OFF)
• Output current reaches the target value before the overload protection (OLP) is activated by the COMP pin voltage reaching
VCOMP(OLP)2 = 4.5 V
Soft-Start Period
Soft-Start Period
COMP Pin
Voltage
FB Pin
Voltage
IC turn on
VCOMP(MIN) = 0.90 V
IC turn on
VFB (MIN) = 0.90 V
S/GND
S/GND
VCC Pin
Voltage
VCC Pin
Voltage
VCC (BIAS )1 = 11.0 V
Target
Current
Output (LED)
Current, IOUT
VCC (BIAS )1 = 11.0 V
S/GND
Constant current operation
S/GND
Target
Current
Output (LED)
Current, IOUT
Constant current operation
GND(IOUT)
GND(IOUT)
Drain
Current, ID
Drain
Current, ID
t ON = tBW(500 ns)
t ON = tBW(500 ns)
GND(ID )
GND(ID )
PWM
PWM
(QR)
(QR)
Duration
Duration
Figure 24. Soft-start operation waveforms at startup (LC551xD)
Figure 25. Soft-start operation waveforms at startup (LC552xD/ LC552xF)
PWM operation Quasi-resonant operation (QR)
VBD(TH1)
OCP Pin
Voltage
S/GND
Drain
Current, ID
GND(ID)
Figure 26. OCP Pin Voltage (with time scale expanded)
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
21
LC552xD/LC552xF series (isolated designs) The soft-start oper-
ation begins when the FB pin voltage reaches VFB(MIN) = 0.9 V
and lasts until the output current becomes constant. During that
period, the output power gradually increases.
During this period, check the items below:
• VCC pin voltage does not drop to the Operation Stop Voltage,
VCC(OFF)
t ONDLY
• Output current reaches the target value before the overload
protection (OLP) is activated by the FB pin voltage reaching
VFB(OLP)2 = 4.5 V
Quasi-Resonant Operation and Bottom-On
Timing
I OFF
When the primary side MOSFET keeps turning off after the
energy is transferred to the secondary, the MOSFET drain node
begins free oscillation based on the transformer LP , and CV across
the drain and source pins, after the energy is completely transferred to the secondary. The quasi-resonant operation is the VDS
bottom-on operation that turns on the MOSFET at the bottom
point of VDS free oscillation. Because of that, switching loss and
switching noise are reduced. Therefore, highly efficient and low
noise converters can be realized. Figure 28 shows an ideal VDS
waveform of this mode. Turning on the MOSFET at the bottom
of VDS is done by creating certain duration, delay time tONDLY , as
figure 28 shows from the start of VDS free oscillation. This delay
time is created by exploiting the auxiliary winding voltage, which
synchronizes to the drain voltage VDS waveform and it is called
the quasi-resonant signal.
ID
tON
Half cycle of free oscillation, tONDLY
ID
NS
LP
V OUT
I OFF
EIN
Ef:
COUT
LC5500-AN, Rev.1.2
Flyback voltage
NP
NS
(VOUT + Vf)
NP:
Number of turns in the primary winding
NS:
Number of turns in the secondary winding
(2)
Output voltage
Vf:
Forward voltage of the secondary rectifier
ID:
Drain current of the power MOSFET
IOFF:
Figure 27. Basic flyback converter circuit
Input voltage
Ef =
VOUT:
CV
≈ √ L P × CV
Figure 28. Waveforms of the ideal Bottom-On mode
EIN:
NP
EIN
Bottom
Point
Figure 27 shows a basic circuit diagram of a flyback converter, in
which the energy of the transformer is transferred to the secondary side after the primary side MOSFET turns off.
Ef
Ef
VDS
Current running through the secondary rectifier during
the power MOSFET off-period
CV:
Voltage resonant capacitor
LP:
Primary inductance
SANKEN ELECTRIC CO., LTD.
22
Figure 29 shows the OCP pin peripheral circuit. D6, R4, C7 and
D7 form a delay circuit, and the auxiliary winding flyback voltage, Erev1 , is fed through the delay circuit and provides positive
voltage, the quasi-resonant signal, to the OCP pin. Figure 30
shows the forward voltages versus the power supply.
T1
EIN
P
C2
Clamping snubber
EIN EF
D5
8(1)
D/ST
C3
2(4)
C4
R1
D6
Efw1
V CC
R4
LC5500
Erev 1
D
OCP 3(5)
S/GND
1(2)
Forward voltage
Flyback voltage
D7
R3
C5
C7
VBD
ROCP
After the power MOSFET turns off, the quasi-resonant signal
immediately goes up and it exceeds the Quasi-Resonant Operation Threshold Voltage-1, VBD(TH1) = 0.24 V. After this occurs,
the power MOSFET remains off until the quasi-resonant signal comes down enough to cross the Quasi-Resonant Operation Threshold Voltage-2, VBD(TH2) = 0.17 V. Then the power
MOSFET again turns on. In addition, at the point, the threshold
voltage goes up to VBD(TH1) automatically to prevent malfunction
of the quasi-resonant operation from noise interference..
During that period, C7 must cause a delay time, tONDLY , such
that the power MOSFET turns on at the bottom point of VDS ; so
select an appropriate C7 value. R3 is recommended to be between
100 and 330 Ω, and C5 to be between 100 and 470 pF.
R4 must set the range for the quasi-resonant signal: greater than
or equal to VBD(TH1) under input and output conditions where VCC
becomes lowest, but less than the OCP Pin Overvoltage Protection (OVP) Threshold Voltage, VOCP(OVP) = 2.6 V, under conditions where VCC becomes highest. Figure 31 defines the pulse
width of the quasi-resonant signal. For initiating quasi-resonant
operation, the quasi-resonant signal pulse width between the
two points VBD(TH1) and VBD(TH2) , tQR, must be equal to 1.2 μs
or more. This pulse width must be ensured, while at the same
time the OCP pin peak voltage, VBD(PK) , is recommended to
be between 1.5 and 2.0 V. Both conditions should be satisfied
throughout the power supply input and output ranges, over variations in R3 and R4 actual component values.
Figure 29. OCP pin peripheral circuit
VD
VBD(PK), 1.5 to 2.0 V recommended, but less than 2.6 V
Erev1
Auxiliary
winding
0
voltage
V BD(TH1) = 0.34 V (max)
Efw1
V BD(TH2 ) = 0.22 V (max)
S/GND
tON
VBD
Quasiresonant
signal
VBD(TH1)
Pulse width, t QR ≥ 1.2 μs
VBD(TH2)
0
Figure 30. Auxiliary winding voltage and quasi-resonant signal
LC5500-AN, Rev.1.2
Figure 31. Definition of the pulse width of the quasi-resonant signal
SANKEN ELECTRIC CO., LTD.
23
The formula below is used to calculate R4:
R4 =
R3 (VCC – VBD(PK) – 2Vf )
250 ns (max) to avoid reacting to it, but if the surge voltage continues longer than that period, the IC responds to it and repeatedly turns the power MOSFET on and off at high frequency.
This results in an increase of the MOSFET power dissipation and
temperature, and it can be damaged.
(3)
VBD(PK)
given R3 = 220 Ω, VBD(PK) = 1.5 V, VCC = 16 V, and the Vf of D6
and D7 = 0.8 V. R4 is approximately 1.89 kΩ, and it is 1.8 kΩ in
the E12 series.
If this phenomenon is observed, countermeasures include:
If the pulse width is not satisfied, increase R3 or decrease R4, in
order to raise VBD(PK) . Alternatively, increasing the capacitance of
resonant capacitor C3 is also effective because it widens the free
oscillation period. However, it causes an additional switching loss
increase; therefore, ensure the IC temperature rise is acceptable.
Figure 32 shows two different OCP pin waveforms, comparing
transformer coupling conditions between the primary and secondary winding. The poor coupling tends to happen in a low output
voltage (small number of LEDs) transformer design with high
NP / NS turns ratio (NP and NS indicate the number of turns of the
primary winding and secondary winding, respectively), and it
results in high leakage inductance. The poor coupling causes high
surge voltage ringing at the power MOSFET drain pin when it
turns off. That high surge voltage ringing is coupled to the auxiliary winding and then the inappropriate quasi-resonant signal, as
in figure 32B, is created. The OCP pin has a blanking period of
• Place C5 as close to the OCP and S/GND pins as possible
• Separate the loop trace between the OCP pin and the S/GND
pin from any high current trace
• Loosen the transformer coupling between the auxiliary winding
and primary winding
• Reinforce the clamping snubber circuit to reduce the surge
voltage
In addition, the OCP pin waveform during operation should be
measured by connecting test probes with leads to the OCP pin
and the GND pin as short as possible, in order to measure any
surge voltage correctly.
Timing adjustment of the bottom-on is done by selecting the value
of C7 (figure 29). To do so, observe the power MOSFET drain
voltage, VDS , the drain current, ID , and the quasi-resonant signal.
Then optimize the C7 value to adjust the delay time of tONDLY so
that the MOSFET turns on at the bottom point of VDS.
VOCP(OVP) = 2.6 V
VBD(TH1) = 0.24 V
VBD(TH2) = 0.17 V
S/GND
(A) Proper OCP Voltage, Erev2
OCP pin blanking
time, 250 ns (max)
(B) Inappropriate OCP Voltage, Erev2
Figure 32. OCP pin waveform of a poorly coupled transformer (B)
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
24
As shown in figure 33:
• If the turn-on point is earlier than the bottom of the VDS signal,
it causes higher switching losses. In that situation, delay the
turn-on point by increasing the C7 value.
• In the converse situation, if the turn-on point is later than the
VDS bottom point, it also causes higher switching losses, but in
that case, advance the turn-on point by decreasing the C7 value.
Latch Function
Thermal shutdown (TSD) protection is latched. When the latch
circuit is activated, the IC stops switching operation, and therefore the VCC voltage declines.
However, the startup circuit turns on again when VCC reaches
VCC(BIAS)1 = 11.0 V, in order to avoid reaching the operation stop-
AC mains frequency (50 Hz / 60 Hz)
2 × AC mains frequency
VDS (peak)
VDS
E IN(max)
GND
Turn-on occurring before the VDS bottom point
Turn-on occurring after the VDS bottom point
Early turn-on point
Delayed turn-on point
V DS
V DS
Bottom point
Bottom point
Free oscillation, fR
I OFF
Free oscillation, fR
I OFF
ID
ID
t ON
t ON
VBD(TH1)
VBD(TH2)
VOCP
Auxiliary
Winding
Voltage
S/GND
S/GND
VBD(TH1)
VBD(TH2)
VOCP
Auxiliary
Winding
Voltage
S/GND
S/GND
1
fR ≈ 2 √ L × C
P
V
Figure 33. Effects of failure to turn on precisely at the VDS bottom point: (left) turn-on too early, (right) turn-on too late
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
25
ping voltage, VCC(OFF) = 9.4 V. Thus IC operation in latch mode
is maintained. To release the IC from latch mode, cut off the AC
mains and let VCC voltage drop below VCC(OFF).
Overvoltage Protection (OVP)
LC551xD series (non-isolated designs) The LC551xD series
has three OVP activation methods link to the VCC pin, to the
OCP pin, and to the ISENSE pin:
• VCC Pin Overvoltage Protection. figure 34 shows the waveforms of the OVP function on the VCC pin. When the VCC pin
voltage with reference to the S/GND pin reaches and exceeds
VCC(OVP) = 31.5 V, OVP is activated and the IC stops switching
operation. During this function, the bias assist function is disabled, and the VCC voltage decreases to VCC(OFF) = 9.4 V. After
that, the startup circuit is activated, and the operation begins
intermittent operation by repeating the restart and operation process as long as the OVP condition remains.
In addition, because VCC voltage is proportional to the output
voltage, it can be used to detect an output overvoltage event, such
as open load condition. In this situation, the detecting voltage is
expressed by the formula below:
VOUT(OVP) =
VOUT(normal operation)
VCC(normal operation)
31.5 (V)
(4)
VCC pin
voltage
COMP pin
voltage
Drain
current, ID
Figure 34. Waveforms when VCC pin OVP is being activated (LC551xD)
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
26
• OCP Pin Overvoltage Protection. Figure 35 shows the OCP pin
OVP function. When the OCP pin voltage with reference to the
S/GND pin reaches VOCP(OVP) = 2.6 V or more, OVP is activated.
During this function, the bias assist function is disabled, and
thus the IC enters intermittent operation as described in the VCC
pin OVP section, above. This can be used as protection in the
event that the quasi-resonant signal setup is mistaken or excess
load current happens in the use of a poor coupling transformer
between the primary and secondary winding.
VCC pin
voltage
• ISENSE Pin Overvoltage Protection. Figure 36 shows the
ISENSE pin OVP operation. When the ISENSE pin voltage with
reference to the S/GND pin reaches and exceeds VISEN(OVP) =
2.0 V or more, OVP is activated.
During this function, the bias assist function is disabled, and thus
the IC enters intermittent operation as described in the VCC pin
OVP section, above. As shown in figure 9, with Zener diode DZ1
this function can be used to detect an excess output voltage, such
as caused by an open load condition, and protect the circuit.
VCC(ON)= 15.1V
VCC(OFF)= 9.4V
VBD(OVP)= 2.6V
OCP pin
voltage
Drain
current, ID
Figure 35. Waveforms when OCP pin OVP is being activated (LC551xD)
VCC pin
voltage
VCC(ON)= 15.1V
VCC(OFF)= 9.4V
VISEN(OVP)= 2.0V
ISENSE pin
voltage
COMP pin
voltage
VCOMP(MIN)= 0.90V
Drain
current, ID
tON= tON(LEB)(500ns)
Figure 36. Waveforms when ISENSE pin OVP is being activated (LC551xD)
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
27
LC552xD/LC552xF series (isolated designs) The LC552xD and
LC552xF series have three OVP activation methods link to the
VCC pin, to the OCP pin, and to the OVP pin:
• VCC Pin Overvoltage Protection. figure 37 shows the waveforms of the OVP function. When the VCC pin voltage with reference to the S/GND pin reaches and exceeds VCC(OVP) = 31.5 V
or more, OVP is activated and the IC stops switching operation.
During this function, the the bias assist function is disabled, and
the VCC voltage decreases to VCC(OFF) = 9.4 V. After that, the
startup circuit is activated, and the operation begins intermittent
operation by repeating the restart and operation process as long as
the OVP condition remains. In addition, because VCC voltage is
proportional to the output voltage, it can be used to detect output
overvoltage events, such as open load condition. In this situation,
the detecting voltage is expressed by equation 4.
VCC(OVP)= 31.5V
VCC pin
voltage
VCC(ON)= 15.1V
VCC(OFF)= 9.4V
FB pin
voltage
VFB(MIN)= 0.90V
Drain
current, ID
tON= tON(LEB)(500ns)
Figure 37. Waveforms when VCC pin OVP is being activated (LC552xD and LC552xF)
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
28
• OCP Pin Overvoltage Protection. Figure 38 shows the OCP pin
OVP function. When the OCP pin voltage with reference to the
S/GND pin reaches VOCP(OVP) = 2.6 V, OVP is activated.
During this function, the bias assist function is disabled, and thus
the IC enters intermittent operation as described in the VCC pin
OVP section, above. This can be used as protection in the event
the quasi-resonant signal setup is mistaken or excess load current
happens in the use of a poor coupling transformer between the
primary and secondary winding.
• OVP pin Overvoltage Protection. Figure 39 shows the OVP
pin OVP function. When the OVP pin voltage with reference to
the S/GND pin reaches and exceeds VOVP(OVP) = 2.0 V, OVP is
activated.
During this function, the bias assist function is disabled, and thus
the IC enters intermittent operation as described in the VCC pin
OVP section, above.. As shown in figure 10 and figure 11, with
PC2 this function can be used to detect high output voltage, such
as an open load condition.
VCC pin
voltage
VCC(ON)= 15.1V
VCC(OFF)= 9.4V
VOCP(OVP)= 2.6V
OCP pin
voltage
Drain
current, ID
Figure 38. Waveforms when OCP pin OVP is being activated (LC552xD and LC552xF)
VCC pin
voltage
VCC(ON)= 15.1V
VCC(OFF)= 9.4V
VOVP(OVP) = 2.0V
OVP pin
voltage
FB pin
voltage
VFB(MIN)= 0.90V
Drain
current, ID
tON= tON(LEB)(500ns)
Figure 39. Waveforms when OVP pin OVP is being activated (LC552xD and LC552xF)
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
29
Overload Protection (OLP)
If the MOSFET drain current is limited by the overcurrent protection for a certain delay period, tDLY , Overload Protection is
activated and the IC enters intermittent oscillation mode operation. This reduces the power-up stress on the incorporated power
MOSFET and secondary rectifier.
LC551xD series (non-isolated designs) Figure 40 shows the
peripheral circuit at the COMP pin, and figure 41 shows operation when OLP is activated.
At an overload condition, the output voltage, the VCC pin voltage, and the ISENSE pin voltage drop. When the VCC pin voltage reaches VCC(BIAS) = 11.0 V, the bias assist function is enabled
in order to avoid reaching VCC(OFF) = 9.4 V. When the ISENSE
pin voltage reaches VSEN(TH) = 0.30 V, the output of the OTA
circuit becomes zero, and therefore the internal constant current
source at the COMP pin starts charging capacitor C6.
When the COMP pin voltage reaches Overload Protection
Threshold Voltage-2, VCOMP(OLP)2 = 4.5 V, the on-width is set to
the Leading Edge Blanking time, tON(LEB) = 500 ns. Meanwhile,
the capacitor charging is ongoing and when it reaches Overload
Protection Threshold Voltage-1, VCOMP(OLP)1 = 5.5 V, the switching operation stops. At the same time, the startup circuit is activated and the operation begins intermittent operation by repeating
the restart and operation stop processes as long as the overload
condition remains.
Figure 40. COMP pin peripheral circuit
VCC pin
voltage
COMP pin
voltage
VCC(ON)= 15.1V
VCC(BIAS)1= 11.0V
VCC(OFF)= 9.4V
VCOMP(OLP)1= 5.5V
VCOMP(OLP)2= 4.5V
VCOMP(MIN)= 0.90V
Drain
current, ID
tON= tON(LEB)(500ns)
Figure 41. Waveforms when OLP is being activated (LC551xD)
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
30
LC552xD/LC552xF series (isolated designs) Figure 42 shows
the peripheral circuits at the FB pin of the LC552xD/LC552xF
series and figure 43 shows the waveforms when the Overload
Protection (OLP) is activated. At an overload condition, the
output voltage drops and it results in a feedback signal from the
secondary output becoming zero. After that, the internal constant
current source at the FB pin starts to charge the C6 capacitor.
When the FB pin voltage reaches the Overload Protection
Threshold Voltage-2, VFB(OLP)2 = 4.5 V, the on-width is set to
Leading Edge Blanking time, tON(LEB) = 500 ns. In the meanwhile, the capacitor charging is ongoing and when it reaches at
Overload Protection Threshold Voltage-1, VFB(OLP)1 = 5.5 V, the
switching operation stops. At the same time, the startup circuit
is activated and the operation begins intermittent operation by
repeating the restart and operation stop processes as long as the
overload condition remains.
7VReg
LC552xD
(LC552x F)
R7
4(6)
S/GND OCP
3(5)
1(2)
FB
C6
ROCP
Figure 42. FB pin peripheral circuit
VCC pin
voltage
FB pin
voltage
VCC(ON)= 15.1V
VCC(BIAS)1= 11.0V
VCC(OFF)= 9.4V
VFB(OLP)1= 5.5V
VFB(OLP)2= 4.5V
VFB(MIN)= 0.90V
Drain
current, ID
tON= tON(LEB)(500ns)
Figure 43. Waveforms when OLP is being activated (LC552xD/ LC552xF)
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
31
Overcurrent Protection (OCP)
C2
The Overcurrent Protection (OCP) feature monitors the power
MOSFET drain current on a pulse-by-pulse basis, in order to limit
output power. The drain current is detected by a current detection
resistor, ROCP , and the voltage across it, VROCP , is fed through
R3 to the OCP pin to be detected by it. When the ROCP voltage,
VROCP , reaches the value of the following formulas, the power
MOSFET turns off.
VROCP = – |VOCP | + R3
|IOCP |
LC55xxD (LC55xxF)
Controller Chip
Logic
C3
Drive
1(2)
OCP
Comparator
+
(5)
where
VOCP: Overcurrent Detection Threshold Voltage, -0.60 V, and
IOCP: OCP Pin Source Current, -40 μA.
In order to minimize effects of variation in the internal resistor, R3 (figure 44) is recommended to have a value from 100 to
330 Ω. and C5 is recommended to have a value from 100 to
470 pF, with good temperature characteristics. Selecting larger
capacitances slows OCP response, and results in an increase in the
drain current peak at transient conditions, such as start-up.
P
D/ST 8(1)
−0.6V
S/GND
3(5)
OCP
Reg
Rocp
C5
Filter
R3
VRocp
Figure 44. Minus detection OCP circuit
tON(LEB)
OCP detection period
S/GND
Because the OCP function is designed for peak current detection,
there is a chance that it will react to the surge current at the power
MOSFET turn-on edge. In order to avoid this, the Leading Edge
Blanking Time is set. The Leading Edge Blanking Time, tON(LEB)
= 500 ns, is set.
VROCP
The surge current pulse width must be less than tON(LEB) as shown
in figure 45. In case its width is longer than that, try these measures:
With the quasi-resonant converter, the peak drain current at the
same output load condition becomes different in various AC input
voltages (85 VAC to 265 VAC), that is, when the AC input voltage is high, the peak drain current is low because the operation
frequency becomes high.
When the OCP threshold voltage is fixed constant, the output current, IOUT , in an OCP operation increases according to an increase
of AC input voltage, as shown in (A) IOUT without input compensation of figure 46.
In the maximum AC input voltage range, in order to control
output current at OCP operation, IOUT(OCP) , an external OCP input
compensation circuit (DX1, DZX1, RX1) is added as shown in figure
47. For more details as to how to set it, refer to the next section,
Input Compensation Function for Overcurrent Protection.
LC5500-AN, Rev.1.2
Figure 45. OCP pin voltage, converted from MOSFET drain
current by ROCP
A
Output Current at OCP, IOUT(OCP)
• adjust the turn-on point to the VDS bottom point
• reduce the voltage resonant capacitor CV (C3 in figure 44)
capacitance
• reduce the secondary rectifier snubber capacitor capacitance
Surge pulse voltage width at turning on
B
IOUT target output level
C
85
265
AC Input Voltage (V)
Figure 46. Input compensation OCP circuit: (A) IOUT without input
compensation; (B) IOUT with appropriate input compensation; (C) with
inappropriately set input compensation, more than enough amount of
compensation, IOUT cannot meet target
SANKEN ELECTRIC CO., LTD.
32
L2
Input Compensation Function for Overcurrent
Protection
8(1)
D/ST
The auxiliary winding forward voltage Efw1 is proportional to
the input voltage, EIN . Efw1 is applied to DZX1 , and RX1 and R3
translate the voltage Efw1 – Zener voltage of DZX1 , into the input
Compensation Current, I.
V 'ROCP= –
¨
©
©
ª
|VOCP | + R3 ×| IOCP | – R3 × I
¨
©
©
ª
(7)
• Determining OCP pin input compensation circuit component
values
Given:
EIN(PK) = C2 voltage
P
C2
D5
8(1)
NS
R1
ND
LC55xxD
(LC55xxF)
S/GND OCP
1(2) C5 3(5)
IOCP
ROCP
R3
Flyback
voltage
Erev1
D
C4
D/ST
ID
S
NP
D6
C7
D7
DX1
R4
Forward
voltage
Efw1
DZX1
RX1
Compensation Current, I
Figure 48. OCP input compensation circuit
AC Input Voltage = 85 V
AC Input Voltage = 265 V
0
Efw1
}DZX1
Time
0
Efw2
OCP input compensation
starting point: Efw1 ≈ DZX1
VFX1 = DX1 forward voltage
LC5500-AN, Rev.1.2
RX1
EIN
IDP = MOSFET peak drain current
DZX1 = DZX1 Zener voltage
DZX1
C7
Figure 47. Input compensation OCP circuit
(6)
In the converse situation, with the input compensation circuit,
as shown in the figure 50 lower panel, the overcurrent detecting
voltage is equal to the sum of the Overcurrent Protection Threshold Voltage, VOCP = −0.60 V, the voltage across R3 from the OCP
pin source current, IOCP , and the voltage across R3 from the input
Compensation Current, I :
DX1
R4
R3
Auxiliary Winding
Forward Voltage
VROCP = – |ROCP × IDP| = – |VOCP | + R3 × |IOCP |
D6
D7
ROCP
D
C4
S/GND OCP
1(2) C5 3(5)
OCP Threshold Voltage with and without the
OCP Input Compensation Circuit
Without the input compensation circuit, as shown in the figure 50
upper panel, the overcurrent detecting voltage is equal to the sum
of the Overcurrent Protection Threshold Voltage, VOCP = −0.60 V,
and the voltage across R3 from the OCP pin source current, IOCP
= – 40 μA.
2(4)
LC55xxD
(LC55xxF)
The DZX1 Zener diode is used to set the voltage at which the input
compensation begins, so choose the Zener voltage value that is
equal to Efw1 at the time when input compensation begins.
R1
D5
VCC
C3
This input Compensation Current, I, creates the voltage of R3 × I,
and it lowers the compensated OCP threshold voltage to less than
the original OCP threshold voltage, VOCP = –0.6 V. This way,
when EIN is high, the compensation amount becomes high.
Optimize the circuit in a way to minimize the difference between
the overcurrent points at low and high AC input voltage. Also
ensure that the output current meets its target over the entire AC
input voltage range, as the normal curve shown in figure 46.
The OCP pin voltage, including surge voltage, must not exceed
its absolute maximum rating of –2.0 to 5.0 V at the highest AC
input voltage.
P
C2
Time
Figure 49. OCP input compensation
SANKEN ELECTRIC CO., LTD.
33
1. The overcurrent detecting peak drain current, IDP(OCP) ,
without the input compensation circuit, is expressed by the
following, based on equation 6, from figure 50, upper panel:
|V | + R3 × |IOCP|
IDP(OCP) = OCP
(8)
ROCP
2. On the other hand, the overcurrent detecting peak drain
current, I'DP(OCP) , with the input compensation circuit, is
expressed by the following, based on equation 7, from figure 50, lower panel:
|V | + R3 × (|IOCP| – I )
I 'DP(OCP) = OCP
(9)
ROCP
Here, I'DP is the peak drain current where the output power
of the maximum AC input voltage becomes the same as that
limited by OCP at the minimum AC input voltage.
3. From equations 8 and 9, the compensation current, I, of the
input compensation circuit, is expressed as follows:
R
I = ( |I DP(OCP) | – |I 'DP(OCP)| ) × OCP
R3
(10)
4. The forward voltage, Efw1 , at C2 peak voltage EIN(PK)(max) is
expressed as follows:
N × EIN(PK)(max)
Efw1 = D
(11)
NP
5. Next, RX1 is expressed by the following, in order to let the
compensation current, I, flow at the maximum AC input voltage, EIN(PK)(max):
OCP
S/GND
1(2)
ROCP
IDP
(12)
Efw1 – DZX1 – VFX1
RX1 + R3 + ROCP
assuming: R3, ROCP << RX1
Efw1 – DZX1 – VFX1
RX1 =
I
(13)
from equations 11 and 13:
RX1 =
ND × EIN(PK)(max)
– (DZX1 + VFX1 )
NP
(14)
I
• AC input compensation circuit design example with universal
input
Here is an example of design specification and calculation:
Given:
AC input voltage: 85 to 265 VAC
Output power: 40 W
Transformer primary winding: 40 T
Transformer auxiliary winding: 6 T
ROCP = 0.2 Ω
R3 = 220 Ω
DX1 forward voltage: 0.8 V
Tentatively, OCP input compensation start voltage is set to the
voltage of 100 to 130 VAC.
At this time, OCP input compensation starting voltage is set to
120 VAC.
R3 × IOCP
3(5)
ROCP × IDP
S/GND
VOCP
Without input
compensation
circuit
I =
ROCP
ROCP×I DP
R3
R3
VOCP
VOCP
I DP
R3 × IOCP
Increase
ID
IOCP
OCP
With input
compensation
circuit
I'DP
R3 × IOCP
3(5)
S/GND
VOCP
S/GND
1(2)
ROCP
VOCP ROCP × I'DP
ROCP
R X1 ROCP × I'DP
IOCP
I
VOCP
R3 × IOCP
R3
R3
R3 × I
I'DP
R3 × I
ID
Decrease
Figure 50. Compensated drain current waveforms
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
34
Design Considerations
1. Calculate Efw1 at 120 VAC input:
N
Efw1 = D × EIN(PK)(max)
NP
N
= D × VIN(OCP_ST) × √2
NP
6
=
× 120 √2 = 25.5 (V)
40
(15)
Peripheral Components
Take care to use properly rated and proper type of components.
Thus, select 27 V as the Zener value for DZX1.
Assuming:
IDP(OCP) at the minimum AC input voltage = 3.0 A
I'DP(OCP) at the maximum AC input voltage (when the output
power of the maximum AC input voltage becomes the same
as that limited by OCP at the minimum AC input voltage)
= 1.9 A
2. The compensation current, I, is calculated using equation 10:
0.2 (Ω)
I = (3.0 (A) – 1.9 (A)) ×
= 1 (mA)
220 (Ω)
3. RX1 can be calculated using equation 14:
6 (T) × 265 (VAC)√2
– (27 (V) + 0.8 (V))
40
(T)
RX1 =
1 (mA)
= 28.4 (kΩ)
Thus, select RX1 = 27 kΩ out of the E12 series.
Finally, ensure that these values work to achieve the output
power cited as (B), IOUT with appropriate input compensation, of
figure 46, by the actual operation, and adjust them if necessary.
Thermal Shutdown Protection
• Output smoothing capacitor. Consider design margins for ratings of ripple current, voltage, and temperature in selecting the
output capacitor. A low impedance capacitor, designed to be
tolerant against high ripple current, is recommended.
• Transformer. Consider design margins for temperature rise,
resulting from copper losses and core losses, in designing or
selecting a transformer.
Switching current contains a high frequency component that
causes the skin effect; therefore, consider a current density of
3 to 4 A/mm2 and select a wire gauge based on RMS current.
In the event further temperature measurement is necessary and
it is necessary to increase surface area of the wire, try the following measures:
▫ Increase the quantity of parallel wires
▫ Use litz wire
▫ Increase the diameter of the wires
• Current detection resistor, ROCP . Choose a low equivalent series
inductance and high surge tolerant type for the current detection
resistor.
If a high inductance type is used, it may cause
malfunctioning because of the high frequency current running
through it.
Transformer Design
The transformer design is the same as for an RCC (ringing choke
converter, or self-oscillation flyback converter) transformer
design. However, a quasi-resonant operation includes a certain
delay to turn-on, so duty cycle must be compensated.
Thermal Shutdown protection is activated when the temperature
of the control circuit in the IC reaches Tj(TSD) = 135°C(min), and
then the IC stops switching operation in latch mode.
Maximum On-Width Limiting Function
The maximum on-width, set at tON(MAX) = 40 μs (figure 51), limits lower side operation frequency, and it minimizes audible noise
from the transformer, as well as power stress on the incorporated
MOSFET and secondary rectifier at low AC input or during transient periods such as at switching AC mains on or off.
Ensure that the actual on-width at the minimum AC input and the
maximum load condition does not reach tON(MAX) = 40 μs. If that
does happen, redesign the transformer, such as by reducing the
primary inductance or reducing the duty cycle by lowering the
turns ratio of NP / NS .
ID
time
VDS
Maximum
On-Time
time
Figure 51. Maximum on-width
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
35
Determine the minimum operation frequency, f0 , and the flyback
voltage, Ef , and then calculate the primary inductance, LP , as
follows:
L'P =
( VINRMS(MIN) × DON
)2

 2×P × f
S(MIN)
O

+ VINRMS(MIN) × DON× fS(MIN)× √ CV
H


Maximum duty cycle, compensated for quasi-resonant delay time
(tONDLY), D'ON:
D'ON = (1 – fS(MIN) × tONDLY) × DON
(21)
Input rms current of the sine wave of the minimum AC input
voltage, IINRMS(MAX):
2
(16)
PO
(22)
η × VINRMS(MAX)
Peak drain current, compensated for quasi-resonant delay time
(tONDLY), IDP(DLY):
I INRMS(MAX) =
where
VINRMS(MIN) is the effective value (rms) of the sine wave of the
minimum AC input voltage,
PO is the maximum output power:
P O = V O × IO
(17)
where VO is the output voltage, and IO is the maximum
output current,
fS(MIN) is the operation frequency at the peak voltage of the sine
wave of AC input voltage (the minimum operation frequency),
η is the efficiency rate: 80% to 90%,
CV is the voltage resonant capacitor (C3) rating: 47 to 470 pF,
for general application
DON is the maximum duty cycle, not compensated for the quasiresonant delay time, at the minimum AC input voltage:
Ef
DON =
(18)
√2 × VINRMS(MIN) + Ef
Ef is the flyback voltage:
Ef = (NP /NS) × (EO +Vf)
(19)
where NP is the number of turns of the primary winding, NS
is the number of turns of the secondary winding, and Vf is the
forward voltage of the secondary rectifier, D8, approximately
0.7 V
I DP(DLY) =
2√2 × PO
η × D'ON × VIN(RMS(MIN)
(23)
In transformer design, AL-value and NP must be set in a way that
the ferrite core does not saturate. Here, use ampere turn value
(AT), the result of IDP(DLY) × NP and the graph of NI-Limit (AT)
versus AL-value (figure 52 is an example of it). NI-Limit is the
limit that the ampere turn value should not exceed; otherwise the
core saturates. So use the graph and equation 24, which expresses
the relationship of LP , AL-value, and NP to appropriately set
these values. In addition, target 30% below the NI-Limit curve as
a design margin in consideration of temperature effects and other
variations, as expressed by the formulas below:
NI-Limit ≤ NP × IDP(DLY) × 130%
(24)
LP
(25)
AL Value
Then, the rest of the winding turns are determined by the formulas below.
NP =
NS =
VO + Vf
× NP
Ef
(26)
ND =
VCC
× NS
VO + Vf
(27)
Ef is determined by the power MOSFET breakdown voltage and
the surge voltage. Because the breakdown voltage of the power
MOSFET of this IC is 650 V, when it is used with the specified
universal input range, the target voltage of Ef is 100 to 150 V.
Quasi-resonant delay time, tONDLY:
(20)
NI-Limit(AT)
tONDLY = √L'P × CV
Saturation region boundary
Margin=30%
Design point
(example)
2
AL-Value(nH/T )
Figure 52. Example of NI-Limit versus AL-Value characteristics
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
36
Trace and Component Layout Design
Switching mode power supplies consist of current traces with
high frequency and high voltage, and thus trace design and
component layout should be done in compliance with all safety
guidelines.
PCB circuit trace design and component layout affect IC functioning during operation. Unless they are proper, malfunction,
significant noise, and large power dissipation may occur.
Circuit loop traces flowing high frequency current, as shown in
figure 53, should be designed as wide and short as possible to
reduce trace impedance.
Furthermore, because an integrated power MOSFET is being
used as the switching device, take account of the positive thermal
coefficient of RDS(on) for thermal design.
In addition, earth ground traces affect radiation noise, and thus
should be designed as wide and short as possible.
Figures 54, 55, and 56 show practical trace design examples and
considerations for the LC551xD, LC552xD and LC552xF series
respectively. In addition, observe the following:
• Traces among the S/GND pin, ROCP , C2, T1(primary winding),
and D/ST pin:
The traces carry the switching current; therefore, widen and
shorten them as much as possible.
If the IC and the electrolytic capacitor C2 are apart, place a film
capacitor (0.1 μF with appropriate voltage rating) close to the
IC or the transformer in order to reduce series inductances of
the traces against high frequency current.
Figure 53. High frequency current loops
T1
Clamping snubber
C8
C2
R5
D8
ZD1
P
D9
S
U1 8
D/ST
6
ISENSE
5
D5
NF
LC551xD
C3
C4
C10
R1
D
S/GND VCC OCP COMP
2
3
4
1
D6
C5
ROCP
C6
A
R3
D7
R4
C7
Main circuit
GND circuit of control circuit
Secondary rectification circuit
Figure 54. LC551xD (non-isolated designs) peripheral circuit connection example
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
37
• Traces among the S/GND pin, C4(–), T1(auxiliary winding D),
R1, D5, C4(+), and VCC pin:
possible (at the point A of figures 54, 55, and 56) with dedicated
traces.
This trace is for supplying voltage to IC. Widen and shorten
the traces as much as possible. If the IC and the electrolytic
capacitor C4 are apart, place a film or ceramic capacitor
(0.1 to 1.0 μF) as close to VCC pin and the S/GND pin as possible.
• Secondary side, traces among T1(secondary winding S), D8,
and C10:
The secondary-side switching current runs through this trace.
Widen and shorten the traces as much as possible.
Thin and long traces cause the series inductance to be high and
it results in high surge voltage on the power MOSFET when
it turns off. Therefore, proper layout pattern design helps to
increase voltage margin of the power MOSFET to its breakdown voltage and reduce power stress and loss of the clamping
snubber circuit.
• Current Detection Resistor ROCP:
Place ROCP as close to the S/GND pin as possible. In addition,
in order to avoid interference of the switching current with the
control circuit, connect the ground of the control circuit to the
S/GND pin as close as possible. Connect R3 as close to ROCP as
T1
Clamping snubber
D8
C2
P
C10
S
D5
U1
8
D/ST
C3
D
LC552xD
S/GND
NF
5
D6
R7
FB
4
OCP
C6
PC1
3
1
A
C4
2
VCC
Controller
Chip
ROCP
R1
C5
R4
D7
C7
R3
C17
Main circuit
Control circuit GND circuit
Secondary rectification circuit
Figure 55. LC552xD (isolated designs) peripheral circuit connection example
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
38
T1
Clamping snubber
D8
C2
P
C10
S
D5
1
D/ST
U1
C3
D
LC552xF
S/GND
2
A
C4
4
VCC
Controller
Chip
ROCP
R1
C5
OCP
5
D6
R7
FB
6
C6
PC1
R4
D7
C17
C7
R3
Main circuit
Control circuit GND circuit
Secondary rectification circuit
Figure 56. LC552xF (isolated designs) peripheral circuit connection example
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
39
• The contents in this document are subject to changes, for improvement and other purposes, without notice. Make sure that this is the latest revision of the document
before use.
• Application and operation examples described in this document are quoted for the sole purpose of reference for the use of the products herein and Sanken can assume
no responsibility for any infringement of industrial property rights, intellectual property rights or any other rights of Sanken or any third party which may result from
its use.
• Although Sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and defect of semiconductor products at a certain rate is
inevitable. Users of Sanken products are requested to take, at their own risk, preventative measures including safety design of the equipment or systems against any
possible injury, death, fires or damages to the society due to device failure or malfunction.
• Sanken products listed in this document are designed and intended for the use as components in general purpose electronic equipment or apparatus (home appliances,
office equipment, telecommunication equipment, measuring equipment, etc.).
When considering the use of Sanken products in the applications where higher reliability is required (transportation equipment and its control systems, traffic
signal control systems or equipment, fire/crime alarm systems, various safety devices, etc.), and whenever long life expectancy is required even in general purpose
electronic equipment or apparatus, please contact your nearest Sanken sales representative to discuss, prior to the use of the products herein.
The use of Sanken products without the written consent of Sanken in the applications where extremely high reliability is required (aerospace equipment, nuclear
power control systems, life support systems, etc.) is strictly prohibited.
• In the case that you use our semiconductor devices or design your products by using our semiconductor devices, the reliability largely depends on the degree of
derating to be made to the rated values. Derating may be interpreted as a case that an operation range is set by derating the load from each rated value or surge
voltage or noise is considered for derating in order to assure or improve the reliability. In general, derating factors include electric stresses such as electric voltage,
electric current, electric power etc., environmental stresses such as ambient temperature, humidity etc. and thermal stress caused due to self-heating of semiconductor
devices. For these stresses, instantaneous values, maximum values and minimum values must be taken into consideration.
In addition, it should be noted that since power devices or IC’s including power devices have large self-heating value, the degree of derating of junction temperature
(Tj) affects the reliability significantly.
• When using the products specified herein by either (i) combining other products or materials therewith or (ii) physically, chemically or otherwise processing or
treating the products, please duly consider all possible risks that may result from all such uses in advance and proceed therewith at your own responsibility.
• Anti radioactive ray design is not considered for the products listed herein.
• Sanken assumes no responsibility for any troubles, such as dropping products caused during transportation out of Sanken’s distribution network.
• The contents in this document must not be transcribed or copied without Sanken’s written consent.
LC5500-AN, Rev.1.2
SANKEN ELECTRIC CO., LTD.
40