TDA5235

Dat a Sh ee t, V1.0 , F eb rua ry 2 01 0
S m a r t L E W I S TM R X +
TDA5235
En hanced Sensitivity
Double- Con fig urat ion Receiver with
Digital Baseb and P rocessin g
Wi re less Co ntro l
N e v e r
s t o p
t h i n k i n g .
Edition February 19, 2010
Published by Infineon Technologies AG,
Am Campeon 1 - 12
85579 Neubiberg, Germany
© Infineon Technologies AG February 19, 2010.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or the Infineon Technologies Companies and our Infineon Technologies
Representatives worldwide (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Dat a Sh ee t, V1.0 , F eb rua ry 2 01 0
S m a r t L E W I S TM R X +
TDA5235
En hanced Sensitivity
Double- Con fig urat ion Receiver with
Digital Baseb and P rocessin g
Wi re less Co ntro l
N e v e r
s t o p
t h i n k i n g .
TDA5235
Revision Number:
Revision History:
010
2010-02-19
Previous Version:
TDA5235_V0.1
V1.0
Page
Subjects (major changes since last revision)
Page 25
Update of Figure 9
Page 27
Update of Figure 10
Page 29
AFC limitation added
Page 31
AGC setting proposal added
Page 32
New Section 2.4.6.5 ADC added
Page 34
Additional information on RSSIPRX register inserted
Page 39
Signal and Noise Detector Procedure adapted
Page 43
x_CDRRI register recommendation changed
Page 47, 50, 54
Data Slicer Modes adapted; limitation added
Page 67
Update of Figure 41
Page 68
Update of Figure 42
Page 76
Additional hint on clock and data recovery algorithm of the user
software inserted
Page 82
PLDLEN limitation added
Page 84
Limitation for ISx readout and Burst-read function added
Page 86
Limitation for Burst-read function added
Page 105
Description of “Parallel Wake-up Search” adapted
Page 123
Additional hints added
Page 125
Adaption of Section 4.1
Page 128
New item C7 added
Page 136 f
Comments added for items I6, I7, I8, I9, J11, J12
Page 136
Item J1 updated
Page 139 ff
General test conditions noted for parameters K, L and M
Page 145
BOM components C7, C8, L1, R2 and R3 updated
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Any information within this document that you feel is wrong, unclear or missing at all?
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TDA5235
Table of Contents
Page
1
1.1
1.2
1.3
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.5.1
2.4.5.2
2.4.6
2.4.6.1
2.4.6.2
2.4.6.3
2.4.6.4
2.4.6.5
2.4.7
2.4.8
2.4.8.1
2.4.8.2
2.4.8.3
2.4.8.4
2.4.8.5
2.4.8.6
2.4.8.7
2.4.8.8
2.4.9
2.4.9.1
2.4.9.2
2.5
2.5.1
2.5.1.1
2.5.1.2
2.5.2
2.5.3
2.5.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Definition and Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
RF/IF Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Crystal Oscillator and Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Sigma-Delta Fractional-N PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PLL Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Digital Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ASK and FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ASK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Automatic Frequency Control Unit (AFC) . . . . . . . . . . . . . . . . . . . . . 28
Digital Automatic Gain Control Unit (AGC) . . . . . . . . . . . . . . . . . . . . 30
Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
RSSI Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Digital Baseband (DBB) Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Data Filter and Signal Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Encoding Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Data Slicer and Line Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Wake-Up Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Message ID Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
RUNIN, Synchronization Search Time and Inter-Frame Time . . . . . . 66
Power Supply Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Chip Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Interfacing to the TDA5235 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Digital Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Interrupt Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Data Sheet
5
7
7
8
8
V1.0, 2010-02-19
TDA5235
Table of Contents
Page
2.5.5
2.5.5.1
2.5.6
2.6
2.6.1
2.6.1.1
2.6.1.2
2.6.1.3
2.6.1.4
2.6.1.5
2.6.1.6
2.6.1.7
2.6.1.8
2.6.2
2.6.2.1
2.6.2.2
2.6.2.3
2.6.2.4
2.6.2.5
2.6.2.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.8
2.8.1
2.8.2
Digital Control (4-wire SPI Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Chip Serial Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
System Management Unit (SMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Master Control Unit (MCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Run Mode Slave (RMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
HOLD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Self Polling Mode (SPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Automatic Modulation Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Multi-Channel in Self Polling Mode . . . . . . . . . . . . . . . . . . . . . . . . . 104
Run Mode Self Polling (RMSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Polling Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Self Polling Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Constant On-Off Time (COO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Fast Fall Back to SLEEP (FFB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Mixed Mode (MM, Const On-Off & Fast Fall Back to SLEEP) . . . . . 120
Permanent Wake-Up Search (PWUS) . . . . . . . . . . . . . . . . . . . . . . . 121
Active Idle Period Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Definition of Bit Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Definition of Manchester Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Definition of Power Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Symbols of SFR Registers and Control Bits . . . . . . . . . . . . . . . . . . . . 126
Digital Control (SFR Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SFR Address Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SFR Register List and Detailed SFR Description . . . . . . . . . . . . . . . . 127
3
3.1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4
4.1
4.1.1
4.1.2
4.1.3
4.2
4.3
4.4
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Circuit - Evaluation Board v1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Board Layout, Evaluation Board v1.0 . . . . . . . . . . . . . . . . . . . . . . .
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
131
131
131
132
133
154
155
157
Appendix - Registers Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Data Sheet
6
V1.0, 2010-02-19
TDA5235
Product Description
1
Product Description
1.1
Overview
The IC is a low power ASK/FSK Receiver for the frequency bands 300-320, 425-450,
863-870 and 902-928 MHz. Bi-phase modulation schemes, like Manchester, bi-phase
mark, bi-phase space and differential Manchester are supported.
The chip offers best-in-class sensitivity performance at a very high level of integration
and needs only a few external components.
The device is qualified to automotive quality standards and operates between -40 and
+105°C at supply voltage ranges of 3.0-3.6 Volts or 4.5-5.5 Volts.
The receiver is realized as a double down conversion super-heterodyne/low-IF
architecture each with image rejection supplemented by digital signal processing in the
baseband. A fully integrated Sigma-Delta Fractional-N PLL Synthesizer allows for highresolution frequency generation and uses a crystal oscillator as the reference. The onchip temperature sensor may be utilized for temperature drift compensation via the
crystal oscillator.
The digital baseband processing unit together with the high performance down converter
is the key element for the exceptional sensitivity performance of the device which take it
close to the theoretical top-performance limits. It comprises signal and noise detectors,
matched data filter, clock and data recovery, data slicer and a format decoder. It
demodulates the received ASK or FSK data stream independently and recovers the data
clock out of the received data stream with very fast synchronization times which can then
be either accessed via separate pins or used for further processing like frame
synchronization and intermediate storage in the on-chip FIFO. The RSSI output signal is
converted to the digital domain with an ADC. All these signals are accessible via the 4wire SPI interface bus. Up to 2 pre-configured telegram formats can be stored into the
device offering independent pre-processing of the received data to an extent not
available till now. The down converter can be also configured in single-conversion mode
at moderately reduced selectivity performance but at the advantage of omitting the IF
ceramic filter.
Data Sheet
7
V1.0, 2010-02-19
TDA5235
Product Description
1.2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Enhanced sensitivity receiver
Multi-band (300-320, 425-450, 863-870 and 902-928 MHz)
One crystal frequency for all supported frequency bands
21-bit Sigma-Delta Fractional-N PLL synthesizer with high resolution of 10.5 Hz
Up to 2 parallel parameter sets for autonomous scanning and receiving from different
sources reduces significantly host processor power consumption and system
standby power consumption
One frequency channels per parameter set is supported with 10.5 Hz resolution
Autonomous receive mode leads to reduced noise of host processor and improved
system performance
Ultrafast Wake-up on RSSI
Fast synchronization on incoming data stream typically within first 4 bits of a telegram
Selectable IF filter bandwidth and optional external filters possible
Double down conversion image reject mixer
ASK and FSK capability
Automatic Frequency Control (AFC) for carrier frequency offset compensation
Supports bi-phase line codes like Manchester, bi-phase mark/space and differential
Manchester
NRZ data pre-processing capability
Digital base band receiver with clock synch, frame synch, format decoding and FIFO
Separate outputs for recovered data and clock
RSSI peak detectors
Wake-up generator and polling timer unit
Message ID scanning
Unique 32-bit serial number
On-chip temperature sensor
Integrated timer usable for external watch unit
Integrated 4-wire SPI interface bus
Supply voltage range 3.0 Volts to 3.6 Volts or 4.5 Volts to 5.5 Volts
Operating temperature range -40 to +105°C
ESD protection +/- 2 kV on all pins
Package PG-TSSOP-28
1.3
•
•
•
•
•
•
•
Features
Applications
Remote keyless entry systems
Remote start applications
Tire pressure monitoring
Short range radio data transmission
Remote control units
Cordless alarm systems
Remote metering
Data Sheet
8
V1.0, 2010-02-19
TDA5235
Functional Description
2
Functional Description
2.1
Pin Configuration
IFBUF_IN
1
28
IF_OUT
IFBUF_OUT
2
27
VDDA
GNDA
3
26
RSSI
IFMIX_INP
4
25
PP3
IFMIX_INN
5
24
GNDRF
VDD5V
6
23
LNA_INP
VDDD
7
22
LNA_INN
VDDD1V5
8
21
T2
GNDD
9
20
T1
PP0
10
19
SDO
PP1
11
18
SDI
PP2
12
17
SCK
P_ON
13
16
NCS
XTAL1
14
15
XTAL2
Figure 1
Data Sheet
TDA5235
Pin-out
9
V1.0, 2010-02-19
TDA5235
Functional Description
2.2
Pin Definition and Pin Functionality
Table 1
Pin Definition and Function
Pin Pad name
No.
1
Equivalent I/O Schematic
Function
IFBUF_IN
Analog input
IF Buffer input
VDDA
VDDA
330Ω
IFBUF
IFBUF_IN
Note: Input is
biased at VDDA/2
VDDA
330Ω
MIX2BUF
IFMIX_INN
2
IFBUF_OUT
VDDA
Analog output
IF Buffer output
VDDA
330Ω
IFBUF_OUT
IFBUF
GNDA
GNDA
3
GNDA
Analog ground
4
IFMIX_INP
Analog input
+ IF mixer input
VDDA
VDDA
330Ω
IFMIX_INP
MIX2BUF
Note: Input is
biased at VDDA/2
IFMIX_INN
5
IFMIX_INN
6
VDD5V
Data Sheet
see schematic of Pin 1 and 4
Analog input.
- IF mixer input
Analog input
5 Volt supply input
10
V1.0, 2010-02-19
TDA5235
Functional Description
Pin Pad name
No.
7
Equivalent I/O Schematic
Function
VDDD
VDD5V
Analog input
digital supply input
+
VReg
-
=
VDDD
GNDD
8
VDDD1V5
VDDD
Analog output
1.5 Volt voltage
regulator
+
VReg
=
-
VDD1V5
GNDD
9
GNDD
Digital ground
10 PP0
VDD5V
VDD5V
PPx
SDO
GNDD
Data Sheet
11
GNDD
Digital output
CLK_OUT,
RX_RUN,
NINT, LOW, HIGH,
DATA,
DATA_MATCHFIL,
CH_DATA,
CH_STR,
RXD and RXSTR
are programmable
via a SFR (Special
Function Register),
default = CLK_OUT
V1.0, 2010-02-19
TDA5235
Functional Description
Pin Pad name
No.
Equivalent I/O Schematic
Function
11 PP1
see schematic of Pin 10
Digital output
CLK_OUT,
RX_RUN,
NINT, LOW, HIGH,
DATA,
DATA_MATCHFIL,
CH_DATA,
CH_STR,
RXD and RXSTR
are programmable
via a SFR,
default = DATA
12 PP2
see schematic of Pin 10
Digital output
CLK_OUT,
RX_RUN,
NINT, LOW, HIGH,
DATA,
DATA_MATCHFIL,
CH_DATA,
CH_STR,
RXD and RXSTR
are programmable
via a SFR,
default = NINT
13 P_ON
VDD5V
VDDD
Digital input
power-on reset
P_ON
NCS
SCK
SDI
GNDD
Data Sheet
GNDD
12
V1.0, 2010-02-19
TDA5235
Functional Description
Pin Pad name
No.
Equivalent I/O Schematic
Function
14 XTAL1
VDDD
VDDD
Analog input
crystal oscillator
input
XTAL1
GNDD
....
GNDD
GNDD
15 XTAL2
VDDD
Analog output
crystal oscillator
output
VDDD
XTAL2
....
GNDD
GNDD
GNDD
16 NCS
see schematic of Pin 13
Digital input
SPI enable
17 SCK
see schematic of Pin 13
Digital input
SPI clock
18 SDI
see schematic of Pin 13
Digital input
SPI data in
19 SDO
see schematic of Pin 10
Digital output
SPI data out
20 T1
Digital input,
connect to Digital
Ground
21 T2
Digital input,
connect to Digital
Ground
Data Sheet
13
V1.0, 2010-02-19
TDA5235
Functional Description
Pin Pad name
No.
Equivalent I/O Schematic
Function
22 LNA_INN
Analog input
LNA - RF input
LNA_INN
GNDRF
23 LNA_INP
Analog input
LNA + RF input
LNA_INP
GNDRF
24 GNDRF
25 PP3
RF analog ground
see schematic of Pin 10
Digital output
RX_RUN,
NINT, LOW, HIGH,
DATA,
DATA_MATCHFIL,
CH_DATA,
CH_STR,
RXD and RXSTR
are programmable
via a SFR,
default = RX_RUN
26 RSSI
VDDA
VDDA
500Ω
RSSI
GNDA
Data Sheet
Analog output
analog RSSI output/
analog test pin
ANA_TST
GNDA
14
V1.0, 2010-02-19
TDA5235
Functional Description
Pin Pad name
No.
Equivalent I/O Schematic
Function
27 VDDA
VDD5V
Analog input
Analog supply
+
VReg
=
-
VDDA
GNDA
28 IF_OUT
Analog output
IF output
VDDA
VDDA
330Ω
IF_OUT
PPFBUF
GNDA
Data Sheet
GNDA
15
V1.0, 2010-02-19
Figure 2
Data Sheet
XTAL
21.948717
MHz
16
GNDD
(9)
XTAL2
(15)
XTAL1
(14)
VDDA
(27)
Vreg
3V3
3.3V-Analog
VDD5V
(6)
XOSC
Vreg
3V3
1st LO-Q
ΣΔ PLL
1st LO-I
PPF
BUF
wide
narrow
VDDD
(7)
3.3V Dig-I/O
5V Dig-O
Clock for
Digital Core
2nd LO-Q
2nd LO-I
T2
(21)
Reset
Generator
to
RX
PPF
2
Reset for
Digital Core
nd
IR-Mix2, 2 IF:
274.35897 kHz
1.5V Dig-Core
2 LO
Div 2
nd
M IX2
BUF
VDDD1V5 P_ON T1
(8)
(13) (20)
Vreg
1V5
1st IF = 10.7 MHz
2nd IF = 1st IF / 39
f cry stal = 2nd IF * 80
double/single
conversion (SDCSEL)
IFBUF
IFBUF_IN (1)
PP3 (25)
[RX_RUN]
GNDA (3)
PPF
IFBUF_OUT (2)
GNDRF
(24)
LNA
IFMIX_INN (5)
LNA_INN
(22)
LNA_INP
(23)
IF_OUT (28)
IR-Mix, 1st IF:
10.7 MHz
IFMIX_INP (4)
matching
+
SAW
Antenna
10.7 MHz
narrow ( opt )
VDDD
AAF
LP
D
AFC
Digital
Demod
PP0
(10)
[CLK_OUT]
ADC
I/F
MUX
PP2
(12)
[NINT]
Interrupt
Generator
Peripheral Bus
PLL
Control I/F
Clock
Generator
to
PLL
A
ADC-MUX
RSSI
System
Management
RX
Control I/F
Temp.Sensor
BPF
select
BW
Limiter
RSSI
(26)
Clock
Recovery
Slicer
RX FIFO
NCS SCK SDI SDO
(16) (17) (18) (19)
SPI Interface
Serial
Number
Framer
Signal & Noise
Detectors
Peak
Detectors
Data
Filter
PP1
(11)
[DATA]
TDA5235
2.3
(CERFSEL)
10.7 MHz
wide
TDA5235
Functional Description
Functional Block Diagram
TDA5235 Block Diagram1)
1) The function on each PPx port pin can be programmed via SFR (see also Table 1). Default values are given
in squared brackets in Figure 2.
V1.0, 2010-02-19
TDA5235
Functional Description
2.4
Functional Block Description
2.4.1
Architecture Overview
A fully integrated Sigma-Delta Fractional-N PLL Synthesizer covers the frequency bands
300-320 MHz, 425-450 MHz, 863-870 MHz, 902-928 MHz with a high frequency
resolution, using only one VCO running at around 3.6 GHz.
For Multi-Configuration applications requiring different RF channels a very good channel
separation is essential. To achieve the necessary high sensitivity and selectivity a double
down conversion super-heterodyne architecture is used. The first IF frequency is located
around 10.7 MHz and the second IF frequency around 274 kHz. For both IF frequencies
an adjustment-free image frequency rejection feature is realized. In the second IF
domain the filtering is done with an on-chip third order bandpass polyphase filter. A multistage bandpass limiter completes the RF/IF path of the receiver. For Single-Channel
applications with relaxed requirements to selectivity, a single down conversion low-IF
scheme can be selected.
For Multi-Configuration systems requiring different RF channels where even higher
channel separation is required, up to two (switchable) external ceramic (CER) filters can
be used to improve the selectivity.
An RSSI generator delivers a DC signal proportional to the applied input power and is
also used as an ASK demodulator. Via an anti-aliasing filter this signal feeds an ADC
with 10 bits resolution.
The harmonic suppressed limiter output signal feeds a digital FSK demodulator. This
block demodulates the FSK data and delivers an AFC signal which controls the divider
factor of the PLL synthesizer.
A digital receiver, which comprises RSSI peak detectors, a matched data filter, a clock
and data recovery, a data slicer, a frame synchronization and a data FIFO, decodes the
received ASK or FSK data stream. The recovered data and clock signals are accessible
via 2 separate pins. The FIFO data buffer is accessible via the SPI bus interface.
The crystal oscillator serves as the reference frequency for the PLL phase detector, the
clock signal of the Sigma-Delta modulator and divided by two as the 2nd local oscillator
signal. To accelerate the start up time of the crystal oscillator two modes are selectable:
a Low Power Mode (with lower precision) and a High Precision Mode.
Data Sheet
17
V1.0, 2010-02-19
TDA5235
Functional Description
2.4.2
Block Overview
The TDA5235 is separated into the following main blocks:
•
•
•
•
•
•
•
•
•
RF / IF Receiver
Crystal Oscillator and Clock Divider
Sigma-Delta Fractional-N PLL Synthesizer
ASK / FSK Demodulator incl. AFC, AGC and ADC
RSSI Peak Detector
Digital Baseband Receiver
Power Supply Circuitry
System Interface
System Management Unit
2.4.3
RF/IF Receiver
The receiver path uses a double down conversion super-heterodyne/low-IF architecture,
where the first IF frequency is located around 10.7 MHz and the second IF frequency
around 274 kHz. For the first IF frequency an adjustment-free image frequency rejection
is realized by means of two low-side injected I/Q-mixers followed by a second order
passive polyphase filter centered at 10.7 MHz (PPF). The I/Q-oscillator signals for the
first down conversion are delivered from the PLL synthesizer. The frequency selection
in the first IF domain is done by an external CER filter (optionally by two, decoupled by
a buffer amplifier). For moderate or low cost applications, this ceramic filter can be
substituted by a simple LC Pi-filter or completely by-passed using the receiver as a
single down conversion low-IF scheme with 274 kHz IF frequency. The down conversion
to the second IF frequency is done by means of two high-side injected I/Q-mixers
together with an on-chip third order bandpass polyphase filter (PPF2 + BPF). The I/Qoscillator signals for the second down conversion are directly derived by division of two
from the crystal oscillator frequency. The bandwidth of the bandpass filter (BPF) can be
selected from 50 kHz to 300 kHz in 5 steps. For a frequency offset of -150 kHz to -120
kHz, the AFC (Automatic Frequency Control) function is mandatory. Activated AFC
option might require a longer preamble sequence in the receive data stream.
The receiver enable signal (RX_RUN) can be offered at each of the port pins to control
external components. Whenever the receiver is active, the RX_RUN output signal is
active. Active high or active low is configurable via PPCFG2 register.
Data Sheet
18
V1.0, 2010-02-19
TDA5235
Functional Description
The frequency relations are calculated with the following formulas:
f IF1 = 10.7MHz
f IF1
f IF2 = --------39
f crystal = f IF2 × 80
f crystal
f LO2 = ---------------2
f LO1 = f crystal × NF divider
Lim ite r
QMix2
3rd order BP /PP F2
IF2 = 274 kH z
IF
Attenuation
adjust
IMix2
SDCSEL-MUX
MIX2BUF
(var. gain)
CERFilter IF1
10.7 MHz
optional
CERFSEL-MUX
Q-Mix
CERFilter
IF1
10 .7 MHz
IFBUF
LNA
PPFBUF
MUX
RX
Input
2nd order PPF
10.7 MHz
I-Mix
RSSI Generator
LP
harm sup
digital
FSK Demod
LP
alias sup
ASK /
RSSI
ADC
RX
FSK Data
RX
ASK Data
Divider
:N
IQ :2
Channel Filter
Bandwidth select
N
AFC
Filter
ΣΔ Modulator
Channel select
VCO
:1/:2/:3
IQ Divider : 4
Multi Modulos
Divider : N_FN
PD
Crystal
oscil lator
Band select
Channel select
LF select
Channel Filter select
Band select
Loop
Filter
Front end
control unit
IF Attenuation adjust
RSSI Gain/ Offset adjust
LF select
Figure 3
Block Diagram RF Section
The front end of the receiver comprises an LNA, an image reject mixer and a digitally
gain controlled buffer amplifier. This buffer amplifier allows the production spread of the
on-chip signal strip, of external matching circuitry and RF SAW and ceramic IF filters to
be trimmed. The second image reject mixer down converts the first IF to the second IF.
Data Sheet
19
V1.0, 2010-02-19
TDA5235
Functional Description
The bandpass filter follows the subsequent formula:
f center =
f corner, low × f corner, high
Therefore asymmetric corner frequencies can be observed. The use of AFC results in
more symmetry.
A multi-stage bandpass limiter at a center frequency of 274 kHz completes the receiver
chain. The -3dB corner frequencies of the bandpass limiter are typically at 75 kHz and
at 520 kHz.
An RSSI generator delivers a DC signal proportional to the applied input power and is
also used as an ASK demodulator. Via a programmable anti-aliasing filter this signal is
converted to the digital domain by means of a 10-bit ADC.
The limiter output signal is connected to a digital FSK demodulator.
The immunity against strong interference frequencies (so called blockers) is determined
by the available filter bandwidth, the filter order and the 3rd order intercept point of the
front end stages. For Single-Channel applications with moderate requirements to the
selectivity the performance of the on-chip 3rd order bandpass polyphase filter might be
sufficient. In this case no external filters are necessary and a single down conversion
architecture can be used, which converts the input signal frequency directly to the 2nd IF
frequency of 274 kHz.
IF
Attenuation
adjust
RSSI Generator
LP
harm sup
LP
alias sup
RX
FSK Data
digital
FSK Demod
ASK /
RSSI
ADC
RX
ASK Data
Divider
:N
Channel Filter
Bandwidth select
1st LO
Figure 4
L im ite r
QMix2
3 rd o rd e r B P /P P F 2
I F2 = 2 7 4 k H z
IMix2
S D C S E L -M U X
Q-Mix
M IX 2 B U F
( va r. g a i n )
C E RF S E L - M UX
IFB U F
LNA
PPF BU F
MUX
RX
Input
2nd order PPF
1 0 .7 M H z
I-Mix
2nd LO
Single Down Conversion (SDC, no external filters required)
For Multi-Configuration applications requiring different RF channels or systems which
demand higher selectivity the double down conversion scheme together with one or two
external CER filters can be selected. The order of such ceramic filters is in a range of 3,
so the selectivity is further improved and a better channel separation is guaranteed.
Data Sheet
20
V1.0, 2010-02-19
TDA5235
Functional Description
IF
Attenuation
adjust
RSSI Generator
LP
harm sup
LP
alias sup
RX
FSK Data
digital
FSK Demod
ASK /
RSSI
ADC
RX
ASK Data
Divider
:N
Channel Filter
Bandwidth select
1st LO
Figure 5
L im ite r
QMix2
3 r d o r d e r B P /P P F 2
IF2 = 2 7 4 k H z
IMix2
S D C S E L -M U X
Q-Mix
M IX 2 B U F
( va r. g a in )
C E RF S E L-M UX
CERFilter
IF1
10.7 MHz
IFB U F
LNA
PPFBUF
MUX
RX
Input
2 nd ord er P P F
1 0 .7 M H z
I-Mix
2nd LO
Double Down Conversion (DDC) with one external filter
For applications which demand very high selectivity and/or channel separation even two
CER filters may be used. Also in applications where one configuration/channel requires
a wider bandwidth than the other (e.g. TPMS and RKE) the second filter can be bypassed.
IF
Attenuation
adjust
Data Sheet
RSSI Generator
LP
harm sup
LP
alias sup
RX
FSK Data
digital
FSK Demod
ASK /
RSSI
ADC
RX
ASK Data
Divider
:N
Channel Filter
Bandwidth select
1st LO
Figure 6
L im ite r
QMix2
3 rd o rde r B P /P P F2
I F2 = 2 7 4 k H z
IMix2
S D C S E L -M U X
M IX 2 B U F
( va r. g a in )
CERFilter IF1
10.7 MHz
optional
C E RF S E L -M UX
Q-Mix
CERFilter
IF1
10.7 MHz
IFB U F
LNA
PPF BU F
MUX
RX
Input
2nd order PPF
1 0 .7 M H z
I-Mix
2nd LO
Double Down Conversion (DDC) with two external filters
21
V1.0, 2010-02-19
TDA5235
Functional Description
2.4.4
Crystal Oscillator and Clock Divider
The crystal oscillator is a Pierce type oscillator which operates together with the crystal
in parallel resonance mode. An automatic amplitude regulation circuitry allows the
oscillator to operate with minimum current consumption. In SLEEP Mode, where the
current consumption should be as low as possible, the load capacitor must be small and
the frequency is slightly detuned, therefore all internal trim capacitors are disconnected.
The internal capacitors are controlled by the crystal oscillator calibration registers
XTALCALx. With a binary weighted capacitor array the necessary load capacitor can be
selected.
Whenever a XTALCALx register value is updated, the selected trim capacitors are
automatically connected to the crystal so that the frequency is precise at the desired
value. The SFR control bit XTALHPMS can be used to activate the High Precision Mode
also during SLEEP Mode.
fsys
9
Setting
automatically
controlled
( ≤ 1pF steps )
XTALCAL0
XTALCAL1
Oscillator -Core
XTAL1
Figure 7
Data Sheet
Binary weighted
Capacitor-Array
Binary weighted
Capacitor-Array
(DGND)
XTALHPMS
XTAL2
Crystal Oscillator
22
V1.0, 2010-02-19
TDA5235
Functional Description
Recommended Trimming Procedure
• Set the registers XTALCAL0 and XTALCAL1 to the expected nominal values
• Set the TDA5235 to Run Mode Slave
• Wait for 0.5ms minimum
• Trim the oscillator by increasing and decreasing the values of XTALCAL0/1
• Register changes larger than 1 pF are automatically handled by the TDA5235 in 1pF
steps
• After the Oscillator is trimmed, the TDA5235 can be set to SLEEP mode and keeps
these values during SLEEP mode
• Add the settings of XTALCAL0/1 to the configuration. It must be set after every power
up or brownout!
Using the High Precision Mode
As discussed earlier, the TDA5235 allows the crystal oscillator to be trimmed by the use
of internal trim capacitors. It is also possible to use the trim functionality to compensate
temperature drift of crystals.
During Run Mode (always when the receiver is active) the capacitors are automatically
connected and the oscillator is working in the High Precision Mode.
On entering SLEEP Mode, the capacitors are automatically disconnected to save
power.
If the High Precision Mode is also required for SLEEP Mode, the automatic disconnection of trim capacitors can be avoided by setting XTALHPMS to 1 (enable XTAL High
Precision Mode during SLEEP Mode).
External Clock Generation Unit
A built in programmable frequency divider can be used to generate an external clock
source out of the crystal reference. The 20 bit wide division factor is stored in the
registers CLKOUT0, CLKOUT1 and CLKOUT2. The minimum value of the
programmable frequency divider is 2. This programmable divider is followed by an
additional divider by 2, which generates a 50% duty cycle of the CLK_OUT signal. So
the maximum frequency at the CLK_OUT signal is the crystal frequency divided by 4.
The minimum CLK_OUT frequency is the crystal frequency divided by 221.
To save power, this programmable clock signal can be disabled by the SFR control bit
CLKOUTEN. In this case the external clock signal is set to low.
Data Sheet
23
V1.0, 2010-02-19
TDA5235
Functional Description
The resulting CLK_OUT frequency can be calculated by:
C L KO UT E N
C LK OU T2
C LK OU T1
C LK OU T0
f sys
f CLKOUT = --------------------------------------------2 ⋅ divisionfactor
Enable
fsys
Enable
2 x f C LK_OU T
20 Bit Counter
Figure 8
Divide
by 2
fC LK _OU T
External Clock Generation Unit
The maximum CLK_OUT frequency is limited by the driver capability of the PPx pin and
depends on the external load connected to this pin. Please be aware that large loads
and/or high clock frequencies at this pin may interfere with the receiver and reduce
performance.
After Reset the PPx pin is activated and the division factor is initialized to 11 (equals
fCLK_OUT = 998 kHz).
A clock output frequency higher than 1 MHz is not supported.
For high sensitivity applications, the use of the external clock generation unit is not
recommended.
Data Sheet
24
V1.0, 2010-02-19
TDA5235
Functional Description
2.4.5
Sigma-Delta Fractional-N PLL Block
The Sigma-Delta Fractional-N PLL is fully integrated on chip. The Voltage Controlled
Oscillator (VCO) with on-chip LC-tank runs at approximately 3.6 GHz and is first divided
with a band select divider by 1, 2 or 3 and then with an I/Q-divider by 4 which provides
an orthogonal local oscillator signal for the first image reject mixer with the necessary
high accuracy.
The multi-modulus divider determines the channel selection and is controlled by a
3rd order Sigma-Delta Modulator (SDM). A type IV phase detector, a charge pump with
programmable current and an on-chip loop filter closes the phase locked loop.
To 1 st mixer
3.6 GHz VCO Loop Filter
IQ Divider
÷4
Band Select
÷1/÷2/÷3
Multimodulus
Divider
Channel FN
CP
PFD
ΣΔ Modulator
QOSC
22MHz
AFC filter
AFC-data
Figure 9
Data Sheet
Synthesizer Block Diagram
25
V1.0, 2010-02-19
TDA5235
Functional Description
When defining a Multi-Configuration system requiring different RF channels, the
correct selection of channel spacing is extremely important. A general rule is not
possible, but following must be considered:
• If an additional SAW filter is used, all channels including their tolerances have to be
inside the SAW filter bandwidth.
• The distance between channels must be high enough, that no overlapping can occur.
Strong input signals may still appear as recognizable input signal in the neighboring
channel because of the limited suppression of IF Filters. Example: a typical 330kHz IF
filter has at 10.3 MHz ( 10.7 MHz - 0.4 MHz ) only 30 dB suppression. A -70 dBm input
signal appears like a -100 dBm signal, which is inside the receiver sensitivity. In critical
cases the use of two IF filters must be considered. See also Chapter 2.4.3 RF/IF
Receiver.
2.4.5.1
PLL Dividers
The divider chain consists of a band select divider 1/2/3, an I/Q-divider by 4 which
provides an orthogonal 1st local oscillator signal for the first image reject mixer with the
necessary high accuracy and a multi-modulus divider controlled by the Sigma-Delta
Modulator. With the band select divider, the wanted frequency band is selected. Divide
by 1 selects the 915 MHz and 868 MHz band, divide by 2 selects the 434 MHz band and
divide by 3 selects the 315 MHz band. The ISM band selection is done via bit group
BANDSEL in x_PLLINTC1 register.
2.4.5.2
Digital Modulator
The 3rd order Sigma-Delta Modulator (SDM) has a 22 bit wide input word, however the
LSB is always high, and is clocked by the XTAL oscillator. This determines the
achievable frequency resolution.
The Automatic Frequency Control Unit filters the actual frequency offset from the FSK
demodulator data and calculates the necessary correction of the divider factor to achieve
the nominal IF center frequency.
Data Sheet
26
V1.0, 2010-02-19
TDA5235
Functional Description
2.4.6
ASK and FSK Demodulator
B = 50..300kHz
channel filter FM limiter
image suppression /
band limitation (noise)
FSK
PPF2
BP
2nd
conversion
33 / 46 / 65 / 93 / 132 /
190 / 239 / 282 kHz
(2sided PDF BW)
RSSI
FSK
demodulator
FSK
demodulator
AFC track/freeze
AFC
loop filter
RF PLL ctrl
FSK/ASK
Rate adapter
Demodulated
Data
Bypass
Rate doubler
Decimation
8 … 16 samples /chip
(data rate dependent )
Temp
VDDD/2
Mux
ADC
RSSI Slope
RSSI Offset
Dig. Gain
Control
Peak Memory
Filter
delog
ASK
buffer
Div
fSystem
RSSI
AGC
RSSI Peak
Detector
register
RSSIPMF
register
RSSIPWU
(internal
signal)
Begin of config /
channel ,
x*WULOT
Figure 10
Analog Gain Control
RSSIPWU
register
End of config/
channel
>
WU event
TH, BL, BH
Functional Block Diagram ASK/FSK Demodulator
The IC comprises two separate demodulators for ASK and FSK.
After combining FSK and ASK data path, a sampling rate adaptation follows to meet an
output oversampling between 8 and 16 samples per chip. Finally, an oversampling of 8
samples per chip can be achieved using a fractional sample rate converter (SRC) with
linear interpolation (for further details see Figure 15).
2.4.6.1
ASK Demodulator
The RSSI generator delivers a DC signal proportional to the applied input power at a
logarithmic scale (dBm) and is also used as an ASK demodulator. Via a programmable
anti-aliasing filter this signal is converted to the digital domain by means of a 10-bit ADC.
For the AM demodulation a signal proportional to the linear power is required. Therefore
a conversion from logarithmic scale to linear scale is necessary. This is done in the digital
domain by a nonlinear filter together with an exponential function. The analog RSSI
signal after the anti-aliasing filter is available at the RSSI pin via a buffer amplifier. To
enable this buffer the SFR control bit RSSIMONEN must be set. The anti-aliasing filter
can be by-passed for visualization on the RSSI pin (see AAFBYP control bit).
Data Sheet
27
V1.0, 2010-02-19
TDA5235
Functional Description
2.4.6.2
FSK Demodulator
The limiter output signal, which has a constant amplitude over a wide range of the input
signal, feeds the FSK demodulator. There is a configurable lowpass filter in front of the
FSK demodulation to suppress the down conversion image and noise/limiter harmonics
(FSK Pre-Demodulation Filter, PDF). This is realized as a 3rd order digital filter. The
sampling rate after FSK demodulation is fixed and independent from the target data rate.
2.4.6.3
Automatic Frequency Control Unit (AFC)
In front of the image suppression filter a second FSK demodulator is used to derive the
control signal for the Automatic Frequency Control Unit, which is actually the DC
value of the FSK demodulated signal. This makes the AFC loop independent from signal
path filtering and allow so a wider frequency capture range of the AFC. The derivation of
the AFC control signal is preferably done during the DC free preamble and is then frozen
for the rest of the datagram.
Since the digital FSK demodulator determines the exact frequency offset between the
received input frequency and the programmed input center frequency of the receiver,
this offset can be corrected through the sigma delta control of the PLL. As shown in
Figure 10, for AFC purposes a parallel demodulation path is implemented. This path
does not contain the digital low pass filter (PDF, Pre-Demodulation Filter). The entire IF
bandwidth, filtered by the analog bandpass filter only, is processed by the AFC
demodulator.
There are two options for the active time of the AFC loop:
•
•
1. always on
2. active for a programmable time relative to a signal identification event (several
options can be programmed in SFR).
In the latter case the AFC can either be started or frozen relative to the signal
identification. After the active time the offset for the sigma-delta PLL (SD PLL) is frozen.
The programming of the active time is especially necessary in case the expected frame
structure contains a gap (noise) between wake-up and payload in order to avoid the AFC
from drifting.
AFC works both for FSK and ASK. In the latter case the AFC loop only regulates during
ASK data = high.
The maximum frequency offset generated by the AFC can be limited by means of the
x_AFCLIMIT register. This limit can be used to avoid the AFC from drifting in the
presence of interferers or when no RF input signal is available (AFC wander). A
maximum AFC limit of 42 kHz is recommended. AFC wandering needs to be kept in mind
especially when using Run Mode Slave.
Data Sheet
28
V1.0, 2010-02-19
TDA5235
Functional Description
K1 = integrator1 gain
x_AFCLIMIT
x_AFCK1CFG0/1
integrator 1
K1
x16
limit
+
AFC Demod out
integrator 2
hold
K2
x4
limit
SDPLL
scaling &
limiting
FreqOffset
HOLD
hold
Freeze* / Track
Delay
x_AFCK2CFG0/1
x_AFCAGCD
K2 = integrator 2 gain
Figure 11
AFC Loop Filter (I-PI Filtering and Mapping)
The bandwidth (and thus settling time) of the loop is programmed by means of the
integrator gain coefficients K1 and K2 (x_AFCK1CFG and x_AFCK2CFG register).
K1 mainly determines the bandwidth. K2 influences the dynamics/damping (overshoot)
- smaller K2 means smaller overshoot, but slower dynamics. The bandwidth of the AFC
loop is approximately 1.3*K1.
To avoid residual FM, limiting the AFC BW to 1/20 ~ 1/40 of the bit rate is suggested,
therefore K1 must be set to approximately 1/50 ~ 1/100 of the bit rate. For most
applications K2 can be set equal to K1 (overshoot is then <25%).
When very fast settling is necessary K1 and K2 can be increased up to bit rate/10,
however, in this case approximately 1dB sensitivity loss is to be expected due to the AFC
counteracting the input FSK signal.
AFC limitation at Local Oscillator (LO) frequencies at multiples of reference frequency
(f_xtal). When AFC is activated and AFC drives the wanted LO frequency over the
integer limit of Sigma Delta (SD) modulator, the SD modulator stucks at frac=1.0 or
frac=0.0 due to saturation. So when AFC can change the integer value for the LO
(register x_PLLINTC1) within the frequency range LO-frequency +/- AFC-limit, a change
of the LO injection side or a smaller AFC-limit is recommended.
The frequency offset found by AFC (AFC loop filter output) can be readout via register
AFCOFFSET, when AFC is activated. The value is in signed representation and has a
frequency resolution of 2.68 kHz/digit. The output can be limited by the x_AFCLIMIT
register.
Data Sheet
29
V1.0, 2010-02-19
TDA5235
Functional Description
2.4.6.4
Digital Automatic Gain Control Unit (AGC)
Automatic Gain Control (AGC) is necessary mainly because of the limited dynamic range
of the on-chip bandpass filter (BPF). The dynamic range reduces to less than 60dB in
case of minimum BPF bandwidth.
AGC is used to cover the following cases:
1. ASK demodulation at large input signals
2. RSSI reading at large input signals
3. Improve IIP3 performance in either FSK or ASK mode
The 1st IF buffer (PPFBUF, see Figure 3) can be fine tuned "manually" by means of 4
bits thus optimizing the overall gain to the application (attenuation of 0dB to -12dB by
means of IFATT0 to IFATT15 in DDC mode; SDC mode has lower IFATT range). This
buffer allows the production spread of external components to be trimmed.
The gain of the 2nd IF path is set to three different values by means of an AGC algorithm.
Depending on whether the receiver is used in single down conversion or in double down
conversion mode the gain control in the 2nd IF path is either after the 2nd poly-phase
network or in front of the 2nd mixer.
The AGC action is illustrated in the RSSI curve below:
Analog (blue) &
digital (black )
RSSI output
Mixer2
saturation
BPF bypassed
AGC OFF
Max . B W
BPF
saturation
AGC ON
Min. B W
margin
Analog AGC
attack point
hy s teres is
Analog AGC
decay point
Max . B W
Front- end
noise x gain
Max. FE gain
(IFA TT 0)
Min. B W
Min. FE gain
(IFA TT 15)
AGCTUP
Data Sheet
AGCTLO
AGCTHOFFS
Figure 12
AGCHYS
AGCHYS
Limiter
noise floor
Input power
Analog RSSI output curve with AGC action ON (blue) vs. OFF (black)
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Functional Description
Digital RSSI, AGC and Delog:
In order to match the analog RSSI signal to the digital RSSI output a correction is
necessary. It adds an offset (RSSIOFFS) and modifies the slope (RSSISLOPE) such
that standardized AGC levels and an appropriate DELOG table can be applied.
Upon entering the AGC unit the digital RSSI signal is passed through a Peak Memory
Filter (PMF). This filter has programmable up and down integration time constants
(PMFUP, PMFDN) to set attack respectively decay time. The integration time for decay
time must be significantly longer than the attack time in order to avoid the AGC interfering
with the ASK modulation.
The integrator is followed by two digital Schmitt triggers with programmable thresholds
(AGCTLO; AGCTUP) - one Schmitt trigger for each of the two attack thresholds (two
digital AGC switching points). The hysteresis of the Schmitt triggers is programmable
(AGCHYS) and sets the decay threshold. The Schmitt triggers control both the analog
gain as well as the corresponding (programmable) digital gain correction (DGC).
The difference ("error") signal in the PMF is actually a normalized version of the
modulation. This signal is then used as input for the DELOG table.
AGC threshold programming
The SFR description for the AGC thresholds are in dBs. The first value to set is the AGC
threshold offset in AGCTHOFFS.
This value is the offset relative to 0 input (no noise, no signal), which for the default
setting of gain, and assuming typical insertion loss of matching network and ceramic
filter, can be extrapolated to be approximately -143dBm.
In this case the default setting of the AGCTHOFFS of 63.9dB corresponds to an input
power of approximately -79dBm (= -143dBm + 63.9dB).
The low (digital) AGC threshold is then -79 + 12.8dB (default AGCTLO) = -66dBm and
the upper (digital) AGC threshold is -79 + 25.6 (default AGCTUP) = -53dBm.
Therefore a margin of about 6dB is indicated before a degradation of the linearity of the
2nd IF can be observed when using the 50kHz BPF or even about 16dB when using the
300kHz BPF.
The input power level at which the AGC switches back to maximum gain is -66dBm 21.3dB (default AGCHYS) = -87dBm. This provides enough margin against the minimum
sensitivity.
Data Sheet
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Functional Description
When AGC is activated, RSSI is untrimmed, IFATT <= 5.6dB and the same RSSI offset
should be applied for all bandpass filter settings, then the settings in Table 2 can be
applied, where a small reduction of the RSSI input range can be observed.
Table 2
AGC Settings 1
AGC Threshold Hysteresis = 21.3 dB
AGC Digital RSSI Gain Correction = 15.5 dB
AGC
AGC
AGC
Threshold Threshold Threshold
Offset
Low
Up
BPF
RSSI Offset
Compensation
(untrimmed) 1)
300 kHz
32
63.9 dB
8
4
5 dB
200 kHz
32
63.9 dB
6
2
5 dB
125 kHz
32
63.9 dB
5
0
5 dB
80 kHz
32
51.1 dB
11
6
2.8 dB
50 kHz
32
51.1 dB
9
5
0 dB
RSSI Input
Range
Reduction
1) Note: This value needs to be used for calculating the register value
For the full RSSI input range, the values in Table 3 can be applied.
Table 3
AGC Settings 2
AGC Threshold Hysteresis = 21.3 dB
AGC Digital RSSI Gain Correction = 15.5 dB
AGC
AGC
AGC
Threshold Threshold Threshold
Offset
Low
Up
BPF
RSSI Offset
Compensation
(untrimmed) 1)
300 kHz
-18
63.9 dB
5
1
200 kHz
-18
51.1 dB
11
7
125 kHz
-18
51.1 dB
10
5
80 kHz
4
51.1 dB
9
5
50 kHz
32
51.1 dB
9
5
1) Note: This value needs to be used for calculating the register value
Data Sheet
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TDA5235
Functional Description
Attack and Decay coefficients PMF-UP & PMF-DOWN:
The settling time of the loop is determined by means of the integrator gain coefficients
PMFUP and PMFDN, which need to be calculated from the wanted attack and decay
times.
The ADC is running at a fixed sampling frequency of 274kHz. Therefore the integrator is
integrating with PMFUP*274k per second, i.e. time constant is 1/(PMFUP*274k). The
attack times are typically 16 times faster than the decay times.
Typical calculation of the coefficients by means of an example:
•
•
PMFUP = 2^-round( ln(AttTime / BitRate * 274kHz) / ln(2) )
PMFDN = 2^-round( ln(DecTime / BitRate * 274kHz) / ln(2) ) / PMFUP
where AttTime, DecTime = attack, decay time in number of bits
Note: PMFDN = overall_PMFDN / PMFUP
Example:
BitRate = 2kbps
AttTime = 0.1 bits
=> PMFUP = 2^-round(ln(0.1bit/2kbps*274kHz)/ln(2)) = 2^-round(3.8) = 2^-4
DecTime = 2 bits
=> PMFDN = 2^-round(ln(2bit/2kbps*274kHz)/ln(2))/PMFUP = 2^-round(8.1)/2^-4 = 2^-4
Note: In case of ASK with large modulation index the attack time (PMFUP) can be up to
a factor 2 slower due to the fact that the ASK signal has a duty cycle of 50% - during the
ASK low duration the integrator is actually slightly discharged due to the decay set by
PMFDN.
The AGC start and freeze times are programmable. The same conditions can be used
as in the corresponding AFC section above. They will however, be programmed in
separate SFR registers.
Data Sheet
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TDA5235
Functional Description
2.4.6.5
Analog to Digital Converter (ADC)
In front of the AD converter there is a multiplexer so that also temperature and VDDD
can be measured (see Figure 10).
The default value of the ADC-MUX is RSSI (register ADCINSEL: 000 for RSSI; 001 for
Temperature; 010 for VDDD/2).
After switching ADC-MUX to a value other than RSSI in SLEEP Mode, the internal
references are activated and this ADC start-up lasts 100µs. So after this ADC start-up
time the readout measurements may begin. The chip stays in this mode until
reconfiguration of register ADCINSEL to setting RSSI. However, it is recommended to
measure temperature during SLEEP mode (This is also valid for VDDD).
Readout of the 10-bit ADC has to be done via ADCRESH register (the lower 2 bits in
ADCRESL register can be inconsistent and should not be used).
Typical the ADC refresh rate is 3.7 µs. Time duration between two ADC readouts has to
be at least 3.7 µs, so this is already achieved due to the maximum SPI rate (16 bit for
SPI command and address last 8µs at an SPI rate of 2MBit/s). The EOC bit (end of
conversion) indicates a successful conversion additionally. Repetition of the readout
measurement for several times is for averaging purpose.
The input voltage of the ADC is in the range of 1 .. 2 V. Therefore VDDD/2 (= 1.65 V
typical) is used to monitor VDDD.
Further details on the measurement and calibration procedure for temperature and
VDDD can be taken from the corresponding application note.
Data Sheet
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TDA5235
Functional Description
2.4.7
RSSI Peak Detector
The IC possesses several digital RSSI peak level detectors. The RSSI level is averaged
over 4 samples before it is fed to any of the peak detectors. This prevents the evaluated
peak values to be dominated by single noise peaks.
f sys
EOM
ADC Sampling
Clock Generation
Compare
Update
Update
Peak Detector
Payload
Peak
Value
Peak Value
Register
RSSIPPL
Load
Divide
by 4
fADC
Integrate
A
from
RSSI
Generator
RSSI Slope
D
FSYNC
Bit
position
Dump
RSSI
I&D Averaging Filter
RSSI Offset
Peak
Detector
Track
Control
fADC/4
Compare
Update
Peak Detector
PeakValue
RSSIPRX
Load
to
ASK path
RX_RUN
&
Read Access to
Register RSSIPRX
from
FSM
from
SPI Controller
RSSIRX
Figure 13
Peak Detector Unit
Peak Detector Payload is used to measure the input signal power of a received and
accepted data telegram. It is read via SFR RSSIPPL.
Observation of the RSSI signal starts at the detection of a TSI (FSYNC) and ends with
the detection of EOM. The internal RSSIPPL value is cleared after FSYNC. The
evaluated RSSI peak level RSSIPPL is transferred to the RSSIPPL register at EOM.
Starting the observation of the RSSI level can be delayed by a selectable number of data
bits and is controlled by the register x_PKBITPOS. A latency in the generation of FSYNC
and EOM of approx. 2..3 bits in relation to the contents of the Peak Detector must be
considered. Within the boundaries described, the register RSSIPPL always contains the
peak value of the last completely received data telegram. The register RSSIPPL is reset
to 0 at power up reset only.
Peak Detector is used to measure RSSI independent of a data transfer and to digitally
trim RSSI. It is read via SFR RSSIPRX.
Observation of the RSSI signal is active whenever the RX_RUN signal is high. The
RSSIPRX register is refreshed and the Peak Detector is reset after every read access to
RSSIPRX.
It may be required to read RSSIPRX twice to obtain the required result. This is because,
for example, during a trim procedure in which the input signal power is reduced, after
Data Sheet
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TDA5235
Functional Description
reading RSSIPRX, the peak detector will still hold the higher RSSI level. After reading
RSSIPRX the lower RSSI level is loaded into the Peak Detector and can be read by
reading RSSIPRX again.
Register RSSIPRX should not be read-out faster than 41µs in case AGC is ON (as
register value would not represent the actual, but a lower value).
When the RX_RUN signal is inactive, a read access has no influence to the peak
detector value. The register RSSIPRX is reset to 0 at power up reset.
Peak Detector Wake-Up RSSIPWU (see Figure 10) is used to measure the input signal
power during Wake-Up search. The internal signal RSSIPWU gets initialized to 0 at start
of the first observation time window at the beginning of each configuration. The peak
value of this signal is tracked during Wake-Up search.
In case of a Wake-Up, the actual peak value is written in the RSSIPWU register. Even
in case no Wake-Up occurred, actual peak value is written in the RSSIPWU register at
the end of the actual configuration of the Self Polling period. So if no Wake-Up occurred,
then the RSSIPWU register contains the peak value of the last configuration of the Self
Polling period, even in a Multi-Configuration setup. This functionality can be used to track
RSSI during unsuccessful Wake-Up search due to no input signal or due to blocking
RSSI detection.
For further details please refer to Chapter 2.4.8.5 Wake-Up Generator and
Chapter 2.6.2 Polling Timer Unit.
Input
Data Pattern
Noise
Run-In
....
TSI D0 D1
Dn
Dn Dn Dn
Dn
-1
+1 +2 +3
....
EOM
Noise
Run-In
TSI D0 D1
....
SPI read out
RSSIPPL&RSSIPRX
internal RSSIPPL
RSSIPPL Register
internal RSSI
FSYNC clears the
internal RSSIPPL
internal RSSIPRX =
RSSIPRX Register
internal RSSI
*1
Reset
*1
FSync
n = PKBITPOS
*1
*1
SPI
EOM
FSync
*1 Computation Delay due to filtering and signal calculation.
Figure 14
Data Sheet
Peak Detector Behavior
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Functional Description
Recommended Digital Trimming Procedure
•
•
•
•
•
•
•
•
•
•
Download configuration file (Run Mode Slave; RSSISLOPE, RSSIOFFS set to
default, i.e. RSSISLOPE=1, RSSIOFFS=0)
Turn off AGC (AGCSTART=0) and set gain to AGCGAIN=0
Apply PIN1 = -85 dBm RF input signal
Read RSSIRX eleven times (minimum 10 ms in-between readings), use average of
last ten readings (always), store as RSSIM1
Apply PIN2 = -65 dBm RF input signal
Read RSSIRX eleven times (minimum 10 ms in-between readings), use average of
last ten readings (always), store as RSSIM2
Calculate measured RSSI slope SLOPEM=(RSSIM2-RSSIM1)/(PIN2-PIN1)
Adjust RSSISLOPE for required RSSI slope SLOPER as follows:
RSSISLOPE=SLOPER/SLOPEM
Adjust RSSIOFFS for required value RSSIR2 at PIN2 as follows:
RSSIOFFS=(RSSIR2-RSSIM2)+(SLOPEM-SLOPER)*PIN2
The new values for RSSISLOPE and RSSIOFFS have to be added to the
configuration!
Notes:
1. The upper RF input level must stay well below the saturation level of the receiver (see
Chapter 2.4.6.4 Digital Automatic Gain Control Unit (AGC))
2. The lower RF input level must stay well above the noise level of the receiver
3. If IF Attenuation is trimmed, this has to be done before trimming of RSSI
4. If RSSI needs to be trimmed in a higher input power range the AGCGAIN must be set
accordingly
Data Sheet
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TDA5235
Functional Description
2.4.8
Digital Baseband (DBB) Receiver
Blind Sync
Initial Phase & Data rate
FSK
detector
CR PLL
Slicer
CDR PLL
sync
chip_data_clock
adjust_length
CH_STR
SRC
bypass
8 to 16
samples
per chip
Matched Filter
fractional SRC
From ASK/
FSK
Demodulator
Signal
Detector
Data
Slicer
Chip Data
Decoder
Chip
Data
Invert
chip_data
CH_DATA
fs out / fs in = 0.5 … 1.0
CHIPDINV
MUX
RAW Data Slicer
for external
processing
Decoder
SIGN
Data
Invert
DINVEXT
DATA
(Sliced RAW Data for
external processing )
Figure 15
Framer
(TSI Detector)
WU Unit
Data
Invert
data_clk
data
eom
fsync
FIFO
wakeup
RXSTR RXD
DATA_MATCHFIL
(Matched Filtered Data
for external processing )
Functional Block Diagram Digital Baseband Receiver
The digital baseband receiver comprises a matched data filter, a clock and data
recovery, a data slicer, a line decoder, a wake-up generator, a frame synchronization
and a data FIFO. The recovered data and clock signals are accessible via 2 separate
pins. The FIFO data buffer is accessible via the SPI bus interface.
2.4.8.1
Data Filter and Signal Detection
The data filter is a matched filter (MF). The frequency response of a matched filter has
ideally the same shape as the power spectral density (PSD) of the originally transmitted
signal, therefore the signal-to-noise ratio (SNR) at the output of the matched filter
becomes maximum. The input sampling rate of the baseband receiver has to be
between 8 and 16 samples per chip. The oversampling factor within this range is
depending on the data rate (see Figure 10). The MF has to be adjusted accordingly to
this oversampling. After the MF a fractional sample rate converter (SRC) is applied using
linear interpolation. Depending on the data rate decimation is adjusted within the range
1...2. Finally, at the output of the fractional SRC the sampling rate is adjusted to 8
samples per chip for further processing.
To distinguish whether the incoming signal is really a signal or only noise adequate
detectors for ASK and FSK are built in.
Data Sheet
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TDA5235
Functional Description
Signal and Noise Detector
The Signal Detector decides between acceptable and unacceptable data (e.g. noise).
This decision is taken by comparing the signal power of the actually received data
(register SPWR) with a configurable threshold level (registers x_SIGDET0/1), which
must be evaluated. In case the actual signal power is above the threshold, acceptable
data has been detected.
To decide in case of FSK whether there is a data signal or simply noise at the output of
the rate adapter, there is a Noise Detector implemented. The principle is based on a
power measurement of the demodulated signal. The current noise power is stored in the
NPWR register and is updated at every SPI controller access. The Noise Detector is
useful if data signal is transmitted with small FSK deviations. In case the current noise
power (register NPWR) is below the configurable threshold (register x_NDTHRES), a
data signal has been detected.
The Signal Recognition mode must be configured based on whether ASK or FSK
modulation is used. Signal Recognition can be a combination of Signal Detector and
Noise Detector:
•
Signal Detector (=Squelch) only (related registers: x_SIGDET0, x_SIGDET1 and
SPWR). This mode is generally used for ASK and recommended for FSK.
• Noise Detector only (related registers: x_NDTHRES and NPWR).
• Signal and Noise Detector simultaneously.
• Signal and Noise Detector simultaneously, but the FSK noise detect signal is valid
only if the x_SIGDETLO threshold is exceeded. This is the recommended FSK mode,
if minimum FSK deviation is not sufficient to use Signal Detector only.
Signal Recognition can also be used as Wake-up on Level criterion (see
Chapter 2.4.8.5).
Figure 16 shows the system characteristics to consider in choosing the best Signal
Detector level. On the one hand, a higher SIGDET threshold level must be set for
achieving good FAR (False Alarm Rate) performance, but then the MER/BER (Message
Error Rate/Bit Error Rate) performance will decrease. On the other hand, the MER/BER
performance can be increased by setting smaller SIGDET threshold levels but then the
FAR performance will worsen.
Data Sheet
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V1.0, 2010-02-19
TDA5235
Functional Description
input data
telegram
signal pow er
better FAR
performance
SD TH R level area
better
MER/BER
performance
high SD THR level
low SD TH R level
Figure 16
Signal Detector Threshold Level
Quick Procedure to Determine Signal and Noise Detector Thresholds
Preparation
A setup is required with original RF hardware as in the final application. The values of
SPWR and NPWR can be read via the final application.
A complete configuration file using right modulation, data rate and Run Mode Slave,
must be prepared and downloaded to the TDA5235.
Signal Detector Threshold for ASK
Take 500 readings of SPWR (50 are also possible, but this leads to less accurate results)
with no RF input signal applied (=noise only). Calculate average and Standard Deviation.
Signal Detector Threshold is average plus 2 times the Standard Deviation. To load the
x_SIGDET0/1 register the calculated value must be rounded and converted to
hexadecimals. For a final application, the Signal Detector Threshold should be varied to
optimize the false alarm rate and the sensitivity.
Signal and Noise Detector Thresholds for FSK
Signal Detector Threshold
Do 500 (50) readings of SPWR with no RF input signal applied (=noise only). Calculate
average and Standard Deviation. Signal Detector Threshold is average plus 2 times the
Standard Deviation. Of course this value has to be rounded and converted to
Data Sheet
40
V1.0, 2010-02-19
TDA5235
Functional Description
hexadecimals. For a final application the Signal Detector Threshold should be varied to
optimize the false alarm rate and the sensitivity.
Verification if Squelch only is possible
Apply a bit pattern (e.g. PRBS9) with correct data rate at about -80 dBm input signal
power and minimum FSK deviation to the RF input. Do 500 (50) readings of SPWR,
calculate average minus three times the Standard Deviation. This value should be higher
than the calculated Signal Detector Threshold calculated above. If this is not the case,
Signal Detector AND Noise Detector must be used.
Noise Detector Threshold
Do 500 (50) readings of NPWR with no RF input signal applied (=noise only). Calculate
average and Standard Deviation. Noise Detector Threshold is average minus the
Standard Deviation. Round this value and convert it to hexadecimals. For a final
application, the Noise Detector Threshold should be varied to optimize false alarm rate
and sensitivity.
Signal Detector Low Threshold
The Signal Detector Low Threshold is always required in combination with the Noise
Detector.
Set register bit SDLORE to 1 and set bit group SDLORSEL to 00. Apply a bit pattern (e.g.
PRBS9) at correct data rate at about -80 dBm input signal power and minimum FSK
deviation to the RF input. Do 500 (50) readings of SPWR, calculate average. If average
is larger than 200 dec (=0xC8), SDLORSEL has to be increased to the next larger value
until average is smaller than 200 dec. x_SIGDETLO = 0.8 * (average - 3 * Standard
Deviation). Set register SDLORE back to 0. The last setting of bit group SDLORSEL
must also be used for configuration!
Verification
Threshold settings should be verified by testing receiver sensitivity over the input
frequency range, with a step size of 100Hz, at minimum FSK deviation with all
combinations of minimum and maximum data rate and duty cycle.
Further detailed information can be taken from the corresponding Application Note.
Data Sheet
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TDA5235
Functional Description
2.4.8.2
Encoding Modes
The IC supports the following Bi-phase encodings:
•
•
•
•
Manchester code
Differential Manchester code
Bi-phase space code
Bi-phase mark code
The encoding mode is set and enabled by bit group CODE in x_DIGRXC configuration
register.
Data
1
0
1
0
0
1
1
0
Clock
Manchester
Differential Manchester
Biphase Space
Biphase Mark
Figure 17
Coding Schemes
The encoding modes Inverted Manchester and Inverted Differential Manchester can also
be decoded internally by usage of CHIPDINV bit in x_DIGRXC register (see Figure 15).
All the Manchester symbol combinations including Code Violations are shown in
Figure 18. Digital 0 and 1 are coded with the change of the amplitude in the middle of
the symbol period. The Code Violations (CV) M (mark) and S (space), are coded as
low/high signal levels.
Figure 18
Data Sheet
0
1
S
M
1st 2nd
Chip Chip
1st 2nd
Chip Chip
1st 2nd
Chip Chip
1st 2nd
Chip Chip
Manchester Symbols including Code Violations
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TDA5235
Functional Description
2.4.8.3
Clock and Data Recovery
CDRDRTHRN
CDRDRTHRP
x_CDRRI
x_CDRTOLB
x_CDRTOLC
An all-digital PLL (ADPLL) recovers the data clock from the incoming data stream. The
second main function is the generation of a signal indicating symbol synchronization.
Synchronization on the incoming data stream generally occurs within the first 4 bits of a
telegram.
Tnom / 16
EOM
from Clock
Recovery Slicer
Symbol
Sync found
Timing Extrapolation
Phase
Detector
PI
Loop Filter
Digital
Controlled
Oscillator
Tnom / 2
x_TSIGAP
(GAPVAL)
x_CDRI
x_CDRP
x_TSIMODE
(TSIGRSYN)
Tnom / 2
x_TVWIN
Figure 19
Recovered
Clock
Clock Recovery (ADPLL)
Clock Recovery is implemented as standard ADPLL PI regulator with Timing
Extrapolation Unit for fast settling.
In the unlocked state, the Timing Extrapolation Unit calculates the frequency offset for
the incoming data stream. If the defined number of Bi-phase encoded bits are detected
(the RUNIN length can be set in the x_CDRRI register), the I-part and the PLL oscillator
will be set and the PLL will be locked.
When x_CDRRI.RUNLEN is set to small values, then the I-part is less accurate (residual
error) and can lead to a longer needed PLL settling time and worse performance in the
Data Sheet
43
V1.0, 2010-02-19
TDA5235
Functional Description
first following bits. Therefore the selected default value is a good compromise between
fast symbol synchronization and accuracy/performance.
Duty cycle and data rate acceptance limits are adjustable via registers. After locking, the
clock must be stable and must follow the reference input. Therefore, a rapid settling
procedure (Timing Extrapolation Unit) and a slow PLL are implemented.
If the PLL is locked, the reference signal from the Clock Recovery Slicer is used in the
phase detector block to compute the actual error. The error is used in the PI loop filter to
set the digital controlled oscillator running frequency. For the P, I and Timing
Extrapolation Unit settings, the default values for the x_CDRP and x_CDRI control
registers are recommended.
The PLL will be unlocked, if a code violation of more than the defined length is detected,
which is set in the x_TVWIN control register. Another criterion for PLL resynchronization
is an End Of Message (EOM) signalled by the Framer block.
The PLL oscillator generates the chip clock (2 * fdata).
The internal PLL lock signal used by the Framer is generated up to 1 bit before RUNIN
ends. The Timing Extrapolation Unit counts the incoming edges and interprets the delay
between two edges as a bit or a chip. Due to the fact that the first edge of a “Low” bit,
coded as ’0’ and ’1’, rises one chip later than a “High” bit, the PLL locks later in this case
(see Figure 20). The real needed RUNIN time can be shorter than the configured
RUNIN length in the x_CDRRI register by up to two chips. This should be considered
when setting the TSI pattern and/or TSI length. See also Chapter 2.4.8.6 Frame
Synchronization.
first edge
RUNIN
1
0
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
0
1
0
1
4 bits detected
first edge
RUNIN
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
4 bits detected
Figure 20
RUNIN Generation Principle
Data Sheet
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TDA5235
Functional Description
Number of Required RUNIN Bits
The number of RUNIN bits specified in x_CDRRI register should always be 3.0. This
setting defines the duration of the internal synchronization. Because of internal
processing delays, the pattern length that must be reserved for RUNIN is longer.
The ideal RUNIN pattern is a series of either Manchester 1’s or Manchester 0’s. This
pattern includes the highest number of edges that can be used for synchronization. In
this case, the number of physically sent RUNIN bits is 4.
For any other RUNIN pattern, 5.5 bits should be reserved for RUNIN.
TVWIN (Timing Violation WINdow length)
The PLL unlocks if the reference signal is lost for more than the time defined in the
x_TVWIN register. During the TSI Gap (see TSI Gap Mode in Chapter 2.4.8.6 Frame
Synchronization), the PLL and the TVWIN are frozen.
TVWIN time is the time during which the Digital Baseband Receiver should stay locked
without any incoming signal edges detected. The time resolution is T/16.
Calculation of TVWIN can be seen at the end of subsection TSI Gap Mode in
Chapter 2.4.8.6 Frame Synchronization.
Data Sheet
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TDA5235
Functional Description
Duty Cycle Variation
Ideally, the input signal to the Clock and Data Recovery (CDR) would have a chip width
of 8 samples and a bit width of 16 samples and the CDR would not lock onto any input
that violates this. However, due to variations in the duty cycle this stringent assumption
for the pulse widths will in general not be true. Therefore it is necessary to loosen this
requirement by using tolerance windows.
TOLCHIPH
TOLBITH
TOLCHIPL
TOLBITL
1
t
lim_chip_low = 8 - TOLCHIPL
lim_bit_low = 16 - TOLBITL
lim_chip_high = 8 + TOLCHIPH
Figure 21
lim_bit_high = 16 + TOLBITH
Definition of Tolerance Windows for the CDR
There exist now two registers - x_CDRTOLC for the chip width tolerance and
x_CDRTOLB for the bit width tolerance - that can be used to tighten or loosen the
windows around the ideal pulse widths. As it can easily be seen from Figure 21, tighter
windows will result in more stringent requirements for the input data to have a 50% duty
cycle and bigger windows will allow the duty cycle to vary more. Figure 21 also depicts
the meaning of the bits in the registers x_CDRTOLC and x_CDRTOLB.
Data Sheet
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Functional Description
Data Rate Acceptance Limitation
The Clock and Data Recovery is able to accept data rate errors of more than +/-15% with
a certain loss of performance. There exist Multi-Configuration applications where the
data rate of both configurations are within this range. So the adjacent data rates of these
configurations are disturbing each other. The limitation of the data rate acceptance can
be activated in this case.
clock recovery
slicer
CLOCK RECOVERY
symbol synchronization
Data Rate
Acceptance
Limitation
&
preset value correlator
cdr_lock
Clock Recovery PLL
Figure 22
cdr_clock
Data Rate Acceptance Limitation
The clock and data recovery (CDR) regenerates the clock based on the input data
delivered from the clock recovery (CR) slicer. Symbol synchronization (cdr_lock) is
achieved when a specified number of chips (can be set via register x_CDRRI.RUNLEN)
has a valid pulse width. In parallel the preset value correlator estimates a preset value
for the clock recovery PLL so that a shorter settling time is achieved. This preset value
is also proportional to the data rate and is therefore used in the data rate acceptance
limitation block. If the preset value is outside a certain range (positive and negative
threshold configurable via registers CDRDRTHRP and CDRDRTHRN), the CDR does
not go into lock and no symbol synchronization is generated.
For each configuration there exists one bit (register x_CDRRI.DRLIMEN) to switch the
data rate acceptance limitation functionality on or off. Data rate acceptance limitation is
disabled by default. All configurations share the same threshold registers, the default
Data Sheet
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Functional Description
thresholds are set so that almost all packets with a data rate error of +/-10% and larger
are rejected.
The following statements summarize some important aspects that need to be kept in
mind when using the described functionality:
•
•
•
•
•
The output of the estimator must be described on statistical terms - this means that
it can not be guaranteed that all packets with a certain data rate outside the allowed
range will be rejected
The quality of the estimated data rate value is mainly influenced by the setting of the
signal and noise detectors
Reducing the RUNIN length in register x_CDRRI reduces the quality of the data rate
estimation, resulting in a degradation of the performance of the data rate acceptance
limitation block
The same threshold can be used for FSK and ASK
If the thresholds are too small it may happen that also packets with a valid data rate
are rejected
2.4.8.4
Data Slicer and Line Decoding
The output signal of the matched filter within the internal data processing path is in the
range of +x to -x (x is the maximum value of the internal bit width). If Code Violations
within a Manchester encoded bitstream have to be detected, the data slicer has to
recover the underlying chipstream instead of the bitstream. In this case zero values at
the matched filter output lead to an additional slicing threshold and an implicit sensitivity
loss. To provide the full reachable sensitivity for applications which do not need the
symbols S (space) and M (mark), the data slicer has two different operating modes:
•
•
Chip mode (Code Violations are allowed)
Bit mode (without Code Violations)
The chip mode introduces an implicit sensitivity loss compared to the bit mode, because
a zero-crossing in the 2-chip matched filter signal must be detectable. This is only
possible when an additional slicing level is introduced in the data slicer.
The data slicer internally maps a positive value to a 1 and a negative value to a -1.
Everything inside the zero thresholds (zero-tube) becomes a 0. After that, the decoding
to the chip-level representation is done by mapping the -1 to a "0" chip and the 1 to a "1"
chip. A zero out of the data slicer is decoded to chip-level by referencing to the previous
chip value.
Data Sheet
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Functional Description
In bit mode the data slicer has only one threshold (zero) to distinguish between the two
levels of the matched filter output. The data slicer internally maps a positive value to a 1
and a negative value to a -1. After that, the selected line decoding is applied.
Summary of data slicer modes in the TDA5235:
Data Slicer Chip mode:
•
•
•
Code violations detectable (TSI, or EOM)
Performance loss compared to bit mode
Activation via setting register x_SLCCFG to a value of
+ 0x90 (Chip Mode EOM-CV: For patterns with code violations in data packet and
optimized for activated EOM code violation criterion (and optional EOM data
length criterion))
+ 0x94 (Chip Mode EOM-Data length: For patterns with code violations in data
packet and optimized for activated EOM data length criterion only)
+ 0x95 (Chip Mode Transparent: When Framer is not used, but CH_DATA /
CH_STR are used for data processing)
Data Slicer Bit mode:
•
•
•
•
No code violations detectable
Full performance
In case of Bi-phase mark and Bi-phase space an additional bit must be sent to ensure
correct decoding of the last bit
Activation via setting register x_SLCCFG to a value of 0x75
In Data Slicer Bit mode an even number of TSI chips needs to be used.
When Data Slicer Bit mode is selected, then the the last chip of RUNIN must be different
from first chip of TSI (e.g. Runin-bit sequence 000000 and TSI bit sequence 0xx...xxx is
OK). Otherwise the TSI will not be detected correctly.
On using Data Slicer Bit Mode, the Wake-up criteria Equal Bits Detection and Pattern
Detection cannot be applied.
A line decoder decodes the incoming data chips according to the encoding scheme (see
Chapter 2.4.8.2).
Data Sheet
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Functional Description
2.4.8.5
Wake-Up Generator
A wake-up generation unit is used only in the Self Polling Mode for the detection of a
predefined wake-up criterion in the received pattern.
There are two groups of configurable wake-up criteria:
•
•
Wake-up on Level criteria
Wake-up on Data criteria
The search for the wake-up data criterion is started if data chip synchronization has
occurred within the predefined number of symbols, otherwise the wake-up search is
aborted. Several different wake-up patterns, like random bit, equal bit, bit pattern or bit
synchronization, are programmable.
Additional level criterion fulfilment for RSSI or Signal Recognition can lead to a fast
wake-up and to a change to Run Mode Self Polling. Whenever one of these Wake-up
Level criteria is enabled and exceeds a programmable threshold, a wake-up has been
detected.
The Wake-up Level criterion can be used very effectively in combination with the
Ultrafast Fall Back to SLEEP Mode (see Chapter 2.6.2.3) for further decreasing the
needed active time of the autonomous receive mode. A configurable observation time
for Wake-up on Level can be set in the x_WULOT register. The Wake-up on Level
criterion can be handled very quickly for FSK modulation, while in case of ASK the nature
of this modulation type has to be kept in mind.
Data Sheet
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Functional Description
RSSI Level
x_WURSSIBH1
Exceeding Threshold
Compare
x_WURSSIBL1
x_WURSSITH1
WU Level
Criterion
Data
x_NDCONFIG
x_SIGDET1
Wake-up on Signal
Recognition
Exceeding Threshold(s)
x_NDTHRES
x_SIGDETLO
Sync Search Time Elapsed
Sync
WU
x_WUBCNT
WUW Chip Counter
Elapsed
Wake-up Window
Chip Counter
Code Violation Detector
Bit Change Detector
Wake-up
Generation
FSM
No WU
Code Violation Detected
Bit Change Detected
3
Chip Data Clock
16-chips Shift Register
Chip Data
0
2
15
16
x_WUPAT0
Pattern Detector
Pattern Detected
x_WUPAT1
RSSI
WU on Level Criteria
Signal
Recognition
Sync
Selection
Random Bits
WU on Data Criteria
Equal Bits
Pattern
x_WUC
Figure 23
Wake-Up Generation Unit
Wake-Up on RSSI
The threshold x_WURSSITH1 is used to decide whether the actual signal is a wanted
signal or just noise. Any kind of interfering RSSI level can be blocked by using an RSSI
blocking window. This window is determined by the thresholds x_WURSSIBL1 and
Data Sheet
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Functional Description
x_WURSSIBH1. These two thresholds can be evaluated during normal operation of the
application to handle the actual interferer environment.
RSSI magnitude
The blocking window can be disabled by setting x_WURSSIBH1 to the minimum value
and x_WURSSIBL1 to the maximum value.
wanted signal
x_WURSSIBH1
interferer
x_WURSSIBL1
wanted signal
x_WURSSITH1
noise floor
Figure 24
RSSI Blocking Thresholds
Threshold evaluation procedure
A statistical noise floor evaluation using read register RSSIPMF (RMS operation) leads
to the threshold x_WURSSITH1. The interferer thresholds x_WURSSIBL1 and
x_WURSSIBH1 are disabled when they are set to their default values.
For evaluation of the interferer thresholds, either use register RSSIPMF for RMS
operation or during SPM and WU (Wake-Up) on RSSI use register RSSIPWU to
statistically evaluate the interferer band. Finally the thresholds x_WURSSIBL1 and
x_WURSSIBH1 can be set.
Wake-Up on RSSI can also be applied as additional criterion when already using a
Wake-Up on Data criterion in Constant On-Off (COO) Mode.
Further details can be seen in Figure 10, Chapter 2.4.7 RSSI Peak Detector,
Chapter 2.6.2.2 Constant On-Off Time (COO) and Chapter 2.6.2.3 Fast Fall Back to
SLEEP (FFB).
NOTE: If e.g. an interferer ends/starts too close after/to the beginning/end of the
observation time, then a decision level error can arise. This is due to the filter dynamics
(settling time). Further, for interferer thresholds evaluation in SPM this changes interferer
statistics. Several interferer measurements are recommended to suppress this, what
makes sense anyway for a better distribution.
Data Sheet
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Functional Description
Wake-Up on Signal Recognition
Instead of the previously mentioned RSSI criterion, the Signal Recognition criterion (see
Chapter 2.4.8.1) can be applied for Wake-Up search. So the x_SIGDET1, x_SIGDETLO
and x_NDTHRES threshold registers can be used.
The observation time has to be specified in the register x_WULOT. This observation time
has to contain the delay in the signal path (12.5 µs + 2.25*Tbit) and the duration for the
comparison of the Signal Recognition criterion.
The number of consecutive valid Signal Recognition samples/levels is compared vs. a
threshold defined in x_WURSSIBH1 register. Please note that x_WURSSIBH1 register
is used for both Wake-Up on RSSI and Wake-Up on Signal Recognition function. This
threshold has an influence on the false alarm rate. So x_WURSSIBH1 defines the
minimum needed consecutive T/16 samples of the Signal Recognition output to be at
high level for a positive Wake-Up event generation.
Wake-Up on Data Criterion
All SFRs configuring the Wake-up Generation Unit support the Multi-Configuration
capability. The search for a wake-up data criterion is started if symbol synchronization is
given within a certain duration (see Chapter 2.4.8.8 RUNIN, Synchronization Search
Time and Inter-Frame Time); otherwise the wake-up search is aborted. During the
observation period, the wake-up data search is aborted immediately if symbol
synchronization is lost. If this is not the case, the wake-up search will last for the number
of chips/bits defined in the register x_WUBCNT.
The Wake-up Window (WUW) Chip/Bit Counter counts the number of received chips/bits
and compares this number vs. the number of chips/bits defined in the register
x_WUBCNT.
The Code Violation Detector checks the incoming chip data stream for being Bi-Phase
coded. A Code Violation is given if three consecutive chips are ’One’ or ’Zero’.
The Bit Change Detector checks the incoming Bi-phase coded bit data stream for
changes from 'Zero' to 'One' or 'One' to 'Zero'.
The Pattern Detector searches for a pattern with 16 chips/bits length within the Wake-up
Window. The pattern is configurable via the registers x_WUPAT0 and x_WUPAT1.
On using Data Slicer Bit Mode, the Wake-up criteria Equal Bits Detection and Pattern
Detection cannot be applied. Further details can be seen at the end of Chapter 2.4.8.4.
The selection of 1 out of 4 wake-up data criteria is done via the x_WUC register.
Data Sheet
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Functional Description
Details on the four wake-up data criteria
Pattern Detection
The incoming signal must match a dedicated pattern of up to 8 bits or 16 chips in WakeUp Pattern Chip Mode. When the WUW chip counter elapses, the search is stopped. The
higher the setting of WUBCNT the longer it is possible to search for the wake-up pattern.
The minimum for the WUBCNT is 0x11!
The pattern detection is stopped either when WUW elapses, or when symbol
synchronization is lost.
The Wake-Up pattern can be extended from 16 chips to 16 bits on activation of
WUPMSEL bit (Wake-Up Pattern Bit Mode). In this Bit Mode no Code Violations (CV)
are allowed and thus Pattern Detection is aborted, when a CV is detected.
Equal Bits Detection
Wake-up condition is fulfilled if all received bits inside of WUW are either 0 or 1.
WUBCNT holds the number of required equal bits. The higher the setting of WUBCNT
the lower the number of wrong wake-ups.
Equal bits detection is stopped if a bit change or a CV has been detected, or symbol
synchronization is lost.
Random Bits Detection
Wake-up condition is fulfilled if there is no code violation inside of WUW. WUBCNT holds
the number of required Bi-phase coded bits. The higher the setting of WUBCNT, the
lower the number of wrong wake-ups.
Random bits detection is stopped if a code violation has been detected, or symbol
synchronization is lost.
Valid Data Rate Detection
Wake-up condition is fulfilled if symbol synchronization is possible inside of Sync Search
Time out (see Chapter 2.4.8.8 RUNIN, Synchronization Search Time and InterFrame Time). WUBCNT is not used.
This is the weakest wake-up data criterion, and should be avoided.
Data Sheet
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Functional Description
SSync Search Time Elapsed = 1
Reset
Init Wakeup Unit
SSync =0
Idle
WU=0
No WU=0
SSync=1
Wakeup Criteria=Pattern Detection
SSync =0
SSync=1
Wakeup Criteria=Random Bits Detection
SSync=1
Wakeup Criteria=Equal Bits Detection
WUW Chip Counter <
WUBCNT
WUW Chip Counter <
WUBCNT
Pattern Detection
Random Bits Detection
WU=0
No WU=0
WU=0
No WU=0
WUW Chip
Counter<WUBCNT
SSync =1
Wakeup Criteria=Valid Data Rate
Detection
Equal Bits
Detection
SSync= 0
WU=0
No WU=0
Bit Change Detected=1
CV= 1
SSync=0
CV=1
WUW Chip Counter elapsed
Pattern Match=1
(WUW Chip Counter =
WUBCNT)
WUW Chip Counter elapsed
(WUW Chip Counter = WUBCNT)
WUW Chip Counter elapsed
(WUW Chip Counter = WUBCNT)
Wake-Up
WU=1
No WU=0
No Wake-Up
WU=0
No WU=1
Figure 25
2.4.8.6
Wake-Up Data Criteria Search
Frame Synchronization
The Frame Synchronization Unit (Framer) synchronizes to a specific pattern to identify
the exact start of a payload data frame within the data stream. This pattern is called
Telegram Start Identifier (TSI).
There are different TSI modes selectable via the configuration:
•
•
•
•
16-Bit TSI Mode, supporting a TSI length of up to 16 bits or 32 chips
8-Bit Parallel TSI Mode, supporting two independent TSI pattern of up to 8 bits length
each. Different payload length is possible for these two TSI pattern.
8-Bit Extended TSI Mode, identical to 8-Bit Parallel TSI Mode, but identifies which
pattern matches by adding a single bit at the beginning of the data frame
8-Bit TSI Gap Mode, supporting two independent TSI pattern separated by a
discontinuity
All SFRs configuring the Frame Synchronization Unit support the Multi-Configuration
capability (Config A and B). The Framer starts working in Run Mode Slave after Symbol
Sync found and in Self Polling Mode after wake-up found and searches for a frame until
TSI is found or synchronization is lost. The input of the Framer is a sequence of Bi-phase
Data Sheet
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TDA5235
Functional Description
encoded data (chips). Basically the Framer consists of two identical correlators of 16
chips in length. It allows a Telegram Start Identifier (TSI) to be composed of Bi-phase
encoded “Zeros” and “Ones”. The active length of each of the 16 chips correlators is
defined independently in the x_TSILENA and x_TSILENB registers. The pattern to
match is defined as a sequence of chips in the x_TSIPTA0, x_TSIPTA1, x_TSIPTB0 and
x_TSIPTB1 registers.
Note that the RUNIN length shown in the figures below is the maximum needed RUNIN
with the length of 8 chips. Further details on the needed RUNIN time of the receiver can
be seen in Chapter 2.4.8.3 Clock and Data Recovery.
Bi-phase- /
Manchester Decoder
Data
Data
Data Clock
Data Clock
EOMCV
Code-Violation
Detector
CV
EOMSYLO
EOM-Detector
EOMDATLEN
EOM
x_EOMDLEN
x_EOMDLENP
Sync
FSync
TSI wild card
from CR
x_TSIMODE(6:3)
Chip-Data Clock
Delay-Line 16-bit
from Chip-Data
DataSlicer
MRB
LRB
Correlator A
Controller
Correlator A 16-bit
MSB LSB
TSI Data -Pattern
CorrAMatch
Frame
Synchron ization
Controller
MSB
x_TSIPTA1
TSI Data-Pattern
x_TSIPTA0
LSB
x_TSILENA
Select
x_TSIMODE
x_TSIGAP
Delay-Line 16-bit
MUX
MRB
LRB
Correlator B
Controller
Correlator B 16-bit
x_TSILENB
MSB LSB
TSI Data -Pattern
MSB
x_TSIPTB1
TSI Data-Pattern
x_TSIPTB0
LSB
Figure 26
Frame Synchronization Unit
Data Sheet
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Functional Description
Please note that for Data Slicer Bit Mode a special constellation of RUNIN bits and TSI
bits has to be ensured. Further details can be seen at the end of Chapter 2.4.8.4.
The two independent correlators can be configured in the x_TSIMODE register to work
in one of the following four TSI modes:
16-Bit Mode: As a single correlator of up to 32 chips
The length of the x_TSILENA register must be set to 16d whenever x_TSILENB is higher
than 0.
x_TSILENA = 16d, x_TSILENB = 6d
RunIn
Incoming Pattern
0 0 0 0 0 1 0 1 0 0 0 1 1 1 1 1 0 1 0 0 1 0
Manchester Coded
01010101011001100101011010101010011001011001
x_TSIPTB
x_TSIPTA
5 4 3 2 1 0 151413121110 9 8 7 6 5 4 3 2 1 0
TSI Pattern Match
FSYNC
Data into FIFO
Figure 27
0110011001010110101010
1 0 1 0 0 1 0
16-Bit TSI Mode
8-Bit Parallel Mode: As two correlators of up to 16 chips length each
working simultaneously in parallel
In the following example, TSI Pattern B matches first and generates an FSYNC. The
lengths of both TSI Patterns are now independent from each other. The payload length
for these two TSI Pattern may be different.
x_TSILENA = 16d, x_TSILENB = 6d
RunIn
Incoming Pattern
Manchester Coded
0 0 0 0 0 1 0 1 0 1 0 0 1 0
0101010101100110011001011001
x_TSIPTB
5 4 3 2 1 0
TSI Pattern B Match
011001
FSYNC
Data into FIFO
Figure 28
Data Sheet
1 0 1 0 0 1 0
8-Bit Parallel TSI Mode
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Functional Description
8-Bit Extended Mode: As two correlators of up to 16 chips length each
working simultaneously in parallel, with matching information insertion
This bit is inserted at the beginning of the payload. “0” is inserted, when correlator A has
matched and “1” when correlator B has matched. The payload length for these two TSI
Pattern may be different.
x_TSILENA = 16d, x_TSILENB = 6d
RunIn
Incoming Pattern
Manchester Coded
0 0 0 0 0 1 0 1 0 1 0 0 1 0
0101010101100110011001011001
x_TSIPTB
5 4 3 2 1 0
TSI Pattern B Match
011001
FSYNC
1 1 0 1 0 0 1 0
Data into FIFO
Matching Information inserted
Figure 29
8-Bit Extended TSI Mode
8-Bit Gap Mode: As two sequentially working correlators of up to 16 chips
length each
This mode is only used in combination with the TSI Gap Mode shown below!
This mode is used to define a gap between the two patterns which is preset in the
x_TSIGAP register. To identify exactly the beginning of the gap it would be helpful on
occasion to place the first CV of the gap into the TSI Pattern A. In this case, the gap
length needed for the x_TSIGAP register must be shortened and the x_TVWIN length
must be extended.
x_TSILENA = 8d, x_TSILENB = 12d
TSIGRSYN = 1
RunIn
Gap
0 0 0 0 0 1 0 S
Incoming Pattern
Manchester Coded
TSI Pattern Match
RunIn
0 0 0 0 1 0 0 0 1 1 1 1 1 0 1
01010101011001000000010101011001010110101010100110
x_TSIPTA
7 6 5 4 3 2 1 0
x_TSIPTB
1110 9 8 7 6 5 4 3 2 1 0
01100100
100101011010
FSYNC
1 1 1 0 1
Data into FIFO
Figure 30
Data Sheet
8-Bit Gap TSI Mode
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Functional Description
Selection of a TSI Pattern
TSI patterns must be different to the wake-up bit stream and the RUNIN to clearly mark
the start of the following payload data frame. It should be considered that the
synchronization has a tolerance of about one bit. In addition, synchronization is related
to data chips, and may occur in the middle of a data bit. This all must be tolerated by the
data framer. Further details can be seen in Chapter 2.4.8.3 Clock and Data Recovery.
Ideal TSI patterns have a unique bit combination at their end, which may also contain a
number of code violations (CVs), when possible (see Chapter 2.4.8.4 Data Slicer and
Line Decoding).
Some examples of TSI patterns:
0000000000000001
0000000000000011
0000000000000010
1111111111111110
When CVs are used:
0000000000000M1
11111111111111M0
Note: CVs in a TSI are practical for better differentiation to the real data, especially if
repetition of data frames is used for wake-up.
End of Message (EOM) Detection
An End Of Message (EOM) detection feature is provided by the EOM detector. Three
criteria can be selected to indicate EOM.
The first is based on the number of received bits since frame synchronization. The
number of expected bits is preset in the x_EOMDLEN register. Sending fewer bits as
defined in the register will result in no EOM. The EOM counter will be reset after new
frame synchronization.
In 8-Bit Parallel TSI Mode and 8-Bit Extended TSI Mode, the payload length for the two
independent TSI pattern may be different. Therefore the payload length for TSI B pattern
can be preset in the x_EOMDLENP register, while payload length for TSI A pattern can
be preset in the x_EOMDLEN register.
The second criterion is the detection of a Code Violation. This EOM criterion is not
applicable for Data Slicer Bit mode.
Data Sheet
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Functional Description
The third criterion is the loss of symbol synchronization. Depending on the x_TVWIN
register, the Sync signal persists for a certain amount of time after the end of the pattern
has been reached. Therefore, more bits could be written into the FIFO than sent. The
three EOM criteria can be combined with each other. If one of the selected EOM criteria
is fulfilled, an EOM signal will be generated.
TSI Gap Mode
The TSI Gap Mode is only used if TSI patterns contain a gap that is not synchronous to
the data rate, e.g. if a gap is 7.7 data bits, or if a gap is longer than 10 data bits. In all
other cases, gaps should be included in the TSI pattern as code violations.
Because of its complexity in configuration, TSI Gap Mode should be only used in
applications as noted above!
For these special protocols, it is possible to lock the actual data frequency during a long
Code Violation period inside a TSI (x_TSIGAP must have a minimum of 8 chips).
TSIGAP is used to lock the PLL after TSI A was found. After the lock period, two different
resynchronization modes are available (TSI Gap ReSYNchronization, TSIGRSYN):
•
Frequency readjustment (PLL starts from the beginning), TSIGRSYN = 1. In this
mode the T/2 gap resolution can be set in the 5 MSB x_TSIGAP register bits. The
value in GAPVAL (3 LSB in x_TSIGAP register) is not used. This is the preferred
mode in TSI Gap Mode.
clock recovery reset
start point
valid data
RUNIN
TSI A
< 1bit
all space or all mark
TSI GAP
PLL sync
valid data
GAPSync
TSI B
< 1bit
internal PLL sync
Figure 31
•
Clock Recovery Gap Resynchronization Mode TSIGRSYN = 1
Phase readjustment only, TSIGRSYN = 0. In this mode, the value in GAPVAL is used
to correct the phase after the gap phase. Overall gap time can be defined in T/16
Data Sheet
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Functional Description
steps. The 5 MSB bits (TSIGAP) define the real gap time and the 3 LSB bits
(GAPVAL) the DCO (digital controlled oscillator) phase correction value.
clock recovery phase
readjustment start point
valid data
RUNIN
TSI A
< 1bit
Figure 32
all space or all mark
TSI GAP
valid data
GAPSync
TSI B
PLL sync
Clock Recovery Gap Resynchronization Mode TSIGRSYN = 0
When the time TSI GAP in the start sequence of the transmitted telegram has elapsed,
the receiver needs a certain time (GAPSync = 5...6 chips) to readjust the PLL settings.
Behavior of the system at the starting position of the TSI B:
The starting position (TSI B start) for the TSI B comparison is independent from the
RUNIN settings (x_CDRRI register) and the resynchronization mode (x_TSIMODE
register):
TSIBstart [ chips ] = TSIGAP [ chips ] + 6…8
The incoming chips at TSI B start and the following incoming chips are compared with
the contents of the register TSI B. Please notice that the receiver’s PLL runs at the data
rate determined before the gap. Therefore, the receiver calculates the gap based on this
data rate.
Behavior of the system at the ending position of TSI B:
The system checks for the TSI B to match within a limited time. If there is no match within
this time, then the receiver starts again to search for the TSI A pattern at the following
incoming chips:
TSIBstop [ chips ] = TSIGAP [ chips ] + TSILENB [ chips ] + 11
For a successful TSI B pattern match, the defined TSI B pattern must be between “Start
of TSI B” and “Stop of TSI B”. In the example below, the earliest possible start position
would be the 18th chip and the latest possible start position would be the 22nd chip.
Data Sheet
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Functional Description
Please note that after a gap, the internal TSI comparison register is cleared (all chips set
to ’0’). In this case, a TSI B criteria of “0000” would always match at the beginning. To
avoid such an unwanted matching, set the highest TSI B match chip to ’1’.
RunIn
TSIA
TSIGAP=10 chips GapSync
TSIB
Incoming Pattern[bits] ... 0 0 1 0 S _ _ _ _ _ 0 0 0 0 1 0 0 0 1 1 1 1 1
12345678901 23456789012345 67890123456
TSIBstart
Start of TSIB
comparison
Figure 33
Stop of TSIB
comparison
TSIGap TSIB Timing
The TVWIN (Timing Violation WINdow) and TSIGAP dependency is shown in Figure 34.
TVWIN
TVWIN
TVWIN
CV
int.
delay
TSIA
TVWIN without GAP
Figure 34
GAP
RUNIN/
TSIGRSYN = 1
TVWIN with GAP
TVWIN and TSIGAP dependency example
TVWIN calculation for pattern without Gap time:
TVWIN = round ( ( 8 + 16 ⋅ CV + 8 ) ⋅ 1.25 )
The entire TVWIN time is made up of the CV1) number itself, the half bit before CV and
the half bit after the CV. To reach all frequency and duty cycle errors, 25% of the overall
sum must be added.
TVWIN calculation with Gap time:
TVWIN = round ( max { ( ( 8 + 16 ⋅ CV + 8 ) ⋅ 1.25 ), ( 8 + 16 ⋅ TSIA CV + 16 ⋅ 1 + 8 ) ⋅ 1.25 } )
1) CV...number of bits containing manchester code violations
Data Sheet
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V1.0, 2010-02-19
TDA5235
Functional Description
2.4.8.7
Message ID Scanning
This unit is used to define an ID or special combination of bits in the payload data stream,
which identifies the pattern. All SFRs configuring the Message ID Scanning Unit feature
the Multi-Configuration capability. Furthermore, it is available in the Slave and Self
Polling Mode. The MID Unit can be mainly configured in two modes: 4-Byte and 2-Byte
organized Message ID. For each configuration there are 20 8-bit registers designed for
ID storage. SFRs are used to configure the MID Unit: Enabling of the MID scanning,
setting of the ID storage organization, the starting position of the comparison and
number of bytes to scan.
When the Message ID Scanning Unit is activated, the incoming data stream is compared
bit-wise serially with all stored IDs. If the Scan End Position is reached and all received
data have matched the observed part of at least one MID the Message ID Scanning Unit
indicates a successful MID scanning to the Master FSM, which generates an MID
interrupt.
Please note that the default register value of the MID registers is set to 0x00. All MID
registers must be set to a pattern value to avoid matching to default value 0x00.
If the MID Unit finishes ID matching without success, the data receiving is stopped and
the FSM waits again for a Frame Start criterion. The received bits are still stored in the
FIFO.
Data Sheet
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V1.0, 2010-02-19
TDA5235
Functional Description
4-Byte Organized Message ID:
In this mode four bytes are merged to define an ID-Pattern. This does not mean that the
ID must be exact four bytes long. The number of bytes used is defined in register
x_MIDC1. Up to 5 ID Patterns are available.
x_MID0
8
MID0:MID3
32
MID4:MID7
32
MID8:MID11
32
MID12:MID15
32
MID16:MID19
32
8
x_MID1
x_MID9
x_MID10
x_MID11
x_MID12
x_MID13
x_MID14
x_MID15
x_MID16
x_MID17
x_MID18
x_MID19
Scanner
Line
Selector
8
8
8
Combiner
8
8
8
8
Scan Start Position
Reached
8
8
Bit Counter
8
MID match
x_MID8
8
Enable Scanner
x_MID7
8
Bit31
x_MID6
8
Bit0
x_MID5
8
MID found
ControlFSM
Scan End Position
Reached
Number
of Startbit
x_MID4
8
Line Number
x_MID3
8
Number
to Scan
x_MID2
MID Scanning finished
Interface to
Master FSM
8
8
Organization
Init MID Scanner
Figure 35
4-Byte Message ID Scanning
Data Sheet
64
Data Clock
Data
x_MIDC0
x_MIDC1
Enable MID Scanning
from
Digital-Receiver
V1.0, 2010-02-19
TDA5235
Functional Description
2-Byte Organized Message ID:
In this mode two bytes are merged to define an ID Pattern. Up to 10 patterns are
possible.
x_MID4
x_MID5
MID2:MID3
16
MID4:MID5
16
MID6:MID7
16
MID8:MID9
16
MID10:MID11
16
MID12:MID13
16
MID14:MID15
16
MID16:MID17
16
MID18:MID19
16
8
8
8
8
8
x_MID6
x_MID9
x_MID10
x_MID11
8
8
8
Combiner
Enable Scanner
x_MID8
8
Bit0
x_MID7
Scanner
x_MID3
16
8
8
x_MID13
x_MID14
Line Number
x_MID12
8
8
Scan Start Position
Reached
8
x_MID15
x_MID18
x_MID19
Bit Counter
8
MID found
ControlFSM
Scan End Position
Reached
Number
of Startbit
x_MID17
8
Number
to Scan
x_MID16
MID match
x_MID2
MID0:MID1
8
Bit15
x_MID1
8
Line
Selector
x_MID0
MID Scanning finished
Interface to
Master FSM
8
8
Organization
Init MID Scanner
Figure 36
Data Clock
Data
x_MIDC0
x_MIDC1
Enable MID Scanning
from
Digital-Receiver
2-Byte Message ID Scanning
ID Position Configuration:
It is possible to choose which part of the incoming data stream is compared against the
stored MIDs. The register x_MIDC0 contains the Scan Start Position. If the Bit Counter
detects the Scan Start Position, the Control FSM enables the Scanner. The register
x_MIDC1 contains the number of bytes to scan. During the observation period, the
Data Sheet
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V1.0, 2010-02-19
TDA5235
Functional Description
Message ID Scanning is aborted immediately by the Master FSM, if symbol
synchronization is lost or an EOM (End Of Message) is detected.
Example:
Start Selection: 00010001b
First Data Bit
Number to scan: 00b, 01b, 10b, 11b
FSYNC
Bit
0
1
2
Number To Scan =00 b
Number To Scan =01 b
Number To Scan =10 b
17 18
23 24 25 26
Byte0
Byte0
Byte0
Byte0
31 32 33 34
Byte1
Byte1
Byte1
39 40 41 42
Byte2
Byte2
47 48 49
Byte3
Number To Scan =11 b
Start MID Scan
Figure 37
MID Scanning
The starting position in this case is Bit 17. Depending on the number to scan, the
corresponding number of bytes is compared with the stored MIDs.
2.4.8.8
RUNIN, Synchronization Search Time and Inter-Frame Time
The functionality of the Digital Baseband Receiver is divided into four consecutive data
processing stages; the data filter, clock and data recovery, data slicer and frame
synchronization unit. The architecture of the Digital Baseband Receiver is optimized for
processing bi-phase coded data streams.
The basic structure of a payload frame is shown in Figure 38. The protocol starts with a
so called RUNIN. The RUNIN with the minimum length of four bi-phase coded symbols
is used for internal filter settling and frequency adjustment. The TSI (Telegram Start
Identifier), which is used as framing word, follows the RUNIN sequence. The payload
contains the effective data. The length of the valid payload data is defined as the length
itself or additional criteria (e.g. loss of Sync).
Please note that almost all transmitted protocols send a wake-up sequence before the
payload frame (see also Figure 72). This wake-up sequence allows a very fast decision,
whether there is a suitable message available or not. Further details on this topic can be
gained from Chapter 2.6.1.5 and Chapter 2.4.8.5.
Data Sheet
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V1.0, 2010-02-19
TDA5235
Functional Description
RUNIN
Figure 38
TSI
PAYLOAD
Structure of Payload Frame
RUNIN
CDR input
TSI
RUNIN
RUNIN
EOM
input data
EOM
Two important system parameters are described in this section: the Synchronization
Search Time Out (SYSRCTO) and the Inter-Frame Time. The processing sequence of
a payload frame is shown in Figure 39.
TSI
RUNIN
PLL re-synchronization
data available
TSI
EOM
chip data available
RUNIN
T4
T1
T2
T2
T2
T3
symbol sync found
Figure 39
Data Latency
The overall system latency time is calculated in two steps: T1 is the delay between ADC
input (ASK) / limiter output (FSK) and the CDR input, and T2 is the time between Symbol
Sync Found and the Framer output (decoded data available).
T4 is the time between Symbol Sync Found and Chip Data output (RX mode TMCDS).
T4 = 1 T. T is the nominal duration of one data bit.
T1 latency time include: (T1 = 12.5µs + 2 T)
• digital frontend processing delay
• matched filter computation time
• signal detector delay
T2 latency time include: (T2 = 1.5 T + 0.5 T1) )
• Data Slicer computation time
• Framer computation time.
1) The 0.5 T have to be added in case of activation of Bi-phase mark / space decoding mode and Data Slicer Bit
mode without Code Violation (see register x_SLCCFG)
Data Sheet
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V1.0, 2010-02-19
TDA5235
Functional Description
The synchronization search time T3 is the time the receiver requires to search for a
pattern in an incoming data stream and needs to be considered in the receivers start-up
phase. The minimum value of the search time out length is the consequence of the
system latency time T1, the RUNIN length and the time of asynchronism between
transmitter and receiver.
This means, that for the minimum length of register value for SYSRCTO, the value 2 bits
plus 12.5 µs plus the RUNIN length, which is set in the x_CDRRI register, plus 2 bits (to
consider worst case RUNIN patterns and TX-RX asynchronism) have to be used. To
reach data rate and duty cycle errors, 10% of the overall sum must be added.
12.5μs
SYSRCT0 = roundup ⎛ ⎛ ⎛ ----------------- + 2 + RUNLEN + 2⎞ ⋅ 16⎞ ⋅ 1.1⎞
⎝ ⎝ ⎝ T bit
⎠
⎠
⎠
A second important system parameter that must be considered, is the minimal InterFrame Time (time between two data frames). This time is equal to the time T2 and has a
length of 1.5 or 2 bits1). The EOM to PLL resynchronization time is negligible in case
INITDRXES is disabled. Otherwise T1 has to be added.2)
Note that the described Inter-Frame Time is based on the input pattern with equal signal
power in the following data frame; in other cases, the Inter-Frame Time can vary from
the calculated value.
T Inter – Frame
⎛ 0.5T 1bit) ⎞ ⎛ T 21 )⎞
= 1.5T bit + ⎜
⎟ +⎜ ⎟
⎝ 0 ⎠ ⎝ 0 ⎠
1) see previous footnote
2) in case INITDRXES is enabled
Data Sheet
68
V1.0, 2010-02-19
TDA5235
Functional Description
2.4.9
Power Supply Circuitry
The chip may be operated within a 5 Volts or a 3.3 Volts environment.
VDD5V
En able
IN
En able
IN
Voltage Regulator
5 → 3.3 V
RX_RUN
OUT
Voltage Regulator
5 → 3.3 V
OUT
VDDA
VDDD
E nable
IN
Analog
Section
RF
Section
Voltage Regulator
3.3 → 1.5 V
Digital-I/O
OUT
GNDA
VDDD1V5
E na ble
GNDRF
P_ON
Power-Up
ResetCircuit
Internal
Reset
Digital-Core
Brownout
Detector
GNDD
Figure 40
Power Supply
For operation within a 5 Volts environment (supply voltage range 1), the chip is supplied
via the VDD5V pin. In this configuration the digital I/O pads are supplied via VDD5V and
a 5 V to 3.3 V voltage regulator supplies the analog/RF section (only active in Run
Modes).
When operating within a 3.3 Volts environment (supply voltage range 2), the VDD5V,
VDDA and VDDD pins must be supplied. The 5 V to 3.3 V voltage regulators are inactive
in this configuration.
The internal digital core is supplied by an additional 3.3 V to 1.5 V regulator.
The regulators for the digital section are controlled by the signal at P_ON (Power On)
pin. A low signal at P_ON disables all regulators and set the IC in Power Down Mode. A
low to high transition at P_ON enables the regulators for the digital section and initiates
a power on reset. The regulator for the analog section is controlled by the Master Control
Unit and is active only when the RF section is active.
To provide data integrity within the digital units, a brownout detector monitors the digital
supply. In case a voltage drop of VDDD below approximately 2.45 V is detected a
RESET will be initiated.
Data Sheet
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V1.0, 2010-02-19
TDA5235
Functional Description
A typical power supply application for a 3.3 Volts and a 5 Volts environment is shown in
the figure below.
*) 22Ω
4.7Ω
TDA5235
4.7Ω
TDA5235
10Ω
VDD5V
VDDA
VDD5V
VDDD
VDDA
100n
100n
VDDD1V5
VDDD
100n
100n
VDDD1V5
100n
100n
GNDA
GNDRF
3.3V
GNDRF
Supply -Application in 3.3V environment
*) 1μ
100n
GNDA
GNDD
5V
100n
GNDD
Supply-Application in 5V environment
*) When operating in a 5V environment, the voltage-drop across the voltage
regulators 5 Æ 3.3V has to be limited , to keep the regulators in a safe
operating range. Resistive or capacitive loads (in excess to the scheme
shown above) on pins VDDA and VDDD are not recommended.
Figure 41
Data Sheet
3.3 Volts and 5 Volts Applications
70
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TDA5235
Functional Description
2.4.9.1
Supply Current
In SLEEP Mode, the Master Control Unit switches the crystal oscillator into Low Power
Mode (all internal load capacitors are disconnected) to minimize power consumption.
This is also valid for Self Polling Mode during Off time (SPM_OFF).
Whenever the chip leaves the SLEEP Mode/SPM_OFF (t1), the crystal oscillator
resumes operation in High Precision Mode and requires tCOSCsettle to settle at the trimmed
frequency. At t2 the analog signal path (RF and IF section) and the RF PLL are activated.
At t3 the chip is ready to receive data. The chip requires tRXstartup when leaving SLEEP
Mode/SPM_OFF until the receiver is ready to receive data.
A transient supply current peak may occur at t1, depending on the selected trimming
capacitance. The average supply current drawn during tRFstartdelay is IRF-FE-startup,BPFcal.
Run Mode*)
SLEEP Mode**)
SPM OFF Time
RX_RUN Signal
Supply
Current
I Run
IRF-FE-startup ,BPFcal
Isleep_low
t1
t2
t3
t
tRFstartdelay
tCOSCsettle
tRXstartup
(Toff )
Ton
(Toff )
*) Run Mode covers the global chip states
: Run Mode Slave/ Receiver active in Self Polling Mode/ Run Mode Self Polling
**) Isleep_low is valid in the chip states: SLEEP / Off time during Self Polling Mode
Figure 42
Supply Current Ramp Up/Down
If the IF buffer amplifier or the clock generation feature (PPx pin active) are enabled, the
respective currents must be added.
Data Sheet
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V1.0, 2010-02-19
TDA5235
Functional Description
2.4.9.2
Chip Reset
Power down and power on are controlled by the P_ON pin. A LOW at this pin keeps the
IC in Power Down Mode. All voltage regulators and the internal biasing are switched off.
A high transition at P_ON pin activates the appropriate voltage regulators and the
internal biasing of the chip. A power up reset is generated at the same time.
Supply Voltage
at VDDD Pin
3V
Reset- / BrownoutThreshold (typ . 2.45 V)
Functional Threshold (typ . 2V)
t
tR eset
Internal Reset
Voltage at PP2 Pin
(NINT Signal)
3V
Reset- / BrownoutThreshold (typ . 2.45 V)
Functional Threshold (typ . 2V)
Level on
NINT signal
is undefined
Supply voltage falls below
Reset- / Brownout-Threshold
Supply voltage
falls below
Functional- Threshold
A ‚LOW’ is generated
at NINT signal
Figure 43
A ‚LOW’ is
generated at
PP2 pin
(NINT signal)
Supply voltage
rises above
Functional-Threshold
t
A ‚HIGH’ is
generated at
PP2 pin
(NINT signal)
µC reads
InterruptStatus-Register
A ‚LOW’ is
generated at
PP2 pin
(NINT signal)
Reset Behavior
A second source that can trigger a reset is a brownout event. Whenever the integrated
brownout detector measures a voltage drop below the brownout threshold on the digital
Data Sheet
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V1.0, 2010-02-19
TDA5235
Functional Description
supply, the integrity of the stored data and configuration can no longer be guaranteed;
thus a reset is generated. While the supply voltage stays between the brownout and the
functional threshold of the chip, the NINT signal is forced to low. When the supply voltage
drops below the functional threshold, the levels of all digital output pins are undefined.
When the supply voltage raises above the brownout threshold, the IC generates a high
pulse at NINT and remains in the reset state for the duration of the reset time. When the
IC leaves the reset state, the Interrupt Status register IS0 is set to 0xFF and the NINT
signal is forced to low. Now, the IC starts operation in the SLEEP Mode, ready to receive
commands via the SPI interface. The NINT signal will go high, when the Interrupt Status
register is read for the first time.
Data Sheet
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V1.0, 2010-02-19
TDA5235
Functional Description
2.5
System Interface
In most applications, the TDA5235 receiver IC is attached to an external microcontroller.
This so-called Application Controller executes a firmware which governs the TDA5235
by reading data from the receiver when data has been received on the RF channel and
by configuring the receiver device. The TDA5235 features an easy to use System
Interface, which is described in this chapter.
Transparent Mode
The TDA5235 supports two levels of integration. In the most elementary fashion, it
provides a rather rudimentary interface by which the incoming RF signal is demodulated
and the corresponding data is made available to the Application Controller. Optionally, a
chip clock is generated by the TDA5235. Since the data signal is always directly the
baseband representation of the RF signal, we call this mode the Transparent Mode. The
usage of the Transparent Mode will be described in Chapter 2.5.1.2.
Packet Oriented Mode
Alternatively, the TDA5235 features the so-called Packet Oriented Mode which supports
the autonomous reception of data telegrams. The Packet Oriented Mode provides a
high-level System Interface which greatly simplifies the integration of the receiver in
data-centric applications. In Packet Oriented Mode, the data interface is based on
chunks of synchronous data which are received in packets. In the easiest way, the
Application Controller only reacts on the synchronous data it receives. The receiver
autonomously handles the line decoding and the deframing of these data, and supports
the timed reception of packets. Data is buffered in a receive FIFO and can be read out
via the data interface. Further, the receiver provides support for the identification of
wake-up signals. Details on the usage of the Packet Oriented Mode of the receiver are
given in Chapter 2.5.1.2.
2.5.1
Interfacing to the TDA5235
The TDA5235 is interfacing with an application by three logical interfaces, see
Figure 44. The RF/IF interface handles the reception of RF signals and is responsible
for the demodulation. Its physical implementation has been described in Chapter 2.4.3
and Chapter 2.4.8, respectively. The other two logical interfaces establish the
connection to the Application Controller. Note that due to the high level of integration of
the receiver, these interfaces impose minor requirements on the Application Controller,
which can be as simple as an 8-bit microcontroller operated at low clock rate. As will be
shown later, the physical implementation of the data interface depends on whether the
receiver is operated in Packet Oriented or in Transparent Mode.
For the sake of clarity, the communication between the TDA5235 and the Application
Controller is split into control flow and data flow. This separation leads to an
independent definition of the data interface and the control interface, respectively.
Data Sheet
74
V1.0, 2010-02-19
TDA5235
Functional Description
SPI /
dig. Out
RX data
SPI &
dig. Out
data interface
configuration
status & alerts
TDA5235
RF interface
Application
Controller
(µC)
control interface
Figure 44
2.5.1.1
Logical and electrical System Interfaces of the TDA5235
Control Interface
The control interface is used in order to configure the TDA5235 after start-up or to reconfigure it during run-time, as well as to properly react on changes in the status of the
receiver in the Application Controller’s firmware. The control interface offers a bidirectional communication link by which
•
•
•
configuration data is sent from the Application Controller to the TDA5235,
the receiver provides status information (e.g. the status of a data reception) as
response to a request it has received from the Application Controller, and
the TDA5235 autonomously alerts the Application Controller that a certain,
configurable event has occurred (e.g. that a packet has been received successfully).
Configuration and status information are sent via the 4-wire SPI interface as described
in Chapter 2.5.5. The configuration data determines the behavior of the receiver, which
comprises
•
•
•
scheduling the inactive power-saving phases as well as the active receive phases,
selecting the properties of the RF/IF interface configuration (e.g. carrier frequency
selection, filter settings),
configuring the properties of the frames (e.g. wake-up patterns, Telegram Start
Identifier (TSI), and optionally specifying the position, format and content of patterns
within packets that stimulate a certain, configurable alerting behavior (Message ID)).
Note that the TDA5235 receiver IC supports reception of up to two configuration sets on
a single channel each in a time-based manner without reconfiguration. Thus, the RF/IF
interface as well as the frame format properties support alternative settings, which can
be activated autonomously by the receiver as part of the scheduling process.
In contrast to the high-level interface used for communicating configuration instructions
and status information, alerts are emitted by the receiver on a digital output pin that may
trigger external interrupts in the Application Controller. Note that the alerting conditions
as well as the polarity of the output pin are configurable, see Chapter 2.5.4.
Data Sheet
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V1.0, 2010-02-19
TDA5235
Functional Description
2.5.1.2
Data Interface
The data interface between the Application Controller and the TDA5235 receiver IC is
used for the transport of the received data, see Figure 44. The physical implementation
as well as the features of the data interface depend on the selected mode of operation.
There are 5 possible receive modes:
•
•
•
•
•
Packet Oriented FIFO Mode (POF)
Packet Oriented Transparent Payload Mode (POTP)
Transparent Mode - Chip Data and Strobe (TMCDS)
Transparent Mode - Matched Filter (TMMF)
Transparent Mode - Raw Data Slicer (TMRDS)
Access points for these receive modes can be seen in Figure 15.
The possible combinations of receive modes and polling mode setup is noted in
Figure 45.
Figure 45
Receive Modes
Packet Oriented FIFO Mode (POF)
In Packet Oriented FIFO Mode, data is transferred via the 4-wire SPI bus. During receive
operation, the incoming RF signal is demodulated in the RF/IF interface, the line
decoding is performed and the data, of which wake-up frames, data frame headers and
optional footers have been stripped off, is stored in the RX FIFO. Then, the received data
can be read from the RX FIFO using the “read FIFO” command described in
Data Sheet
76
V1.0, 2010-02-19
TDA5235
Functional Description
Chapter 2.5.2 and Chapter 2.5.5. The data which is read from the RX FIFO is
accompanied by information which contains the status of the respective receive
operation. Note that the availability of received data packets is communicated via alerts
in the control interface.
RF Interface
data
interface
line decoder
framer
RX FIFO
RX data
bit
synchronizer
Application Controller
TDA5235
scheduler
Figure 46
Data interface for the Packet Oriented FIFO Mode
Packet Oriented Transparent Payload Mode (POTP)
This mode is very similar to POF Mode as data which is going into FIFO is also available
via RXD and RXSTR signals (see Chapter 2.5.3 Digital Output Pins).
line decoder
framer
RX FIFO
data
interface
bit
synchronizer
RX data
Strobe
Application Controller
RF Interface
TDA5235
scheduler
Figure 47
Data interface for the Packet Oriented Transparent Payload Mode
In the TDA5235, there are specific digital output lines (PPx pin) for the Bi-phase decoded
data and an appropriate Strobe signal. During inactivity of the receiver, the line is in
default mode switched to low.
Data Sheet
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TDA5235
Functional Description
In default mode the Strobe signal is active high and has a delay of TBIT/16 relative to the
data bit and a duration of TBIT/2. The polarity of the Strobe signal is programmable, this
can be done via PPCFG2 register.
RXD
Dn
Dn+1
RXSTR
TBIT/16
Figure 48
TBIT/2
Timing of the Packet Oriented Transparent Payload Mode
Transparent Mode - Chip Data and Strobe (TMCDS)
The receiver’s simple plain data interface in this Transparent Mode is shown in
Figure 49. In this mode, the demodulated data signal is made directly available on the
data output pin of the data interface. Concurrently, an estimate of the chip clock is
optionally provided on the respective clock output line. Note that a sensible chip clock
can only be generated if the selected line encoding exhibits a constant chip rate. The
chip clock generation can be significantly improved by using a run-in signal of alternating
one-zero chips (maximum number of transitions within a data stream).
data
interface
RX data
RX chip strobe
bit
synchronizer
Application Controller
RF Interface
TDA5235
scheduler
Figure 49
Data interface for the Transparent Mode - Chip Data and Strobe
In the TDA5235, there is a specific digital output line for the chip clock estimate as well
as for the data output line, which delivers the encoded chip data. During inactivity of the
receiver, the line is in default mode switched to low.
The PPx pin provides the estimated chip clock, if CH_STR is selected. Further details
are given in Chapter 2.5.3.
Data Sheet
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V1.0, 2010-02-19
TDA5235
Functional Description
In default mode the CH_STR signal is active high and has a delay of TCHIP/8 relative to
the data chip and a duration of TCHIP/2. The polarity of the CH_STR signal is
programmable, this can be done via PPCFG2 register.
CH_DATA
Dn
Dn+1
CH_STR
TCHIP /8
Figure 50
TCHIP/2
Timing of the Transparent Mode - Chip Data and Strobe
Transparent Mode - Matched Filter (TMMF)
The received data after the Matched Filter (Two-Chip Matched Filter) with an additional
SIGN function is provided via the DATA_MATCHFIL signal (PPx pin). In this mode
sensitivity measurements with ideal data clock can be performed very simple. For further
details see the block diagram in Figure 15.
Sensitivity in this transparent mode is significantly depending on the implemented clock
and data recovery algorithm of the user software in the application controller.
data
interface
RF Interface
RX data
Application Controller
TDA5235
scheduler
Figure 51
Data interface for the Transparent Modes TMMF / TMRDS
Transparent Mode - Raw Data Slicer (TMRDS)
This mode supports processing of data even without bi-phase encoding (e.g. NRZ
coding) by providing the received data via the One-Chip Matched Filter on the DATA
signal (PPx pin). See more details in the block diagram in Figure 15.
Data Sheet
79
V1.0, 2010-02-19
TDA5235
Functional Description
Sensitivity in this transparent mode is significantly depending on the implemented clock
and data recovery algorithm of the user software in the application controller.
The data interface can be seen from Figure 51.
Self Polling capabilities are possible as well, but only Constant On-Off Mode and Wakeup on RSSI makes sense. Assume one of the TDA5235 configurations (e.g.
Configuration B) is set for external data processing mode. See also example in
Figure 52. The needed On time (latency through TDA5235) is configured in the
corresponding On time registers of the chip. The interrupt for Wake-Up Config B (WUB)
is enabled and suitable RSSI thresholds are set.
If the RSSI signal is in a valid threshold area, the TDA5235 changes to Run Mode Self
Polling and an interrupt can be signaled to the Application Controller.
In case the RSSI signal is outside the valid threshold area, the chip stays in Self Polling
Mode and the external controller gets no interrupt (as the desired RSSI level is not
reached).
It should be mentioned that all Timeout Timers (TOTIMs) should be disabled in the
configuration set of the external processing mode as the microcontroller takes over the
control (see SFR bit group EXTPROC in the x_CHCFG register).
It is recommended to put this external configuration at the end of the On time within the
polling cycle (so right before the Off time). This is helpful when using the "EXTTOTIM"
command (goto Self Polling Mode, next configuration or Configuration A; see
Figure 77). When the external configuration is the last configuration before the Off time,
then the next configuration within the polling cycle would be the sequence of the Off time.
When data is available and the RSSI is within a valid threshold area, an interrupt is
generated (NINT). So the Application Controller can process the data and decide about
valid data.
In case the controller decides that wrong data was sent, the microcontroller can send the
register command "EXTTOTIM" (see Figure 77 and EXTPCMD register).
When the microcontroller detects valid data, then the controller can send the register
command "EXTEOM found" (see Figure 77 and EXTPCMD register) after completing
the data reception.
The functionality described above can also be used for other receive modes (mainly
TMMF, TMCDS), where the external microcontroller takes on responsibility for further
data processing.
Data Sheet
80
V1.0, 2010-02-19
TDA5235
Functional Description
Good input signal
Wrong input signal
No input signal
SelfPolling Mode
SelfPolling scenario
Sleep Mode
Figure 52
ConfigA
ConfigB
OFF-time
RSSI level too low Î
Chip stays in Self Polling Mode
and sends no interrupt
Interrupt signal
for RSSI
RunMode SelfPolling
SelfPolling / Sleep
Interrupt signal
for RSSI
RunMode SelfPolling
µC detects invalid data and sends
„EXTTOTIM“Î goto SPM
SelfPolling / Sleep
Interrupt signal
for RSSI
µC finished data reception,
sends „EXTEOM found“
RunMode SelfPolling
SelfPolling / Sleep
External Data Processing
The SFR bit group EXTPROC in the x_CHCFG register can be activated for each
configuration set for an easier handling of external data processing by the Application
Controller. Depending on the intended transparent receive mode an activation of this
function means:
•
•
•
•
•
Data path in front of Framer Unit is no longer closed (so that no data is going into
Framer Unit accidentally)
Interrupts for FSync, MID and EOM are deactivated internally
Some/all TOTIM counters are deactivated
Some/all Wake-up on Data Criteria are disabled
Wake-up on Signal Recognition is/is not disabled
Data Sheet
81
V1.0, 2010-02-19
TDA5235
Functional Description
2.5.2
Receive FIFO
The Receive FIFO is the storage of the received data frames and is only used in the POF
Mode. It is written during data reception. The host microcontroller is able to start reading
via SPI right after frame sync (interrupt) or in the most common case right after detection
of EOM (interrupt). The FIFO can store up to 256 received data bits. If the expected data
transmission contains more bits (note that in TSI 8-bit Extended Mode one bit is added
in front of the real payload to indicate which of the two TSI pattern has matched), reading
from FIFO must start a certain time after frame sync to prevent an overrun.
Architecture
The 256-bit receive FIFO is based on a bit-addressable 2-port memory architecture.
Data
Write Address
Pointer
(Up-Counter)
Write-Port
Bit-Address
In
1 of 16 Decoder
Data Clock
1 of 16 Decoder
byte 16
byte 1
byte 17
byte 2
byte 18
byte 3
byte 19
byte 4
byte 20
byte 5
byte 21
byte 6
byte 22
7
6
5
4
3
2
byte 0
256-bit byte 23
byte
8
byte 24
Memory-Array
byte 7
from FSM
INITFIFO
byte 9
byte 25
byte 10
byte 26
byte 11
byte 27
byte 12
byte 28
byte 13
byte 29
byte 14
byte 30
byte 15
byte 31
Read Address
Pointer
(Up-Counter)
7
6
5
4
3
2
1
0
FSINITFIFO
1
RESET
0
ENABLE
1 of 16 Decoder
from
DigitalReceiver
16 to 1 MUX
InitFIFO
Out
Bit-Address
Read-Port
SCLK
RESET
ENABLE
to
SPI-Bus
from
DigitalReceiver
FSync
EOM
FIFO-Overflow
FIFOController
SDO-Frame
Generator
SDO
# of Valid Bits
FIFOLK
fifolk
to FSM
Figure 53
Receive FIFO
The write port is controlled by the Digital Receiver using the Write Address Pointer.
Writing data into the FIFO starts with the detection of a TSI. The Write Address Pointer
is incremented with each data clock signal generated by the Digital Receiver. The read
port is controlled by the SPI controller using the Read Address Pointer. Each bit read
from the SPI controller increments the Read Address Pointer. The Read and Write
Address Pointers jump from their maximum value (255d) to address zero. Writing to the
FIFO stops at EOM or after Sync loss.
Data Sheet
82
V1.0, 2010-02-19
TDA5235
Functional Description
FIFO Lock Behavior
The FIFO possesses a lock mechanism that is enabled via the SFR control bit FIFOLK
in the CMC1 register. If this mechanism is enabled, the FIFO will enter a FIFO Lock state
at the detection of the EOM criterion. During the time that the FIFO is locked, it is not
possible to receive additional data in Run Mode Self Polling. This means that it is only
possible to detect another wake-up in the Self Polling Mode, but no more data in the Run
Mode Self Polling. This will guarantee that only the first complete data packet is stored
in the FIFO. Enabling FIFOLK also locks the digital receive chain at EOM until release
from FIFO lock state.
The FIFO will remain locked unless one of three conditions occurs:
1.) The remaining contents of the FIFO are completely read out via the SPI
2.) The SFR control bit FIFOLK is cleared
3.) INITFIFO at Cycle Start is set in the CMC1 register and
a) FSM is switched to Run Mode Slave or
b) FSM switches from Self Polling Mode to Run Mode Self Polling
INITFIFO (Init Fifo@ Cycle Start) = 1
Accept Data
EOM=0
Write Data into FIFO
EOM=1
FIFOLK=0
EOM=1
FIFOLK=1
FIFO Lock
FIFO Empty = 0
FIFOLK=1
Wait till FIFO is empty
FIFOLK=0
Figure 54
Data Sheet
FIFO Empty=1
FIFO Lock Behavior
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TDA5235
Functional Description
FIFO Status Word
The FIFO Status Word is attached at the end of a FIFO SPI transmission, and shows if
there was an overflow, and how many valid data bits were transmitted. The number of
valid FIFO bits is indicated at bit positions S0 to S5. S6 of the Status Word is always
undefined.
SDI
I7
I6
I1
I0
32 FIFO Bits
SDO
high impedance Z
Figure 55
D0
D1
D30
Status Word
D31
S7
S6
S1
S0
SPI Data FIFO Read
If the Write Address Pointer outruns the Read Address Pointer, an overflow is indicated
in the FIFO Overflow Status bit in the FIFO Read Status Word at position S7. All 32 FIFO
bits and the bits S5 to S0 of the Status Word are undefined while the Overflow Status bit
is set.
If a TSI is detected after an overflow, the FIFO Overflow Status bit is cleared and the
entire receive FIFO is initialized.
Initialization
Additionally, there are two possibilities to initialize the receive FIFO.
•
If the INITFIFO bit is set in the CMC1 register (“Init FIFO at Cycle Start”) the entire
receive FIFO is always initialized
a.) after switching to Run Mode Slave or
b.) switching from Self Polling Mode to Run Mode Self Polling.
•
If the FSINITFIFO bit in CMC1 register is set, the entire receive FIFO is initialized
when a TSI is detected and the receive FIFO is not locked (“Init FIFO at Frame
Start”).
Last received message length
For application protocols with several payload frames and only a short pause inbetween, the microcontroller would have to read out the FIFO very fast after detection of
an EOM. Thus even slow or overloaded Application Controllers have the possibility now
to determine the end of the last message, when reading out the FIFO, while the next
payload frame gets already received and payload data is further stored in the FIFO.
Data Sheet
84
V1.0, 2010-02-19
TDA5235
Functional Description
Therefore the last received message length (e.g. after an EOM event) is stored in
register PLDLEN and the upper two bits of register RFPLLACC at TSI detection of the
next message. The upper two bits of register RFPLLACC hold the MSBs, thus a
message length of 256 up to 1023 payload bits can be depicted. A saturation of the
message length at the maximum value of 1023 is realized. Storage at TSI of the next
message ensures that even wrong payload data (e.g. if MID is not matching, no EOM
will be generated, but payload is kept in FIFO. Or EOM data length criterion is selected
only and a sync loss prevents from generating an EOM event) can be identified.
On initialization of the FIFO, the register PLDLEN and the upper two bits of register
RFPLLACC are cleared. The corresponding internal counter is cleared with every TSI
detection and initialization of the FIFO.
PLDLEN will work correctly in case:
(INITDRXES = 0) AND ( (Data rate > 22kBit/s) OR (EOM2SPM = 0) )
If the condition above is not fulfilled, then the chip internal state machine can set
PLDLEN to 0 and a correct function of PLDLEN cannot be guaranteed.
2.5.3
Digital Output Pins
As long as the P_ON pin is high, all digital output pins operate as described. If the P_ON
pin is low, all digital output pins are switched to high impedance mode.
The digital outputs PP0, PP1, PP2 and PP3 are configurable, where each of the signals
CLK_OUT, RX_RUN, NINT, a LOW level (GND) and a HIGH level, DATA,
DATA_MATCHFIL, CH_DATA, CH_STR, RXD and RXSTR can be routed to any of the
four output pins. There is only one exception, CLK_OUT is not available on PP3. The
default configuration for these four output pins can be seen in Table 1.
Each port pin can be inverted by usage of PPCFG2 register.
The RX_RUN signal is active high for all Configurations by default. It can be deactivated
for every Configuration separately. Every PPx can be configured with an individual
RX_RUN setup. This can be set in RXRUNCFG0 and RXRUNCFG1 registers.
Interfacing to 3.3V Logic:
The TDA5235 is able to interface directly to a 3.3V logic, when chip is operated in 3.3V
environment.
Interfacing to 5V Logic:
The TDA5235 is able to interface directly to a 5V logic, when chip is operated in 5V
environment.
Data Sheet
85
V1.0, 2010-02-19
TDA5235
Functional Description
EMC Reduction of Digital I/Os:
Because electromagnetic distortion generated by digital I/Os may interfere with the high
sensitivity radio receiver, it is recommended that all inputs are filtered by adding an RC
low pass circuit.
2.5.4
Interrupt Generation Unit
The TDA5235 is able to signal interrupts (NINT signal) to the external Application
Controller on one of the PPx port pins (for further details see Chapter 2.5.3 Digital
Output Pins). The Interrupt Generation Unit receives all possible interrupts and sets the
NINT signal based on the configuration of the Interrupt Mask register IM0. The Interrupt
Status register IS0 is set from the Interrupt Generation Unit, depending on which
interrupt occurred. The polarity of the interrupt can be changed in the PPCFG2 register.
Please note that during power up and brownout reset, the polarity of NINT signal is
always as described in Chapter 2.4.9.2 Chip Reset.
A Reset event has the highest priority. It sets all bits in the Status register to “1” and sets
the interrupt signal to “0”. The first interrupt after the Reset event will clear the Status
register and will set the interrupt signal to “1”, even if this interrupt is masked.
A Wake-up interrupt clears the FsyncA, FsyncB and the complementary Wake-up flag.
An Fsync interrupt clears the EOMA, EOMB, MIDA, MIDB and the complementary Fsync
flag.
The Interrupt Status register is always cleared after read out via SPI.
It is not possible to disable the Power On Reset Indicator Interrupt using the Interrupt
Mask register.
Some interrupts are not usable depending on the selected receive mode, which is
described in Chapter 2.5.1.2 Data Interface.
Interrupts for WU can be used in all receive modes.
Interrupts for FSync, MID and EOM can only be used in the receive modes POTP and
POF.
Data Sheet
86
V1.0, 2010-02-19
TDA5235
Wake-up Cfg A
WUA
FSync Cfg A
FSyncA
Message ID Cfg A
MIDA
EOM Cfg A
EOMA
Wake-up Cfg B
WUB
FSyncB
FSync Cfg B
Message ID Cfg B
MIDB
EOMB
EOM Cfg B
Power-Up / Brownout
Functional Description
IS0
IM0
Interrupt-Mask
NINT
Reset
Interrupt-Signalling
NINT signal
Figure 56
Interrupt Generation Unit
RESET
PP2_select=NINT
PP2INV
SPI READ IS0
IS0
X
FF
01
03
07
0F
1C
30
70
F0
00
PP2(NINT)
WU(A,B)
FSYNC(A,B)
MID(A,B)
EOM(A,B)
ConfigA
Figure 57
Data Sheet
ConfigB
Interrupt Generation Waveform (Example for Configuration A+B)
87
V1.0, 2010-02-19
TDA5235
Functional Description
The following handling mechanism for read-clear registers was chosen due to
implementation of the Burst Read command:
•
•
the current Interrupt Status (ISx) register 8-bit content is latched into the SPI shift
register after the last address bit is clocked-in (point A in Figure 58)
the IS register is then cleared after last IS register bit is clocked out of the SPI
interface (point B in Figure 58)
Consequence: any interrupt event occurring in the window-time between points A and B
is cleared at point B and not stored/shown in an later readout of ISx.
(However: NINT signal is toggling in any case, if occurring interrupt is not masked in IMx
register)
A
B
8-bit @2MHz = 4us
irq1 (masked?)
irq2 (masked?)
nint
ncs
SPI IF
inst
addr
read /readb data = IS(t+0)
read/capture IS*
content
SFR IS* IS(t-1)
IS(t+0)
SFR IS* read clear
@end of data frame
IS(t+1) 0x00
NOTE:
SFR IS(j) status flag is cleared
before it can be read if an IRQ
occurs during SPI data frame
Figure 58
ISx Readout Set Clear Collision
Please see also the IMPORTANT NOTE in the Burst Read section !
Data Sheet
88
V1.0, 2010-02-19
TDA5235
Functional Description
2.5.5
Digital Control (4-wire SPI Bus)
The control interface used for device control and data transmission is a 4-wire SPI
interface.
•
•
•
•
NCS - select input, active low
SDI
- data input
SDO - data output
SCK - clock input: Data bits on SDI are read in at rising SCK edges and written out
on SDO at falling SCK edges.
Level definition:
logic 0 = low voltage level
logic 1 = high voltage level
Note for non-Burst modes: It is possible to send multiple frames while the device is
selected. It is also possible to change the access mode while the device is selected by
sending a different instruction.
Note: In all bus transfers MSB is sent first, except for the received data read from the
FIFO. There the bit order is given as first bit received is first bit transferred via the bus.
To read from the device, the SPI master has to select the SPI slave unit first. Therefore,
the master must set the NCS line to low. After this, the instruction byte and the address
byte are shifted in on SDI and stored in the internal instruction and address register. The
data byte at this address is then shifted out on SDO. After completing the read operation,
the master sets the NCS line to high.
NCS
Frame
1
8
1
Frame
8
1
8
1
8
1
8
1
8
SCK
Instruction
SDI
SDO
Register Address
Instruction
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0
high impedance Z
Figure 59
Data Sheet
Register Address
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0
Data Out
Data Out
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Read Register
89
V1.0, 2010-02-19
TDA5235
Functional Description
To read from the device in Burst mode, the SPI master has to select the SPI slave unit
first. Therefore the master has to drive the NCS line to low. After the instruction byte and
the start address byte have been transferred to the SPI slave (MSB first), the slave unit
will respond by transferring the register contents beginning from the given start address
(MSB first). Driving the NCS line to high will end the Burst frame.
NCS
1
8
1
8
1
8
1
8
1
8
SCK
Instruction
SDI
Register Start Address
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0
Data Out (i)
SDO
high impedance Z
Figure 60
Data Out (i+1)
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7
Data Out (i+x)
D0 D7 D6 D5 D4 D3 D2 D1 D0
Burst Read Registers
IMPORTANT NOTE - for being upwards compatible with further versions of the
product, we give following strong recommendation:
For read-clear registers at address (N), no read-burst access stopping at address
(N-1) is allowed, because read-clear register will be cleared without being read out.
Use single read command to read out the register at address (N-1) or extend the
burst read to include the read-clear register at address (N).
To write to the device, the SPI master has to select the SPI slave unit first. Therefore,
the master must set the NCS line to low. After this, the instruction byte and the address
byte are shifted in on SDI and stored in the internal instruction and address register. The
following data byte is then stored at this address.
After completing the writing operation, the master sets the NCS line to high.
Additionally the received address byte is stored into the register SPIAT and the received
data byte is stored into the register SPIDT. These two trace registers are readable.
Therefore, an external controller is able to check the correct address and data
transmission by reading out these two registers after each write instruction. The trace
registers are updated at every write instruction, so only the last transmission can be
checked by a read out of these two registers.
Data Sheet
90
V1.0, 2010-02-19
TDA5235
Functional Description
NCS
Frame
1
8
1
Frame
8
1
8
1
8
1
8
1
8
SCK
Instruction
SDI
SDO
Register Address
Data Byte
Instruction
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Register Address
Data Byte
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
high impedance Z
Figure 61
Write Register
To write to the device in Burst mode, the SPI master has to select the SPI slave unit
first. Therefore the master has to drive the NCS line to low. After the instruction byte and
the start address byte have been transferred to the SPI slave (MSB first) the successive
data bytes will be stored into the automatically addressed registers.
To verify the SPI Burst Write transfer, the current address (start address, start address
+ 1, etc.) is stored in register SPIAT and the current data field of the frame is stored in
register SPIDT. At the end of the Burst Write frame the latest address as well as the
latest data field can be read out to verify the transfer. Note that some error in one of the
intermediate data bytes can not be detected by reading SPIDT.
Driving the NCS line to high will end the Burst frame.
A single SPI Burst Write command can be applied very efficiently for data transfer either
within a register block of configuration dependent registers or within the block of
configuration independent registers.
NCS
1
8
1
8
1
8
1
8
1
8
SCK
Instruction
SDI
SDO
Register Start Address
Data Byte (i)
Data Byte (i+1)
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Data Byte (i+x)
D7 D6 D5 D4 D3 D2 D1 D0
high impedance Z
Figure 62
Data Sheet
Burst Write Registers
91
V1.0, 2010-02-19
TDA5235
Functional Description
The SPI also includes a safety feature by which the checksum is calculated with an
XOR operation from the address and the data when writing SFR registers. The
checksum is in fact an XOR of the data 8-bitwise after every 8 bits of the SPI write
command. The calculated checksum value is automatically written in the SPICHKSUM
register and can be compared with the expected value. After the SPICHKSUM register
is read, its value is cleared.
In case of an SPI Burst Write frame, a checksum is calculated from the SPI start address
and consecutive data fields.
enable every 8 bit
SPI shift register
Figure 63
Checksum SFR
XOR
read/clear
SPI Checksum Generation
To read the FIFO, the SPI master has to select the SPI slave unit first. Therefore, the
master must set the NCS line to low. After this, the instruction byte is shifted in on SDI
and stored in the internal instruction register. The data bits of the FIFO are then shifted
out on SDO. The following byte is a status word that contains the number of valid bits in
the data packet. After completing the read operation, the master sets the NCS line to
high.
NCS
Frame
1
8
Frame
1
32
1
8
1
8
1
32
1
8
SCK
Instruction
SDI
I7
I6
Instruction
I1
I0
I7
32 FIFO Bits
SDO
high impedance Z
D0
D1
D30
I6
I1
I0
Status Word
D31
S7
Figure 64
Read FIFO
Table 4
Instruction Set
S6
S1
32 FIFO Bits
S0
D0
D1
D30
Status Word
D31
S7
S6
S1
S0
Instruction
Description
Instruction Format
WR
Write to chip
0000 0010
RD
Read from chip
0000 0011
RDF
Read FIFO from chip
0000 0100
WRB
Write to chip in Burst mode
0000 0001
RDB
Read from chip in Burst mode 0000 0101
Data Sheet
92
V1.0, 2010-02-19
TDA5235
Functional Description
2.5.5.1
Timing Diagrams
tDeselect
NCS
tnot_hold
tSetup
tCLK_H
thold
tnot_setup
SCK
tSDI_setup
tSDI_hold
tCLK_L
SDI
high impedance Z
SDO
Figure 65
Serial Input Timing
NCS
tCLK_H
SCK
tCLK_SDO
tCLK_SDO
tCLK_L
tSDO_r
tSDO_disable
tSDO_f
Z
SDO
SDI
Z
ADDR LSB
Figure 66
Data Sheet
Serial Output Timing
93
V1.0, 2010-02-19
TDA5235
Functional Description
Table 5
SPI Bus Timing Parameter
Symbol
Parameter
fclock
Clock frequency
tCLK_H
Clock High time
tCLK_L
Clock Low time
tsetup
Active setup time
tnot_setup
Not active setup time
thold
Active hold time
tnot_hold
Not active hold time
tDeselect
Deselect time
tSDI_setup
SDI setup time
tSDI_hold
SDI hold time
tCLK_SDO
Clock low to SDO valid
tSDO_r
SDO rise time
tSDO_f
SDO fall time
tSDO_disable
SDO disable time
2.5.6
Chip Serial Number
Every device contains a unique, preprogrammed 32-bit wide serial number. This number
can be read out from SN3, SN2, SN1 and SN0 registers via the SPI interface. The
TDA5235 always has SN0.6 set to 1 and SN0.5 set to 0.
SN0
......
......
Fuses
FuseReadoutInterface
SN1
SN2
SN3
Figure 67
Data Sheet
Chip Serial Number
94
V1.0, 2010-02-19
TDA5235
Functional Description
2.6
System Management Unit (SMU)
The System Management Unit consists of two main units:
•
•
Master Control Unit, where the various operating modes can be configured.
Polling Timer Unit, where the receiver’s On and Off times and modes are defined.
The Polling Timer Unit is only working in the Self Polling Mode.
2.6.1
Master Control Unit (MCU)
2.6.1.1
Overview
The Master Control Unit controls the operation modes, the global states, and is generally
responsible for automating data reception, verification, identification, extraction, and
storage into the FIFO. The payload data without RUNIN, TSI and optional EOM can be
read from the FIFO via SPI by the external microcontroller.
Alternatively, a transparent data stream can also be processed externally by the
Application Controller (see Chapter 2.5.1.2 Data Interface).
The following operation modes and the behavior of the Master Control Unit are fully
automatic and only influenced by SFR settings and by incoming RF data streams.
The TDA5235 has two major operation modes, which are switched by SFR bit MSEL.
In Slave Mode the device is controlled via SPI by the external microcontroller. This mode
supports:
•
•
•
Run Mode Slave (RMS), where the receiver is continuously active
SLEEP Mode, where the receiver is switched off for power saving. This mode can
also be used to change register settings
HOLD Mode, allows register settings to be changed. The change to HOLD Mode and
back to RMS is faster than changing to SLEEP Mode and back to RMS.
In Slave Mode, switching between configurations, as well as between Run and SLEEP
Mode must be initiated by the microcontroller.
In Self Polling Mode, TDA5235 autonomously polls for incoming RF signals. The
receiver switches automatically between up to two configurations (Configuration A and
B). Further information can be found in Chapter 2.6.2.
Between the RF signal scans, the receiver is automatically switched to Low Power Mode
for reducing the average power consumption. If an incoming signal fulfills the selected
wake-up criterion an interrupt can be generated and Run Mode Self Polling will be
entered. If the following received data matches to the TSI pattern, and passes the
optional message ID screening, the payload is loaded into the FIFO, and, if not masked,
an interrupt is generated. Then the payload data can be read via SPI.
Data Sheet
95
V1.0, 2010-02-19
TDA5235
Functional Description
Init
Reset
Bit:SLRXEN == 1
Bit:MSEL == 0
Bit:SLRXEN == 0
Bit:MSEL == 0
Sleep Mode
Initialize RX-Part
Bit:SLRXEN == 0
or
Bit:MSEL == 1
Bit:SLRXEN == 0
or
Bit:MSEL == 1
Chip is idle
Bit:SLRXEN == 1
Bit:MSEL == 0
Run Mode
Slave
Bit:SLRXEN == 1
Bit:MSEL == 0
Chip is permanently
active
Bit:SLRXEN == X
Bit:MSEL == 1
Bit:SLRXEN == X
Bit:MSEL == 0
Init
Initialize RX-Part
Bit:SLRXEN == X
Bit:MSEL == 0
Bit:SLRXEN == X
Bit:MSEL == 1
Bit:SLRXEN == X
Bit:MSEL == 0
ToTim Timeout == X
Self Polling
Mode
Bit:SLRXEN == X
Bit:MSEL == 1
EOM2SPM == 1
Chip is periodically active
and searching for
WU criteria
Bit:SLRXEN == X
Bit:MSEL == 1
ToTim Timeout == 1
Run Mode
Self Polling
Chip is permanently
active
Figure 68
2.6.1.2
Bit:SLRXEN == X
Bit:MSEL == 1
WUC found == 0
Bit:SLRXEN == X
Bit:MSEL == 1
WUC found == 1
Bit:SLRXEN == X
Bit:MSEL == 1
ToTim Timeout == 0
Global State Diagram
Run Mode Slave (RMS)
In Run Mode Slave, the receiver is able to continuously scan for incoming data streams.
Detection and validation of a wake-up criterion are not performed, but RUNIN and TSI
are required.
Recognition of TSI and validation of the optional MID (Message IDentification) are done
automatically. The data payload is extracted from the data stream, and moved to the
FIFO.
The various recognition steps are communicated by interrupts. Interrupts can be
generated at frame-start (when a valid TSI has been detected), when a valid MID has
been found and at EOM (End of Message).
Alternatively, a transparent data stream can also be processed externally by the
Application Controller (see Chapter 2.5.1.2 Data Interface).
Run Mode Slave is entered by setting SFR CMC0 bits MSEL to 0 and SLRXEN to 1.
Data Sheet
96
V1.0, 2010-02-19
TDA5235
Functional Description
Configurations are switched via SFR bit MCS in the CMC0 register. The RF channel can
be selected by SFRs x_PLLINTC1, x_PLLFRAC0C1, x_PLLFRAC1C1,
x_PLLFRAC2C1, where x = A or B.
The configuration may be changed only in SLEEP or in HOLD Mode before returning to
the previously selected operation mode. This is necessary to restart the state machine
with defined settings at a defined state. Otherwise the state machine may hang up.
Reconfigurations in HOLD Mode are faster, because there is no Start-Up sequence.
The following flowchart and explanation show and help to understand the internal
behavior of the Finite State Machine (FSM) in Run Mode Slave.
Data Sheet
97
V1.0, 2010-02-19
TDA5235
Functional Description
0
Wait
Startup Finished == 0
Wait Till Startup
Has Finished
Startup Finished == 1
4
1
FIFO locked
Wait Till FIFO Read Out
INIT
fifolk == 1
EXTPROC==00 Init FIFO=Init FIFO@Cyc.
Symbol Sync ==0
INITDRXES==1
fifolk == 0
2
fifolk == 1
INIT
fifolk == 0
INITDRXES==1
Init Digital Receiver
Symbol Sync ==0
INITDRXES==0
3
fifolk == 0
INITDRXES==0
Symbol Sync == 0
Generating A Frame Start
Interrupt If Not Masked
Symbol Sync == 1
EXTPROC<>10
Hold == 0
12
5
Hold
Ready for
reconfiguration
Wait
Wait Till Symbol
Synchronization
Is Found
Wait
Frame Sync == 0
Hold == 1
Wait Till Frame Start
Is Found
Frame Sync == 1
EXTPROC==00
6
INIT FIFO
Init FIFO =
Init FIFO@FSYNC
7
Check
MID Setup
MID Screening enable == 0
Check The MID Setup
Register
MID Screening enable == 1
8
Init MID
Scanning Unit
Initialize The MID
Scanning Unit
9
MID Scanning Finished == 0
Wait
Store RX Data Into FIFO
Wait For Scan Finish
MID Scanning Finished == 1
10
MID Found == 0
Generating A MID Found
Interrupt If Not Masked
Checking ID
Scanning Result
Store RX Data Into FIFO
Analyze The Scanning
Result
Generating A EOM Interrupt If
Not Masked
MID Found=1
11
EOM Check
EOM Found == 1
Store RX Data Into FIFO
Check For EOM
EOM Found == 0
Figure 69
Data Sheet
Run Mode Slave
98
V1.0, 2010-02-19
TDA5235
Functional Description
2.6.1.3
HOLD Mode
This state (item 12 in Figure 69) is used for fast reconfiguration of the chip in Run Mode
Slave. This state can be reached after the Start-Up Sequencer and Initialization of the
chip have been completed from any state from 3 to 11. To reconfigure the chip the SFR
control bit HOLD must be set. After reconfiguration in this state the SFR control bit HOLD
must be cleared again. After leaving the HOLD state, the INIT state is entered and the
receiver can work with the new settings. Be aware that the time between changing the
configuration and reinitialization of the chip has to be at least 40us. Take note that one
SPI command for clearing the SFR control bit HOLD needs 24 bits or 12μs at an SPI
data rate of 2.0Mbit/s. The remaining 28μs must be guaranteed by the application.
FSM State
EOM-Check
SPI Command
Instruction Address
Write
CMC0
0x02
HOLD
Data
HOLD=1
Instruction Address
Write
x_PLL...
0x02
INIT
Data
(sel. other
channel)
Instruction Address
Write
CMC0
0x02
Wait till
SSync
Data
HOLD=0
12us @ 2.0MHz
40us
Figure 70
HOLD State Behavior (INITPLLHOLD disabled)
In case of large frequency steps, an additional VAC routine (VCO Automatic Calibration)
has to be activated when recovering from HOLD Mode (INITPLLHOLD bit). The
maximum allowed frequency step in HOLD Mode without activation of VAC routine is
depending on the selected frequency band. The limits are +/- 1 MHz for the 315 MHz
band, +/- 1.5 MHz for the 434 MHz band and +/- 3 MHz for the 868/915 MHz band.
When this additional VAC routine is enabled, the TDA5235 starts initialization of the
Digital Receiver block after release from HOLD and an additional Channel Hop time.
FSM State
SPI Command
EOM-Check
Instruction Address
Write
CMC0
0x02
HOLD
Data
HOLD=1
Instruction Address
Write
x_PLL...
0x02
Data
(sel. other
channel)
VAC
Instruction Address
Write
CMC0
0x02
VAC
INIT
Wait till
SSync
Data
HOLD=0
12us @ 2.0MHz
tC _Hop
40us
Figure 71
HOLD State Behavior (INITPLLHOLD enabled)
HOLD Mode is only available in Run Mode Slave. Configuration changes in Self Polling
Mode have to be done by switching to SLEEP Mode and returning to Self Polling Mode
after reconfiguration.
Data Sheet
99
V1.0, 2010-02-19
TDA5235
Functional Description
2.6.1.4
SLEEP Mode
The SLEEP Mode is a power save mode. The complete RF part is switched off and the
oscillator is in Low Power Mode. As in HOLD Mode, the chip can be reconfigured. When
switching from SLEEP to Run Mode Slave, the state machine starts with the internal
Start-Up Sequence.
2.6.1.5
Self Polling Mode (SPM)
In Self Polling Mode TDA5235 autonomously polls for incoming RF wake-up data
streams. There is no processing load on the host microcontroller. When a wake-up
criterion has been found, an interrupt can be generated and the TDA5235 mode is
changed to Run Mode Self Polling for automatic verification of TSI, optional MIDs and
for transfer of payload data into the FIFO.
A general overview on a typically transmitted protocol and the behaviour of the TDA5235
is given in Figure 72.
TX - RX interaction in RX - Self Polling Mode
TX Telegram:
Wake-up Frame
Wake-up Frame continued or Gap
RUNIN + Wake-up sequence
1)
Data Frame
(RUNIN)
TSI
PAYLOAD
EOM
RX Mode:
On time 2)
Self Polling Mode
On time 2)
Self Polling Mode
a
b
Run Mode Self Polling
Legend:
1) There can either be a Wake -up Frame directly followed by a Data Frame or the Wake -up Frame is separated from the Data Frame by a Gap in -between .
2) The position of the O n time can vary (a, b, ...) as there is no synchronization between transmitted telegram and start of the receiver’s On time.
Figure 72
SPM - TX-RX Interaction
Alternatively, a transparent data stream can also be processed externally by the
Application Controller (see Chapter 2.5.1.2 Data Interface).
Self Polling Mode is entered by setting the MSEL register bit to 1.
Configuration changes are allowed only by switching to SLEEP Mode, and returning to
Self Polling Mode after reconfiguration.
Data Sheet
100
V1.0, 2010-02-19
TDA5235
Functional Description
The Polling Timer Unit controls the timing for scanning (On time) and sleeping (Off
time, SPM_OFF). Up to two independent configuration sets (A and B) can automatically
be processed, thus enabling scanning from different transmit sources. See also
Chapter 2.6.2 Polling Timer Unit.
The Wake-Up Generation Unit identifies, whether an incoming data stream matches
the configurable wake-up criterion.
After fulfillment of the wake-up criterion, modulation can be switched automatically.
See also Chapter 2.6.1.6 Automatic Modulation Switching, Chapter 2.4.8.5 WakeUp Generator and Chapter 2.5.1.2 Data Interface (in Subsection TMRDS).
The following state diagrams and explanations help to illustrate the behavior during Self
Polling Mode. First there is a search for a wake-up criterion according to Configuration
A. Then, there is an optional search for a wake-up criterion according to Configuration B.
In applications using only Single-Configuration, settings are always taken from
Configuration A.
Data Sheet
101
V1.0, 2010-02-19
TDA5235
Functional Description
RX_RUN=0
RX_RUN == 0
1
IDLE
Permanent WU Search Mode Enable == 0
Chip is idle
RX_RUN == 1
2
Wait
Startup Finished == 0
Wait Till Startup
Has Finished
From Run Mode Self Polling
Startup Finished == 1
Init
Loop Counter
3
Permanent WU Search Mode Enable == 1
CfgLoopCounter
is Initialized
WU Search With
Configuration A
Modulation
Switching CFG A
4
Modulation Selection
Depending On Register
Setting
Init With
CFG A
5
Initialize RX- Part
Configuration A
Permanent WU Search Mode Enable == 0
Const On Time
Fast Fall Back To Sleep
7
ON Time elapsed == 0
WU Found == 0
Permanent WU Search Mode Enable == 1
7
WU Search
CFG A FFTS
WU Search
CFG A COOT
Search For A Configurated
Wake Up Criteria
Fast Fall Back
Search For A Configurated
Wake Up Criteria
Const On Off
ON Time elapsed == 1
WU Found == 0
WU Search Finished == 1
WU Found == 1
ON Time elapsed == X
WU Found == 1
WU Search Finished == 0
WU Search Finished == 1
WU Found == 0
9
Compare
Compare Loop Counter
Against Number Of
Configs
CfgLoopCounter <> CfgNr
CfgLoopCounter == CfgNr
8
Store
Channel
Store The Current Channel
Configuration Into Actual
Channel Register
12
Generating WU CFG A
Interrupt If Not Masked
Run Mode
Self Polling
Chip is permanently
active
To Init Loop Counter
of Config B
Figure 73
Data Sheet
From Compare of
Config B
Wake-up Search with Configuration A
102
V1.0, 2010-02-19
TDA5235
Functional Description
To Init Loop
Counter / Idle of
Config A
From Compare of
Config A
WU Search With
Configuration B
4
Modulation
Switching CFG B
Modulation Selection
Depending On Register
Setting
5
Init With
CFG B
Initialize RX-Part
Configuration B
Permanent WU Search Mode Enable == 0
Const On Time
Fast Fall Back To Sleep
7
ON Time elapsed == 0
WU Found == 0
Permanent WU Search Mode Enable == 1
7
WU Search
CFG B COOT
WU Search
CFG B FFTS
Search For A Configurated
Wake Up Criteria
Const On Off
Search For A Configurated
Wake Up Criteria
Fast Fall Back
ON Time elapsed == X
WU Found == 1
ON Time elapsed == 1
WU Found == 0
WU Search Finished == 1
WU Found == 1
WU Search Finished == 0
WU Search Finished == 1
WU Found == 0
9
Compare
Compare Loop Counter
Against Number Of
Configs
(CfgLoopCounter == CfgNr)
8
Store
Channel
Store The Current Channel
Configuration Into Actual
Channel Register
12
Generating WU CFG B
Interrupt If Not Masked
Run Mode
Self Polling
Chip is permanently
active
Figure 74
Data Sheet
Wake-up Search with Configuration B
103
V1.0, 2010-02-19
TDA5235
Functional Description
2.6.1.6
Automatic Modulation Switching
In Self Polling Mode, the chip is able to automatically change the type of modulation
after a wake-up criterion was fulfilled in a received data stream. The type of modulation
used in the different operational modes is selected by the SFR control bit MT.
2.6.1.7
Multi-Channel in Self Polling Mode
A simple Multi-Channel behavior can be realized when the same application parameters
are programmed in both Configuration sets and only the RF PLL frequency differs.
Channel frequencies are defined in registers x_PLLINTC1, x_PLLFRAC0C1,
x_PLLFRAC1C1, x_PLLFRAC2C1, where x = A or B.
See also Chapter 2.4.5 Sigma-Delta Fractional-N PLL Block.
2.6.1.8
Run Mode Self Polling (RMSP)
The chip enters Run Mode Self Polling after a successful fulfillment of a wake-up
criterion in Self Polling Mode.
When Wake-Up criterion for RSSI or Signal Recognition (see Chapter 2.4.8.1) is
selected and fulfilled, this leads to a change to Run Mode Self Polling. This will be
interesting especially in case of a transparent data stream being processed externally by
the Application Controller (see Chapter 2.5.1.2 Data Interface).
The following steps are performed automatically, depending on register settings:
•
•
•
•
Modulation switching (see Chapter 2.6.1.6 Automatic Modulation Switching)
Wait for valid TSI (see Chapter 2.4.8.6 Frame Synchronization)
Initialize FIFO (see Chapter 2.5.2 Receive FIFO) and write data to FIFO
Scan for MIDs (see Chapter 2.4.8.7 Message ID Scanning)
Depending on interrupt masking, the host microcontroller is alerted when
•
•
•
a data frame has started,
an MID has been found, (if enabled) or
EOM (End of Message) has been detected.
See also Chapter 2.5.4 Interrupt Generation Unit
Run Mode Self Polling is left, when synchronization is lost and the timeout timer for loss
of synchronization (TOTIM_SYNC) has elapsed, or when one of the other timeout timers
(TOTIM_TSI, TOTIM_EOM) for each configuration (A, B) has elapsed, or when an EOM
occurred and the SFR bit EOM2SPM is activated, or when the operating mode is
switched to SLEEP or Run Mode Slave by the host microcontroller.
Data Sheet
104
V1.0, 2010-02-19
TDA5235
Functional Description
Timeout timers for getting no TSI or getting no EOM within a certain time period can be
used to avoid a deadlock situation, e.g. TOTIM_TSI can be used in case an interfering
transmit signal fulfilled the wake-up criterion and keeps on transmitting, but no TSI can
be found in this data stream within a certain programmable time period. TOTIM_EOM
might be used in case EOM criterion “EOM by payload data length” cannot be applied.
The timeout timer functionality in the absence/presence of an interfering signal is shown
in Figure 75 and Figure 76.
Without interfering signal:
Wake-up
RI TSI Payload1
RI TSI Payload2
EOM
TX signal
EOM
WU frame and Payload frame have the same modulation type
e.g. TOTIM_TSI is set to 15ms
RX_RUN
WU-data Interrupt
RunMode SelfPolling
SelfPolling / Sleep
Init TOTIMs
TOTIM_SYNC
counter activity
TOTIM_TSI
counter activity
9.5ms
5ms
5ms
TOTIM_EOM
counter activity
Figure 75
Data Sheet
TOTIM Behavior without Presence of Interferer
105
V1.0, 2010-02-19
TDA5235
Functional Description
With interfering signal (interferer signal has same data rate as wanted wake-up signal):
WU frame and Payload frame have the same modulation type
e.g. TOTIM_TSI is set to 15ms
RI TSI Payload1
Wake-up
RI TSI Payload2
EOM
TX signal
EOM
TX interferer
RX_RUN
WU-data Interrupt
RunMode SelfPolling
SelfPolling / Sleep
*)
Init TOTIMs
TOTIM_SYNC
counter activity
TOTIM_TSI
counter activity
15ms
TOTIM_EOM
counter activity
*) Chip proceeds with Self Polling Mode
Figure 76
TOTIM Behavior in Presence of Interferer
On expiring of one of the timeout timers, the receiver proceeds with Self Polling Mode
and with searching for a suitable wake-up criterion on the next configuration or a search
for a wake-up criterion in Configuration A is initiated.
As long as the chip is in Run Mode Self Polling, incoming data frames (including a
RUNIN sequence and TSI, but without necessity of additional wake-up patterns) can be
received and stored.
The data FIFO can be initialized and cleared either at
• Cycle Start, that means whenever Run Mode Self Polling is entered or
• Frame Start, when a TSI has been successfully identified (and Receive FIFO is not
locked).
Further information about the Receive FIFO can be found in the Chapter 2.5.2 Receive
FIFO.
After an EOM was found, the information about the RF channel and the configuration of
the actual payload data is saved in the RFPLLACC register.
Data Sheet
106
V1.0, 2010-02-19
TDA5235
Functional Description
After detection of EOM the TDA5235 can either proceed with a search for a wake-up
criterion in the next configuration or a search for wake-up in Configuration A can follow
or the TOTIMs of the current configuration are reloaded for being prepared to receive
another (redundant) payload data frame within the same configuration.
Alternatively, a transparent data stream can also be processed externally by the
Application Controller. Therefore the external controller needs the possibility to send
following commands, which would normally be generated by the TDA5235 itself (see
Figure 77 and EXTPCMD register as well):
•
•
EXTTOTIM: So the TDA5235 can proceed with Self Polling Mode (either with the
next configuration or with Configuration A).
EXTEOM found: In this case the TDA5235 can either proceed with Self Polling Mode
(either with the next configuration or with Configuration A) or stay in Run Mode Self
Polling.
EXTTOTIM and EXTEOM are only available, when the external processing mode is
deactivating functional blocks (see bit group x_CHCFG.EXTPROC).
When the actual processed configuration is right before the Off time and the Application
Controller sends one of the above mentioned commands, then the TDA5235 can
proceed with the Off time (in case next configuration is selected).
If the autonomous Wake-up Search with Configuration A follows a TOTIM or EOM event,
then also the Polling Timer is initialized, this means a new On period is started. In case
the Wake-up Search gets started with Next Configuration (after a TOTIM or EOM event),
then the Polling Timer is not initialized. This means that the On time counter proceeds
with the old value from leaving the previous Wake-up search period successfully. This is
the case for Fast Fall Back to SLEEP Mode.
In Constant On-Off Time Mode the Polling Timer is always initialized after a TOTIM or
EOM event.
Data Sheet
107
V1.0, 2010-02-19
TDA5235
Functional Description
0
All Operations Are Done With
The Wake Up Configuration
Modulation
Switching
Modulation Selection
Depending On Register
Setting
1
INIT
If PWUF == 0 then
{ Init FIFO =
Init FIFO@Cycle Start }
PWUF = 0
To Self Polling Mode
(WU Search With Next
Configuration )
To Self Polling Mode
(WU Search With
Configuration A )
1.1
17
INIT
INIT
Generating WU
CFG X Interrupt
If Not Masked
Goto SP Next
Configuration
If INITFRCS== 1 then
Init Framer
Init Digital Receiver
EXTTOTIM
(from external controller)
INITDRXES==1
2
3
Init TOTIMs
Symbol Sync ==0
Wait Till FIFO Read Out
INITDRXES==0
16
3.1
fifolk == 0
Parallel Wake-Up
Found
To Self Polling Mode
(WU Search With
Configuration A)
Wait
ToTim Timeout TSI == 0
Frame Sync == 1
EXTPROC==00
Start ToTimEOM (If Enab.)
Init FIFO=
InitFIFO@FSYNC
Check
MID Setup
MID Screening
enable == 0
Check The MID Setup
Register
13
It Is Possible To Disable
The Timeout Feature
Generating A Frame Start
Interrupt If Not Masked
INIT FIFO
6
7
INITDRXES==1
ToTim Timeout TSI == 1
Frame Sync == X
EXTPROC == 00
Start ToTim TSI (If Enabl.)
Wait Till Frame Start
Is Found
EOM2SPM == 0
Symbol Sync ==0
ToTim Timeout TSI == 0
Frame Sync == 0
5
EOM2nCfg == 1
EOM2SPM == 1
ToTim Timeout SYNC == 0
Symbol Sync == 0
ToTim Timeout SYNC == 0
Symbol Sync == 1
EXTPROC <> 10
ToTim Timeout SYNC == 1
Symbol Sync == X
ToTim Timeout SYNC == 1
Symbol Sync == X
EXTPROC <> 10
(If Enabled)
EOM2nCfg == 0
Goto Next
Config After EOM
fifolk == 0
Wait
WU Found == 1
PWUF == 1
Start ToTim Timer SYNC
To Self Polling Mode
(WU Search With
Next Configuration)
14
INIT
Init
Digital Receiver
4
WU Found == 1
PWUF == 1
ToTim Timeout == 1
EXTPROC==00
fifolk == 1
FIFO locked
Initialize TOTIM timers
MID Screening
enable == 1
Goto SelfPolling
After EOM
8
Init MID
Scanning Unit
ToTim Timeout
EOM == 1
Initialize The MID
Scanning Unit
9
Wait
Store RX Data Into FIFO
Wait For Scan Finish
Save
Channel and
Configuration
Information
MID Scanning
Finished == 0
Generating A MID Found
Interrupt If Not Masked
MID Scanning
Finished == 1
MID Found == 0
Checking ID 10
Scanning Result
Store RX Data Into FIFO
Analyze The Scanning
Result
Generating A EOM
Interrupt If Not Masked
MID Found == 1
11
EOM Found == 1
EXTEOM found
EOM Check
Store RX Data Into FIFO
Check For EOM
PWUF = PWUEN bit
(from external controller)
Figure 77
Data Sheet
15
TOTIM2nCh == 0
INITDRXES==0
12
TOTIM2nCh == 1
ToTim Timeout EOM == 1
EOM Found == X
ToTim Timeout EOM == 0
EOM Found == 0
Run Mode Self Polling
108
V1.0, 2010-02-19
TDA5235
Functional Description
While the TDA5235 is in Run Mode Self Polling, further Wake-ups would normally not be
detected by the receiver. If the functionality of a parallel Wake-up search during the
search for a TSI is desired, this can be activated by the PWUEN bit. In this case the
Wake-up search is not active during a recognized payload and is only active after the
first received payload frame, as can be seen from Figure 77. This feature can only be
used, when modulation type is the same for SPM and RMSP.
So after a reception of the EOM from the current payload, the parallel WU search can
take place in this mode. The WU search will be active after Symbol Sync has been
detected. The WU search will be active until the Synchronization gets lost or wake-up is
generated. After the Synchronization gets lost the WU search will be finished and wakeup can not be detected any more (the TSI search continues as usual).
Following procedure can be applied with help of 3 SPI Write command sequences.
The idea is to generate external EOM every time the Symbol Sync goes to inactive state
and no interrupt (TSI or WU) has been detected. This will bring the MCU to the cycle start
and reinitialize the WU search.
Configuration:
Write x_WUC.PWUEN = 1
// Enable Parallel Wake-up search
Write x_WURSSITH1 0xFF
// Set RSSI threshold to max value (avoid WU during the reinitialization procedure)
Write x_WULOT 0xFF
// Set WULOT to max value (avoid WU during the reinitialization procedure)
Data Sheet
109
V1.0, 2010-02-19
TDA5235
Functional Description
Wait for Wake-up interrupt
TIMEOUT -> SLEEP -> SPM
or (dependent on application )
EXT_TOTIM:
* Select external processing (for ext. TOTIM)
(Write x_CHCFG.EXTROC = 0x2)
* Generate external TOTIM
(Write EXTPCMD 0x02)
* Disable external processing
(Write x_CHCFG.EXTROC = 0x0)
WU IRQ
WU IRQ
Wait for TSI interrupt
TSI IRQ
TSI IRQ
Wait for EOM interrupt
EOM IRQ
Only necessary if other PPx signals needed during self -polling
otherwise configure PPx once at the beginning
Activate Symbol Sync on PPx
(example for PP 0;
for other PPx see notes below )
Write 0xF4 0x07
Write PPCFG0.PP0CFG = 0xE
Deactivate Symbol Sync on PPx
(example for PP 0 = RX_RUN)
Write PPCFG0.PP0CFG = 0x1
1. Force Symbol Sync for MCU to 0
Write 0xED 0x40
2. Select external processing (for ext. EOM)
Write x_CHCFG.EXTPROC = 0x2
3. Generate external EOM
Write EXTPCMD 0x01
4. Disable external processing
Write x_CHCFG.EXTPROC = 0x0
5. Unforce Symbol Sync
Write 0xED 0x00
Wait for Symbol Sync
(on PPx)
(if no ISR impl.)
Symbol Sync = 1
Interrupt
Wait for interrupt
Wait for SW Timeout
Symbol Sync = 0
EOM generation
- must be faster than
RUNIN duration
SW Timeout
Figure 78
Parallel Wake-up Search
Notes:
- Symbol Sync can be activated on any PPx port
PP0: Write 0xF4 0x07 & Write PPCFG0 0x0E
PP1: Write 0xF4 0x70 & Write PPCFG0 0xE0
PP2: Write 0xF5 0x01 & Write PPCFG1 0x0E
PP3: Write 0xF5 0x10 & Write PPCFG1 0xE0
- Symbol Sync monitoring necessary only in run mode between frames and WU pattern
or till software timeout generated
Data Sheet
110
V1.0, 2010-02-19
TDA5235
Functional Description
- generation of external EOM will reinitialize also the TOTIM timers
- external EOM generation period should be smaller than the RUNIN length
(7 chips RUNIN = ~62 us @ 112 kchip/s , 5 SPI write commands = ~ 60 us @ 2 Mbit)
- minimal Symbol Sync active period = TVWIN, minimal Symbol Sync inactive period =
RUNIN
For protocols where no ASK/FSK switching is required between the Wake-up and
payload frame, the Wake-up and TSI pattern can share the same bits (e.g. Wake-up
pattern = ..00000, TSI = 000001, all bits Manchester encoded). This function can be
activated by the INITFRCS bit, so then there is no reset of the framer compare shift
register after a Wake-up event, which can shorten the required processing time.
Data Sheet
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Functional Description
SPMIP
Timer-Status
Timer-Status
SPM
Active-Idle Period Timer
(5 / 8 Bit)
Timer-Control
fOnOff
Receiver-Enable
Self-Polling-Mode (SPM)
FSM
No WU
SPMC
Polling Mode
Figure 79
SPMAP
SPMOFFT1
SPMOFFT0
SPM
On-Off-Timer
(14 Bit)
fRT
Timer-Control
SPM
Reference-Timer
(8 Bit)
Timer-Control
f sys / 64
SPMONTx1
SPMONTx0
Polling Timer Unit
SPMRT
2.6.2
to
Master-Control-Unit
Polling Timer Unit
The Polling Timer Unit consists of a Counter Stage and a Control FSM (Finite State
Machine).
The Counter Stage is divided into three sub-modules.
The Reference Timer is used to divide the state machine clock (fsys/64) into the slower
clock required for the SPM timers.
The On-Off Timer and the Active Idle Period Timer are used to generate the polling
signal. The entire unit is controlled by the SPM FSM.
The TDA5235 is able to handle up to two different sets of configurations automatically.
Data Sheet
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Functional Description
2.6.2.1
Self Polling Modes
Four polling modes are available to fit the polling behavior to the expected wake-up
patterns and to optimize power consumption in Self Polling Mode.
The following 4 Polling Modes are available and can be configured via 2 bits in the
configuration register SPMC:
•
•
•
•
Constant On-Off (COO)
Fast Fall Back to SLEEP (FFB)
Mixed Mode (MM)
Permanent Wake-Up Search (PWUS)
A detected wake-up data sequence or an actual value for RSSI or Signal Recognition (a
combination of Signal Detector and Noise Detector, see Chapter 2.4.8.1) exceeding a
certain adjustable threshold forces the TDA5235 into Run Mode Self Polling.
In all modes the timing resolution is defined by the Reference Timer, which scales the
incoming frequency (fsys/64) corresponding to the value, which is defined in the Self
Polling Mode Reference Timer (SPMRT) register. Changing values of SPMRT helps to
fit the final On-Off timing to the calculated ideal timing.
2.6.2.2
Constant On-Off Time (COO)
In this mode there is a constant On and a constant Off time. Therefore also the resulting
master period time is constant. The On and Off time are set in the SPMONTA0,
SPMONTA1, SPMONTB0, SPMONTB1, SPMOFFT0 and SPMOFFT1 registers. The
On time configuration is done separately for Configuration A and B.
When Single-Configuration is selected then only Configuration A is used. MultiConfiguration Mode allows reception of up to 2 different transmit sources. The diagram
below shows possible scenarios.
All receive modes described in Chapter 2.5.1.2 Data Interface can be used.
Data Sheet
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Functional Description
Single Config
run mode
RX polling
sleep mode
A
TAON
TMasterPeriod = TAON + TOFF
TOFF
TMasterPeriod
Multi Config
run mode
RX polling
sleep mode
A
B
TAON TBON
TMasterPeriod = TAON + TBON + T OFF
TOFF
TMasterPeriod
Figure 80
Constant On-Off Time
Calculation of the On time:
The On time must be long enough to ensure proper detection of a specified wake-up
criterion. Therefore the On time depends on the wake-up pattern, and the wake-up
criterion. It has to include transmitter data rate tolerances.
A widely used wake-up pattern is a sequence of equal Bi-phase encoded bits or a certain
Bi-phase encoded bit pattern.
TON also must include the relevant start-up times. In case of the first configuration after
TOFF, this is the Receiver Start-Up Time. In case of the following Configuration B (RF
Receiver is already on, there is only a change of the configuration), e.g. if Configuration
B is used, this is the Configuration Change Latency Time. In addition, it has to be
considered that some data bits are required for synchronization and internal latency, see
Chapter 2.4.8.8 RUNIN, Synchronization Search Time and Inter-Frame Time.
There are other wake-up patterns in use as well, which have several (up to 10 and more)
short wake-up sequences (a few byte each) that are separated by a certain pause (again
a few byte each). In this case the On time has to be set, so that a possible wake-up can
be found within two wake-up sequences including the pause in-between.
Calculation of the Off time:
The longer the Off time, the lower the average power consumption in Self Polling Mode.
On the other hand, the Off time has to be short enough that no transmitted wake-up
Data Sheet
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TDA5235
Functional Description
pattern is missed. Therefore the Off time depends mainly on the duration of the expected
wake-up pattern.
For basic timing of WU on RSSI in COO mode, please see Figure 81.
RF signal
e.g . ASK
t
RX ON
SLEEP
t
t WULOT t WULOT
t Startup
1
t WULOT t WULOT_part
n-1
2
npartially
last observation time
window is forced to end by
end of t ON
latest decision here !
tON
Figure 81
COO Polling in WU on RSSI Mode
Always check at the end of the current observation time window, if there is a WU (WakeUp) event or NOT. This means, in algorithmic description (see also Figure 10,
Chapter 2.4.7 RSSI Peak Detector and Chapter 2.4.8.5 Wake-Up Generator):
if (RSSIPWU_value > x_WURSSITH1) and (RSSIPWU_value > x_WURSSIBH1)
then WU
else NOT
Here, ‘NOT‘ means to keep on evaluating and move on to the next observation time
window, also keep on peak value tracking of RSSIPWU signal. Keep on walking through
the observation time windows until there is a WU event from the algorithm above or
finally decide at the end of the On time with the following algorithm:
if (RSSIPWU_value > x_WURSSITH1) and (RSSIPWU_value < x_WURSSIBL1 or
RSSIPWU_value > x_WURSSIBH1)
then WU
else NOT
If there is a WU event at the end of an observation time window while walking through
the observation time windows, freeze/hold this decision/peak value in register RSSIPWU
for optional read out and switch to run mode self polling.
Instead of the single RSSI criterion also the Signal Recognition criterion can be
activated.
Data Sheet
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Functional Description
Combined Level and Data criterion in COO mode
On using the Wake-Up on Data criterion in COO mode, the RSSI criterion (including the
RSSI blocking window) can be applied additionally by setting the bit
x_WUC.UFFBLCOO. This means that a Wake-Up interrupt will not be generated, when
a blocking RSSI level (e.g. an interfering signal) is detected even when the Data criterion
is fulfilled.
The behavior of the additional RSSI criterion is similar to the behavior in Ultrafast Fall
Back Mode.
After the level observation time the receiver checks, if the RSSI level is within a valid
range. If RSSI is within a valid range, the state machine will go on to check the Data
criterion. If the RSSI is within a forbidden range, a new level observation time is started
(Note that no parts of the Wake-Up pattern are lost in this case, when the RSSI criterion
succeeds within the following observation time).
This will be done as long as the RSSI value is within a forbidden range and the On time
is not elapsed.
If the receiver loses synchronization within the search for the Data criterion (e.g. pattern
detection), the WU unit will be initialized and checks again for the RSSI criterion.
Instead of the additional RSSI criterion also Signal Recognition criterion can be applied.
When the Signal Recognition threshold (x_WURSSIBH1) is not exceeded at
Observation Time, the Wake-Up on Level FSM (finite state machine) and Wake-Up on
Data FSM are initialized.
If the threshold is exceeded, then the Wake-Up on Level FSM enters the READY state
and has no further impact on Wake-up search until the Wake-up unit is initialized again.
When afterwards a Data Criterion is found to be OK (e.g. pattern matches, number of
equal bits or random bits is reached), the Wake-up search is completed positively.
When a Data Criterion is found to be not OK, the Wake-up search is terminated
independent of the state of the Wake-Up on Level FSM. Therefore both FSMs are
initialized.
Data Sheet
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Functional Description
2.6.2.3
Fast Fall Back to SLEEP (FFB)
This mode is used to switch off the receiver, if there is no RF signal, as quickly as
possible to reduce power consumption.
During the search for wake-up data, there is a check for a bit stream, to which the system
can be synchronized. If there is no synchronization to a bit stream within the so-called
Sync Search Time Out (SYSRCTO), the wake-up search for this channel is stopped. If
synchronization to a bit stream is possible (and not lost again), the TDA5235 waits if the
wake-up criterion is fulfilled. If the wake-up criterion is not fulfilled (in worst case, if the
last bit of an expected wake-up data pattern is wrong), the wake-up procedure for this
configuration is stopped, and the TDA5235 tries to synchronize on the next
configuration, or falls back to sleep. That means that the effective search time and,
consequently, the receiver active time is significantly shorter, and power consumption is
reduced, when no input signal is present. Calculation of Sync Search Time Out can be
found in Chapter 2.4.8.8 RUNIN, Synchronization Search Time and Inter-Frame
Time.
The needed time for detecting that no relevant transmission took place can be further
reduced by using Ultrafast Fall Back to SLEEP (UFFB). When there was no Wake-up on
Level criterion fulfilled in UFFB Mode during the Observation Time (TWULOT, see
Chapter 2.4.8.5), then the system goes back to SLEEP (or to next config). This can
further reduce the receiver active time, when no data is available. When Wake-up on
Level criterion was fulfilled, then the system proceeds with normal FFB functionality
(SYSRCTO, optional Wake-up data criterion).
Note: UFFB and FFB start working at the same time!
Ultrafast Fall Back to SLEEP is working, when a Wake-up on Data criterion is selected,
the UFFBLCOO bit is enabled and FFB or PWUS mode is selected. The UFFB level
criterion can be selected in the x_WUC register.
RF signal
e.g. ASK
t
RX ON
UFFB
FFB
FFB
SLEEP
t
t WULOT
t Startup
t SYSRCTO
tWU-data-pattern
tON
Figure 82
Ultrafast Fall Back to SLEEP
Data Sheet
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Functional Description
At the end of the observation time the RSSI peak tracking value of RSSIPWU signal is
compared to the 3 thresholds. Then the decision is made. The algorithmic description is
as follows (see also Figure 10, Chapter 2.4.7 RSSI Peak Detector and
Chapter 2.4.8.5 Wake-Up Generator):
if (RSSIPWU_value > x_WURSSITH1) and (RSSIPWU_value < x_WURSSIBL1 or
RSSIPWU_value > x_WURSSIBH1)
then WU
else NOT
Instead of the RSSI criterion also Signal Recognition criterion can be applied. When the
Signal Recognition threshold (x_WURSSIBH1) is not exceeded at Observation Time,
then the system goes back to SLEEP or the Wake-Up on Level FSM (finite state
machine) is initialized and a Wake-up search is performed on the next specified
configuration.
WULCUFFB
0
1
RSSI
&
UFFB criterion
4
WU on Level Criterion
Signal
Recognition
5
Sync
3
Random Bits
1
Equal Bits
2
Pattern
0
WU criterion
WU on Data Criterion
Wake-up
Generation
FSM
WUCRT
WUCRT (2)
WUCRT (1)
WUCRT (0)
&
&
UFFBLCOO
FFB is selected
Figure 83
Data Sheet
UFFB activation
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Functional Description
The On and Off time setting is different from the Constant On-Off Time Mode. The entire
On time is defined in the SPMONTA0 and SPMONTA1 registers. Regardless of the
numbers of Configurations, the On time is defined with the Configuration A On-Timer.
The deactivation of the receiver can happen at different times, but this event does not
influence the timer stage, because the On time is still the same. So the master period is
constant. The following scenarios are the same as before, but with Fast Fall Back to
SLEEP.
Only the following receive modes (see Chapter 2.5.1.2 Data Interface) can be used:
•
•
•
Packet Oriented FIFO Mode (POF)
Packet Oriented Transparent Payload Mode (POTP)
Transparent Mode - Chip Data and Strobe (TMCDS)
Single Config
run mode
RX polling A
sleep mode
TAON
TOFF
TMasterPeriod = TAON + TOFF
TMasterPeriod
Multi Config
run mode
RX polling A
TMasterPeriod = TAON + TOFF
B
sleep mode
TAON
TOFF
TMasterPeriod
Figure 84
Fast Fall Back to SLEEP
Calculation of the On time:
The On time, which is now a sum for all of the configurations used, must include enough
time to ensure proper detection of the specified wake-up pattern on all configurations. To
cover the worst case scenario, the maximum time is required on all configurations as in
Constant On-Off.
TON must also include the relevant start-up times. In case of the first configuration after
TOFF, this is the Receiver Start-Up Time. In case of the following Configuration B (RF
Receiver is already on, there is only a change of the configuration), e.g. if Configuration
B is used, this is the Configuration Change Latency Time.
Data Sheet
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Functional Description
In addition, it has to be considered that some data bits are required for synchronization
and internal latency (see Chapter 2.4.8.8 RUNIN, Synchronization Search Time and
Inter-Frame Time).
Calculation of the Off time:
The same general rules apply as for Constant On-Off Time. The Off time has to be short
enough that no wake-up pattern reception is missed.
2.6.2.4
Mixed Mode (MM, Const On-Off & Fast Fall Back to SLEEP)
This mode combines Constant-On Time and Fast Fall Back to SLEEP within different
configuration sets: Cfg.A: COO; Cfg.B: FFB
TON for Configuration A is always calculated according to Const On-Off rules.
TON for Configuration B is always calculated according to Fast Fall Back to SLEEP rules.
In Mixed Mode the On time of Configuration B is used for the FFB group. Below there
are shown the same scenarios as before, but now for Mixed Mode. Note that SingleConfiguration can be set, but is not recommended in Mixed Mode.
Only the following receive modes (see Chapter 2.5.1.2 Data Interface) can be used:
•
•
•
Packet Oriented FIFO Mode (POF)
Packet Oriented Transparent Payload Mode (POTP)
Transparent Mode - Chip Data and Strobe (TMCDS)
Single Config
run mode
RX polling
sleep mode
A
T AON
TBON
T MasterPeriod = TAON + T BON + TOFF
TOFF
TMasterPeriod
Multi Config
run mode
RX polling
sleep mode
A
TAON
B
TBON
TOFF
T MasterPeriod = TAON + T BON + TOFF
TMasterPeriod
Figure 85
Data Sheet
Mixed Mode
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Functional Description
2.6.2.5
Permanent Wake-Up Search (PWUS)
In this mode the receiver will work in Fast Fall Back Mode, but it will not go back to the
SLEEP state after the last configuration has been searched. Instead, it will start again
from the beginning (Configuration A) until the On time has elapsed. The timing
calculation can be seen in Figure 86. Ultrafast Fall Back to SLEEP functionality can be
used as well.
Only the following receive modes (see Chapter 2.5.1.2 Data Interface) can be used:
•
•
•
Packet Oriented FIFO Mode (POF)
Packet Oriented Transparent Payload Mode (POTP)
Transparent Mode - Chip Data and Strobe (TMCDS)
Single Config
run mode
RX polling A A A A AA
sleep mode
TAO N
TMasterPeriod = TAON + TOFF
TOFF
TMasterPeriod
Multi Config
run mode
RX polling A B A
B
A
TMasterPeriod = TAO N + TOFF
sleep mode
TAON
TOFF
TMasterPeriod
Figure 86
Data Sheet
Permanent Wake-Up Search
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Functional Description
2.6.2.6
Active Idle Period Selection
This mode is used to deactivate some polling periods and can additionally be applied to
each of the above mentioned Polling Modes.
Normally, polling starts again after the TMasterPeriod. With this Active Idle Period selection
some of the polling periods can be deactivated, independent from the Polling Mode. The
active and the idle sequence is set with the SPMAP and the SPMIP registers. The values
of these registers determine the factor M and N.
run mode
RX polling
sleep mode
TOn
TOff
TMasterPeriod
Figure 87
Data Sheet
M*TMasterPeriod
N*TMasterPeriod
Active
Idle
Active Idle Period
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Functional Description
2.7
Definitions
2.7.1
Definition of Bit Rate
The definition for the bit rate in the following description is:
symbols
bitrate = ---------------------s
If a symbol contains n chips (for Manchester n=2; for NRZ n=1) the chip rate is n times
the bit rate:
chiprate = n × bitrate
2.7.2
Definition of Manchester Duty Cycle
Several different definitions for the Manchester duty cycle (MDC) are in place. To avoid
wrong interpretation some of the definitions are given below.
Level-based Definition
MDC = Duration of H-level / Symbol period
bit = 1
1
0
0
1
0
1
1. chip
2. chip
Tb it
Tc hip
MDC < 50%
1
1
0
TH
ΔT
TH
Tb it
Tc hip
Tb it
MDC > 50%
ΔT
Tc hip
Figure 88
TH
TH
Tb it
Tb it
Definition A: Level-based definition
This definition determinates the duty cycle to be the ratio of the high pulse width and the
ideal symbol period. The DC content is constant and directly proportional to the specified
duty cycle.
For ΔT > 0 the high period is longer than the chip-period and for ΔT < 0 the high period
is shorter than the chip-period.
Data Sheet
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Functional Description
Depending on the bit content, the same type of edge (e.g. rising edge) is sometimes
shifted and sometimes not.
With this definition the Manchester duty cycle is calculated to
T chip + ΔT
TH
MDC A = --------- = --------------------------T bit
T bit
Chip-based Definition
MDC = Duration of the first chip / Symbol period
bit = 1
1
0
0
1
0
1
1. chip
2. chip
Tb it
Tc hip
MDC < 50%
1
1
ΔT
0
T1 .ch ip
T1.ch ip
Tb it
Tc hip
Tbit
MDC > 50%
ΔT
Tc hip
Figure 89
T1.ch ip
T1 .chip
Tb it
Tbit
Definition B: Chip-based definition
This definition determinates the duty cycle to be the ratio of the first symbol chip and the
ideal symbol period independently of the information bit content. The DC content
depends on the information bit and it is balanced only if the message itself is balanced.
For ΔT > 0 the first chip-period is longer than the ideal chip-period and for ΔT < 0 the first
chip-period is shorter than the ideal chip-period.
Depending on the bit content, the same type of edge (e.g. rising edge) is sometimes
shifted and sometimes not.
Data Sheet
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TDA5235
Functional Description
With this definition the Manchester duty cycle is calculated to
T chip + ΔT
T 1.chip
MDC B = ---------------- = -------------------------T bit
T bit
Edge delay Definition
MDC = Duration delayed edge / Symbol period
bit = 1
1
0
0
1
1
1. chip
2. chip
Tb it
Tc hip
MDC < 50% Tf = 0
1
Tr
ΔT
1
0
0
Tb it
Tbit
Tb it
TH
Tc hip
Tr
TH
MDC > 50% Tr = 0
1
1
ΔT
Tc hip
Figure 90
0
0
Tf
1
Tf
TH
TH
Tb it
Tbit
Tb it
Definition C: Edge delay definition
This definition determinates the duty cycle to be the ratio of the duration of the delayed
high-chip and the ideal symbol period independently of the information bit content. The
position of the high-chip is determined by the delayed rising edge and/or the delayed
falling edge. For ΔT = Tfall -Trise the Manchester duty cycle is calculated to
T chip + ΔT
T chip + T fall – T rise
T delayedHighchip
MDC C = ---------------------------------------- = -------------------------- = -----------------------------------------------T bit
T bit
T bit
Independent on the bit content, the same type of edge (rising edge and/or falling edge)
is shifted.
Data Sheet
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TDA5235
Functional Description
2.7.3
Definition of Power Level
The reference plane for the power level is the input of the receiver board. This means,
the power level at this point (Pr) is corrected for all offsets in the signal path (e.g.
attenuation of cables, power combiners etc.).
The specification value of power levels in terms of sensitivity is related to the peak power
of Pr in case of On-Off Keying (OOK). This is noted by the unit dBm peak.
Specification value of power levels is related to a Manchester encoded signal with a
Manchester duty cycle of 50% in case of ASK modulation.
An RF signal generator usually displays the level of the unmodulated carrier (Pcarrier).
This has following consequences for the different modulation types:
Table 6
Power Level
Modulation
scheme
Realization with RF signal
generator
Power level specification
value
ASK
AM 100%
Pr = Pcarrier + 6dB
ASK
Pulse modulation (=OOK)
Pr = Pcarrier
FSK
FM with deviation Δf:
f1 = fcarrier - Δf
f2 = fcarrier + Δf
Pr = Pcarrier
For power levels in sensitivity parameters given as average power, this is noted by the
unit dBm. Peak power can be calculated by adding 3 dB to the average power level in
case of ASK modulation and a Manchester duty cycle of 50%.
2.7.4
Figure 91
Data Sheet
Symbols of SFR Registers and Control Bits
CONTROL
Symbolizes unique SFR registers or SFR control bit(s),
which are common for all configuration sets .
CONTROL
Symbolizes SFR registers or SFR control bit (s) with
Multi-Configuration capability (protocol specific).
In case of SFR register, the name starts with A _ or B_,
depending on the selected configuration. This is
generally noted by the prefix „x _“.
SFR Symbols
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Functional Description
2.8
Digital Control (SFR Registers)
2.8.1
SFR Address Paging
An SPI instruction allows a maximum address space of 8 bit. The address space for
supporting more than one configuration set is exceeding this 8 bit address room.
Therefore a page switch is introduced, which can be applied via register SFRPAGE (see
Figure 92).
logical address space
0x000
Configuration A 1) - Page 0
physical address space
0
d
Reserved 2)
0x080
0x0FF
0x100
Common Registers 3)
Reserved
4)
Configuration B 1) - Page 1
Reserved 2)
128 d
255 d
256 d
Reserved 2)
0x180
0x1FF
1)
2), 4)
3)
Figure 92
2.8.2
Configuration A 1) - Page 0
Common Registers 3)
Reserved
4)
Configuration B 1) - Page 1
Reserved 2)
Common Registers 3)
384 d
Reserved 4)
511 d
Configuration dependent register block (2 protocol specific sets)
page switch via SFRPAGE register
Reserved – Forbidden area
Configuration independent registers (common for all configurations )
map (“mirror“ ) to the same physical address space
SFR Address Paging
SFR Register List and Detailed SFR Description
The register list is attached in the Appendix at the end of the document.
Registers for Configuration B are equivalent and not shown in detail.
All registers with prefix “A_” are related to Configuration A. All these registers are also
available for Configuration B having the prefix “B_”.
Data Sheet
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Functional Description
Data Sheet
128
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TDA5235
Applications
3
Applications
RF in
SAW
filter
to µC
SPI Bus
SDI 18
SCK 17
NCS 16
XTAL2 15
11 PP1
12 PP2
13 P_ON
14 XTAL1
SDO 19
T1 20
T2 21
LNA_INN 22
LNA_INP 23
GNDRF 24
PP3 25
RSSI 26
IFMIX_INP
IFMIX_INN
VDD5V
VDDD
VDDD1V5
GNDD
4
5
6
7
8
9
10 PP0
GNDA
TDA5235
3
IFBUF_OUT
2
VDDA 27
IFBUF_IN
1
IF CER
filter
(opt.)
IF_OUT 28
VS
IF CER
filter
(opt.)
VS
to/from µC
Figure 93
Typical Application Schematic
Note: As a good practice in any RF design, shielding around sensitive nodes can
improve the EMC performance of the application.
For achieving the best sensitivity results the following has to be kept in mind. Every
digital system generates certain frequencies (fSRC, e.g. the crystal frequency or a
microcontroller clock) and harmonics (N * fSRC) of it, which can act as interferer (EMI
source) and therefore sensitivity can be reduced.
Data Sheet
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TDA5235
Applications
There are two different cases, which need to be checked for the desired receive
channel(s):
Elimination of in-band EMI mixing with (2*M + 1) * fLO, where M > 0:
A square wave is used as LO (Local Oscillator) for the switching-type mixer, which also
has odd harmonics. When the harmonics of the EMI source are exactly the IF frequency
away from the harmonics of the LO, these spurs will be down-converted to the IF
frequency and act as a co-channel interferer within the receiver’s channel bandwidth
mainly in the 315 MHz band.
In this case a change of the LO injection side (high side or low side injection) can be
applied.
Example (Low Side LO-injection):
Wanted channel fRF = 314.233MHz ==> fLO = 303.533MHz ==> 3*fLO = 910.599MHz
fXOSC = 21.948717 MHz ==> 41 * fXOSC = 899.8974 MHz
Resulting IF = 910.599 - 899.8974 MHz = 10.702 MHz ==> co-channel interferer
within the receiver’s channel bandwidth ==> change LO injection side
Example (High Side LO-injection):
Wanted channel fRF = 314.233 MHz ==> fLO = 324.933 MHz ==> 3*fLO = 974.799 MHz
fXOSC = 21.948717 MHz ==> 44 * fXOSC = 965.744 MHz; 45 * fXOSC = 987.692 MHz
==> both XOSC harmonics are not generating a co-channel interferer at 10.7 MHz
A final sensitivity measurement on the application hardware is recommended.
Elimination of in-band EMI mixing with 1 * fLO:
Assuming a harmonic (N * fSRC) is falling within the BW of the wanted channel and has
an impact on the sensitivity there. In this case another XTAL frequency shall be selected,
e.g. 10 kHz away
| N * fSRC - fLocalOscillator | < BWChannel
Example (e.g. EMI source TDA5235 XOSC):
fXOSC = 21.948717 MHz ==> 42 * fXOSC = 921.846114 MHz
For further details please refer to the corresponding application note or to the latest
configuration software.
3.1
Configuration Example
Please see configuration files supplied with the Explorer tool.
Data Sheet
130
V1.0, 2010-02-19
TDA5235
Reference
4
Reference
4.1
Electrical Data
4.1.1
Absolute Maximum Ratings
Attention: The maximum ratings must not be exceeded under any circumstances,
not even momentarily and individually, as permanent damage to the IC
may result.
Table 7
#
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min.
max.
Unit Remarks
A1
Supply Voltage at VDD5V pin
Vsmax
-0.3
+6
V
A2
Supply Voltage at VDDD,
VDDA pin
Vsmax
-0.3
+4
V
A3
Voltage between VDD5V vs
VDDD and VDD5V vs VDDA
Vsmax
-0.3
+4
V
A4
Junction Temperature
Tj
-40
+125
°C
A5
Storage Temperature
Ts
-40
+150
°C
A6
Thermal resistance junction to
air
Rth(ja)
140
K/W
A7
Total power dissipation at
Tamb = 105°C
Ptot
100
mW
A8
ESD HBM integrity
VHBMRF
-2
2
KV
A9
ESD SDM integrity (All pins
except corner pins)
VSDM
-500
500
V
A10
ESD SDM integrity (All corner
pins)
VSDM
-750
750
V
A11
Latch up
ILU
100
A12
Maximum input voltage at
digital input pins
Vinmax
-0.3
A13
Maximum current into digital
input and output pins
IIOmax
Data Sheet
131
According to ESD
Standard JEDEC EIA /
JESD22-A114-B
mA
AEC-Q100 (transient
current)
VDD5V+0.5
or 6.0
V
whichever is lower
4
mA
V1.0, 2010-02-19
TDA5235
Reference
4.1.2
Operating Range
Table 8
#
Supply Operating Range and Ambient Temperature
Parameter
Symbol
Limit Values
min.
max.
Unit Remarks
B1
Supply voltage at pin VDD5V
VDD5V
4.5
5.5
V
Supply voltage range 1
B2
Supply voltage at pin
VDD5V=VDDD=VDDA
VDD3V3
3.0
3.6
V
Supply voltage range 2
B3
Ambient temperature
Tamb
-40
105
°C
Data Sheet
132
V1.0, 2010-02-19
TDA5235
Reference
4.1.3
AC/DC Characteristics
Supply voltage VDD5V = 4.5 to 5.5 Volt or VDD5V = VDDA = VDDD = 3.0 to 3.6 Volt
Ambient temperature Tamb = -40...105oC; Tamb = +25oC and VDD5V = 5.0V or VDD5V =
VDDA = VDDD = 3.3V for typical parameters, unless otherwise specified.
■ not subject to production test - verified by characterization/design
Table 9
#
AC/DC Characteristics
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
max.
General DC Characteristics
C1.1
Supply Current
in Run Mode and
Double Down
Conversion Mode
IRun, Double
12
15
mA
ASK or FSK mode
Pin < -50dBm
C1.2
Supply Current
in Run Mode and
Single Down
Conversion Mode
IRun, Single
10.5
14
mA
ASK or FSK mode
Pin < -50dBm
C2
Supply current
in Sleep Mode
Isleep_low
crystal oscillator in Low
Power Mode;
clock generator off;
valid for SLEEP Mode
and during SPM Off time
Tamb = 25 °C
40
50
µA
Tamb = 85 °C
60
110
µA
Tamb = 105 °C
90
160
µA
115
350
µA
Tamb = 25 °C
0.8
1.5
µA
Tamb = 85 °C
3.7
13
µA
■
Tamb = 105 °C
9.0
27
µA
■
C3
Supply current
in Sleep Mode
Isleep_high
C4
Supply current
IPDN
in Power Down Mode
■
■
crystal oscillator in High
Precision Mode
Cload = 25 pF;
clock generator off;
valid for SLEEP Mode
and during SPM Off time
C5
Supply current
clock generator
Iclock
23
27
µA
fclockout = 1 kHz
Cload = 10 pF
■
C6
Supply current
IF-Buffer
IBuffer
0.5
0.7
mA
fIF_1 = 10.7 MHz
Rload = 330 Ω
no AC signal
■
Data Sheet
133
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Supply current
during RF-FE startup
/ BPF calibration
IRF-FE-
C8
Brownout detector
threshold
VBOR
2.3
C9
Receiver reset time
tReset
1.0
C10
Receiver startup
time
tRXstartup
455
C11
RF Channel Hop
Latency Time and
Configuration (Hop)
Change Latency
Time (e.g. Cfg A to
Cfg B)
tC_Hop
C12
RF Frontend startup
delay
C13
C7
Unit
Test Conditions
Remarks
max.
■
2.2
2.9
mA
2.45
2.6
V
3.0
ms
Note: No SPI
communication is allowed
before XOSC start-up is
finished and chip reset is
already finished
455
455
µs
Time to startup RF
frontend (comprises time
required to switch crystal
oscillator from Low Power
Mode to High Precision
Mode
■
111
111
111
µs
Time to switch RF PLL
between different RF
Channels (does not
include settling of Data
Clock Recovery) and time
to change Configuration
■
tRFstartdelay
350
350
350
µs
Delay of startup of RF
frontend
■
P_ON pulse width
tP_ON
15
µs
Minimal pulse width to
reset the chip
■
C14
NINT pulse length
tNINT_Pulse
µs
Pulse width of interrupt
■
C15
Accuracy of Temperature Sensor
startup,BPFcal
12
Valid for temperature
range -40°C .. +105°C;
using upper 8 ADC bits
(ADCRESH)
C15.1 uncalibrated
TError, uncal
+/- 23
°C
uncalibrated (3 sigma)
value
■
C15.2 calibrated
TError, cal
+/- 4.5
°C
after 1-point calibration at
room temperature (3
sigma)
■
C16
Accuracy of VDDD readout
C16.1 uncalibrated
Valid for temperature
range -40°C .. +105°C;
using upper 8 ADC bits
(ADCRESH)
VDDD, Error,
+/- 200
mV
uncalibrated (3 sigma)
value
■
+/- 25
mV
after 1-point calibration at
room temperature (3
sigma)
■
uncal
C16.2 calibrated
VDDD, Error,
cal
Data Sheet
134
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
1st Local Oscillator
Low Side LO-injection
and High Side LOinjection allowed;
See also Chapter 3
max.
General RF Characteristics (overall)
D1
Frequency
Range 1
fband_1
300
320
MHz
Range 2
fband_2
425
450
MHz
Range 3
fband_3
863
870
MHz
Range 4
fband_4
902
928
MHz
D2
Frequency step of
Sigma-Delta PLL
fstep
10.5
D3
ASK Demodulation
Data Rate
Rdata
0.5
40
kchip/s
■
Data rate tol.
Rdata_tol
-10
+10
%
■
Modulation index
mASK
50
100
%
ASK
■
mOOK
99
100
%
ON-OFF keying
■
Data Rate
Rdata
0.5
112
kchip/s
including tolerance
■
Data rate tol.
Rdata_tol
-10
+10
%
Frequency deviation
Δf
1
64
kHz
Modulation index
mFSK
1.0
D4
D5
Hz
fstep = fXTAL / 221
■
FSK Demodulation
■
frequency deviation
zero-peak
■
m = frequency_
deviationzero-peak /
maximum_occuring_data
_frequency;
m >= 1.25 is
recommended at small
frequency deviation
■
Decoding schemes
Manchester, differential Manchester,
Bi-phase Mark / Bi-phase Space
D6
Duty cycle ASK
Tchip/
Tdata
35
55
%
see Chapter 2.7.2
Definition C
■
Duty cycle FSK
Tchip/
Tdata
45
55
%
see Chapter 2.7.2
Definition B
■
Overall noise figure
Noise figure
Data Sheet
NF
6
135
8
dB
RF input matched to 50 Ω
@ Tamb = 25 °C
■
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
D7
Unit
Test Conditions
Remarks
max.
BER Sensitivity (FSK)
Manchester coding;
for additional test conditions see right after this
table
BER = 2*10-3
RF input matched to 50 Ω
@ Tamb = 25 °C;
Single-Ended Matching
without SAW;
Insertion loss of input
matching network = 1dB;
Receive Mode = TMMF
(sampled with ideal data
clock);
Double Down Conversion
D7.1
Data Rate 2 kBit/s;
Δf = 10 kHz
SFSK1BER
-119
-116
dBm
2nd IF BW = 50 kHz
PDF = 33 kHz, AFC off,
IFATT=0
■
D7.2
Data Rate 10 kBit/s;
Δf = 14 kHz
SFSK2BER
-114
-111
dBm
2nd IF BW = 50 kHz
PDF = 65 kHz, AFC off,
IFATT=0
■
D7.3
Data Rate 10 kBit/s;
Δf = 50 kHz
SFSK3BER
-112
-109
dBm
2nd IF BW = 125 kHz
PDF = 132 kHz, AFC off,
IFATT=0
■
D7.4
Data Rate 50 kBit/s;
Δf = 50 kHz
SFSK4BER
-105
-102
dBm
2nd IF BW = 300 kHz
PDF = 239 kHz, AFC off,
IFATT=0
■
D7.5
Data Rate 2 kBit/s;
Δf = 10 kHz
SFSK5BER
-110
-107
dBm
2nd IF BW = 300 kHz
■
PDF = 282 kHz, IFATT=7
Note: 3dB sensitivity loss
@ foffset=+/-90kHz @ AFC on
D7.6
Data Rate 10 kBit/s;
Δf = 14 kHz
SFSK6BER
-106
-103
dBm
2nd IF BW = 300 kHz
■
PDF = 282 kHz, IFATT=7
Note: 3dB sensitivity loss
@ foffset=+/-90kHz @ AFC on
D7.7
Data Rate 10 kBit/s;
Δf = 50 kHz
SFSK7BER
-110
-107
dBm
2nd IF BW = 300 kHz
■
PDF = 282 kHz, IFATT=7
Note: 3dB sensitivity loss
@ foffset=+/-90kHz @ AFC on
Data Sheet
136
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
D8
Unit
Test Conditions
Remarks
max.
BER Sensitivity (OOK)
Manchester coding;
for additional test conditions see right after this
table
BER = 2*10-3
RF input matched to 50 Ω
@ Tamb = 25 °C,
peak power level (see
Chapter 2.7.3);
Single-Ended Matching
without SAW;
Insertion loss of input
matching network = 1dB;
Receive Mode = TMMF
(sampled with ideal data
clock);
Double Down Conversion
D8.1
Data Rate 0.5 kBit/s
SASK1BER
-120
-117
dBm
peak
m = 100%, IFATT=0
2nd IF BW = 50 kHz
■
D8.2
Data Rate 2 kBit/s
SASK2BER
-116
-113
dBm
peak
m = 100%, IFATT=0
2nd IF BW = 50 kHz
■
D8.3
Data Rate 10 kBit/s
SASK3BER
-111
-108
dBm
peak
m = 100%, IFATT=0
2nd IF BW = 50 kHz
■
D8.4
Data Rate 16 kBit/s
SASK4BER
-109
-106
dBm
peak
m = 100%, IFATT=0
2nd IF BW = 80 kHz
■
D8.5
Data Rate 0.5 kBit/s
SASK5BER
-115
-112
dBm
peak
m = 100%, IFATT=7
2nd IF BW = 300 kHz;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
■
D8.6
Data Rate 2 kBit/s
SASK6BER
-112
-109
dBm
peak
m = 100%, IFATT=7
2nd IF BW = 300 kHz;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
■
D8.7
Data Rate 10 kBit/s
SASK7BER
-106
-103
dBm
peak
m = 100%, IFATT=7
2nd IF BW = 300 kHz;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
■
D8.8
Data Rate 16 kBit/s
SASK8BER
-104
-101
dBm
peak
m = 100%, IFATT=7
2nd IF BW = 300 kHz;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
■
D9.1
Sensitivity increase
for Single Down
Conversion mode
ΔSSDC
0.5
1
dB
■
D9.2
Double Down
Conversion sensitivity
decrease for higher
blocking performance
(IFATT=0 => IFATT=7)
1
2
dB
■
Data Sheet
ΔSDDC,
0
IFATT7
137
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
D9.3
Single Down Conversion
sensitivity decrease for
higher blocking
performance
(IFATT=4 => IFATT=7)
ΔSSDC,
0.5
Unit
Test Conditions
Remarks
max.
1
dB
■
IFATT7
D10.1 Sensitivity variation
due to temperature
(-40...+105°C)
ΔPin
2
dB
relative to Tamb = 25 °C;
temperature drift of crystal
not considered
■
D10.2 Sensitivity variation
due to frequency
offset 1)
ΔPin
3
dB
AFC inactive;
For Sensitivity Bandwidth
see Table 11
■
D10.3 Sensitivity variation
due to frequency
offset
ΔPin
3
dB
AFC active, slow AFC;
For Sensitivity Bandwidth
see Table 11 and applied
AFCLIMIT
■
D10.4 Sensitivity loss when
AFC active at center
frequency
ΔPin
1
dB
AFC active;
center frequency - no
AFC wander (see
Chapter 2.4.6.3)
■
D11
3rd order intercept
IIP3
PIIP3
-16
-14
dBm
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB;
IFATT = 7;
valid for Single and
Double Down Conversion
Mode
■
D12
1 dB compression
point CP1dB
PCP1dB
-27
-25
dBm
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB;
IFATT = 7;
valid for Single and
Double Down Conversion
Mode
■
D13
1st IF image rejection dimage1
30
40
dB
1st IF = 10.7 MHz
without front end SAW
filter;
valid for Double Down
Conversion Mode
D14
2nd IF image
rejection
30
34
dB
2nd IF = 274 kHz
without 1st IF CER filter;
valid for Single and
Double Down Conversion
Mode
Data Sheet
dimage2
138
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
max.
RF Front End Characteristics
(Unless otherwise noted, all values apply for the specified frequency ranges)
E1
LNA input impedance
E1.1
fRF = 315 MHz
E1.2
E1.3
E1.4
E1.5
E1.6
E1.7
E1.8
fRF = 434MHz
fRF = 868MHz
fRF = 915MHz
fRF = 315 MHz
fRF = 434MHz
fRF = 868MHz
fRF = 915MHz
Rin_p,diff
680
Ω
Cin_p,diff
1.05
pF
Rin_p,diff
570
Ω
■
Cin_p,diff
0.87
pF
■
Rin_p,diff
550
Ω
■
Cin_p,diff
0.63
pF
■
Rin_p,diff
540
Ω
■
Cin_p,diff
0.63
pF
■
Rin_p, SE
500
Ω
Cin_p, SE
1.87
pF
Rin_p, SE
400
Ω
Cin_p, SE
1.63
pF
■
Rin_p, SE
322
Ω
■
Cin_p, SE
1.59
pF
■
Rin_p, SE
312
Ω
■
Cin_p, SE
1.56
pF
■
differential parallel
equivalent input between
LNA_INP and LNA_INN
single-ended parallel
equivalent input between
LNA_INP and GNDRF /
LNA_INN and GNDRF
E2
FE output
impedance
Rout_IF
290
330
380
Ω
fIF = 10.7 MHz
E3
FE voltage
conversion gain
AVFE, max
34
36
38
dB
min. IF attenuation
(IFATT = 0);
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB
Rload_IF = 330 Ω;
tested at 434 MHz
E4
FE voltage
conversion gain
AVFE_7
29
31
33
dB
IF attenuation
(IFATT = 7);
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB
Rload_IF = 330 Ω;
tested at 434 MHz
Data Sheet
139
■
■
■
■
■
■
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
E5
FE voltage
conversion gain
E6
FE voltage
conversion gain step
Symbol
AVFE, min
Limit Values
min. typ.
max.
22
26
24
0.8
Unit
Test Conditions
Remarks
dB
max. IF attenuation
(IFATT = 15);
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB
Rload_IF = 330 Ω;
tested at 434 MHz
dB
12dB / 15 = 0.8dB/step
■
Double Down
Conversion: 16 gain
settings (4 bit)
Single Down Conversion:
7 gain settings
E7
1st Local Oscillator SSB Noise
E7.1
PLL loop Bandwidth
BW
E7.2
fin_R1 = 315MHz
dSSB_LO
E7.3
E7.4
E7.5
fin_R2 = 434MHz
fin_R3 = 868MHz
fin_R4 = 915MHz
dSSB_LO
dSSB_LO
dSSB_LO
closed loop
100
BW and its tolerances
■
150
200
kHz
-81
-76
dBc/Hz @ foffset = 1 kHz
-85
-80
@ foffset = 10 kHz
■
-82
-77
@ foffset = 100 kHz
■
-120
-115
@ foffset = 1 MHz
■
-130
-125
@ foffset => 10 MHz
■
-78
-73
-83
-78
@ foffset = 10 kHz
■
-82
-77
@ foffset = 100 kHz
■
-117
-112
@ foffset = 1 MHz
■
-130
-125
@ foffset => 10 MHz
■
-75
-70
-79
-74
@ foffset = 10 kHz
■
-77
-72
@ foffset = 100 kHz
■
-114
-109
@ foffset = 1 MHz
■
-130
-125
@ foffset => 10 MHz
■
-71
-66
-79
-74
@ foffset = 10 kHz
■
-77
-72
@ foffset = 100 kHz
■
-116
-111
@ foffset = 1 MHz
■
-130
-125
@ foffset => 10 MHz
■
dBc/Hz @ foffset = 1 kHz
dBc/Hz @ foffset = 1 kHz
dBc/Hz @ foffset = 1 kHz
■
■
■
■
E8.1
Spurious emission < 1 GHz
-57
dBm
■
E8.2
Spurious emission > 1 GHz
-47
dBm
■
Data Sheet
140
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
E9
Inband fractional spur
E10
3dB Overall Analog
Frontend Bandwidth
Test Conditions
Remarks
max.
-40
■
dBc
230
BWANA
Unit
kHz
LNA input to Limiter
output, excluding external
CER filter
■
1st IF Buffer Characteristics
F1
Input impedance
Rin_IF
290
330
370
Ω
fIF = 10...12 MHz
■
F2
Output impedance
Rout_IF
290
330
370
Ω
fIF = 10...12 MHz
■
F3
Voltage gain
AVBuffer
3
4
5
dB
fIF = 10...12 MHz
Zsource = 330 Ω
Zload = 330 Ω
F4
Buffer switch
disolation
isolation (CERFSEL)
dB
fIF = 10...12 MHz
see Figure 6
■
Ω
fIF = 10...12 MHz
■
60
2nd IF Mixer, RSSI and Filter Characteristics
G1
Mixer input
impedance
G2
RSSI
G2.1
Dynamic range
(Linearity +/- 2 dB)
Rin_IF
290
330
390
Related to RF input
matched to 50 Ω
DRRSSI
-110
-30
dBm
applies for digital RSSI;
AGC on
■
-115
-60
dBm
applies for analog RSSI
@ 50kHz BPF, AGC off
■
-110
-50
dBm
applies for analog RSSI
@ 300kHz BPF, AGC off
■
G2.2
Linearity
DRLIN
-1
+1
dB
-95 dBm...-35 dBm;
applies for digital RSSI
■
G2.3
Temperature drift
within linear dynamic
range
DRTEMP
-2.5
+1.5
dB
-95 dBm...-35 dBm;
applies for digital RSSI
■
G2.4
Output dynamic
range
VRSSI+
0.8
2.0
V
G2.5
analog RSSI error,
untrimmed
DRSSIana
-4
+2
dB
at RSSI pin
G2.6
analog RSSI slope,
untrimmed
dVRSSI/
dVmix_in
8
12
mV/dB
at RSSI pin;
typical 600 mV/60 dB =
10 mV/dB
G2.7
digital RSSI error,
untrimmed
DRSSIdig_u -4
+2
dB
RSSI register readout
Data Sheet
10
141
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
Unit
Test Conditions
Remarks
min. typ.
max.
+1
dB
RSSI register readout
G2.8
digital RSSI error,
user trimmed via
SFRs RSSISLOPE
and RSSIOFFS
DRSSIdig_t
-1
G2.9
digital RSSI slope,
untrimmed
dVRSSI/
dVmix_in
2
2.5
3
LSB
/dB
RSSI register readout;
typical 600 mV/60 dB =
10 mV/dB,
1mV = 1 LSB (10-bit ADC)
8-bit readout: 4mV=1LSB
G2.10 digital RSSI slope,
user trimmed via
SFRs RSSISLOPE
and RSSIOFFS
dVRSSI/
dVmix_in
2.35
2.5
2.65
LSB
/dB
RSSI register readout;
typical 600 mV/60 dB =
10 mV/dB,
1mV = 1 LSB (10-bit ADC)
8-bit readout: 4mV=1LSB
G2.11 Resistive load at
RSSI pin
RL,RSSImax
100
G2.12 Capacitive load at
RSSI pin
CL,RSSI
■
■
kΩ
■
20
pF
■
288
kHz
G3
2nd IF Filter (3rd order Bandpass Filter)
G3.1
Center frequency
fcenter
G3.2
-3 dB BW
BW-3dB
G3.3
-3 dB BW tolerance
tol_BW-3dB -5
+5
%
For BW = 125, 200, 300
kHz
■
G3.4
-3 dB BW tolerance
tol_BW-3dB -6
+6
%
For BW = 50, 80 kHz
■
Data Sheet
262
274
■
kHz
50
80
125
200
300
142
Asymmetric BPF corners:
f_center=sqrt(flow * fhigh);
Use AFC for more
symmetry
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
max.
Crystal Oscillator Characteristics
H1
Frequency range
fXTAL
H2
Crystal parameters
H2.1
Motional
capacitance
C1
H2.2
Motional resistance
H2.3
MHz
21.948
717
6
10
fF
■
R1
18
80
Ω
■
Shunt capacitance
C0
2
4
pF
■
H2.4
Load capacitance
CLoad
12
H2.5
Initial frequency
tolerance
fXTAL_Tol
-30
H2.6
Frequency trimming
range
ΔfXTAL
-50
H2.7
Trimming step
ΔfX_step
H3
Clock output
fclock_out
frequency at PPx pin
H4
Crystal oscillator
settling time
(switching from Low
Power to High
Precision Mode)
tCOSCsettle
H5
Start up time
tstart_up
Data Sheet
3
pF
nominal value
■
+30
ppm
oscillator untrimmed (trim
capacitor default settings,
usage of recommended
crystal);
not including crystal
tolerances
■
+50
ppm
larger trimming range
possible via SD PLL
4
ppm
see also step size of
SD PLL
5.5M
Hz
10pF load
292
292
µs
0.45
1
ms
1
11
292
143
■
■
crystal type:
NDK NX5032SD;
See also BOM for ext.
load caps;
Note: No SPI
communication is allowed
before XOSC start-up is
finished and chip reset is
already finished
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
max.
Digital Inputs/Outputs Characteristics
I1
High level input
voltage
VIn_High
I2
High level input
leakage current
IIn_High
I3
Low level input
voltage (except
P_ON pin)
VIn_Low
I4
0.7*
VDDD
VDD5V V
+0.1
5
µA
0
0.8
V
Low level input
voltage (at P_ON
pin)
VIn_Low_PON 0
0.5
V
I5
Low level input
leakage current
IIn_Low
-5
I6
High level output
voltage 1
VOut_High1
VDD5V
-0.4
VDD5V V
IOH=-500 µA, static driver
capability;
Normal Pad Mode
(see register PPCFG2
and CMC0)
I7
Low level output
voltage 1
VOut_Low1
0
0.4
IOL=500 µA, static driver
capability;
Normal Pad Mode
(see register PPCFG2
and CMC0)
I8
High level output
voltage 2
VOut_High2
VDD5V
-0.8
VDD5V V
IOH=-4 mA, static driver
capability;
High Power Pad Mode
(see register PPCFG2
and CMC0)
I9
Low level output
voltage 2
VOut_Low2
0
0.8
IOL=4 mA, static driver
capability;
High Power Pad Mode
(see register PPCFG2
and CMC0)
Data Sheet
µA
144
V
V
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
MHz
Note: A high SPI clock
rate during data reception
can reduce sensitivity
max.
Timing SPI-Bus Characteristics
J1
Clock frequency
fclock
2.2
J2
Clock High time
tCLK_H
200
ns
■
J3
Clock Low time
tCLK_L
200
ns
■
J4
Active setup time
tsetup
200
ns
■
J5
Not active setup time tnot_setup
200
ns
■
J6
Active hold time
thold
200
ns
■
J7
Not active hold time
tnot_hold
200
ns
■
J8
Deselect time
tDeselect
200
ns
■
J9
SDI setup time
tSDI_setup
100
ns
■
J10
SDI hold time
tSDI_hold
100
ns
■
J11
Clock low to SDO
valid
tCLK_SDO
145
ns
@ Cload = 80 pF
High Power Pad not
enabled (Normal Mode)
(see register PPCFG2
and CMC0)
J12
Clock low to SDO
valid
tCLK_SDO
40
ns
@ Cload = 10 pF
High Power Pad not
enabled (Normal Mode)
(see register PPCFG2
and CMC0)
J13
SDO rise time
tSDO_r
90
ns
@ Cload = 80 pF
■
J14
SDO fall time
tSDO_f
90
ns
@ Cload = 80 pF
■
J15
SDO rise time
tSDO_r
15
ns
@ Cload = 10 pF
■
J16
SDO fall time
tSDO_f
15
ns
@ Cload = 10 pF
■
J17
SDO disable time
tSDO_disable
25
ns
■
■
1) Please note that the system bandwidth is smaller than the smallest bandwidth in the signal path.
Data Sheet
145
V1.0, 2010-02-19
TDA5235
Reference
Unless explicitly otherwise noted, the following test conditions apply to the given
specification values in Table 10 and items D7 and D8:
* Hardware: TDA5240 Platform Testboard V1.0
* Single-Ended Matching for 315.0 MHz / 433.92 MHz / 868.3 MHz / 915.0 MHz
* RF input matched to 50 Ω; Insertion loss of input matching network = 1dB
* Receive Frequency 315.0 MHz / 433.92 MHz / 868.3 MHz / 915.0 MHz; Lo-Side LO-Injection
* Reference Clock: XTAL=21.948717 MHz
* IF-Gain: Attenuation set to default value (IFATT = 7)
* Double Down Conversion
* 1 IF-Filter: Center=10.7MHz; BW=330kHz; Connected between IF_OUT and IFBUF_IN
* 2nd IF Filter BW: Depending on Data Rate and FSK Deviation
* Received Signal at zero Offset to IF Center Frequency
* RSSI trimmed
* FSK Pre-Demodulation Filter (PDF) BW: Depending on Data Rate and FSK Deviation
* No SPI-traffic during telegram reception, CLK_OUT disabled
* AFC and AGC are OFF, unless otherwise noted
* Specification values are in respect to Manchester-coded Infineon-Reference Pattern 1
(7 Bits '0', 1 Bit ’1', 1 Bits '0', 1 Bit ’1', 1 Bits '0', 1 Bit ’1', PRBS5 (31 Bit), 1 Bit 'M') according to Figure 18
However a Code Violation is not used as EOM criterion
BER sensitivity measurements use Receive Mode TMMF (sampled with ideal data clock)
MER sensitivity measurements use Receive Mode POF
* DRE ... Data Date Error of received telegram vs. adjusted Data Rate
* DC ... Duty Cycle
* MER ... Message Error Rate
[MER = 1 - (number_of_correctly_received_messages / number_of_transmitted messages)]
* FAR ... False Alarm Rate
[FAR = number_of_mistakenly_wake_ups / number_of_periods_searching_for_data_on_channel]
* MMR ... Missed Message Rate
[MMR = number_of_mistakenly_missed_wake_up_patterns /
number_of_periods_with_wake_up_pattern_transmitted_and_searching_for_wake_up_pattern]
* BER ... Bit Error Rate (using a PRBS9 Pseudo-Random Binary Sequence)
[BER = 1 - (number_of_correctly_received_bits / number_of_transmitted bits)]
Data Sheet
146
V1.0, 2010-02-19
TDA5235
Reference
Table 10
#
MER Characteristics (Receive Mode = POF)
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
max.
Characteristics of Digital Data Filter and Data Clock Recovery
Acceptance Criterion is: MER <= 10%. For additional test conditions see right before this table.
Double Down Conversion Mode
%
at DC = 50%
■
55
%
According to Definition B
in Chapter 2.7.2;
including
DRE of -10% to +10%;
Data Rate < 50 kBit/s
■
35
55
%
According to Definition C
in Chapter 2.7.2
including
DRE of -10% to +10%
Data Rate < 10 kBit/s
■
tolManch_DefB
45
55
%
According to Definition B
in Chapter 2.7.2;
including
DRE of -10% to +10%;
Data Rate >= 50 kBit/s
■
tolManch_DefC
35
55
%
According to Definition C
in Chapter 2.7.2
including
DRE of -10% to +10%
Data Rate >= 10 kBit/s
Note:
If BPF_BW / Bitrate < 12,
the selected data rate in
the configuration tool
needs to be set 5%
higher.
■
K1
Db
Data Rate Error of
received Telegram
Sensitivity loss < 1dB
K2
Duty Cycle Error of Manchester coding of received Telegram
K2.1
Sensitivity loss < 1dB
tolManch_DefB
45
K2.2
Sensitivity loss <
3.5dB
tolManch_DefC
K2.3
Sensitivity loss <
1.5dB
K2.4
Sensitivity loss < 4dB
Data Sheet
-10
10
147
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
max.
Sensitivity of Receiver
Acceptance Criterion is: MER <= 10%. For additional test conditions see right before this table.
Double Down Conversion Mode
L1
Sensitivity Limit in ASK (OOK) Mode;
Manchester coding
L1.1
Data Rate 0.5 kBit/s
SASK1
-120
-117
dBm
peak
■
m = 100%
2nd IF BW = 50 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode;
868/915MHz: <=1dB loss
L1.2
Data Rate 2 kBit/s
SASK2
-116
-113
dBm
peak
m = 100%
■
2nd IF BW = 50 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
L1.3
Data Rate 10 kBit/s
SASK3
-111
-108
dBm
peak
m = 100%
■
2nd IF BW = 50 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
L1.4
Data Rate 16 kBit/s
SASK4
-109
-106
dBm
peak
■
m = 100%
2nd IF BW = 80 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode;
868/915MHz: <=1dB loss
L1.5
Data Rate 0.5 kBit/s
SASK5
-115
-112
dBm
peak
m = 100%
2nd IF BW = 300 kHz;
IFATT = 7, CDR = fast;
Data Slicer Bit Mode;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
■
L1.6
Data Rate 2 kBit/s
SASK6
-112
-109
dBm
peak
m = 100%
2nd IF BW = 300 kHz;
IFATT = 7, CDR = fast;
Data Slicer Bit Mode;
868/915MHz: <=1dB loss;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
■
L1.7
Data Rate 10 kBit/s
SASK7
-106
-103
dBm
peak
m = 100%
2nd IF BW = 300 kHz;
IFATT = 7, CDR = fast;
Data Slicer Bit Mode;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
■
Data Sheet
At DC = 50% and
DRE = 0%.
Tamb = 25 °C,
peak power level (see
Chapter 2.7.3)
148
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
SASK8
-104
Unit
Test Conditions
Remarks
dBm
peak
m = 100%
2nd IF BW = 300 kHz;
IFATT = 7, CDR = fast;
Data Slicer Bit Mode;
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
max.
-101
■
L1.8
Data Rate 16 kBit/s
L2
Sensitivity Limit in FSK Mode;
Manchester coding
L2.1
Data Rate 2 kBit/s;
Δf = 10 kHz
SFSK1
-118
-115
dBm
■
2nd IF BW = 50 kHz;
PDF = 33 kHz, AFC off;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
L2.2
Data Rate 10 kBit/s;
Δf = 14 kHz
SFSK2
-113
-110
dBm
2nd IF BW = 50 kHz;
■
PDF = 65 kHz, AFC off;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
L2.3
Data Rate 10 kBit/s;
Δf = 50 kHz
SFSK3
-112
-109
dBm
■
2nd IF BW = 125 kHz;
PDF = 132 kHz, AFC off;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode;
868/915MHz: <=1dB loss
L2.4
Data Rate 50 kBit/s;
Δf = 50 kHz
SFSK4
-106
-103
dBm
2nd IF BW = 300 kHz;
■
PDF = 239 kHz, AFC off;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
L2.5
Data Rate 2 kBit/s;
Δf = 10 kHz
SFSK5
-108
-105
dBm
2nd IF BW = 300 kHz;
PDF = 282 kHz;
IFATT = 7, CDR = fast;
Data Slicer Bit Mode;
868/915MHz: <=1dB loss;
At DC = 50% and
DRE = 0%.
Tamb = 25 °C
■
Note: 3dB sensitivity loss
@ foffset=+/-90kHz @ AFC on
L2.6
Data Rate 10 kBit/s;
Δf = 14 kHz
SFSK6
-107
-104
dBm
2nd IF BW = 300 kHz;
PDF = 282 kHz;
IFATT = 7, CDR = fast;
Data Slicer Bit Mode;
■
Note: 3dB sensitivity loss
@ foffset=+/-90kHz @ AFC on
L2.7
Data Rate 10 kBit/s;
Δf = 50 kHz
SFSK7
-109
-106
dBm
2nd IF BW = 300 kHz;
PDF = 282 kHz;
IFATT = 7, CDR = fast;
Data Slicer Bit Mode;
■
Note: 3dB sensitivity loss
@ foffset=+/-90kHz @ AFC on
Data Sheet
149
V1.0, 2010-02-19
TDA5235
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
max.
Dynamic Range of Receiver
Acceptance Criteria are: MER <= 1E-3, FAR < 1E-5, MMR < 1E-4 (Criterion: 8 Equal Bits), Manchester coding.
For additional test conditions see right before this table.
Double Down Conversion Mode
M1
Dynamic Range in ASK (OOK) Mode, AGC on
M1.1
Data Rate 2 kBit/s
DR2,OOK
-10
-109
dBm
peak
■
m = 100%
2nd IF BW = 50 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
M1.2
Data Rate 10 kBit/s
DR10,OOK
-10
-105
dBm
peak
■
m = 100%
2nd IF BW = 50 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
M1.3
Data Rate 2 kBit/s
DR2,ASK50
-45
-103
dBm
peak
■
m = 50%
2nd IF BW = 50 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
M1.4
Data Rate 10 kBit/s
DR10,ASK50
-60
-99
dBm
peak
■
m = 50%
2nd IF BW = 50 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
M2
Dynamic Range in FSK Mode, AGC on
Data Rate 10 kBit/s & Δf = 50 kHz
M2.1
0% AM Modulation
DR10,AM0
-10
-106
dBm
■
2nd IF BW = 125 kHz
PDF = 132 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
M2.2
90% AM Modulation,
100 Hz
DR10,AM90
-10
-90
dBm
■
2nd IF BW = 125 kHz
PDF = 132 kHz;
IFATT = 0, CDR = normal;
Data Slicer Bit Mode
Data Sheet
At DC = 50% and
DRE = 0%.
Tamb = 25 °C,
peak power level (see
Chapter 2.7.3)
At DC = 50% and
DRE = 0%.
Tamb = 25 °C
150
V1.0, 2010-02-19
TDA5235
Reference
Table 11
Typical Achievable Sensitivity Bandwidth [kHz]
Ceramic Filter BW = 330 kHz
Table is valid for DDC (Double Down Conversion) and SDC (Single Down Conversion)
Valid for AFC=off; For FSK & AFC=on the BW can be increased by 2*AFCLIMIT, where AFCLIMIT < 43 kHz
BPF/PDF
Filter [Hz]
BPF = 300 k
PDF = 282 k
Modulation FSK Deviation
[+/- Hz]
ASK
FSK
-
0.5 k
1k
5k
10 k
15 k
20 k
40 k
50 k
Data Sheet
Sensitivity
Loss
Data Rate [bit/s], Manchester
0.5 k
1k
5
10 k
20 k
50 k
3 dB
230
230
230
230
230
-
6 dB
280
280
280
280
280
-
3 dB
160
150
-
-
-
-
6 dB
230
220
-
-
-
-
3 dB
140
160
-
-
-
-
6 dB
220
230
-
-
-
-
3 dB
120
130
150
140
-
-
6 dB
200
210
220
220
-
-
3 dB
120
120
140
140
150
-
6 dB
180
190
210
210
210
-
3 dB
-
-
130
140
150
-
6 dB
-
-
200
200
210
-
3 dB
110
-
130
130
140
-
6 dB
160
-
190
190
190
-
3 dB
-
-
-
120
-
-
6 dB
-
-
-
160
-
-
3 dB
110
110
110
110
100
100
6 dB
140
140
140
140
140
140
151
V1.0, 2010-02-19
TDA5235
Reference
Table 11
Typical Achievable Sensitivity Bandwidth [kHz]
Ceramic Filter BW = 330 kHz
Table is valid for DDC (Double Down Conversion) and SDC (Single Down Conversion)
Valid for AFC=off; For FSK & AFC=on the BW can be increased by 2*AFCLIMIT, where AFCLIMIT < 43 kHz
BPF/PDF
Filter [Hz]
BPF = 200 k
PDF = 239 k
Modulation FSK Deviation
[+/- Hz]
ASK
FSK
-
0.5 k
1k
5k
10 k
15 k
20 k
40 k
50 k
Data Sheet
Sensitivity
Loss
Data Rate [bit/s], Manchester
0.5 k
1k
5
10 k
20 k
50 k
3 dB
180
180
180
180
180
-
6 dB
220
220
220
220
220
-
3 dB
140
140
-
-
-
-
6 dB
190
190
-
-
-
-
3 dB
130
130
-
-
-
-
6 dB
180
190
-
-
-
-
3 dB
100
120
130
130
-
-
6 dB
160
170
180
180
-
-
3 dB
100
100
120
120
140
-
6 dB
140
150
170
170
170
-
3 dB
-
-
110
110
120
-
6 dB
-
-
150
150
160
-
3 dB
90
-
100
100
110
-
6 dB
130
-
140
150
150
-
3 dB
-
-
-
90
-
-
6 dB
-
-
-
120
-
-
3 dB
-
-
-
-
-
-
6 dB
-
-
-
-
-
-
152
V1.0, 2010-02-19
TDA5235
Reference
Table 11
Typical Achievable Sensitivity Bandwidth [kHz]
Ceramic Filter BW = 330 kHz
Table is valid for DDC (Double Down Conversion) and SDC (Single Down Conversion)
Valid for AFC=off; For FSK & AFC=on the BW can be increased by 2*AFCLIMIT, where AFCLIMIT < 43 kHz
BPF/PDF
Filter [Hz]
BPF = 125 k
PDF = 132 k
Modulation FSK Deviation
[+/- Hz]
ASK
FSK
-
0.5 k
1k
5k
10 k
15 k
20 k
40 k
50 k
Data Sheet
Sensitivity
Loss
Data Rate [bit/s], Manchester
0.5 k
1k
5
10 k
20 k
50 k
3 dB
120
120
120
120
120
-
6 dB
150
150
150
150
150
-
3 dB
100
100
-
-
-
-
6 dB
120
120
-
-
-
-
3 dB
90
100
-
-
-
-
6 dB
120
120
-
-
-
-
3 dB
70
80
80
90
-
-
6 dB
100
110
110
110
-
-
3 dB
70
70
80
80
80
-
6 dB
90
100
100
100
100
-
3 dB
-
-
70
80
80
-
6 dB
-
-
90
90
100
-
3 dB
60
-
70
70
70
-
6 dB
80
-
90
90
90
-
3 dB
-
-
-
-
-
-
6 dB
-
-
-
-
-
-
3 dB
-
-
-
-
-
-
6 dB
-
-
-
-
-
-
153
V1.0, 2010-02-19
TDA5235
Reference
4.2
Figure 94
Data Sheet
Test Circuit - Evaluation Board v1.0
Test Circuit Schematic
154
V1.0, 2010-02-19
TDA5235
Reference
4.3
Test Board Layout, Evaluation Board v1.0
Figure 95
Test Board Layout, Top View
Figure 96
Test Board Layout, Bottom View
Data Sheet
155
V1.0, 2010-02-19
TDA5235
Reference
Figure 97
Data Sheet
Test Board Layout, Component View
156
V1.0, 2010-02-19
TDA5235
Reference
4.4
Bill of Materials
Pos
Part
Value
1
IC1
TDA5235
PG-TSSOP-28
2
C1
3.9 pF
0603
C0G
+/- 0.1 pF
crystal oscillator load
3
C2
3.9 pF
0603
C0G
+/- 0.1 pF
crystal oscillator load
4
C3
100 nF
0603
X7R
+/- 10 %
5
C4
100 nF
0603
X7R
+/- 10 %
6
C5
100 nF /
( 1 µF )
0603
X7R /
X5R
+/- 10 %
7
C6
100 nF
0603
X7R
+/- 10 %
8
C7
1 pF
0603
C0G
+/- 0.1 pF
matching for 315MHz
0.5 pF
0603
C0G
+/- 0.1 pF
matching for 434MHz
open
0603
C0G
1 pF
0603
C0G
open
0603
C0G
matching for 315MHz
open
0603
C0G
matching for 434MHz
2.7 pF
0603
C0G
+/- 0.1 pF
matching for 868MHz
5.1 pF
0603
C0G
+/- 0.1 pF
matching for 915MHz
polarized capacitor
9
C8
Package
Device /
Type
Tolerance
Manufacturer
Remark/Options
(RF+supply variant)
Infineon
3.3V /
( 5 V environment)
matching for 868MHz
+/- 0.1 pF
matching for 915MHz
10
C9
1 µF
SMC-A
Tantal
+/- 10%
11
C10
100 nF
0603
X7R
+/- 10%
12
C11
10 nF
0603
X7R
+/- 10%
13
L1
68 nH
0603
+/- 2%
matching for 315MHz
39 nH
0603
+/- 2%
matching for 434MHz
22 nH
0603
+/- 2%
matching for 868MHz
15 nH
0603
+/- 2%
matching for 915MHz
14
R1
10 Ohm /
(open)
0603
+/- 5%
3.3 V /
( 5 V environment)
15
R2
4.7 Ohm /
(open)
0603
+/- 5%
3.3 V /
( 5 V environment)
16
R3
4.7 Ohm /
(22 Ohm)
0603
+/- 5%
3.3 V /
( 5 V environment)
17
R4
0 Ohm
0603
18
IF1
SFECF10
M7EA00
19
Q1
21.948717 NX5032SD
MHz
Data Sheet
C0=1.7 pF
C1=7 fF
CL=12 pF
157
Murata
BW = 330 kHz
NDK (Frischer
Electronic),
EXS00ACS01580
SMD crystal
V1.0, 2010-02-19
TDA5235
Reference
Pos
Part
Value
Package
Device /
Type
Tolerance
Manufacturer
Remark/Options
(RF+supply variant)
Interface / optional
20
IC2
AT24C32 SOIC8
C-SH-B or
AT24C512
EEPROM for board
detection
21
C12
open
0603
X7R
+/- 10%
22
C13
100 nF
0603
X7R
+/- 10%
23
C14
1 µF
SMC-A
Tantal
+/- 10%
polarized capacitor
24
C15
10 nF
0603
X7R
+/- 10%
filter network on
supply line
25
C16
10 nF
0603
X7R
+/- 10%
filter network on
supply line
26
L2
0 Ohm
0603
no filter network on
supply line
27
R5
open
0603
RSSI measurement
low pass
28
R6
1 kOhm
0603
29
R7
0 Ohm
0603
30
D1
LED
31
IF2
open
32
X1
SMA
socket
RF input
33
X2
3 pins
Board supply
34
X3
2 pins
Chip supply current
(jumper closed)
35
X4
50 pins
36
X5
2 pins
RSSI measuring
point
37
X6
12 pins
Interface line
measuring point
38
X7
4 pins
GND
39
X8
4 pins
GND
40
Jumper 1
2 pins
Jumper for X3
41
Jumper 2
2 pins
Jumper for X2 Supply by interface
RSSI measurement
low pass
write protection for
EEPROM
LS M676P251-1
status indication LED
Murata
SIB-QTS-02501-X-D-RA
Samtec
2nd IF filter is
optional
Connector to
PC/µC/Interface
Board material 1.5mm FR4 with 35µm copper on both sides
Data Sheet
158
V1.0, 2010-02-19
TDA5235
Package Outlines
Package Outlines
0˚...8˚
B
-0.035
1.2 MAX.
1 +0.05
-0.2
0.1 ±0.05
4.4 ±0.1 1)
0.125 +0.075
5
0.65
0.22 +0.08
-0.03
C
2)
0.1
0.6 +0.15
-0.1
0.1 M A C 28x
28
6.4
15
1
0.2 B 28x
14
9.7 ±0.1 1)
A
Index Marking
1)
2)
Does not include plastic or metal protrusion of 0.15 max. per side
Does not include dambar protrusion
Figure 98
PG-TSSOP-28 Package Outline (green package)
Table 12
Order Information
Type
TDA5235
Ordering Code
Package
SP000507674
PG-TSSOP-28
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”:http://www.infineon.com/products
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
159
V1.0, 2010-02-19
TDA5235
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Data Sheet
Page
Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
AGC Settings 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AGC Settings 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SPI Bus Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Power Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Supply Operating Range and Ambient Temperature . . . . . . . . . . . . . 132
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
MER Characteristics (Receive Mode = POF) . . . . . . . . . . . . . . . . . . 147
Typical Achievable Sensitivity Bandwidth [kHz] . . . . . . . . . . . . . . . . . 151
Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
160
V1.0, 2010-02-19
TDA5235
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Data Sheet
Page
Pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TDA5235 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Block Diagram RF Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Single Down Conversion (SDC, no external filters required) . . . . . . . . 20
Double Down Conversion (DDC) with one external filter . . . . . . . . . . . 21
Double Down Conversion (DDC) with two external filters . . . . . . . . . . 21
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
External Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Synthesizer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Functional Block Diagram ASK/FSK Demodulator . . . . . . . . . . . . . . . 27
AFC Loop Filter (I-PI Filtering and Mapping) . . . . . . . . . . . . . . . . . . . . 29
Analog RSSI output curve with AGC action ON (blue) vs. OFF (black) 30
Peak Detector Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Peak Detector Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Functional Block Diagram Digital Baseband Receiver. . . . . . . . . . . . . 38
Signal Detector Threshold Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Coding Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Manchester Symbols including Code Violations . . . . . . . . . . . . . . . . . 42
Clock Recovery (ADPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
RUNIN Generation Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Definition of Tolerance Windows for the CDR . . . . . . . . . . . . . . . . . . . 46
Data Rate Acceptance Limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Wake-Up Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
RSSI Blocking Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Wake-Up Data Criteria Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Frame Synchronization Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
16-Bit TSI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8-Bit Parallel TSI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8-Bit Extended TSI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8-Bit Gap TSI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Clock Recovery Gap Resynchronization Mode TSIGRSYN = 1 . . . . . 60
Clock Recovery Gap Resynchronization Mode TSIGRSYN = 0 . . . . . 61
TSIGap TSIB Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
TVWIN and TSIGAP dependency example . . . . . . . . . . . . . . . . . . . . . 62
4-Byte Message ID Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2-Byte Message ID Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
MID Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Structure of Payload Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Data Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.3 Volts and 5 Volts Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Supply Current Ramp Up/Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
161
V1.0, 2010-02-19
TDA5235
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
Figure 69
Figure 70
Figure 71
Figure 72
Figure 73
Figure 74
Figure 75
Figure 76
Figure 77
Figure 78
Figure 79
Figure 80
Figure 81
Figure 82
Figure 83
Figure 84
Figure 85
Data Sheet
Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Logical and electrical System Interfaces of the TDA5235 . . . . . . . . . . 75
Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Data interface for the Packet Oriented FIFO Mode . . . . . . . . . . . . . . . 77
Data interface for the Packet Oriented Transparent Payload Mode . . 77
Timing of the Packet Oriented Transparent Payload Mode . . . . . . . . . 78
Data interface for the Transparent Mode - Chip Data and Strobe . . . . 78
Timing of the Transparent Mode - Chip Data and Strobe . . . . . . . . . . 79
Data interface for the Transparent Modes TMMF / TMRDS . . . . . . . . 79
External Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
FIFO Lock Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SPI Data FIFO Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Interrupt Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Interrupt Generation Waveform (Example for Configuration A+B). . . . 87
ISx Readout Set Clear Collision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Burst Read Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Burst Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SPI Checksum Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Read FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Serial Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Chip Serial Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Global State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Run Mode Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
HOLD State Behavior (INITPLLHOLD disabled) . . . . . . . . . . . . . . . . . 99
HOLD State Behavior (INITPLLHOLD enabled) . . . . . . . . . . . . . . . . . 99
SPM - TX-RX Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Wake-up Search with Configuration A . . . . . . . . . . . . . . . . . . . . . . . . 102
Wake-up Search with Configuration B . . . . . . . . . . . . . . . . . . . . . . . . 103
TOTIM Behavior without Presence of Interferer . . . . . . . . . . . . . . . . 105
TOTIM Behavior in Presence of Interferer . . . . . . . . . . . . . . . . . . . . . 106
Run Mode Self Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Parallel Wake-up Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Polling Timer Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Constant On-Off Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
COO Polling in WU on RSSI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Ultrafast Fall Back to SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
UFFB activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Fast Fall Back to SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Mixed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
162
V1.0, 2010-02-19
TDA5235
Figure 86
Figure 87
Figure 88
Figure 89
Figure 90
Figure 91
Figure 92
Figure 93
Figure 94
Figure 95
Figure 96
Figure 97
Figure 98
Data Sheet
Permanent Wake-Up Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active Idle Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition A: Level-based definition . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition B: Chip-based definition . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition C: Edge delay definition . . . . . . . . . . . . . . . . . . . . . . . . . . .
SFR Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SFR Address Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Circuit Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Board Layout, Top View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Board Layout, Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Board Layout, Component View . . . . . . . . . . . . . . . . . . . . . . . .
PG-TSSOP-28 Package Outline (green package). . . . . . . . . . . . . . .
163
121
122
123
124
125
126
127
129
154
155
155
156
159
V1.0, 2010-02-19
TDA5235
Data Sheet
164
V1.0, 2010-02-19
TDA5235
Appendix - Registers Chapter
Data Sheet
165
V1.0, 2010-02-19
TDA5235
Appendix
Register Overview
Appendix - Registers Chapter
Register Overview
Table 1
Register Overview
Register Short Name
Register Long Name
Offset Address
Page Number
Appendix - Registers Chapter, Register Description
A_MID0
Message ID Register 0
000H
179
A_MID1
Message ID Register 1
001H
179
A_MID2
Message ID Register 2
002H
179
A_MID3
Message ID Register 3
003H
180
A_MID4
Message ID Register 4
004H
180
A_MID5
Message ID Register 5
005H
180
A_MID6
Message ID Register 6
006H
181
A_MID7
Message ID Register 7
007H
181
A_MID8
Message ID Register 8
008H
182
A_MID9
Message ID Register 9
009H
182
A_MID10
Message ID Register 10
00AH
182
A_MID11
Message ID Register 11
00BH
183
A_MID12
Message ID Register 12
00CH
183
A_MID13
Message ID Register 13
00DH
183
A_MID14
Message ID Register 14
00EH
184
A_MID15
Message ID Register 15
00FH
184
A_MID16
Message ID Register 16
010H
184
A_MID17
Message ID Register 17
011H
185
A_MID18
Message ID Register 18
012H
185
A_MID19
Message ID Register 19
013H
186
A_MIDC0
Message ID Control Register 0
014H
186
A_MIDC1
Message ID Control Register 1
015H
186
A_IF1
IF1 Register
016H
187
A_WUC
Wake-Up Control Register
017H
188
A_WUPAT0
Wake-Up Pattern Register 0
018H
189
A_WUPAT1
Wake-Up Pattern Register 1
019H
190
A_WUBCNT
Wake-Up Bit or Chip Count Register
01AH
190
A_WURSSITH1
RSSI Wake-Up Threshold for Channel 1 Register 01BH
191
A_WURSSIBL1
RSSI Wake-Up Blocking Level Low Channel 1
Register
01CH
191
A_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
01DH
192
A_SIGDETSAT
Signal Detector Saturation Threshold Register
024H
192
Data Sheet
166
V1.0, 2010-02-19
TDA5235
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
Page Number
A_WULOT
Wake-up on Level Observation Time Register
025H
193
A_SYSRCTO
Synchronization Search Time-Out Register
026H
193
A_TOTIM_SYNC
SYNC Timeout Timer Register
027H
194
A_TOTIM_TSI
TSI Timeout Timer Register
028H
194
A_TOTIM_EOM
EOM Timeout Timer Register
029H
195
A_AFCLIMIT
AFC Limit Configuration Register
02AH
195
A_AFCAGCD
AFC/AGC Freeze Delay Register
02BH
196
A_AFCSFCFG
AFC Start/Freeze Configuration Register
02CH
196
A_AFCK1CFG0
AFC Integrator 1 Gain Register 0
02DH
197
A_AFCK1CFG1
AFC Integrator 1 Gain Register 1
02EH
198
A_AFCK2CFG0
AFC Integrator 2 Gain Register 0
02FH
198
A_AFCK2CFG1
AFC Integrator 2 Gain Register 1
030H
198
A_PMFUDSF
Peak Memory Filter Up-Down Factor Register
031H
199
A_AGCSFCFG
AGC Start/Freeze Configuration Register
032H
200
A_AGCCFG0
AGC Configuration Register 0
033H
201
A_AGCCFG1
AGC Configuration Register 1
034H
202
A_AGCTHR
AGC Threshold Register
035H
202
A_DIGRXC
Digital Receiver Configuration Register
036H
202
A_PKBITPOS
RSSI Peak Detector Bit Position Register
037H
204
A_ISUPFCSEL
Image Supression Fc Selection Register
038H
204
A_PDECF
Pre Decimation Factor Register
039H
205
A_PDECSCFSK
Pre Decimation Scaling Register FSK Mode
03AH
205
A_PDECSCASK
Pre Decimation Scaling Register ASK Mode
03BH
205
A_MFC
Matched Filter Control Register
03CH
206
A_SRC
Sampe Rate Converter NCO Tune
03DH
206
A_EXTSLC
Externel Data Slicer Configuration
03EH
207
A_SIGDET0
Signal Detector Threshold Level Register - Run
Mode
03FH
207
A_SIGDET1
Signal Detector Threshold Level Register Wakeup
040H
208
A_SIGDETLO
Signal Detector Threshold Low Level Register
041H
208
A_SIGDETSEL
Signal Detector Range Selection Register
042H
209
A_SIGDETCFG
Signal Detector Configuration Register
043H
210
A_NDTHRES
FSK Noise Detector Threshold Register
044H
210
A_NDCONFIG
FSK Noise Detector Configuration Register
045H
211
A_CDRP
Clock and Data Recovery P Configuration
Register
046H
211
A_CDRI
Clock and Data Recovery Configuration Register
047H
212
Data Sheet
167
V1.0, 2010-02-19
TDA5235
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
Page Number
A_CDRRI
Clock and Data Recovery RUNIN Configuration
Register
048H
214
A_CDRTOLC
CDR DC Chip Tolerance Register
049H
214
A_CDRTOLB
CDR DC Bit Tolerance Register
04AH
215
A_TVWIN
Timing Violation Window Register
04BH
216
A_SLCCFG
Slicer Configuration Register
04CH
216
A_TSIMODE
TSI Detection Mode Register
04DH
217
A_TSILENA
TSI Length Register A
04EH
217
A_TSILENB
TSI Length Register B
04FH
218
A_TSIGAP
TSI Gap Length Register
050H
218
A_TSIPTA0
TSI Pattern Data Reference A Register 0
051H
219
A_TSIPTA1
TSI Pattern Data Reference A Register 1
052H
219
A_TSIPTB0
TSI Pattern Data Reference B Register 0
053H
220
A_TSIPTB1
TSI Pattern Data Reference B Register 1
054H
220
A_EOMC
End Of Message Control Register
055H
220
A_EOMDLEN
EOM Data Length Limit Register
056H
221
A_EOMDLENP
EOM Data Length Limit Parallel Mode Register
057H
222
A_CHCFG
Channel Configuration Register
058H
222
A_PLLINTC1
PLL MMD Integer Value Register Channel 1
059H
223
A_PLLFRAC0C1
PLL Fractional Division Ratio Register 0 Channel 1 05AH
224
A_PLLFRAC1C1
PLL Fractional Division Ratio Register 1 Channel 1 05BH
224
A_PLLFRAC2C1
PLL Fractional Division Ratio Register 2 Channel 1 05CH
225
SFRPAGE
Special Function Register Page Register
080H
225
PPCFG0
PP0 and PP1 Configuration Register
081H
226
PPCFG1
PP2 and PP3 Configuration Register
082H
227
PPCFG2
PPx Port Configuration Register
083H
228
RXRUNCFG0
RX RUN Configuration Register 0
084H
229
RXRUNCFG1
RX RUN Configuration Register 1
085H
230
CLKOUT0
Clock Divider Register 0
086H
231
CLKOUT1
Clock Divider Register 1
087H
231
CLKOUT2
Clock Divider Register 2
088H
232
RFC
RF Control Register
089H
232
BPFCALCFG0
BPF Calibration Configuration Register 0
08AH
233
BPFCALCFG1
BPF Calibration Configuration Register 1
08BH
234
XTALCAL0
XTAL Coarse Calibration Register
08CH
234
XTALCAL1
XTAL Fine Calibration Register
08DH
235
RSSIMONC
RSSI Monitor Configuration Register
08EH
235
ADCINSEL
ADC Input Selection Register
08FH
236
RSSIOFFS
RSSI Offset Register
090H
236
Data Sheet
168
V1.0, 2010-02-19
TDA5235
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
Page Number
RSSISLOPE
RSSI Slope Register
091H
237
CDRDRTHRP
CDR Data Rate Acceptance Positive Threshold
Register
092H
237
CDRDRTHRN
CDR Data Rate Acceptance Negative Threshold
Register
093H
238
IM0
Interrupt Mask Register 0
094H
238
SPMAP
Self Polling Mode Active Periods Register
096H
239
SPMIP
Self Polling Mode Idle Periods Register
097H
240
SPMC
Self Polling Mode Control Register
098H
240
SPMRT
Self Polling Mode Reference Timer Register
099H
241
SPMOFFT0
Self Polling Mode Off Time Register 0
09AH
241
SPMOFFT1
Self Polling Mode Off Time Register 1
09BH
242
SPMONTA0
Self Polling Mode On Time Config A Register 0
09CH
242
SPMONTA1
Self Polling Mode On Time Config A Register 1
09DH
243
SPMONTB0
Self Polling Mode On Time Config B Register 0
09EH
243
SPMONTB1
Self Polling Mode On Time Config B Register 1
09FH
244
EXTPCMD
External Processing Command Register
0A4H
244
CMC1
Chip Mode Control Register 1
0A5H
245
CMC0
Chip Mode Control Register 0
0A6H
246
RSSIPWU
Wakeup Peak Detector Readout Register
0A7H
247
IS0
Interrupt Status Register 0
0A8H
248
RFPLLACC
RF PLL Actual Channel and Configuration
Register
0AAH
249
RSSIPRX
RSSI Peak Detector Readout Register
0ABH
250
RSSIPPL
RSSI Payload Peak Detector Readout Register
0ACH
250
PLDLEN
Payload Data Length Register
0ADH
251
ADCRESH
ADC Result High Byte Register
0AEH
251
ADCRESL
ADC Result Low Byte Register
0AFH
252
VACRES
VCO Autocalibration Result Readout Register
0B0H
252
AFCOFFSET
AFC Offset Read Register
0B1H
252
AGCGAINR
AGC Gain Readout Register
0B2H
253
SPIAT
SPI Address Tracer Register
0B3H
253
SPIDT
SPI Data Tracer Register
0B4H
254
SPICHKSUM
SPI Checksum Register
0B5H
254
SN0
Serial Number Register 0
0B6H
255
SN1
Serial Number Register 1
0B7H
255
SN2
Serial Number Register 2
0B8H
255
SN3
Serial Number Register 3
0B9H
256
RSSIRX
RSSI Readout Register
0BAH
256
Data Sheet
169
V1.0, 2010-02-19
TDA5235
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
Page Number
RSSIPMF
RSSI Peak Memory Filter Readout Register
0BBH
256
SPWR
Signal Power Readout Register
0BCH
257
NPWR
Noise Power Readout Register
0BDH
257
B_MID0
Message ID Register 0
100H
B_MID1
Message ID Register 1
101H
B_MID2
Message ID Register 2
102H
B_MID3
Message ID Register 3
103H
B_MID4
Message ID Register 4
104H
B_MID5
Message ID Register 5
105H
B_MID6
Message ID Register 6
106H
B_MID7
Message ID Register 7
107H
B_MID8
Message ID Register 8
108H
B_MID9
Message ID Register 9
109H
B_MID10
Message ID Register 10
10AH
B_MID11
Message ID Register 11
10BH
B_MID12
Message ID Register 12
10CH
B_MID13
Message ID Register 13
10DH
B_MID14
Message ID Register 14
10EH
B_MID15
Message ID Register 15
10FH
B_MID16
Message ID Register 16
110H
B_MID17
Message ID Register 17
111H
B_MID18
Message ID Register 18
112H
B_MID19
Message ID Register 19
113H
B_MIDC0
Message ID Control Register 0
114H
B_MIDC1
Message ID Control Register 1
115H
B_IF1
IF1 Register
116H
B_WUC
Wake-Up Control Register
117H
B_WUPAT0
Wake-Up Pattern Register 0
118H
B_WUPAT1
Wake-Up Pattern Register 1
119H
B_WUBCNT
Wake-Up Bit or Chip Count Register
11AH
B_WURSSITH1
RSSI Wake-Up Threshold for Channel 1 Register 11BH
B_WURSSIBL1
RSSI Wake-Up Blocking Level Low Channel 1
Register
11CH
B_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
11DH
B_SIGDETSAT
Signal Detector Saturation Threshold Register
124H
B_WULOT
Wake-Up on Level Observation Time Register
125H
B_SYSRCTO
Synchronization Search Time-Out Register
126H
B_TOTIM_SYNC
SYNC Timeout Timer Register
127H
Data Sheet
170
V1.0, 2010-02-19
TDA5235
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
B_TOTIM_TSI
TSI Timeout Timer Register
128H
B_TOTIM_EOM
EOM Timeout Timer Register
129H
B_AFCLIMIT
AFC Limit Configuration Register
12AH
B_AFCAGCD
AFC/AGC Freeze Delay Register
12BH
B_AFCSFCFG
AFC Start/Freeze Configuration Register
12CH
B_AFCK1CFG0
AFC Integrator 1 Gain Register 0
12DH
B_AFCK1CFG1
AFC Integrator 1 Gain Register 1
12EH
B_AFCK2CFG0
AFC Integrator 2 Gain Register 0
12FH
B_AFCK2CFG1
AFC Integrator 2 Gain Register 1
130H
B_PMFUDSF
Peak Memory Filter Up-Down Factor Register
131H
B_AGCSFCFG
AGC Start/Freeze Configuration Register
132H
B_AGCCFG0
AGC Configuration Register 0
133H
B_AGCCFG1
AGC Configuration Register 1
134H
B_AGCTHR
AGC Threshold Register
135H
B_DIGRXC
Digital Receiver Configuration Register
136H
B_PKBITPOS
RSSI Peak Detector Bit Position Register
137H
B_ISUPFCSEL
Image Supression Fc Selection Register
138H
B_PDECF
Pre Decimation Factor Register
139H
B_PDECSCFSK
Pre Decimation Scaling Register FSK Mode
13AH
B_PDECSCASK
Pre Decimation Scaling Register ASK Mode
13BH
B_MFC
Matched Filter Control Register
13CH
B_SRC
Sampe Rate Converter NCO Tune
13DH
B_EXTSLC
Externel Data Slicer Configuration
13EH
B_SIGDET0
Signal Detector Threshold Level Register - Run
Mode
13FH
B_SIGDET1
Signal Detector Threshold Level Register Wakeup
140H
B_SIGDETLO
Signal Detector Threshold Low Level Register
141H
B_SIGDETSEL
Signal Detector Range Selection Register
142H
B_SIGDETCFG
Signal Detector Configuration Register
143H
B_NDTHRES
FSK Noise Detector Threshold Register
144H
B_NDCONFIG
FSK Noise Detector Configuration Register
145H
B_CDRP
Clock and Data Recovery P Configuration
Register
146H
B_CDRI
Clock and Data Recovery Configuration Register
147H
B_CDRRI
Clock and Data Recovery RUNIN Configuration
Register
148H
B_CDRTOLC
CDR DC Chip Tolerance Register
149H
B_CDRTOLB
CDR DC Bit Tolerance Register
14AH
Data Sheet
171
Page Number
V1.0, 2010-02-19
TDA5235
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
B_TVWIN
Timing Violation Window Register
14BH
B_SLCCFG
Slicer Configuration Register
14CH
B_TSIMODE
TSI Detection Mode Register
14DH
B_TSILENA
TSI Length Register A
14EH
B_TSILENB
TSI Length Register B
14FH
B_TSIGAP
TSI Gap Length Register
150H
B_TSIPTA0
TSI Pattern Data Reference A Register 0
151H
B_TSIPTA1
TSI Pattern Data Reference A Register 1
152H
B_TSIPTB0
TSI Pattern Data Reference B Register 0
153H
B_TSIPTB1
TSI Pattern Data Reference B Register 1
154H
B_EOMC
End Of Message Control Register
155H
B_EOMDLEN
EOM Data Length Limit Register
156H
B_EOMDLENP
EOM Data Length Limit Parallel Mode Register
157H
B_CHCFG
Channel Configuration Register
158H
B_PLLINTC1
PLL MMD Integer Value Register Channel 1
159H
B_PLLFRAC0C1
PLL Fractional Division Ratio Register 0 Channel 1 15AH
B_PLLFRAC1C1
PLL Fractional Division Ratio Register 1 Channel 1 15BH
B_PLLFRAC2C1
PLL Fractional Division Ratio Register 2 Channel 1 15CH
Table 2
Page Number
Register Overview and Reset Value
Register Short Name
Register Long Name
Offset Address
Reset Value
Appendix - Registers Chapter, Register Description
A_MID0
Message ID Register 0
000H
00H
A_MID1
Message ID Register 1
001H
00H
A_MID2
Message ID Register 2
002H
00H
A_MID3
Message ID Register 3
003H
00H
A_MID4
Message ID Register 4
004H
00H
A_MID5
Message ID Register 5
005H
00H
A_MID6
Message ID Register 6
006H
00H
A_MID7
Message ID Register 7
007H
00H
A_MID8
Message ID Register 8
008H
00H
A_MID9
Message ID Register 9
009H
00H
A_MID10
Message ID Register 10
00AH
00H
A_MID11
Message ID Register 11
00BH
00H
A_MID12
Message ID Register 12
00CH
00H
A_MID13
Message ID Register 13
00DH
00H
A_MID14
Message ID Register 14
00EH
00H
A_MID15
Message ID Register 15
00FH
00H
Data Sheet
172
V1.0, 2010-02-19
TDA5235
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
Register Long Name
Offset Address
Reset Value
A_MID16
Message ID Register 16
010H
00H
A_MID17
Message ID Register 17
011H
00H
A_MID18
Message ID Register 18
012H
00H
A_MID19
Message ID Register 19
013H
00H
A_MIDC0
Message ID Control Register 0
014H
00H
A_MIDC1
Message ID Control Register 1
015H
00H
A_IF1
IF1 Register
016H
20H
A_WUC
Wake-Up Control Register
017H
04H
A_WUPAT0
Wake-Up Pattern Register 0
018H
00H
A_WUPAT1
Wake-Up Pattern Register 1
019H
00H
A_WUBCNT
Wake-Up Bit or Chip Count Register
01AH
00H
A_WURSSITH1
RSSI Wake-Up Threshold for Channel 1 Register 01BH
00H
A_WURSSIBL1
RSSI Wake-Up Blocking Level Low Channel 1
Register
01CH
FFH
A_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
01DH
00H
A_SIGDETSAT
Signal Detector Saturation Threshold Register
024H
10H
A_WULOT
Wake-up on Level Observation Time Register
025H
00H
A_SYSRCTO
Synchronization Search Time-Out Register
026H
87H
A_TOTIM_SYNC
SYNC Timeout Timer Register
027H
FFH
A_TOTIM_TSI
TSI Timeout Timer Register
028H
00H
A_TOTIM_EOM
EOM Timeout Timer Register
029H
00H
A_AFCLIMIT
AFC Limit Configuration Register
02AH
02H
A_AFCAGCD
AFC/AGC Freeze Delay Register
02BH
00H
A_AFCSFCFG
AFC Start/Freeze Configuration Register
02CH
00H
A_AFCK1CFG0
AFC Integrator 1 Gain Register 0
02DH
00H
A_AFCK1CFG1
AFC Integrator 1 Gain Register 1
02EH
00H
A_AFCK2CFG0
AFC Integrator 2 Gain Register 0
02FH
00H
A_AFCK2CFG1
AFC Integrator 2 Gain Register 1
030H
00H
A_PMFUDSF
Peak Memory Filter Up-Down Factor Register
031H
42H
A_AGCSFCFG
AGC Start/Freeze Configuration Register
032H
00H
A_AGCCFG0
AGC Configuration Register 0
033H
2BH
A_AGCCFG1
AGC Configuration Register 1
034H
03H
A_AGCTHR
AGC Threshold Register
035H
08H
A_DIGRXC
Digital Receiver Configuration Register
036H
40H
A_PKBITPOS
RSSI Peak Detector Bit Position Register
037H
00H
A_ISUPFCSEL
Image Supression Fc Selection Register
038H
07H
A_PDECF
Pre Decimation Factor Register
039H
00H
A_PDECSCFSK
Pre Decimation Scaling Register FSK Mode
03AH
00H
Data Sheet
173
V1.0, 2010-02-19
TDA5235
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
Register Long Name
Offset Address
Reset Value
A_PDECSCASK
Pre Decimation Scaling Register ASK Mode
03BH
20H
A_MFC
Matched Filter Control Register
03CH
07H
A_SRC
Sampe Rate Converter NCO Tune
03DH
00H
A_EXTSLC
Externel Data Slicer Configuration
03EH
02H
A_SIGDET0
Signal Detector Threshold Level Register - Run
Mode
03FH
00H
A_SIGDET1
Signal Detector Threshold Level Register Wakeup
040H
00H
A_SIGDETLO
Signal Detector Threshold Low Level Register
041H
00H
A_SIGDETSEL
Signal Detector Range Selection Register
042H
7FH
A_SIGDETCFG
Signal Detector Configuration Register
043H
00H
A_NDTHRES
FSK Noise Detector Threshold Register
044H
00H
A_NDCONFIG
FSK Noise Detector Configuration Register
045H
07H
A_CDRP
Clock and Data Recovery P Configuration
Register
046H
E6H
A_CDRI
Clock and Data Recovery Configuration Register
047H
65H
A_CDRRI
Clock and Data Recovery RUNIN Configuration
Register
048H
01H
A_CDRTOLC
CDR DC Chip Tolerance Register
049H
0CH
A_CDRTOLB
CDR DC Bit Tolerance Register
04AH
1EH
A_TVWIN
Timing Violation Window Register
04BH
28H
A_SLCCFG
Slicer Configuration Register
04CH
90H
A_TSIMODE
TSI Detection Mode Register
04DH
80H
A_TSILENA
TSI Length Register A
04EH
00H
A_TSILENB
TSI Length Register B
04FH
00H
A_TSIGAP
TSI Gap Length Register
050H
00H
A_TSIPTA0
TSI Pattern Data Reference A Register 0
051H
00H
A_TSIPTA1
TSI Pattern Data Reference A Register 1
052H
00H
A_TSIPTB0
TSI Pattern Data Reference B Register 0
053H
00H
A_TSIPTB1
TSI Pattern Data Reference B Register 1
054H
00H
A_EOMC
End Of Message Control Register
055H
05H
A_EOMDLEN
EOM Data Length Limit Register
056H
00H
A_EOMDLENP
EOM Data Length Limit Parallel Mode Register
057H
00H
A_CHCFG
Channel Configuration Register
058H
04H
A_PLLINTC1
PLL MMD Integer Value Register Channel 1
059H
93H
A_PLLFRAC0C1
PLL Fractional Division Ratio Register 0 Channel 1 05AH
F3H
A_PLLFRAC1C1
PLL Fractional Division Ratio Register 1 Channel 1 05BH
07H
A_PLLFRAC2C1
PLL Fractional Division Ratio Register 2 Channel 1 05CH
09H
SFRPAGE
Special Function Register Page Register
00H
Data Sheet
174
080H
V1.0, 2010-02-19
TDA5235
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
Register Long Name
Offset Address
Reset Value
PPCFG0
PP0 and PP1 Configuration Register
081H
50H
PPCFG1
PP2 and PP3 Configuration Register
082H
12H
PPCFG2
PPx Port Configuration Register
083H
00H
RXRUNCFG0
RX RUN Configuration Register 0
084H
FFH
RXRUNCFG1
RX RUN Configuration Register 1
085H
FFH
CLKOUT0
Clock Divider Register 0
086H
0BH
CLKOUT1
Clock Divider Register 1
087H
00H
CLKOUT2
Clock Divider Register 2
088H
00H
RFC
RF Control Register
089H
07H
BPFCALCFG0
BPF Calibration Configuration Register 0
08AH
07H
BPFCALCFG1
BPF Calibration Configuration Register 1
08BH
04H
XTALCAL0
XTAL Coarse Calibration Register
08CH
10H
XTALCAL1
XTAL Fine Calibration Register
08DH
00H
RSSIMONC
RSSI Monitor Configuration Register
08EH
01H
ADCINSEL
ADC Input Selection Register
08FH
00H
RSSIOFFS
RSSI Offset Register
090H
80H
RSSISLOPE
RSSI Slope Register
091H
80H
CDRDRTHRP
CDR Data Rate Acceptance Positive Threshold
Register
092H
1EH
CDRDRTHRN
CDR Data Rate Acceptance Negative Threshold
Register
093H
23H
IM0
Interrupt Mask Register 0
094H
00H
SPMAP
Self Polling Mode Active Periods Register
096H
01H
SPMIP
Self Polling Mode Idle Periods Register
097H
01H
SPMC
Self Polling Mode Control Register
098H
00H
SPMRT
Self Polling Mode Reference Timer Register
099H
01H
SPMOFFT0
Self Polling Mode Off Time Register 0
09AH
01H
SPMOFFT1
Self Polling Mode Off Time Register 1
09BH
00H
SPMONTA0
Self Polling Mode On Time Config A Register 0
09CH
01H
SPMONTA1
Self Polling Mode On Time Config A Register 1
09DH
00H
SPMONTB0
Self Polling Mode On Time Config B Register 0
09EH
01H
SPMONTB1
Self Polling Mode On Time Config B Register 1
09FH
00H
EXTPCMD
External Processing Command Register
0A4H
00H
CMC1
Chip Mode Control Register 1
0A5H
04H
CMC0
Chip Mode Control Register 0
0A6H
10H
RSSIPWU
Wakeup Peak Detector Readout Register
0A7H
00H
IS0
Interrupt Status Register 0
0A8H
FFH
RFPLLACC
RF PLL Actual Channel and Configuration
Register
0AAH
00H
Data Sheet
175
V1.0, 2010-02-19
TDA5235
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
Register Long Name
Offset Address
Reset Value
RSSIPRX
RSSI Peak Detector Readout Register
0ABH
00H
RSSIPPL
RSSI Payload Peak Detector Readout Register
0ACH
00H
PLDLEN
Payload Data Length Register
0ADH
00H
ADCRESH
ADC Result High Byte Register
0AEH
00H
ADCRESL
ADC Result Low Byte Register
0AFH
00H
VACRES
VCO Autocalibration Result Readout Register
0B0H
00H
AFCOFFSET
AFC Offset Read Register
0B1H
00H
AGCGAINR
AGC Gain Readout Register
0B2H
00H
SPIAT
SPI Address Tracer Register
0B3H
00H
SPIDT
SPI Data Tracer Register
0B4H
00H
SPICHKSUM
SPI Checksum Register
0B5H
00H
SN0
Serial Number Register 0
0B6H
00H
SN1
Serial Number Register 1
0B7H
00H
SN2
Serial Number Register 2
0B8H
00H
SN3
Serial Number Register 3
0B9H
00H
RSSIRX
RSSI Readout Register
0BAH
00H
RSSIPMF
RSSI Peak Memory Filter Readout Register
0BBH
00H
SPWR
Signal Power Readout Register
0BCH
00H
NPWR
Noise Power Readout Register
0BDH
00H
B_MID0
Message ID Register 0
100H
00H
B_MID1
Message ID Register 1
101H
00H
B_MID2
Message ID Register 2
102H
00H
B_MID3
Message ID Register 3
103H
00H
B_MID4
Message ID Register 4
104H
00H
B_MID5
Message ID Register 5
105H
00H
B_MID6
Message ID Register 6
106H
00H
B_MID7
Message ID Register 7
107H
00H
B_MID8
Message ID Register 8
108H
00H
B_MID9
Message ID Register 9
109H
00H
B_MID10
Message ID Register 10
10AH
00H
B_MID11
Message ID Register 11
10BH
00H
B_MID12
Message ID Register 12
10CH
00H
B_MID13
Message ID Register 13
10DH
00H
B_MID14
Message ID Register 14
10EH
00H
B_MID15
Message ID Register 15
10FH
00H
B_MID16
Message ID Register 16
110H
00H
B_MID17
Message ID Register 17
111H
00H
B_MID18
Message ID Register 18
112H
00H
Data Sheet
176
V1.0, 2010-02-19
TDA5235
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
Register Long Name
Offset Address
Reset Value
B_MID19
Message ID Register 19
113H
00H
B_MIDC0
Message ID Control Register 0
114H
00H
B_MIDC1
Message ID Control Register 1
115H
00H
B_IF1
IF1 Register
116H
20H
B_WUC
Wake-Up Control Register
117H
04H
B_WUPAT0
Wake-Up Pattern Register 0
118H
00H
B_WUPAT1
Wake-Up Pattern Register 1
119H
00H
B_WUBCNT
Wake-Up Bit or Chip Count Register
11AH
00H
B_WURSSITH1
RSSI Wake-Up Threshold for Channel 1 Register 11BH
00H
B_WURSSIBL1
RSSI Wake-Up Blocking Level Low Channel 1
Register
11CH
FFH
B_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
11DH
00H
B_SIGDETSAT
Signal Detector Saturation Threshold Register
124H
10H
B_WULOT
Wake-Up on Level Observation Time Register
125H
00H
B_SYSRCTO
Synchronization Search Time-Out Register
126H
87H
B_TOTIM_SYNC
SYNC Timeout Timer Register
127H
FFH
B_TOTIM_TSI
TSI Timeout Timer Register
128H
00H
B_TOTIM_EOM
EOM Timeout Timer Register
129H
00H
B_AFCLIMIT
AFC Limit Configuration Register
12AH
02H
B_AFCAGCD
AFC/AGC Freeze Delay Register
12BH
00H
B_AFCSFCFG
AFC Start/Freeze Configuration Register
12CH
00H
B_AFCK1CFG0
AFC Integrator 1 Gain Register 0
12DH
00H
B_AFCK1CFG1
AFC Integrator 1 Gain Register 1
12EH
00H
B_AFCK2CFG0
AFC Integrator 2 Gain Register 0
12FH
00H
B_AFCK2CFG1
AFC Integrator 2 Gain Register 1
130H
00H
B_PMFUDSF
Peak Memory Filter Up-Down Factor Register
131H
42H
B_AGCSFCFG
AGC Start/Freeze Configuration Register
132H
00H
B_AGCCFG0
AGC Configuration Register 0
133H
2BH
B_AGCCFG1
AGC Configuration Register 1
134H
03H
B_AGCTHR
AGC Threshold Register
135H
08H
B_DIGRXC
Digital Receiver Configuration Register
136H
40H
B_PKBITPOS
RSSI Peak Detector Bit Position Register
137H
00H
B_ISUPFCSEL
Image Supression Fc Selection Register
138H
07H
B_PDECF
Pre Decimation Factor Register
139H
00H
B_PDECSCFSK
Pre Decimation Scaling Register FSK Mode
13AH
00H
B_PDECSCASK
Pre Decimation Scaling Register ASK Mode
13BH
20H
B_MFC
Matched Filter Control Register
13CH
07H
B_SRC
Sampe Rate Converter NCO Tune
13DH
00H
Data Sheet
177
V1.0, 2010-02-19
TDA5235
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
Register Long Name
Offset Address
Reset Value
B_EXTSLC
Externel Data Slicer Configuration
13EH
02H
B_SIGDET0
Signal Detector Threshold Level Register - Run
Mode
13FH
00H
B_SIGDET1
Signal Detector Threshold Level Register Wakeup
140H
00H
B_SIGDETLO
Signal Detector Threshold Low Level Register
141H
00H
B_SIGDETSEL
Signal Detector Range Selection Register
142H
7FH
B_SIGDETCFG
Signal Detector Configuration Register
143H
00H
B_NDTHRES
FSK Noise Detector Threshold Register
144H
00H
B_NDCONFIG
FSK Noise Detector Configuration Register
145H
07H
B_CDRP
Clock and Data Recovery P Configuration
Register
146H
E6H
B_CDRI
Clock and Data Recovery Configuration Register
147H
65H
B_CDRRI
Clock and Data Recovery RUNIN Configuration
Register
148H
01H
B_CDRTOLC
CDR DC Chip Tolerance Register
149H
0CH
B_CDRTOLB
CDR DC Bit Tolerance Register
14AH
1EH
B_TVWIN
Timing Violation Window Register
14BH
28H
B_SLCCFG
Slicer Configuration Register
14CH
90H
B_TSIMODE
TSI Detection Mode Register
14DH
80H
B_TSILENA
TSI Length Register A
14EH
00H
B_TSILENB
TSI Length Register B
14FH
00H
B_TSIGAP
TSI Gap Length Register
150H
00H
B_TSIPTA0
TSI Pattern Data Reference A Register 0
151H
00H
B_TSIPTA1
TSI Pattern Data Reference A Register 1
152H
00H
B_TSIPTB0
TSI Pattern Data Reference B Register 0
153H
00H
B_TSIPTB1
TSI Pattern Data Reference B Register 1
154H
00H
B_EOMC
End Of Message Control Register
155H
05H
B_EOMDLEN
EOM Data Length Limit Register
156H
00H
B_EOMDLENP
EOM Data Length Limit Parallel Mode Register
157H
00H
B_CHCFG
Channel Configuration Register
158H
04H
B_PLLINTC1
PLL MMD Integer Value Register Channel 1
159H
93H
B_PLLFRAC0C1
PLL Fractional Division Ratio Register 0 Channel 1 15AH
F3H
B_PLLFRAC1C1
PLL Fractional Division Ratio Register 1 Channel 1 15BH
07H
B_PLLFRAC2C1
PLL Fractional Division Ratio Register 2 Channel 1 15CH
09H
Data Sheet
178
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Register Description
Message ID Register 0
A_MID0
Offset
Message ID Register 0
Reset Value
000H
00H
0,'
Z
Field
Bits
Type
Description
MID0
7:0
w
Message ID Register 0
Reset: 00H
Message ID Register 1
A_MID1
Offset
Message ID Register 1
Reset Value
001H
00H
0,'
Z
Field
Bits
Type
Description
MID1
7:0
w
Message ID Register 1
Reset: 00H
Message ID Register 2
A_MID2
Offset
Message ID Register 2
002H
Data Sheet
179
Reset Value
00H
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
0,'
Z
Field
Bits
Type
Description
MID2
7:0
w
Message ID Register 2
Reset: 00H
Message ID Register 3
A_MID3
Offset
Message ID Register 3
Reset Value
003H
00H
0,'
Z
Field
Bits
Type
Description
MID3
7:0
w
Message ID Register 3
Reset: 00H
Message ID Register 4
A_MID4
Offset
Message ID Register 4
Reset Value
004H
00H
0,'
Z
Field
Bits
Type
Description
MID4
7:0
w
Message ID Register 4
Reset: 00H
Message ID Register 5
Data Sheet
180
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
A_MID5
Offset
Message ID Register 5
Reset Value
005H
00H
0,'
Z
Field
Bits
Type
Description
MID5
7:0
w
Message ID Register 5
Reset: 00H
Message ID Register 6
A_MID6
Offset
Message ID Register 6
Reset Value
006H
00H
0,'
Z
Field
Bits
Type
Description
MID6
7:0
w
Message ID Register 6
Reset: 00H
Message ID Register 7
A_MID7
Offset
Message ID Register 7
Reset Value
007H
00H
0,'
Z
Field
Bits
Type
Description
MID7
7:0
w
Message ID Register 7
Reset: 00H
Data Sheet
181
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Message ID Register 8
A_MID8
Offset
Message ID Register 8
Reset Value
008H
00H
0,'
Z
Field
Bits
Type
Description
MID8
7:0
w
Message ID Register 8
Reset: 00H
Message ID Register 9
A_MID9
Offset
Message ID Register 9
Reset Value
009H
00H
0,'
Z
Field
Bits
Type
Description
MID9
7:0
w
Message ID Register 9
Reset: 00H
Message ID Register 10
A_MID10
Offset
Reset Value
Message ID Register 10
00AH
00H
0,'
Z
Data Sheet
182
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
MID10
7:0
w
Message ID Register 10
Reset: 00H
Message ID Register 11
A_MID11
Offset
Reset Value
Message ID Register 11
00BH
00H
0,'
Z
Field
Bits
Type
Description
MID11
7:0
w
Message ID Register 11
Reset: 00H
Message ID Register 12
A_MID12
Offset
Reset Value
Message ID Register 12
00CH
00H
0,'
Z
Field
Bits
Type
Description
MID12
7:0
w
Message ID Register 12
Reset: 00H
Message ID Register 13
A_MID13
Offset
Reset Value
Message ID Register 13
00DH
00H
Data Sheet
183
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
0,'
Z
Field
Bits
Type
Description
MID13
7:0
w
Message ID Register 13
Reset: 00H
Message ID Register 14
A_MID14
Offset
Message ID Register 14
Reset Value
00EH
00H
0,'
Z
Field
Bits
Type
Description
MID14
7:0
w
Message ID Register 14
Reset: 00H
Message ID Register 15
A_MID15
Offset
Message ID Register 15
Reset Value
00FH
00H
0,'
Z
Field
Bits
Type
Description
MID15
7:0
w
Message ID Register 15
Reset: 00H
Message ID Register 16
Data Sheet
184
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
A_MID16
Offset
Message ID Register 16
Reset Value
010H
00H
0,'
Z
Field
Bits
Type
Description
MID16
7:0
w
Message ID Register 16
Reset: 00H
Message ID Register 17
A_MID17
Offset
Message ID Register 17
Reset Value
011H
00H
0,'
Z
Field
Bits
Type
Description
MID17
7:0
w
Message ID Register 17
Reset: 00H
Message ID Register 18
A_MID18
Offset
Message ID Register 18
Reset Value
012H
00H
0,'
Z
Field
Bits
Type
Description
MID18
7:0
w
Message ID Register 18
Reset: 00H
Data Sheet
185
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Message ID Register 19
A_MID19
Offset
Message ID Register 19
Reset Value
013H
00H
0,'
Z
Field
Bits
Type
Description
MID19
7:0
w
Message ID Register 19
Reset: 00H
Message ID Control Register 0
A_MIDC0
Offset
Message ID Control Register 0
Reset Value
014H
00H
8186('
66326
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
SSPOS
6:0
w
Message ID Scan Start Position
Min: 00h = Comparision starts one Bit after FSYNC
Max: 7F = Comparision starts 128 Bits after FSYNC
Reset: 00H
Message ID Control Register 1
A_MIDC1
Offset
Message ID Control Register 1
015H
Data Sheet
186
Reset Value
00H
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
8186('
0,'6(1
0,'%2
0,'176
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
MIDSEN
3
w
Enable Message ID Screening
0B
Disabled
1B
Enabled
Reset: 0H
MIDBO
2
w
Message ID Byte Organisation
0B
2 Byte Mode
1B
4 Byte Mode
Reset: 0H
MIDNTS
1:0
w
Message ID Number of Bytes To Scan (4 Byte Mode / 2 Byte Mode)
00B 1 Byte to scan / 1 Byte to scan
01B 2 Bytes to scan / 2 Bytes to scan
10B 3 Bytes to scan / 2 Bytes to scan
11B 4 Bytes to scan / 2 Bytes to scan
Reset: 0H
IF1 Register
A_IF1
Offset
IF1 Register
Reset Value
016H
8186('
66%6(/
Z
20H
%3)%:6(/
6'&6(/
,)%8)(1
&(5)6(/
Z
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
SSBSEL
6
w
RXRF Receive Side Band Select
0B
RF = LO + IF1 (Lo-side LO-injection)
1B
RF = LO - IF1 (Hi-side LO-injection)
Reset: 0H
Data Sheet
187
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
BPFBWSEL
5:3
w
Band Pass Filter Bandwidth Selection
000B 50 kHz
001B 80 kHz
010B 125 kHz
011B 200 kHz
100B 300 kHz
101B not used
110B not used
111B not used
Reset: 4H
SDCSEL
2
w
Single / Double Conversion Selection
0B
Double Conversion (10.7 MHz/274 kHz)
1B
Single Conversion (274 kHz)
Reset: 0H
IFBUFEN
1
w
IF Buffer Enable
0B
Disabled
1B
Enabled
Reset: 0H
CERFSEL
0
w
Number of external Ceramic Filters
0B
1 Ceramic Filter
1B
2 Ceramic Filters
Reset: 0H
Wake-Up Control Register
A_WUC
Offset
Wake-Up Control Register
Reset Value
017H
04H
8186('
3:8(1
:8306(/
:8/&8))
%
8))%/&2
2
:8&57
Z
Z
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
PWUEN
6
w
Parallel Wake Up Mode Enable
This feature can only be used, when modulation type is the same for SPM
and RMSP
0B
Disabled
1B
Enabled
Reset: 0H
Data Sheet
188
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
WUPMSEL
5
w
Wake Up Pattern Mode Selection
0B
Chip mode
1B
Bit mode
Reset: 0H
WULCUFFB
4
w
Select a "Wake Up on Level Criterion", when UFFBLCOO is enabled.
0B
RSSI
automatically selected, when A_CHCFG.EXTPROC = "10"
1B
Signal Recognition
Reset: 0H
UFFBLCOO
3
w
Ultrafast Fall Back to SLEEP or additional Level criterion in
Constant On Off.
Enables additional parallel processing of "Level Criterion", when a "Data
Criterion" is selected in WUCRT.
In case of Fast Fall Back to SLEEP or Permanent Wake-Up Search, this
mode is called UFFB (Ultrafast Fall Back). Same Mode can be used in
Constant On-Off.
0B
Disabled
1B
Enabled
Reset: 0H
WUCRT
2:0
w
Select a "Wake Up Criterion"
000B Pattern Detection (Data Criterion)
When A_CHCFG.EXTROC = "01" this setting is mapped to 0x3
001B Random Bits (Data Criterion)
When A_CHCFG.EXTROC = "01" this setting is mapped to 0x3
010B Equal Bits (Data Criterion)
When A_CHCFG.EXTROC = "01" this setting is mapped to 0x3
011B Wake Up on Symbol Sync, Valid Data Rate (Data Criterion); The
A_WUBCNT Register is
not used in this mode
100B RSSI (Level Criterion)
automatically selected, when A_CHCFG.EXTPROC = "10"
101B Signal Recognition (Level Criterion)
110B n.u.
111B n.u.
Reset: 4H
Wake-Up Pattern Register 0
A_WUPAT0
Wake-Up Pattern Register 0
Offset
Reset Value
018H
00H
:83$7
Z
Data Sheet
189
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
WUPAT0
7:0
w
Wake Up Detection Pattern: Bit 7...Bit 0(LSB) (in Bits/Chips)
Reset: 00H
Wake-Up Pattern Register 1
A_WUPAT1
Offset
Wake-Up Pattern Register 1
Reset Value
019H
00H
:83$7
Z
Field
Bits
Type
Description
WUPAT1
7:0
w
Wake Up Detection Pattern: (MSB) Bit 15...Bit 8 (in Bits/Chips)
Reset: 00H
Wake-Up Bit or Chip Count Register
A_WUBCNT
Offset
Reset Value
Wake-Up Bit or Chip Count Register
01AH
00H
8186('
:8%&17
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
Data Sheet
190
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
WUBCNT
6:0
w
Wake Up Bit/Chip Count Register (unit is bits; only exception is WU
Pattern Chip Mode, where unit is chips, see A_WUC.WUPMSEL)
Counter Register to define the maximum counts of bits/chips for Wake Up
detection.
Min: 00h = 0 Bits/Chips to count
In Random Bits or Equal Bits Mode this will cause a Wake Up
on Data Criterion immediately after Symbol Synchronization is found.
In Pattern Detection Mode this will cause no Wake Up on Data Criterion.
In this
Mode there is needed minimum 11h = 17 Bits/Chips to shift
one Pattern through the whole Pattern Detector. Because
comparision can only be started when at least the comparision
register is completely filled.
Max: 7Fh: 127 Bits/Chips to count after Symbol Sync found
Reset: 00H
RSSI Wake-Up Threshold for Channel 1 Register
A_WURSSITH1
Offset
Reset Value
RSSI Wake-Up Threshold for Channel 1
Register
01BH
00H
:8566,7+
Z
Field
Bits
Type
Description
WURSSITH1
7:0
w
Wake Up on RSSI Threshold level for Channel 1
Wake Up Request generated when actual RSSI level is above this
threshold
Reset: 00H
RSSI Wake-Up Blocking Level Low Channel 1 Register
A_WURSSIBL1
Offset
Reset Value
RSSI Wake-Up Blocking Level Low Channel 1
Register
01CH
FFH
Data Sheet
191
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
:8566,%/
Z
Field
Bits
Type
Description
WURSSIBL1
7:0
w
Wake Up on RSSI Blocking Level LOW for Channel 1
Reset: FFH
RSSI Wake-Up Blocking Level High Channel 1 Register
A_WURSSIBH1
Offset
Reset Value
RSSI Wake-Up Blocking Level High Channel
1 Register
01DH
00H
:8566,%+
Z
Field
Bits
Type
Description
WURSSIBH1
7:0
w
Wake Up on RSSI Blocking Level HIGH for Channel 1, when RSSI is
selected as WU criterion or FFB criterion.
In case of Signal Recognition as WU criterion or FFB criterion, the
register defines the minimum consecutive T/16 samples of the Signal
Recognition output to be at high level for a positive wake up event
generation or FFB generation
Reset: 00H
Signal Detector Saturation Threshold Register
A_SIGDETSAT
Signal Detector Saturation Threshold
Register
Offset
Reset Value
024H
10H
6,*'(76$7
Z
Data Sheet
192
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
SIGDETSAT
7:0
w
Saturation threshold of the Sigdet peak detector used for zero-tube
threshold calculation.
Reset: 10H
Wake-up on Level Observation Time Register
A_WULOT
Offset
Wake-up on Level Observation Time Register
Reset Value
025H
00H
:8/2736
:8/27
Z
Z
Field
Bits
Type
Description
WULOTPS
7:5
w
Wake-Up Level Observation Time PreScaler
000B 4
001B 8
010B 16
011B 32
100B 64
101B 128
110B 256
111B 512
Reset: 0H
WULOT
4:0
w
Wake-Up Level Observation Time
Min. 01h : Twulot = 1 * WULOTPS * 64 / Fsys
Max 1Fh : Twulot = 31 * WULOTPS * 64 / Fsys
Value 00h : Twulot = 32 * WULOTPS * 64 / Fsys
Reset: 00H
Synchronization Search Time-Out Register
A_SYSRCTO
Synchronization Search Time-Out Register
Offset
Reset Value
026H
87H
6<65&72
Z
Data Sheet
193
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
SYSRCTO
7:0
w
Synchronization search time out
FFh: 15 15/16 bit
00h: 0 bit
Reset: 87H
SYNC Timeout Timer Register
A_TOTIM_SYNC
Offset
SYNC Timeout Timer Register
Reset Value
027H
FFH
727,06<1&
Z
Field
Bits
Type
Description
TOTIMSYNC
7:0
w
Set value of Time-Out Timer (Symbol Synchronization)
Timer is used to get back from Run Mode Self Polling to the Self Polling
Mode whenever there is no Symbol Synchronization.
Timer is set back at new cycle start of Run Mode Self Polling.
TimeOut= (TOTIMSYNC * 64 * 512) / fsys
Min: 01h = (1 * 64 * 512)/ fsys
Max: FFh= (255 * 64 * 512) / fsys
00h: disabled
Reset: FFH
TSI Timeout Timer Register
A_TOTIM_TSI
TSI Timeout Timer Register
Offset
Reset Value
028H
00H
727,076,
Z
Data Sheet
194
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
TOTIMTSI
7:0
w
Set value of Time-Out Timer (Telegram Start Identifier)
Timer is used to get back from Run Mode Self Polling to the Self Polling
Mode whenever a Symbol Synchronisation is available but there is no TSI
detected.
Timer is set back at new cycle start of Run Mode Self Polling.
TimeOut= (TOTIMTSI * 64 * 512) / fsys
Min: 01h = (1 * 64 * 512)/ fsys
Max: FFh= (255 * 64 * 512) / fsys
00h: disabled
Reset: 00H
EOM Timeout Timer Register
A_TOTIM_EOM
Offset
EOM Timeout Timer Register
Reset Value
029H
00H
727,0(20
Z
Field
Bits
Type
Description
TOTIMEOM
7:0
w
Set value of Time-Out Timer (End of Message)
Timer is used to get back from Run Mode Self Polling to the Self Polling
Mode whenever a TSI has been detected but there is no EOM detected.
Timer is set back at new cycle start of Run Mode Self Polling.
TimeOut= (TOTIMEOM * 64 * 512 * 2) / fsys
Min: 01h = (1 * 64 * 512 * 2)/ fsys
Max: FFh= (255 * 64 * 512 * 2) / fsys
00h: disabled
Reset: 00H
AFC Limit Configuration Register
A_AFCLIMIT
Offset
Reset Value
AFC Limit Configuration Register
02AH
02H
Data Sheet
8186('
$)&/,0,7
Z
195
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
AFCLIMIT
3:0
w
AFC Frequency Offset Saturation Limit ==> 1...15 x 21.4 kHz
Min: 1h = +/- Fsys / 2^(22-12) Hz
Max: Fh = +/- 15 * Fsys / 2^(22-12) Hz
Reg. value 0h = 0 Hz - no AFC correction
Reset: 2H
AFC/AGC Freeze Delay Register
A_AFCAGCD
Offset
Reset Value
AFC/AGC Freeze Delay Register
02BH
00H
$)&$*&'
Z
Field
Bits
Type
Description
AFCAGCD
7:0
w
AFC/AGC Freeze Delay Counter Division Ratio
The base period for the delay counter is the 8-16 samples/chip
(predecimation strobe) divided by 4
Reset: 00H
AFC Start/Freeze Configuration Register
A_AFCSFCFG
Offset
Reset Value
AFC Start/Freeze Configuration Register
02CH
00H
8186('
$)&%/$6
.
$)&5(6$
7&&
$)&)5((=(
$)&67$57
Z
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
Data Sheet
196
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
AFCBLASK
6
w
AFC blocking during a low phase in the ASK signal
0B
Disabled
1B
Enabled
Reset: 0H
AFCRESATC
C
5
w
Enable AFC Restart at the beginning of the current configuration in
Self Polling Mode
and at leaving the HOLD state (when bit CMC0.INITPLLHOLD is set) in
Run Mode Slave
0B
Disabled
1B
Enabled
Reset: 0H
AFCFREEZE
4:2
w
AFC Freeze Configuration
When selecting a Level criterion here,
please note to use the same Level criterion as for Wake-Up
000B Stay ON
001B Freeze on RSSI Event + Delay (AFCAGCDEL)
010B Freeze on Signal Recognition Event + Delay (AFCAGCDEL)
011B Freeze on Symbol Synchronization + Delay (AFCAGCDEL)
100B SPI Command - write to EXTPCMD.AFCMANF bit
101B n.u.
110B n.u.
111B n.u.
Reset: 0H
AFCSTART
1:0
w
AFC Start Configuration
When selecting a Level criterion here,
please note to use the same Level criterion as for Wake-Up
00B OFF
01B Direct ON
10B Start on RSSI event
11B Start on Signal Recognition event
Reset: 0H
AFC Integrator 1 Gain Register 0
A_AFCK1CFG0
Offset
Reset Value
AFC Integrator 1 Gain Register 0
02DH
00H
$)&.B
Z
Data Sheet
197
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
AFCK1_0
7:0
w
AFC Filter coefficient K1, AFCK1(11:0) = AFCK1_1(MSB) &
AFCK1_0(LSB)
Reset: 00H
AFC Integrator 1 Gain Register 1
A_AFCK1CFG1
Offset
AFC Integrator 1 Gain Register 1
Reset Value
02EH
00H
8186('
$)&.B
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
AFCK1_1
3:0
w
AFC Filter coefficient K1, AFCK1(11:0) = AFCK1_1(MSB) &
AFCK1_0(LSB)
Reset: 0H
AFC Integrator 2 Gain Register 0
A_AFCK2CFG0
Offset
AFC Integrator 2 Gain Register 0
Reset Value
02FH
00H
$)&.B
Z
Field
Bits
Type
Description
AFCK2_0
7:0
w
AFC Filter coefficient K2, AFCK2(11:0) = AFCK2_1(MSB) &
AFCK2_0(LSB)
Reset: 00H
AFC Integrator 2 Gain Register 1
Data Sheet
198
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
A_AFCK2CFG1
Offset
AFC Integrator 2 Gain Register 1
Reset Value
030H
00H
8186('
$)&.B
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
AFCK2_1
3:0
w
AFC Filter coefficient K2, AFCK2(11:0) = AFCK2_1(MSB) &
AFCK2_0(LSB)
Reset: 0H
Peak Memory Filter Up-Down Factor Register
A_PMFUDSF
Offset
Peak Memory Filter Up-Down Factor Register
Reset Value
031H
42H
8186('
30)83
8186('
30)'1
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
PMFUP
6:4
w
Peak Memory Filter Attack (Up) Factor
000B 2^-1
001B 2^-2
010B 2^-3
011B 2^-4
100B 2^-5
101B 2^-6
110B 2^-7
111B 2^-8
Reset: 4H
UNUSED
3
-
UNUSED
Reset: 0H
Data Sheet
199
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
PMFDN
2:0
w
Peak Memory Filter Decay (Down) Factor (additional to Attack
Factor)
000B 2^-2
001B 2^-3
010B 2^-4
011B 2^-5
100B 2^-6
101B 2^-7
110B 2^-8
111B 2^-9
Reset: 2H
AGC Start/Freeze Configuration Register
A_AGCSFCFG
Offset
AGC Start/Freeze Configuration Register
Reset Value
032H
00H
8186('
$*&5(6$
7&&
$*&)5((=(
$*&67$57
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
AGCRESATC
C
5
w
Enable AGC Restart at the beginning of the current configuration in
Self Polling Mode
and at leaving the HOLD state (when bit CMC0.INITPLLHOLD is set) in
Run Mode Slave
0B
Disabled
1B
Enabled
Reset: 0H
AGCFREEZE
4:2
w
AGC Freeze Configuration
When selecting a Level criterion here,
please note to use the same Level criterion as for Wake-Up
000B Stay ON
001B Freeze on RSSI Event + Delay (AFCAGCDEL)
010B Freeze on Signal Recognition Event + Delay (AFCAGCDEL)
011B Freeze on Symbol Synchronization + Delay (AFCAGCDEL)
100B SPI Command - write to EXTPCMD.AGCMANF bit
101B n.u.
110B n.u.
111B n.u.
Reset: 0H
Data Sheet
200
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
AGCSTART
1:0
w
AGC Start Configuration
When selecting a Level criterion here,
please note to use the same Level criterion as for Wake-Up
00B OFF
01B Direct ON
10B Start on RSSI event
11B Start on Signal Recognition event
Reset: 0H
AGC Configuration Register 0
A_AGCCFG0
Offset
AGC Configuration Register 0
Reset Value
033H
2BH
8186('
$*&'*&
$*&+<6
$*&*$,1
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
AGCDGC
6:4
w
AGC Digital RSSI Gain Correction Tuning
000B 14.5 dB
001B 15.0 dB
010B 15.5 dB
011B 16.0 dB
100B 16.5 dB
101B 17.0 dB
110B 17.5 dB
111B 18.0 dB
Reset: 2H
AGCHYS
3:2
w
AGC Threshold Hysteresis
00B 12.8 dB
01B 17.1 dB
10B 21.3 dB
11B 25.6 dB
Reset: 2H
AGCGAIN
1:0
w
AGC Gain Control
00B 0 dB
01B -15 dB
10B -30 dB
11B Automatic
Reset: 3H
Data Sheet
201
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
AGC Configuration Register 1
A_AGCCFG1
Offset
AGC Configuration Register 1
Reset Value
034H
03H
8186('
$*&7+2))6
Z
Field
Bits
Type
Description
UNUSED
7:2
-
UNUSED
Reset: 00H
AGCTHOFFS
1:0
w
AGC Threshold Offset
00B 25.5 dB
01B 38.3 dB
10B 51.1 dB
11B 63.9 dB
Reset: 3H
AGC Threshold Register
A_AGCTHR
Offset
AGC Threshold Register
Reset Value
035H
08H
$*&783
$*&7/2
Z
Z
Field
Bits
Type
Description
AGCTUP
7:4
w
AGC Upper Attack Threshold [dB]
AGC Upper Threshold = A_AGCCFG1.AGCTHOFFS + 25.6 +
AGCTUP*1.6
Reset: 0H
AGCTLO
3:0
w
AGC Lower Attack Threshold [dB]
AGC Lower Threshold = A_AGCCFG1.AGCTHOFFS + AGCTLO*1.6
Reset: 8H
Digital Receiver Configuration Register
Data Sheet
202
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
A_DIGRXC
Offset
Digital Receiver Configuration Register
,1,7'5;
(6
,1,7)5&
6
Z
Z
Reset Value
036H
40H
&2'(
&+,3',1
9
',19(;7
$$)%<3
$$))&6(
/
Z
Z
Z
Z
Z
Field
Bits
Type
Description
INITDRXES
7
w
Init the Digital Receiver at EOM or Loss of Symbol Sync (e.g. for
initialization of the Peak Memory Filter)
0B
Disabled
1B
Enabled
Reset: 0H
INITFRCS
6
w
Init the Framer at Cycle Start in RMSP.
If disabled, the WUP Data can be used as part of TSI as well in case the
modulation type is the same for SPM and RMSP
0B
Disabled
1B
Enabled
Reset: 1H
CODE
5:4
w
Encoding Mode Selection
00B Manchester Code
01B Differential Manchester Code
10B Biphase Space
11B Biphase Mark
Reset: 0H
CHIPDINV
3
w
Baseband Chip Data Inversion for CH_DATA and Decoder/Framer
input. Therefore Inverted Manchester and Inverted Differential
Manchester can be decoded internally.
0B
Not inverted
1B
Inverted
Reset: 0H
DINVEXT
2
w
Data Inversion of signal DATA and DATA_MATCHFIL for External
Processing
0B
Not inverted
1B
Inverted
Reset: 0H
AAFBYP
1
w
Anti-Alliasing Filter Bypass for RSSI pin
0B
Not bypassed
1B
Bypassed
Reset: 0H
AAFFCSEL
0
w
Anti-Alliasing Filter Corner Frequency Select
0B
40 kHz
1B
80 kHz
Reset: 0H
Data Sheet
203
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
RSSI Peak Detector Bit Position Register
A_PKBITPOS
Offset
RSSI Peak Detector Bit Position Register
Reset Value
037H
00H
566,'/<
Z
Field
Bits
Type
Description
RSSIDLY
7:0
w
RSSI Detector Start-up Delay for RSSIPPL register
Min: 00h: 0 bit delay (Start with first bit after FSYNC)
Max: FFh: 255 bit delay
Note: Due to filtering and signal computation, the latency T1 and T2 have
to be added
Reset: 00H
Image Supression Fc Selection Register
A_ISUPFCSEL
Offset
Image Supression Fc Selection Register
Reset Value
038H
07H
5HV
8186('
)&6(/
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
FCSEL
2:0
w
Image Supression Filter Corner Frequency Selection for FSK signal
path
000B 33 kHz
001B 46 kHz
010B 65 kHz
011B 93 kHz
100B 132 kHz
101B 190 kHz
110B 239 kHz
111B 282 kHz
Reset: 7H
Data Sheet
204
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Pre Decimation Factor Register
A_PDECF
Offset
Pre Decimation Factor Register
Reset Value
039H
00H
8186('
35('(&)
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
PREDECF
6:0
w
Predecimation Filter Decimation Factor
Predecimation Factor = PREDECF + 1
Reset: 00H
Pre Decimation Scaling Register FSK Mode
A_PDECSCFSK
Offset
Reset Value
Pre Decimation Scaling Register FSK Mode
03AH
00H
5HV
,1732/(
1)
3'6&$/()
Z
Z
Field
Bits
Type
Description
INTPOLENF
5
w
FSK Data Interpolation Enable
0B
Disabled
1B
Enabled
Reset: 0H
PDSCALEF
4:0
w
Predecimation Block Scaling Factor for FSK
Min 00h : 2^-10
Max 17h : 2^13
Reset: 00H
Pre Decimation Scaling Register ASK Mode
Data Sheet
205
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
A_PDECSCASK
Offset
Reset Value
Pre Decimation Scaling Register ASK Mode
03BH
20H
8186('
5HV
,1732/(
1$
3'6&$/($
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
INTPOLENA
5
w
ASK Data Interpolation Enable
0B
Disabled
1B
Enabled
Reset: 1H
PDSCALEA
4:0
w
Predecimation Block Scaling Factor for ASK
Min 00h : 2^-10
Max 17h : 2^13
Reset: 00H
Matched Filter Control Register
A_MFC
Offset
Reset Value
Matched Filter Control Register
03CH
07H
8186('
0)/
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
MFL
3:0
w
Matched Filter Length
MF Length = MFL + 1
Reset: 7H
Sampe Rate Converter NCO Tune
A_SRC
Offset
Reset Value
Sampe Rate Converter NCO Tune
03DH
00H
Data Sheet
206
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
65&1&2
Z
Field
Bits
Type
Description
SRCNCO
7:0
w
Sample Rate Converter NCO Tune
Min 00h : Fout = Fin
Max FFh : Fout = Fin / 2
Reset: 00H
Externel Data Slicer Configuration
A_EXTSLC
Offset
Externel Data Slicer Configuration
03EH
5HV
8186('
Reset Value
02H
(6/&6&$
(6/&%:
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
ESLCSCA
4:3
w
External Slicer BW Selection Scaling
00B 1/2
01B 1/4
10B 1/8
11B 1/16
Reset: 0H
ESLCBW
2:0
w
External Slicer Manual BW Selection
000B 1/8
001B 1/16
010B 1/24
011B 1/32
100B 1/40
101B 1/48
110B n.u.
111B n.u.
Reset: 2H
Signal Detector Threshold Level Register - Run Mode
Data Sheet
207
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
A_SIGDET0
Offset
Signal Detector Threshold Level Register Run Mode
Reset Value
03FH
00H
6'7+5
Z
Field
Bits
Type
Description
SDTHR
7:0
w
Signal Detector Threshold Level for Run Mode
Reset: 00H
Signal Detector Threshold Level Register - Wakeup
A_SIGDET1
Offset
Signal Detector Threshold Level Register Wakeup
Reset Value
040H
00H
6'7+5
Z
Field
Bits
Type
Description
SDTHR
7:0
w
Signal Detector Threshold Level for Wakeup
Reset: 00H
Signal Detector Threshold Low Level Register
A_SIGDETLO
Signal Detector Threshold Low Level
Register
Offset
Reset Value
041H
00H
6'/27+5
Z
Data Sheet
208
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
SDLOTHR
7:0
w
Signal Detector Threshold Low Level. This threshold level is
only valid, if the FSK Noise detector selection in the A_NDCONFIG
register is
set to 11b
Reset: 00H
Signal Detector Range Selection Register
A_SIGDETSEL
Offset
Signal Detector Range Selection Register
5HV
Reset Value
042H
7FH
6'56(/$6.
6'56(/)6.
6'/256(/
Z
Z
Z
Field
Bits
Type
Description
SDRSELASK
5:4
w
A_SIGDET0/1 range selection factor for ASK. The selected signal
detector value is multiplied by the 2^range selection factor. Use the
right setting to fit the measured SPWR value.
00B 6
01B 7
10B 7+6
11B 8
Reset: 3H
SDRSELFSK
3:2
w
A_SIGDET0/1 range selection factor for FSK. The selected signal
detector value is multiplied by the 2^range selection factor. Use the
right setting to fit the measured SPWR value.
00B 2
01B 4
10B 6
11B 8
Reset: 3H
SDLORSEL
1:0
w
SIGDETLO range selection factor. The selected signal detector
value is multiplied by the 2^range selection factor. Use the right
setting to fit the measured SPWR value.
00B 2
01B 4
10B 6
11B 8
Reset: 3H
Data Sheet
209
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Signal Detector Configuration Register
A_SIGDETCFG
Offset
Signal Detector Configuration Register
Reset Value
043H
00H
8186('
5HV
6'/25(
6'&17
6'&17
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
SDLORE
2
w
Source selection of Signal Power Readout Register
0B
Signal Power for A_SIGDET0/1
1B
Signal for minimal usable FSK deviation, the sigdet low level can
be read out with SPWR register
Reset: 0H
SDCNT1
1
w
Signal Detector Threshold Counter for Wakeup
0B
Disabled
1B
1/2 bit
Reset: 0H
SDCNT0
0
w
Signal Detector Threshold Counter for Run Mode
0B
Disabled
1B
1/2 bit
Reset: 0H
FSK Noise Detector Threshold Register
A_NDTHRES
Offset
FSK Noise Detector Threshold Register
Reset Value
044H
00H
1'7+5(6
Z
Field
Bits
Type
Description
NDTHRES
7:0
w
FSK Noise Detector Threshold
Reset: 00H
Data Sheet
210
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
FSK Noise Detector Configuration Register
A_NDCONFIG
Offset
FSK Noise Detector Configuration Register
Reset Value
045H
07H
1'56(/
1'6(/
1'7/
1'3'65
Z
Z
Z
Z
Field
Bits
Type
Description
NDRSEL
7:6
w
FSK Noise Detector Range Selection
00B 2^7
01B 2^6
10B 2^5
11B 2^4
Reset: 0H
NDSEL
5:4
w
Signal and Noise Detector Selection
00B Signal detection (=Squelch) only. This mode is recommended for
ASK.
01B Noise detection only
10B Signal and noise detection simultaneously
11B Signal and noise detection simultaneously, but the FSK noise
detect signal is valid only if the SIGDETLO threshold is exceeded.
This is the recommended mode for FSK.
Reset: 0H
NDTL
3:2
w
FSK Noise Detector Threshold Level
00B 1/2
01B 3/8
10B 1/4
11B 1/8
Reset: 1H
NDPDSR
1:0
w
FSK Noise Detector - Peak Detector Slew Rate
00B 1/256
01B 1/128
10B 1/64
11B 1/32
Reset: 3H
Clock and Data Recovery P Configuration Register
A_CDRP
Offset
Clock and Data Recovery P Configuration
Register
046H
Data Sheet
211
Reset Value
E6H
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
3'65
3+'(1
3+'(1
39$/
36$7
Z
Z
Z
Z
Z
Field
Bits
Type
Description
PDSR
7:6
w
Peak-Detector slew rate. The slew rate of the Peak-Detector in the
clock-recovery path will be set with
PDSR. Actually, Peak-Detector part of Signal Detector Block
00B up/down = 1/64
01B up = 1/64; down = 1/128
10B up = 1/32; down = 1/128
11B up = 1/32; down = 1/256
Reset: 3H
PHDEN1
5
w
Phase detector error (PDE) outer tolerance range
0B
Disabled: PDEout = PDEin.
1B
Enabled: If PDEin > abs(7/16) bit then PDEout = 0 else PDEout =
PDEin.
Reset: 1H
PHDEN0
4
w
Phase detector error (PDE) inner tolerance range
0B
Disabled: PDEout = PDEin.
1B
Enabled: If PDEin < abs(1/16) bit then PDEout = 0 else PDEout =
PDEin.
Reset: 0H
PVAL
3:2
w
P Value. The PVAL is the P value of the Clock-Recovery PI LoopFilter. The PhaseDetector output error will be multiplied with the set value.
00B 1/1 phase detector error
01B 1/2 phase detector error
10B 1/4 phase detector error
11B 1/8 phase detector error
Reset: 1H
PSAT
1:0
w
P Value Saturation. The saturation of the P-Loop-Filter path will be
set according to the PSAT
value. Remark that the internal phase resolution of the phase detector is
1/16 bit.
00B saturation to 1/16 bit
01B saturation to 2/16 bit
10B saturation to 4/16 bit
11B saturation to 8/16 bit
Reset: 2H
Clock and Data Recovery Configuration Register
Data Sheet
212
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
A_CDRI
Offset
Clock and Data Recovery Configuration
Register
Reset Value
047H
65H
&256$7
/)6$7
,9$/
,6$7
Z
Z
Z
Z
Field
Bits
Type
Description
CORSAT
7:6
w
Correlator output value (Timing extrapolation unit). The timing
extrapolation unit output value will be multiplied with the LFSAT
value. The timing extrapolation unit measures the data rate error during
the
RUNIN sequence and sets the I-Loop-Filter path when the RUNIN length
is
reached.
00B 1/4 calculated value
01B 1/8 calculated value
10B 1/16 calculated value
11B 1/32 calculated value
Reset: 1H
LFSAT
5:4
w
Loop Filter Saturation. The saturation of the I-Loop-Filter path will
be set according to the LFSAT
value.Remark that the internal phase resolution of the phase detector is
1/16 bit.
00B saturation to 1/32 bit
01B saturation to 1/16 bit
10B saturation to 2/16 bit
11B saturation to 4/16 bit
Reset: 2H
IVAL
3:2
w
I Value. The IVAL is the I value of the Clock-Recovery PI Loop-Filter.
The PhaseDetector output error will be multiplied with this set value.
00B 1/32 phase detector error
01B 1/64 phase detector error
10B 1/128 phase detector error
11B 1/256 phase detector error
Reset: 1H
Data Sheet
213
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
ISAT
1:0
w
I Value Saturation. The saturation of the I-Loop-Filter accumulator
will be set according to the
ISAT value. Remark that the internal phase resolution of the phase
detector is 1/16 bit.
00B saturation to 1/16 bit
01B saturation to 2/16 bit
10B saturation to 4/16 bit
11B saturation to 8/16 bit
Reset: 1H
Clock and Data Recovery RUNIN Configuration Register
A_CDRRI
Offset
Clock and Data Recovery RUNIN
Configuration Register
Reset Value
048H
01H
8186('
'5/,0(1
581/(1
Z
Z
Field
Bits
Type
Description
UNUSED
7:3
-
UNUSED
Reset: 00H
DRLIMEN
2
w
Enable data rate error acceptance limitation.
The limits are defined in CDRDRTHRP and CDRDRTHRN registers.
0B
Disabled
1B
Enabled
Reset: 0H
RUNLEN
1:0
w
RUNIN Length. The RUNIN length is equal to PLL-start-value
calculation time. This means
that the shorter RUNIN length decreases the data rate offset calculation
accuracy and symbol synchronization found signal generation stability.
Note that the RUNLEN have to be changed together with the TSI
configuration registers.
00B 8 chips
01B 7 chips
10B 6 chips
11B 5 chips
Reset: 1H
CDR DC Chip Tolerance Register
Data Sheet
214
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
A_CDRTOLC
Offset
CDR DC Chip Tolerance Register
Reset Value
049H
0CH
8186('
72/&+,3+
72/&+,3/
Z
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
TOLCHIPH
5:3
w
Duty Cycle Tolerance for Chip Border High Level. Represents the
number of 1/16 bit sample deviation from the ideal chip border
where an edge can occur in direction to the following chip border.
Reset: 1H
TOLCHIPL
2:0
w
Duty Cycle Tolerance for Chip Border Low Level. Represents the
number of 1/16 bit sample deviation from the ideal chip border
where an edge can occur in direction to the previous chip border.
Reset: 4H
CDR DC Bit Tolerance Register
A_CDRTOLB
Offset
Reset Value
CDR DC Bit Tolerance Register
04AH
1EH
8186('
72/%,7+
72/%,7/
Z
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
TOLBITH
5:3
w
Duty Cycle Tolerance for Bit Border High Level. Represents the
number of 1/16 bit sample deviation from the ideal bit border where
an edge can occur in direction to the following bit border.
Reset: 3H
TOLBITL
2:0
w
Duty Cycle Tolerance for Bit Border Low Level. Represents the
number of 1/16 bit sample deviation from the ideal bit border where
an edge can occur in direction to the previous bit border.
Reset: 6H
Data Sheet
215
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Timing Violation Window Register
A_TVWIN
Offset
Reset Value
Timing Violation Window Register
04BH
28H
79:,1
Z
Field
Bits
Type
Description
TVWIN
7:0
w
Timing Violation Window Length.
Defines the maximal number of 1/16 data samples without detected edge
which will be tolerated by CDR with no Loss of Symbol Synchronization
28h: 40/16 bit ((8 + 16 *CV + 8)*1.25)
FFh: 255/16 bit
Note: in TSIGAP mode the value must be higher.
Reset: 28H
Slicer Configuration Register
A_SLCCFG
Offset
Reset Value
Slicer Configuration Register
04CH
90H
6/&&)*
Z
Field
Bits
Type
Description
SLCCFG
7:0
w
Data Slicer Configuration
Value 90H : Chip Mode EOM-CV: For patterns with code violations in data
packet and optimized for activated EOM code violation criterion (and
optional EOM data length criterion)
Value 94H : Chip Mode EOM-Datalength: For patterns with code
violations in data packet and optimized for activated EOM data length
criterion only (EOMDATLEN)
Value 95H : Chip Mode Transparent: When Framer is not used, but
CH_DATA / CH_STR are used for data processing
Value 75H : Bit Mode: Only for patterns without Code Violations
Reset: 90H
Data Sheet
216
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
TSI Detection Mode Register
A_TSIMODE
Offset
Reset Value
TSI Detection Mode Register
04DH
80H
76,*56<
1
76,:&$
&3+5$
76,'(702'
Z
Z
Z
Z
Field
Bits
Type
Description
TSIGRSYN
7
w
TSI Gap Resync Mode (only for TSIDETMODE=2H)
0B
Disabled - In this mode the GAPVAL and TSIGAP values are used,
so the overall GAP time can be
defined in T/16 steps.
1B
Enabled - PLL resync after TSI Gap
In this mode the T/2 GAP resolution can be set in the 5 MSB
TSIGAP register bits.
GAPVAL value is not used. Prefered in TSI Gap Mode.
Reset: 1H
TSIWCA
6:3
w
Wild Cards for 4 LSB chips of Correlator A
If all 4 chips are 0, the whole TSI pattern for Correlator A is valid
if a chip is 1, the corresponding chip from the TSI pattern is ignored
Reset: 0H
CPHRA
2
w
Code Phase Readjustment in Payload
0B
disabled - code polarity is defined by the TSI pattern
1B
enabled - code phase readjustment in payload
Reset: 0H
TSIDETMOD
1:0
w
TSI Detection Mode
00B 16 Bit TSI Mode - TSI configuration B AND A valid (sequentially),
B is valid if A_TSILENA=16 (=10H) and the A_TSILENB > 0
01B 8 Bit Parallel TSI Mode - TSI configurations A OR B (parallel)
10B 8 Bit TSI Gap Mode - TSI configurations A AND B with Gap
(sequentially with Gap between TSIA & TSIB)
11B 8 Bit Extended TSI Mode - TSI configurations A OR B (parallel with
matching information), dependent on found TSI A or B, 0 resp. 1 will
be sent as 1st received bit.
Reset: 0H
TSI Length Register A
A_TSILENA
TSI Length Register A
Data Sheet
Offset
04EH
217
Reset Value
00H
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
8186('
76,/(1$
Z
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
TSILENA
4:0
w
TSI A Length (in chips):
(11H up to 1FH not used)
Min: 01 = 1 Chip; Be aware that such small values makes it
impossible to find the right phase of the pattern in the data stream and
therefore wrong data and code violations can be generated.
Max: 10h = 16 Chips = 8 Bit
Reset: 00H
TSI Length Register B
A_TSILENB
Offset
TSI Length Register B
Reset Value
04FH
00H
8186('
76,/(1%
Z
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
TSILENB
4:0
w
TSI B Length (in chips):
(11H up to 1FH not used)
Min:
For 16 Bit TSI Mode:
Min: 00h = 0 Chip (see also A_TSILENA)
For all other TSI Modes:
Min: 01h = 1 Chip (see also A_TSILENA)
Max: 10h = 16 Chips = 8 Bit
Reset: 00H
TSI Gap Length Register
Data Sheet
218
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
A_TSIGAP
Offset
TSI Gap Length Register
Reset Value
050H
00H
76,*$3
*$39$/
Z
Z
Field
Bits
Type
Description
TSIGAP
7:3
w
TSI Gap (T/2 bit resolution)
1Fh: 15 1/2 bit gap
00h: 0 bit gap
TSIGAP is used to lock the PLL after TSI A is found, if the TSI detection
mode 10b is selected.
Reset: 00H
GAPVAL
2:0
w
TSI Gap (T/16 bit resolution)
111b: 7/16 bit gap
000b: 0 bit gap
GAPVAL is used to correct the DCO phase after TSIGAP time, if
A_TSIMODE.TSIGRSYN is disabled
Reset: 0H
TSI Pattern Data Reference A Register 0
A_TSIPTA0
Offset
TSI Pattern Data Reference A Register 0
Reset Value
051H
00H
76,37$
Z
Field
Bits
Type
Description
TSIPTA0
7:0
w
Data Pattern for TSI comparison: Bit 7...Bit 0(LSB) (in Chips)
Reset: 00H
TSI Pattern Data Reference A Register 1
A_TSIPTA1
Offset
TSI Pattern Data Reference A Register 1
052H
Data Sheet
219
Reset Value
00H
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
76,37$
Z
Field
Bits
Type
Description
TSIPTA1
7:0
w
Data Pattern for TSI comparison: Bit 15(MSB)...Bit 8 (in Chips)
Reset: 00H
TSI Pattern Data Reference B Register 0
A_TSIPTB0
Offset
TSI Pattern Data Reference B Register 0
Reset Value
053H
00H
76,37%
Z
Field
Bits
Type
Description
TSIPTB0
7:0
w
Data Pattern for TSI comparison: Bit 7...Bit 0(LSB) (in Chips)
Reset: 00H
TSI Pattern Data Reference B Register 1
A_TSIPTB1
Offset
TSI Pattern Data Reference B Register 1
Reset Value
054H
00H
76,37%
Z
Field
Bits
Type
Description
TSIPTB1
7:0
w
Data Pattern for TSI comparison: Bit 15(MSB)...Bit 8 (in Chips)
Reset: 00H
End Of Message Control Register
Data Sheet
220
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
A_EOMC
Offset
End Of Message Control Register
Reset Value
055H
05H
8186('
5HV
(206</2
(20&9
(20'$7/
(1
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
EOMSYLO
2
w
EOM by Sync Loss
0B
Disabled
1B
Enabled
Reset: 1H
EOMCV
1
w
EOM by Code Violation
0B
Disabled
1B
Enabled
Reset: 0H
EOMDATLEN
0
w
EOM by Data Length
0B
Disabled
1B
Enabled
Reset: 1H
EOM Data Length Limit Register
A_EOMDLEN
EOM Data Length Limit Register
Offset
Reset Value
056H
00H
'$7/(1
Z
Data Sheet
221
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
DATLEN
7:0
w
Length of Data Field in Telegram, only valid when EOM criterion is
EOMDATLEN
Counting of number of payload bits starts after the last TSI Bit. EOM will
be generated after the last payload bit.
In 8-bit extended TSI mode, the value must be the payload length + 1,
because of the additional bit inserted (matching information).
Min: 00h = 256 payload bits
Reg. value 01h = 1 payload bit
Max: FFh = 255 payload bits
Reset: 00H
EOM Data Length Limit Parallel Mode Register
A_EOMDLENP
Offset
EOM Data Length Limit Parallel Mode
Register
Reset Value
057H
00H
'$7/(13
Z
Field
Bits
Type
Description
DATLENP
7:0
w
Length of Data Field in Telegram in Parallel Mode for TSI Pattern B,
only valid when EOM criterion is EOMDATLEN
Counting of number of payload bits starts after the last TSI Bit. EOM will
be generated after the last payload bit.
In 8-bit extended TSI mode, the value must be the payload length + 1,
because of the additional bit inserted (matching information).
Min: 00h = 256 payload bits
Reg. value 01h = 1 payload bit
Max: FFh = 255 payload bits
Reset: 00H
Channel Configuration Register
A_CHCFG
Offset
Channel Configuration Register
058H
Data Sheet
222
Reset Value
04H
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
8186('
(;7352&
(20630
8186('
12&
07
Z
Z
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
EXTPROC
6:5
w
External Data Processing
00B No deactivation of functional blocks
01B Chip Data (RX Mode: TMCDS)
- no framing
- FSYNC, MID and EOM interrupts disabled
- only TOTIM_SYNC is active
- random, equal and pattern WU are disabled (mapped to sync)
10B Data + Data MF (RX Mode: TMMF, TMRDS)
- no framing
- FSYNC, MID and EOM interrupts disabled
- all TOTIMs are inactive
- only WU on RSSI (Level Criterion) possible
11B not used
Reset: 0H
EOM2SPM
4
w
Continue with Self Polling Mode after EOM detected in Run Mode
Self Polling
0B
Disabled - stay in Run Mode Self Polling (next Payload Frame is
expected)
1B
Enabled - leave Run Mode Self Polling after EOM
Reset: 0H
UNUSED
3
w
UNUSED
Reset: 0H
NOC
2
w
Number of Channels (Run Mode Slave / Self Polling Mode - Run
Mode Self Polling)
0B
Channel 1 / Channel 1
1B
Channel 1 / Channel 1
Reset: 1H
MT
1:0
w
Modulation Type (Run Mode Slave / Self Polling Mode - Run Mode
Self Polling)
00B ASK / ASK - ASK
01B FSK / FSK - FSK
10B ASK / FSK - ASK
11B FSK / ASK - FSK
Reset: 0H
PLL MMD Integer Value Register Channel 1
Data Sheet
223
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
A_PLLINTC1
Offset
PLL MMD Integer Value Register Channel 1
Reset Value
059H
93H
%$1'6(/
3//,17&
Z
Z
Field
Bits
Type
Description
BANDSEL
7:6
w
Frequency Band Selection
00B not used
01B 915MHz/868MHz
10B 434MHz
11B 315MHz
Reset: 2H
PLLINTC1
5:0
w
SDPLL Multi Modulus Divider Integer Offset value for Channel 1
PLLINT(5:0) = dec2hex(INT(f_LO / f_XTAL))
Reset: 13H
PLL Fractional Division Ratio Register 0 Channel 1
A_PLLFRAC0C1
Offset
Reset Value
PLL Fractional Division Ratio Register 0
Channel 1
05AH
F3H
3//)5$&&
Z
Field
Bits
PLLFRAC0C1 7:0
Type
Description
w
Synthesizer channel frequency value (21 bits, bits 7:0), fractional
division ratio for Channel 1
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: F3H
PLL Fractional Division Ratio Register 1 Channel 1
A_PLLFRAC1C1
Offset
Reset Value
PLL Fractional Division Ratio Register 1
Channel 1
05BH
07H
Data Sheet
224
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
3//)5$&&
Z
Field
Bits
PLLFRAC1C1 7:0
Type
Description
w
Synthesizer channel frequency value (21 bits, bits 15:8), fractional
division ratio for Channel 1
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 07H
PLL Fractional Division Ratio Register 2 Channel 1
A_PLLFRAC2C1
Offset
Reset Value
PLL Fractional Division Ratio Register 2
Channel 1
05CH
09H
8186('
3//)&20
3&
3//)5$&&
Z
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
PLLFCOMPC1 5
w
Fractional Spurii Compensation enable for Channel 1
0B
Disabled
1B
Enabled
Reset: 0H
PLLFRAC2C1 4:0
w
Synthesizer channel frequency value (21 bits, bits 20:16), fractional
division ratio for Channel 1
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 09H
Special Function Register Page Register
SFRPAGE
Offset
Special Function Register Page Register
080H
Data Sheet
225
Reset Value
00H
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
8186('
6)53$*(
Z
Field
Bits
Type
Description
UNUSED
7:1
-
UNUSED
Reset: 00H
SFRPAGE
0
w
Selection of Register Page File (Configuration A..D) for SPI
communication
0B
Page 0 (Config. A, start address: 000H)
1B
Page 1 (Config. B, start address: 100H)
Reset: 0H
PP0 and PP1 Configuration Register
PPCFG0
Offset
PP0 and PP1 Configuration Register
Reset Value
081H
50H
33&)*
33&)*
Z
Z
Field
Bits
Type
Description
PP1CFG
7:4
w
Port Pin 1 Output Signal Selection
0000B CLK_OUT
0001B RX_RUN
0010B NINT
0011B LOW
0100B HIGH
0101B DATA
0110B DATA_MATCHFIL
0111B n.u.
1000B CH_DATA
1001B CH_STR
1010B RXD
1011B RXSTR
1100B n.u.
1101B n.u.
1110B n.u.
1111B n.u.
Reset: 5H
Data Sheet
226
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
PP0CFG
3:0
w
Port Pin 0 Output Signal Selection
0000B CLK_OUT
0001B RX_RUN
0010B NINT
0011B LOW
0100B HIGH
0101B DATA
0110B DATA_MATCHFIL
0111B n.u.
1000B CH_DATA
1001B CH_STR
1010B RXD
1011B RXSTR
1100B n.u.
1101B n.u.
1110B n.u.
1111B n.u.
Reset: 0H
PP2 and PP3 Configuration Register
PPCFG1
Offset
PP2 and PP3 Configuration Register
Data Sheet
Reset Value
082H
12H
33&)*
33&)*
Z
Z
227
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
PP3CFG
7:4
w
Port Pin 3 Output Signal Selection
0000B n.u.
0001B RX_RUN
0010B NINT
0011B LOW
0100B HIGH
0101B DATA
0110B DATA_MATCHFIL
0111B n.u.
1000B CH_DATA
1001B CH_STR
1010B RXD
1011B RXSTR
1100B n.u.
1101B n.u.
1110B n.u.
1111B n.u.
Reset: 1H
PP2CFG
3:0
w
Port Pin 2 Output Signal Selection
0000B CLK_OUT
0001B RX_RUN
0010B NINT
0011B LOW
0100B HIGH
0101B DATA
0110B DATA_MATCHFIL
0111B n.u.
1000B CH_DATA
1001B CH_STR
1010B RXD
1011B RXSTR
1100B n.u.
1101B n.u.
1110B n.u.
1111B n.u.
Reset: 2H
PPx Port Configuration Register
PPCFG2
Offset
PPx Port Configuration Register
083H
Data Sheet
228
Reset Value
00H
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
33+33(
1
33+33(
1
33+33(
1
33+33(
1
33,19
33,19
33,19
33,19
Z
Z
Z
Z
Z
Z
Z
Z
Field
Bits
Type
Description
PP3HPPEN
7
w
PP3 High Power Pad Enable
0B
Normal
1B
High Power
Reset: 0H
PP2HPPEN
6
w
PP2 High Power Pad Enable
0B
Normal
1B
High Power
Reset: 0H
PP1HPPEN
5
w
PP1 High Power Pad Enable
0B
Normal
1B
High Power
Reset: 0H
PP0HPPEN
4
w
PP0 High Power Pad Enable
0B
Normal
1B
High Power
Reset: 0H
PP3INV
3
w
PP3 Inversion Enable
0B
Not Inverted
1B
Inverted
Reset: 0H
PP2INV
2
w
PP2 Inversion Enable
0B
Not Inverted
1B
Inverted
Reset: 0H
PP1INV
1
w
PP1 Inversion Enable
0B
Not Inverted
1B
Inverted
Reset: 0H
PP0INV
0
w
PP0 Inversion Enable
0B
Not Inverted
1B
Inverted
Reset: 0H
RX RUN Configuration Register 0
RXRUNCFG0
Offset
RX RUN Configuration Register 0
084H
Data Sheet
229
Reset Value
FFH
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
8186('
5;58133
%
5;58133
$
Z
Z
Z
8186('
5;58133
%
5;58133
$
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7:6
w
UNUSED
Reset: 3H
RXRUNPP1B
5
w
RXRUN Active Level on PP1 for Configuration B
0B
Active Low
1B
Active High
Reset: 1H
RXRUNPP1A
4
w
RXRUN Active Level on PP1 for Configuration A
0B
Active Low
1B
Active High
Reset: 1H
UNUSED
3:2
w
UNUSED
Reset: 3H
RXRUNPP0B
1
w
RXRUN Active Level on PP0 for Configuration B
0B
Active Low
1B
Active High
Reset: 1H
RXRUNPP0A
0
w
RXRUN Active Level on PP0 for Configuration A
0B
Active Low
1B
Active High
Reset: 1H
RX RUN Configuration Register 1
RXRUNCFG1
Offset
RX RUN Configuration Register 1
085H
8186('
5;58133
%
5;58133
$
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7:6
w
UNUSED
Reset: 3H
Data Sheet
Reset Value
FFH
230
8186('
5;58133
%
5;58133
$
Z
Z
Z
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
RXRUNPP3B
5
w
RXRUN Active Level on PP3 for Configuration B
0B
Active Low
1B
Active High
Reset: 1H
RXRUNPP3A
4
w
RXRUN Active Level on PP3 for Configuration A
0B
Active Low
1B
Active High
Reset: 1H
UNUSED
3:2
w
UNUSED
Reset: 3H
RXRUNPP2B
1
w
RXRUN Active Level on PP2 for Configuration B
0B
Active Low
1B
Active High
Reset: 1H
RXRUNPP2A
0
w
RXRUN Active Level on PP2 for Configuration A
0B
Active Low
1B
Active High
Reset: 1H
Clock Divider Register 0
CLKOUT0
Offset
Clock Divider Register 0
Reset Value
086H
0BH
&/.287
Z
Field
Bits
Type
Description
CLKOUT0
7:0
w
Clock Out Divider: CLKOUT(19:0) = CLKOUT2(MSB) & CLKOUT1 &
CLKOUT0(LSB)
Min: 00002h = Clock divided by 2*2
Max: FFFFFh = Clock divided by ((2^20)-1)*2
Reg. value 00000h = Clock divided by (2^20)*2
Reset: 0BH
Clock Divider Register 1
CLKOUT1
Offset
Clock Divider Register 1
087H
Data Sheet
231
Reset Value
00H
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
&/.287
Z
Field
Bits
Type
Description
CLKOUT1
7:0
w
Clock Out Divider: CLKOUT(19:0) = CLKOUT2(MSB) & CLKOUT1 &
CLKOUT0(LSB)
Min: 00002h = Clock divided by 2*2
Max: FFFFFh = Clock divided by ((2^20)-1)*2
Reg. value 00000h = Clock divided by (2^20)*2
Reset: 00H
Clock Divider Register 2
CLKOUT2
Offset
Clock Divider Register 2
Reset Value
088H
00H
8186('
&/.287
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
CLKOUT2
3:0
w
Clock Out Divider: CLKOUT(19:0) = CLKOUT2(MSB) & CLKOUT1 &
CLKOUT0(LSB)
Min: 00002h = Clock divided by 2*2
Max: FFFFFh = Clock divided by ((2^20)-1)*2
Reg. value 00000h = Clock divided by (2^20)*2
Reset: 0H
RF Control Register
RFC
Offset
RF Control Register
089H
Data Sheet
232
Reset Value
07H
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
8186('
5)2))
,)$77
Z
Z
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
RFOFF
4
w
Switch off RF-path (for RSSI trimming)
0B
RF path enabled
1B
RF path disabled
Reset: 0H
IFATT
3:0
w
Adjust IF attenuation from LNA_IN to IF_OUT (Double-Down
Conversion / Single-Down Conversion)
Used to trim out external component tolerances.
0000B 0 dB / n.u.
0001B 0.8 dB / n.u.
0010B 1.6 dB / n.u.
0011B 2.4 dB / n.u.
0100B 3.2 dB / 0 dB
0101B 4.0 dB / 0.8 dB
0110B 4.8 dB / 1.6 dB
0111B 5.6 dB / 2.4 dB
1000B 6.4 dB / 3.2 dB
1001B 7.2 dB / 4.0 dB
1010B 8.0 dB / 4.8 dB
1011B 8.8 dB / n.u.
1100B 9.6 dB / n.u.
1101B 10.4 dB / n.u.
1110B 11.2 dB / n.u.
1111B 12.0 dB / n.u.
Reset: 7H
BPF Calibration Configuration Register 0
BPFCALCFG0
Offset
Reset Value
BPF Calibration Configuration Register 0
08AH
07H
8186('
5HV
%3)&$/67
Data Sheet
Z
233
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
BPFCALST
3:0
w
BPF Calibration Time (use default = 07H)
Min: 0h= Txtal * 80 * 7 * (0 + 4)
Max: Fh= Txtal * 80 * 7 * (15 + 4)
Reset: 7H
BPF Calibration Configuration Register 1
BPFCALCFG1
Offset
Reset Value
BPF Calibration Configuration Register 1
08BH
04H
8186('
%3)&$/%:
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
BPFCALBW
5:0
-
Band Pass Filter Bandwidth Selection during Calibration
04H - 50 kHz (=default)
0DH - 80 kHz
16H - 125 kHz
1FH - 200 kHz
27H - 300 kHz
Reset: 04H
XTAL Coarse Calibration Register
XTALCAL0
Offset
Reset Value
XTAL Coarse Calibration Register
08CH
10H
Data Sheet
8186('
;7$/6:&
Z
234
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
XTALSWC
4:0
w
Xtal Trim Capacitor Value
Min 00h: 0pF
Value 01h: 1pF
Max 18h: 24pF
higher values than 18h are automatically mapped to 24pF
Reset: 10H
XTAL Fine Calibration Register
XTALCAL1
Offset
Reset Value
XTAL Fine Calibration Register
08DH
00H
8186('
;7$/6:)
;7$/6:)
;7$/6:)
;7$/6:)
Z
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
XTALSWF3
3
w
Connect 500 fF XTAL Trim capacitor
0B
not connected
1B
connected
Reset: 0H
XTALSWF2
2
w
Connect 250 fF XTAL Trim capacitor
0B
not connected
1B
connected
Reset: 0H
XTALSWF1
1
w
Connect 125 fF XTAL Trim capacitor
0B
not connected
1B
connected
Reset: 0H
XTALSWF0
0
w
Connect 62.5 fF XTAL Trim capacitor
0B
not connected
1B
connected
Reset: 0H
RSSI Monitor Configuration Register
Data Sheet
235
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
RSSIMONC
Offset
RSSI Monitor Configuration Register
Reset Value
08EH
01H
566,021
(1
5HV
8186('
Z
Field
Bits
Type
Description
UNUSED
7:3
-
UNUSED
Reset: 00H
RSSIMONEN
0
w
Enable Buffer for RSSI pin
0B
Disabled
1B
Enabled
Reset: 1H
ADC Input Selection Register
ADCINSEL
Offset
ADC Input Selection Register
Reset Value
08FH
00H
8186('
$'&,16(/
Z
Field
Bits
Type
Description
UNUSED
7:3
-
UNUSED
Reset: 00H
ADCINSEL
2:0
w
ADC Input Selection
000B RSSI
001B Temperature
010B VDDD / 2
011B n.u.
100B n.u.
101B n.u.
110B n.u.
111B n.u.
Reset: 0H
RSSI Offset Register
Data Sheet
236
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
RSSIOFFS
Offset
RSSI Offset Register
Reset Value
090H
80H
566,2))6
Z
Field
Bits
Type
Description
RSSIOFFS
7:0
w
RSSI Offset Compensation Value
Min: 00h= -256
Max: FFh= 254
Reset: 80H
RSSI Slope Register
RSSISLOPE
Offset
RSSI Slope Register
Reset Value
091H
80H
566,6/23(
Z
Field
Bits
Type
Description
RSSISLOPE
7:0
w
RSSI Slope Compensation Value (Multiplication Value)
Multiplication Factor = RSSISLOPE * 2^-7
Min: 00h= 0.0
Max: FFh= 1.992
Reset: 80H
CDR Data Rate Acceptance Positive Threshold Register
CDRDRTHRP
Offset
CDR Data Rate Acceptance Positive
Threshold Register
092H
Data Sheet
237
Reset Value
1EH
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
&'5'57+53
Z
Field
Bits
CDRDRTHRP 7:0
Type
Description
w
Data Rate Acceptance Positive Threshold Value
This feature can be turned on with *_CDRRI.DRLIMEN.
Higher the value, more percent of the datarate is tolerated.
Default => 10%
Reset: 1EH
CDR Data Rate Acceptance Negative Threshold Register
CDRDRTHRN
Offset
CDR Data Rate Acceptance Negative
Threshold Register
Reset Value
093H
23H
&'5'57+51
Z
Field
Bits
CDRDRTHRN 7:0
Type
Description
w
Data Rate Acceptance Negative Threshold Value
This feature can be turned on with *_CDRRI.DRLIMEN.
Higher the value, more percent of the datarate is tolerated.
Default => 10%
Reset: 23H
Interrupt Mask Register 0
IM0
Offset
Interrupt Mask Register 0
Reset Value
094H
00H
,0(20%
,00,')%
,0)6<1&
%
,0:8%
,0(20$
,00,')$
,0)6<1&
$
,0:8$
Z
Z
Z
Z
Z
Z
Z
Z
Data Sheet
238
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
IMEOMB
7
w
Mask Interrupt on "End of Message" for Configuration B
0B
Interrupt enabled
1B
Interrupt disabled
Reset: 0H
IMMIDFB
6
w
Mask Interrupt on "Message ID Found" for Configuration B
0B
Interrupt enabled
1B
Interrupt disabled
Reset: 0H
IMFSYNCB
5
w
Mask Interrupt on "Frame Sync" for Configuration B
0B
Interrupt enabled
1B
Interrupt disabled
Reset: 0H
IMWUB
4
w
Mask Interrupt on "Wake-up" for Configuration B
0B
Interrupt enabled
1B
Interrupt disabled
Reset: 0H
IMEOMA
3
w
Mask Interrupt on "End of Message" for Configuration A
0B
Interrupt enabled
1B
Interrupt disabled
Reset: 0H
IMMIDFA
2
w
Mask Interrupt on "Message ID Found" for Configuration A
0B
Interrupt enabled
1B
Interrupt disabled
Reset: 0H
IMFSYNCA
1
w
Mask Interrupt on "Frame Sync" for Configuration A
0B
Interrupt enabled
1B
Interrupt disabled
Reset: 0H
IMWUA
0
w
Mask Interrupt on "Wake-up" for Configuration A
0B
Interrupt enabled
1B
Interrupt disabled
Reset: 0H
Self Polling Mode Active Periods Register
SPMAP
Offset
Self Polling Mode Active Periods Register
Data Sheet
Reset Value
096H
01H
8186('
630$3
Z
239
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
SPMAP
4:0
w
Self Polling Mode Active Periods value
Min: 01h = 1 (Master) Period
Max: 1Fh = 31(Master) Periods
Reg. value 00h = 32 (Master) Periods
Reset: 01H
Self Polling Mode Idle Periods Register
SPMIP
Offset
Self Polling Mode Idle Periods Register
Reset Value
097H
01H
630,3
Z
Field
Bits
Type
Description
SPMIP
7:0
w
Self Polling Mode Idle Periods value
Min: 01h = 1 (Master) Period
Max: FFh = 255 (Master) Periods
Reg. value 00h = 256 (Master) Periods
Reset: 01H
Self Polling Mode Control Register
SPMC
Offset
Self Polling Mode Control Register
098H
00H
8186('
630$,(1
6306(/
Z
Z
Field
Bits
Type
Description
UNUSED
7:3
-
UNUSED
Reset: 00H
Data Sheet
Reset Value
240
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
SPMAIEN
2
w
Self Polling Mode Active Idle Enable
0B
Disabled
1B
Enabled
Reset: 0H
SPMSEL
1:0
w
Self Polling Mode Selection
00B Constant On/Off (COO)
01B Fast Fall Back to Sleep (FFB)
10B Mixed Mode (MM, Combination of Const On/Off and Fast Fall Back
to Sleep for different Configurations: COO, FFB, FFB, FFB)
11B Permanent Wake Up Search (PWUS)
Reset: 0H
Self Polling Mode Reference Timer Register
SPMRT
Offset
Self Polling Mode Reference Timer Register
Reset Value
099H
01H
63057
Z
Field
Bits
Type
Description
SPMRT
7:0
w
Self Polling Mode Reference Timer value
The output of this timer is used as input for the On/Off Timer
Incoming Periodic Time = 64 / fsys
Output Periodic Time = TRT = (64 * SPMRT) / fsys
Min: 01h = (64*1) / fsys
Max: 00h = (64 * 256) / fsys
Reset: 01H
Self Polling Mode Off Time Register 0
SPMOFFT0
Offset
Reset Value
Self Polling Mode Off Time Register 0
09AH
01H
6302))7
Z
Data Sheet
241
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
SPMOFFT0
7:0
w
Self Polling Mode Off Time value: SPMOFFT(13:0) =
SPMOFFT1(MSB) & SPMOFFT0(LSB)
Off -Time = TRT * SPMOFFT
Min: 0001h = 1 * TRT
Reg.Value 3FFFh = 16383 * TRT
Max: 0000h = 16384 * TRT
Reset: 01H
Self Polling Mode Off Time Register 1
SPMOFFT1
Offset
Reset Value
Self Polling Mode Off Time Register 1
09BH
00H
8186('
6302))7
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
SPMOFFT1
5:0
w
Self Polling Mode Off Time value: SPMOFFT(13:0) =
SPMOFFT1(MSB) & SPMOFFT0(LSB)
Off -Time = TRT * SPMOFFT
Min: 0001h = 1 * TRT
Reg.Value 3FFFh = 16383 * TRT
Max: 0000h = 16384 * TRT
Reset: 00H
Self Polling Mode On Time Config A Register 0
SPMONTA0
Offset
Reset Value
Self Polling Mode On Time Config A Register
0
09CH
01H
630217$
Z
Data Sheet
242
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
SPMONTA0
7:0
w
Set Value Self Polling Mode On Time: SPMONTA(13:0) =
SPMONTA1(MSB) & SPMONTA0(LSB)
On-Time = TRT *SPMONTA
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 01H
Self Polling Mode On Time Config A Register 1
SPMONTA1
Offset
Reset Value
Self Polling Mode On Time Config A Register
1
09DH
00H
8186('
630217$
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
SPMONTA1
5:0
w
Set Value Self Polling Mode On Time: SPMONTA(13:0) =
SPMONTA1(MSB) & SPMONTA0(LSB)
On-Time = TRT *SPMONTA
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 00H
Self Polling Mode On Time Config B Register 0
SPMONTB0
Self Polling Mode On Time Config B Register
0
Offset
Reset Value
09EH
01H
630217%
Z
Data Sheet
243
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
SPMONTB0
7:0
w
Set Value Self Polling Mode On Time: SPMONTB(13:0) =
SPMONTB1(MSB) & SPMONTB0(LSB)
On-Time = TRT *SPMONTB
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 01H
Self Polling Mode On Time Config B Register 1
SPMONTB1
Offset
Self Polling Mode On Time Config B Register
1
Reset Value
09FH
00H
8186('
630217%
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
SPMONTB1
5:0
w
Set Value Self Polling Mode On Time: SPMONTB(13:0) =
SPMONTB1(MSB) & SPMONTB0(LSB)
On-Time = TRT *SPMONTB
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 00H
External Processing Command Register
EXTPCMD
Offset
Reset Value
External Processing Command Register
0A4H
00H
5HV
Data Sheet
8186('
$*&0$1)
$)&0$1)
(;7727,
0
(;7(20
ZF
ZF
ZF
ZF
244
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
6:4
-
UNUSED
Reset: 0H
AGCMANF
3
wc
AGC Manual Freeze
When *_AGCSFCFG.AGCFREEZE set to SPI Command, this bit sets the
AGC to freeze mode
0B
Inactive
1B
Active
Reset: 0H
AFCMANF
2
wc
AFC Manual Freeze
When *_AFCSFCFG.AFCFREEZE set to SPI Command, this bit sets the
AFC to freeze mode
0B
Inactive
1B
Active
Reset: 0H
EXTTOTIM
1
wc
Force TOTIM signal in external data processing mode
(*_CHCFG.EXTROC = 1H or 2H)
0B
no external TOTIM signal forced
1B
external TOTIM signal forced
Reset: 0H
EXTEOM
0
wc
Force EOM signal in external data processing mode
(*_CHCFG.EXTROC = 1H or 2H)
0B
no external EOM signal forced
1B
external EOM signal forced
Reset: 0H
Chip Mode Control Register 1
CMC1
Offset
Reset Value
Chip Mode Control Register 1
0A5H
04H
8186('
(201&)
*
727,01
&+
,1,7),)
2
)6,1,7)
,)2
),)2/.
;7$/+30
6
Z
Z
Z
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
EOM2NCFG
5
w
Continue with next Configuration in Self Polling Mode after EOM
detected in Run Mode Self Polling
0B
Continue with Configuration A in Self Polling Mode
1B
Continue with next Configuration in Self Polling Mode
Reset: 0H
Data Sheet
245
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
TOTIM2NCH
4
w
Continue with next Configuration in Self Polling Mode after TOTIM
detected in Run Mode Self Polling.
0B
Continue with Configuration A in Self Polling Mode
1B
Continue with next Configuration in Self Polling Mode
Reset: 0H
INITFIFO
3
w
Initialization of FIFO at Cycle Start
This Initialization of the FIFO can be configured in both Run Mode Slave
and Self Polling Mode. In Run Mode Slave this happens at the beginning.
In Self Polling Mode the initialization is done after Wake up found
(switching from Self Polling Mode to Run Mode Self Polling).
0B
Initialization disabled
1B
Initialization enabled
Reset: 0H
FSINITFIFO
2
w
Initialization of FIFO at Frame Start
0B
Initialization disabled
1B
Initialization enabled
Reset: 1H
FIFOLK
1
w
Lock Data FIFO at EOM
0B
FIFO lock is disabled
1B
FIFO lock is enabled at EOM. This also locks the digital receive
chain at EOM until release from FIFO lock state.
Reset: 0H
XTALHPMS
0
w
XTAL High Precision Mode in Sleep Mode
0B
Disabled
1B
Enabled
Reset: 0H
Chip Mode Control Register 0
CMC0
Offset
Reset Value
Chip Mode Control Register 0
0A6H
10H
6'2+33(
1
,1,73//
+2/'
+2/'
&/.287(
1
8186('
0&6
6/5;(1
06(/
Z
Z
Z
Z
Z
Z
Z
Z
Field
Bits
Type
Description
SDOHPPEN
7
w
SDO High Power Pad Enable
0B
Normal
1B
High Power
Reset: 0H
Data Sheet
246
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
INITPLLHOLD 6
w
Init PLL after coming from HOLD (when new channel programmed).
This requires an additional Channel Hop Time before initialization of the
Digital Receiver.
0B
No init of PLL
1B
Init of PLL
Reset: 0H
HOLD
5
w
Holds the chip in the Register Configuration state (only in Run Mode
Slave)
0B
Normal Operation
1B
Jump into the Register Config state Hold
Reset: 0H
CLKOUTEN
4
w
CLK_OUT Enable
0B
Disabled
1B
Enable programmable clock output
Reset: 1H
UNUSED
3
w
UNUSED
Reset: 0H
MCS
2
w
Multi Configuration Selection (Run Mode Slave / Self Polling Mode)
0B
Config A / Config A
1B
Config B / Config A + B
Reset: 0H
SLRXEN
1
w
Slave Receiver Enable
This Bit is only used in Operating Mode Run Mode Slave / Sleep Mode
0B
Receiver is in Sleep Mode
1B
Receiver is in Run Mode Slave
Reset: 0H
MSEL
0
w
Operating Mode Selection
0B
Run Mode Slave / Sleep Mode
1B
Self Polling Mode
Reset: 0H
Wakeup Peak Detector Readout Register
RSSIPWU
Offset
Reset Value
Wakeup Peak Detector Readout Register
0A7H
00H
566,3:8
Data Sheet
247
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
RSSIPWU
7:0
-
Peak Detector Level at Wakeup
Set at every WU event and also set at the end of every
configuration/channel cycle within a Self Polling period.
Cleared at Reset only.
Reset: 00H
Interrupt Status Register 0
IS0
Offset
Reset Value
Interrupt Status Register 0
0A8H
FFH
(20%
0,')%
)6<1&%
:8%
(20$
0,')$
)6<1&$
:8$
UF
UF
UF
UF
UF
UF
UF
UF
Field
Bits
Type
Description
EOMB
7
rc
Interrupt Request by "End of Message" from Configuration B (Reset
event sets all Bits to 1)
0B
Not detected
1B
Detected
Reset: 1H
MIDFB
6
rc
Interrupt Request by "Message ID Found" from Configuration B
(Reset event sets all Bits to 1)
0B
Not detected
1B
Detected
Reset: 1H
FSYNCB
5
rc
Interrupt Request by "Frame Sync" from Configuration B (Reset
event sets all Bits to 1)
0B
Not detected
1B
Detected
Reset: 1H
WUB
4
rc
Interrupt Request by "Wake Up" from Configuration B (Reset event
sets all Bits to 1)
0B
Not detected
1B
Detected
Reset: 1H
EOMA
3
rc
Interrupt Request by "End of Message" from Configuration A (Reset
event sets all Bits to 1)
0B
Not detected
1B
Detected
Reset: 1H
Data Sheet
248
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
MIDFA
2
rc
Interrupt Request by "Message ID Found" from Configuration A
(Reset event sets all Bits to 1)
0B
Not detected
1B
Detected
Reset: 1H
FSYNCA
1
rc
Interrupt Request by "Frame Sync" from Configuration A (Reset
event sets all Bits to 1)
0B
Not detected
1B
Detected
Reset: 1H
WUA
0
rc
Interrupt Request by "Wake Up" from Configuration A (Reset event
sets all Bits to 1)
0B
Not detected
1B
Detected
Reset: 1H
RF PLL Actual Channel and Configuration Register
RFPLLACC
Offset
Reset Value
RF PLL Actual Channel and Configuration
Register
0AAH
00H
3/'/(1
8186('
5063$&)
*
8186('
5063$&
8186('
630$&
U
U
U
U
U
U
U
Field
Bits
Type
Description
PLDLEN
7:6
r
Payload Data Length stored at TSI detection of the next message,
PLDLEN(9:0) = RFPLLACC.PLDLEN(MSB) & PLDLEN(LSB).
Cleared with INIT FIFO
Min. 000h = 0 bits received
Max. 3FFh = 1023 bits received
Reset: 0H
UNUSED
5
r
UNUSED
Reset: 0H
RMSPACFG
4
r
RF PLL Run Mode Self Polling Actual Configuration
0B
Configuration A
1B
Configuration B
Reset: 0H
UNUSED
3
r
UNUSED
Reset: 0H
Data Sheet
249
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
RMSPAC
2
r
RF PLL Run Mode Self Polling Actual Channel
0B
No valid data in FIFO from any channel and configuration
1B
Data in FIFO belong to Channel 1
Reset: 0H
UNUSED
1
r
UNUSED
Reset: 0H
SPMAC
0
r
RF PLL Self Polling Mode Actual Channel
0B
No Wake Up from any Channel was actually found
1B
Wake Up was found from Channel 1
Reset: 0H
RSSI Peak Detector Readout Register
RSSIPRX
Offset
Reset Value
RSSI Peak Detector Readout Register
0ABH
00H
566,35;
UF
Field
Bits
Type
Description
RSSIPRX
7:0
rc
RSSI Peak Level during Receiving
Tracking is active when Digital Receiver is enabled
Set at higher peak levels than stored
Cleared at Reset and SPI read out
Reset: 00H
RSSI Payload Peak Detector Readout Register
RSSIPPL
Offset
Reset Value
RSSI Payload Peak Detector Readout
Register
0ACH
00H
566,33/
U
Data Sheet
250
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
RSSIPPL
7:0
r
RSSI Peak Level during Payload
Tracking starts after FSYNC + PKBITPOS
Set at every EOM
Cleared at the Reset only
Reset: 00H
Payload Data Length Register
PLDLEN
Offset
Reset Value
Payload Data Length Register
0ADH
00H
3/'/(1
U
Field
Bits
Type
Description
PLDLEN
7:0
r
Payload Data Length stored at TSI detection of the next message,
PLDLEN(9:0) = RFPLLACC.PLDLEN(MSB) & PLDLEN(LSB).
Cleared with INIT FIFO
Min. 000h = 0 bits received
Max. 3FFh = 1023 bits received
Reset: 00H
ADC Result High Byte Register
ADCRESH
Offset
Reset Value
ADC Result High Byte Register
0AEH
00H
$'&5(6+
UF
Field
Bits
Type
Description
ADCRESH
7:0
rc
ADC Result Value ADCRES(9:0) = ADCRESH(7:0) & ADCRESL(1:0)
Note: RC for control signal generation only, no clear
Reset: 00H
Data Sheet
251
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
ADC Result Low Byte Register
ADCRESL
Offset
Reset Value
ADC Result Low Byte Register
0AFH
00H
8186('
$'&(2&
$'&5(6/
U
U
Field
Bits
Type
Description
UNUSED
7:3
-
UNUSED
Reset: 00H
ADCEOC
2
r
ADC End of Conversion detected
0B
not detected
1B
detected
Reset: 0H
ADCRESL
1:0
r
ADC Result Value ADCRES(9:0) = ADCRESH(7:0) & ADCRESL(1:0)
The 2 LSBs of the ADC result are captured when the SFR register
ADCRESH is readout.
Reset: 0H
VCO Autocalibration Result Readout Register
VACRES
Offset
Reset Value
VCO Autocalibration Result Readout
Register
0B0H
00H
5HV
8186('
9$&5(6
U
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
VACRES
3:0
r
VCO Autocalibration Result
Returns the VCO range selected by VCO Autocalibration
Reset: 0H
AFC Offset Read Register
Data Sheet
252
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
AFCOFFSET
Offset
Reset Value
AFC Offset Read Register
0B1H
00H
$)&2))6
U
Field
Bits
Type
Description
AFCOFFS
7:0
r
Readout of the Frequency Offset found by AFC (AFC loop filter
output).
Value is in signed representation.
Frequency resolution is 2.68 kHz/digit
Output can be limited by x_AFCLIMIT register
Update rate is 548 kHz
Reset: 00H
AGC Gain Readout Register
AGCGAINR
Offset
Reset Value
AGC Gain Readout Register
0B2H
00H
8186('
,)*$,1
0,;*$,
1
U
U
Field
Bits
Type
Description
UNUSED
7:3
-
UNUSED
Reset: 00H
IF2GAIN
2:1
r
AGC IF2 Gain Readout
00B 0 dB
01B -15 dB
10B -30 dB
11B n.u.
Reset: 0H
MIX2GAIN
0
r
AGC MIX2 Gain Readout
0B
0 dB
1B
-15 dB
Reset: 0H
SPI Address Tracer Register
Data Sheet
253
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
SPIAT
Offset
Reset Value
SPI Address Tracer Register
0B3H
00H
63,$7
U
Field
Bits
Type
Description
SPIAT
7:0
r
SPI Address Tracer, Readout of the last address of a SFR Register
written by SPI
Reset: 00H
SPI Data Tracer Register
SPIDT
Offset
Reset Value
SPI Data Tracer Register
0B4H
00H
63,'7
U
Field
Bits
Type
Description
SPIDT
7:0
r
SPI Data Tracer, Readout of the last written data to a SFR Register
by SPI
Reset: 00H
SPI Checksum Register
SPICHKSUM
Offset
Reset Value
SPI Checksum Register
0B5H
00H
63,&+.680
UF
Data Sheet
254
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
SPICHKSUM
7:0
rc
SPI Checksum Readout
Reset: 00H
Serial Number Register 0
SN0
Offset
Reset Value
Serial Number Register 0
0B6H
00H
61
U
Field
Bits
Type
Description
SN0
7:0
r
Serial Number: SN(31:0) = SN3(MSB) & SN2 & SN1 & SN0(LSB)
Reset: 00H
Serial Number Register 1
SN1
Offset
Reset Value
Serial Number Register 1
0B7H
00H
61
U
Field
Bits
Type
Description
SN1
7:0
r
Serial Number: SN(31:0) = SN3(MSB) & SN2 & SN1 & SN0(LSB)
Reset: 00H
Serial Number Register 2
SN2
Offset
Reset Value
Serial Number Register 2
0B8H
00H
Data Sheet
255
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
61
U
Field
Bits
Type
Description
SN2
7:0
r
Serial Number: SN(31:0) = SN3(MSB) & SN2 & SN1 & SN0(LSB)
Reset: 00H
Serial Number Register 3
SN3
Offset
Reset Value
Serial Number Register 3
0B9H
00H
61
U
Field
Bits
Type
Description
SN3
7:0
r
Serial Number: SN(31:0) = SN3(MSB) & SN2 & SN1 & SN0(LSB)
Reset: 00H
RSSI Readout Register
RSSIRX
Offset
Reset Value
RSSI Readout Register
0BAH
00H
566,5;
U
Field
Bits
Type
Description
RSSIRX
7:0
r
RSSI value after averaging over 4 samples
Reset: 00H
RSSI Peak Memory Filter Readout Register
Data Sheet
256
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
RSSIPMF
Offset
Reset Value
RSSI Peak Memory Filter Readout Register
0BBH
00H
566,30)
Field
Bits
Type
Description
RSSIPMF
7:0
-
RSSI Peak Memory Filter Level
Reset: 00H
Signal Power Readout Register
SPWR
Offset
Reset Value
Signal Power Readout Register
0BCH
00H
63:5
U
Field
Bits
Type
Description
SPWR
7:0
r
Signal Power
The register contains the actual signal power which should be used to
calculate the value of x_SIGDET0, x_SIGDET1 and x_SIGDETLO
registers
Reset: 00H
Noise Power Readout Register
NPWR
Offset
Reset Value
Noise Power Readout Register
0BDH
00H
13:5
U
Data Sheet
257
V1.0, 2010-02-19
TDA5235
Appendix
Register Description
Field
Bits
Type
Description
NPWR
7:0
r
FSK Noise Power
The register contains the actual noise power which should be used to
calculate the value for the x_NDTHRES register
Reset: 00H
Data Sheet
258
V1.0, 2010-02-19
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG