SSC7150 Motion Coprocessor Product Features Hardware Features • • • • • The hardware features in the SSC7150 motion coprocessor include the following: High Performance 32-bit Embedded Controller Low power 7.65mA (typ) in active mode System in deep sleep consumes 70μA (typ) 3.3-Volt I/O Package - 6mm x 6mm, 28-pin QFN Sensor Firmware • Sensor fusion firmware features include: - Self-contained 9-axis sensor fusion - Sensor data pass-through - Fast in-use background calibration of all sensors and calibration monitor - Magnetic immunity: Enhanced magnetic distortion detection and suppression - Gyroscope drift cancellation • Easy to implement complete turnkey sensor fusion solution • Sensor power management • Sensors Supported - Bosch BMC150 Geomagnetic Sensor/Accelerometer - Bosch BMG160 Gyroscope 2015 Microchip Technology Inc. • Two I2C Controllers - Supports I2C bus speeds to 400kHz - Host Interface Supports Slave Operation - Sensor Interface Supports Master Operation • Low Power Modes Target Markets • Remote Controls, Gaming • Fitness Monitoring • Internet of Things Applications Description The SSC7150 motion coprocessor is a low-power, flexible, turnkey solution. SSC7150 makes implementing sensor fusion easy for motion-based embedded applications. Microchip created this solution, enabling faster time to market without the need for sensor-fusion expertise. The SSC7150 is extremely efficient. Low average current while running complex sensor-fusion algorithms results in lower power consumption for multiple applications. DS00001885A-page 1 SSC7150 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at [email protected]. We welcome your feedback. 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SSC7150 Table of Contents 1.0 Pin Configuration ............................................................................................................................................................................ 4 2.0 System Block Diagram .................................................................................................................................................................. 10 3.0 Guidelines for Getting Started ....................................................................................................................................................... 11 4.0 Electrical Characteristics ............................................................................................................................................................... 14 Appendix A: Revision History .............................................................................................................................................................. 25 The Microchip Web Site ...................................................................................................................................................................... 26 Customer Change Notification Service ............................................................................................................................................... 26 Customer Support ............................................................................................................................................................................... 26 Product Identification System ............................................................................................................................................................. 27 2015 Microchip Technology Inc. DS00001885A-page 3 SSC7150 1.0 PIN CONFIGURATION 1.1 Description The Pin Configuration chapter includes a Pin Diagram, Pin List, Pin Description and Package Details. Terminology and Symbols for Pins/Buffers Term # The ‘#’ sign at the end of a signal name indicates an active-low signal. Pin Diagram 28 PIN QFN PIN DIAGRAM Note: 26 25 24 23 28 27 NC I2C2_RESET# MCLR# FIGURE 1-1: AVDD AVSS NC VSS 1.3 Definition 22 1.2 19 NC I2C_CL2 4 18 NC VSS 5 17 VCAP NC 6 16 VSS I2C_D2_WAKE# 7 15 I2C_DA1 14 3 I2C_CL1 VDD I2C_DA2 10 11 12 13 20 VDD NC VSS I2C2_ALERT# 21 2 8 9 1 NC I2C2_WAKE VSENSOR_EN NC NC The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS00001885A-page 4 2015 Microchip Technology Inc. SSC7150 1.4 Pin List The Pin List is shown in Table 1-1. TABLE 1-1: SSC7150 28 QFN PIN CONFIGURATION 28 QFN Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1.4.1 Pin Name NC NC I2C_DA2 I2C_CL2 VSS NC I2C_D2_WAKE# I2C2_WAKE VSENSOR_EN VDD NC VSS I2C2_ALERT# I2C_CL1 I2C_DA1 VSS VCAP NC NC VDD NC VSS NC AVSS AVDD MCLR# I2C2_RESET# NC FIVE VOLT TOLERANT PINS Table 1-2 lists the 5 Volt tolerant pins in the SSC7150. All other pins in the device are 3.3V only. TABLE 1-2: 5V-TOLERANT PINS Pin Number 13 14 15 26 2015 Microchip Technology Inc. Pin Name I2C2_ALERT# I2C_CL1 I2C_DA1 MCLR# DS00001885A-page 5 SSC7150 1.5 1.5.1 Pin Description OVERVIEW The following tables describe the signal functions in the SSC7150 pin configuration. See Section 1.6, "Notes for Tables in this Chapter," on page 7 for notes that are referenced in the Pin Description tables. 1.5.2 HOST INTERFACE The SSC7150 can be used with an I2C host interface. The pins required for each interface are shown in Table 1-3 and Table 1-4. See the associated Notes for board connection information for the unused interface. TABLE 1-3: I2C HOST INTERFACE I2C Inte rfa ce S igna ls P in Re f. Num be r S igna l Na m e 4 I2C_CL2 3 I2C_DA 2 13 7 I2C_D2_W A K E # 8 I2C2_W A K E Description I2C Controller Clock to Sensor Interface I2C Controller Data to Sensor Interface Notes I2C2_RE S E T# I2C SENSOR INTERFACE TABLE 1-4: I2C SENSOR INTERFACE I2C Sensor Interface Pin Ref. Number Signal Name 14 I2C_CL1 I2C_DA1 15 1.5.4 Note s I2C2_A LE RT# 27 1.5.3 De scription I2C Controller Cloc k to Hos t Interfac e I2C Controller Data to Hos t Interfac e A lert Interrupt s ignal from m otion c oproc es s or to Hos t. Us ed to tell Hos t data from m otion c oproc es s or is ready to be s ent out. A c tive low output. Us ed to wak e the m otion c oproc es s or from a low power s tate due to hos t I2C c om m unic ation. A c tive low input. Connec t to I2C_DA 2. Us ed to wak e m otion c oproc es s or from a S leep s tate. This s ignal m us t be driven high at leas t 11m s prior to s ending any I2C traffic to the m otion c oproc es s or. A c tive high input. Res et input. Us ed to res et the hos t I2C interfac e. MISCELLANEOUS FUNCTIONS TABLE 1-5: MISCELLANEOUS FUNCTIONS Miscellaneous Functions Pin Ref. Number Signal Name 26 MCLR# 9 VSENSOR_EN 1, 2, 6, 11, 18, 19, 21, NC 23, 28 DS00001885A-page 6 Description Master Clear (Reset) Input Sensor voltage switch control output. Pins labelled NC should be left unconnected on the board Notes Note 1 2015 Microchip Technology Inc. SSC7150 1.5.5 POWER INTERFACE TABLE 1-6: POWER INTERFACE Power Interface Pin Ref. Number 17 10, 20 5, 12, 16, 22 25 24 1.6 Note 1 Note 2 Signal Name VCAP VDD VSS AVDD AVSS Description Internal Voltage Regulator Capacitor VDD supply VDD associated ground AVDD supply AVDD associated ground Notes Note 2 Notes for Tables in this Chapter A pull-up to VDD is required on the MCLR# pin. Use a 10K ohm pull-up resistor. A low-ESR (1 Ohm) capacitor is required on the VCAP pin, which is used to stabilize the internal voltage regulator output. The VCAP pin must not be connected to VDD, and must have a CEFC capacitor, with at least a 6V rating, connected to ground. The type can be ceramic or tantalum. 2015 Microchip Technology Inc. DS00001885A-page 7 SSC7150 1.7 Package Details This section provides the technical details of the packages. /HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH0/±[PP%RG\>4)1@ ZLWKPP&RQWDFW/HQJWK 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D D2 EXPOSED PAD e E b E2 2 2 1 1 N K N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO+HLJKW $ 6WDQGRII $ &RQWDFW7KLFNQHVV $ 2YHUDOO:LGWK ( ([SRVHG3DG:LGWK ( 2YHUDOO/HQJWK ' ([SRVHG3DG/HQJWK %6& 5() %6& %6& ' &RQWDFW:LGWK E &RQWDFW/HQJWK / &RQWDFWWR([SRVHG3DG . ± 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 3DFNDJHLVVDZVLQJXODWHG 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ ± 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS00001885A-page 8 2015 Microchip Technology Inc. SSC7150 /HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH0/±[PP%RG\>4)1@ ZLWKPP&RQWDFW/HQJWK 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ 2015 Microchip Technology Inc. DS00001885A-page 9 SSC7150 2.0 SYSTEM BLOCK DIAGRAM The SSC7150 system block diagram is shown in Figure 2-1. FIGURE 2-1: SSC7150 SYSTEM BLOCK DIAGRAM Host Processor I2C2_RESET# 3D ACCELEROMETER I2C2_ALERT# I2C_DA2/ I2C_CL2 I2C2_WAKE 3D GYROSCOPE I2C_D2_WAKE# SSC7150 I2C_DA1/ I2C_CL1 VSENSOR_EN DS00001885A-page 10 9-AXIS SENSOR FUSION INPUTS 3D MAGNETOMETER Sensor Power 2015 Microchip Technology Inc. SSC7150 3.0 GUIDELINES FOR GETTING STARTED 3.1 Basic Connection Requirements Getting started with the SSC7150 requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • All VDD and VSS pins (see Section 3.2 “Decoupling Capacitors”) • All AVDD and AVSS pins, even if the ADC module is not used (see Section 3.2 “Decoupling Capacitors”). Note that there is no ADC support in this device. See Note below. • VCAP pin (see Section 3.3 “Capacitor on Internal Voltage Regulator (Vcap)”) • MCLR# pin (see Section 3.4 “Master Clear (MCLR#) Pin”) Note: The AVDD and AVSS pins must be connected, regardless of ADC use and the ADC voltage reference source. Refer to the following schematic for connection information: SSC7150 Sensor Hub Module, Assy. 6753, Schematic Revision 1.4. 3.2 Decoupling Capacitors The use of decoupling capacitors on power supply pins, such as VDD, VSS, AVDD and AVSS is required. See Figure 3-1. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A value of 0.1 µF (100 nF), 10-20V is recommended. The capacitor should be a low Equivalent Series Resistance (low-ESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is further recommended that ceramic capacitors be used. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended that the capacitors be placed on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. • Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF. • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance. 2015 Microchip Technology Inc. DS00001885A-page 11 SSC7150 FIGURE 3-1: RECOMMENDED MINIMUM CONNECTION R R1(3) MCLR# C(3) VCAP Tantalum or ceramic 10 µF ESR ≤ 3Ω(2) VDD SSC7150 VDD VSS 0.1 µF Ceramic AVSS 0.1 µF Ceramic AVDD VDD VSS 0.1 µF Ceramic Note 3.2.1 1: Aluminum or electrolytic capacitors should not be used. ESR ≤ 3W from -40ºC to 125ºC @ SYSCLK frequency (i.e., MIPS) 2: Recommended components. See Figure 3-2. BULK CAPACITORS The use of a bulk capacitor is recommended to improve power supply stability. Typical values range from 4.7 µF to 47 µF. This capacitor should be located as close to the device as possible. 3.3 3.3.1 Capacitor on Internal Voltage Regulator (VCAP) INTERNAL REGULATOR MODE A low-ESR (1 Ohm) capacitor is required on the VCAP pin, which is used to stabilize the internal voltage regulator output. The VCAP pin must not be connected to VDD, and must have a CEFC capacitor, with at least a 6V rating, connected to ground. The type can be ceramic or tantalum. Refer to Section 4.0 “Electrical Characteristics” for additional information on CEFC specifications. DS00001885A-page 12 2015 Microchip Technology Inc. SSC7150 3.4 Master Clear (MCLR#) Pin The MCLR# pin is the Device Reset pin. Pulling the MCLR# pin low generates a device Reset. Figure 3-2 illustrates a typical MCLR# circuit. FIGURE 3-2: MCLR# PIN CONNECTIONS VDD R 10k R1(1) MCLR# ICSP™ 0.1 µF(2) 1 5 4 2 3 6 C 1 kΩ VDD VSS NC SSC7150 PGECx(3) PGEDx(3) Recommended Components: Note 1: 470Ω ≤ R1 ≤ 1Ω will limit any current flowing into MCLR# from the external capacitor C, in the event of MCLR# pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). 2: The capacitor can be sized to prevent unintentional Resets from brief glitches or to extend the device Reset period during POR. 2015 Microchip Technology Inc. DS00001885A-page 13 SSC7150 4.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the SSC7150 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the SSC7150 devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings (See Note 1) Ambient temperature under bias ...............................................................................................................-40°C to +85°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3) ....................................... - 0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 2.3V (Note 3) ....................................... - 0.3V to +5.5V Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3) ....................................... - 0.3V to +3.6V Maximum current out of VSS pin(s) .......................................................................................................................300 mA Maximum current into VDD pin(s) (Note 2)........................................................................................................... 300 mA Maximum output current sunk by any I/O pin..........................................................................................................15 mA Maximum output current sourced by any I/O pin.....................................................................................................15 mA Maximum current sunk by all ports........................................................................................................................200 mA Maximum current sourced by all ports (Note 2) ....................................................................................................200 mA Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 4-1). 3: See the “Pin List” section for the 5V tolerant pins. DS00001885A-page 14 2015 Microchip Technology Inc. SSC7150 4.1 DC Characteristics TABLE 4-1: THERMAL OPERATING CONDITIONS Rating Symbol Min. Typical Max. Unit Industrial Temperature Devices Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD – S IOH) PD PINT + PI/O W PDMAX (TJ – TA)/θJA W I/O Pin Power Dissipation: I/O = S (({VDD – VOH} x IOH) + S (VOL x IOL)) Maximum Allowed Power Dissipation TABLE 4-2: THERMAL PACKAGING CHARACTERISTICS Characteristics Symbol Typical θJA Package Thermal Resistance, 28-pin QFN Note 1: Unit Notes — °C/W 1 35 Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations. TABLE 4-3: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS DC CHARACTERISTICS Param. No. Max. Symbol Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Characteristics Min. Typ. Max. Units Conditions Operating Voltage DC10 VDD Supply Voltage (Note 2) 2.3 — 3.6 V DC12 VDR RAM Data Retention Voltage (Note 1) 1.75 — — V DC16 VPOR VDD Start Voltage to Ensure Internal Power-on Reset Signal 1.75 — 2.1 V DC17 SVDD VDD Rise Rate to Ensure Internal Power-on Reset Signal 0.00005 — 0.115 Note 1: 2: This is the limit to which VDD can be lowered without losing RAM data. Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. Refer to parameter BO10 in Table 4-7 for BOR values. 2015 Microchip Technology Inc. — — — V/μs — DS00001885A-page 15 SSC7150 TABLE 4-4: DC CHARACTERISTICS: OPERATING/POWER-DOWN CURRENT DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Parameter Symbol Typical (3) No. Max. Units Conditions Operating/Power-Down Current (Note 1, 2) DC20 IPEAK 19.5 20.0 mA — DC30 IACTIVE 7.65 7.90 mA — DC40 IIDLE 1.77 1.95 mA — 70 150 μA — DC50 IPD Note 1: 2: A device’s supply current is mainly a function of the operating voltage and frequency, as well as temperature. The current measurements are as follows: • Peak current (IPEAK): This is the peak active current value when a sensor is actively providing environmental changes. • Active current (IACTIVE): This is the average operating current value when a sensor is actively providing environmental changes. • Idle current (IIDLE): This is the average idle current value when no sensor is actively providing environmental changes (and the device is not in power-down mode). • Power-Down current (IPD): This is the current value when the device is in power-down mode. This is the state entered when the Host issues the SET_POWER (Sleep) Command. Wakeup from power-down mode requires the I2C2_WAKE pin. 3: Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. DS00001885A-page 16 2015 Microchip Technology Inc. SSC7150 TABLE 4-5: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param. Symbol No. VIL Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature-40°C ≤ TA ≤ +85°C Min. Typical (1) Max. Units Conditions Input Low Voltage DI10 I/O Pins VSS — 0.2 VDD V DI18 I2C_DAx, I2C_CLx VSS — 0.3 VDD V I2C disabled (Note 4) DI19 I2C_DAx, I2C_CLx VSS — 0.8 V I2C enabled (Note 4) (Note 4,6) VIH Input High Voltage I/O Pins not 5V-tolerant (5) DI20 0.65 VDD — VDD V I/O Pins 5V-tolerant (5) 0.65 VDD — 5.5 V DI28 I2C_DAx, I2C_CLx 0.65 VDD — 5.5 V I2C disabled (Note 4,6) DI29 I2C_DAx, I2C_CLx 2.1 — 5.5 V I2C enabled, 2.3V ≤ VPIN ≤ 5.5 (Note 4,6) IIL Input Leakage Current (Note 3) DI50 I/O Ports — — +1 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance DI55 MCLR#(2) — — +1 μA VSS ≤ VPIN ≤ VDD Note 1: 2: 3: 4: 5: 6: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR# pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. This parameter is characterized, but not tested in manufacturing. See the “Pin List” section for the 5V-tolerant pins. The VIH specifications are only in relation to externally applied inputs, and not with respect to the userselectable internal pull-ups. External open drain input signals utilizing the internal pull-ups of the device are provided to be recognized only as a logic “high” internally to the device. For External “input” logic inputs that require a pull-up source, to ensure the minimum VIH of those components, it is recommended to use an external pull-up resistor rather than the internal pull-ups of the device. 2015 Microchip Technology Inc. DS00001885A-page 17 SSC7150 TABLE 4-6: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Param. Symbol DO10 Vol DO20 VOH Characteristic Min. Typ. Max. Units Conditions — — 0.4 V IOL ≤ 10 mA, VDD = 3.3V Output High Voltage 1.5 (1) — — V IOH ≥ -14 mA, VDD = 3.3V I/O Pins 2.0 (1) — — IOH ≥ -12 mA, VDD = 3.3V 2.4 — — IOH ≥ -10 mA, VDD = 3.3V 3.0 (1) — — IOH ≥ -7 mA, VDD = 3.3V Output Low Voltage I/O Pins Note 1: Parameters are characterized, but not tested. TABLE 4-7: ELECTRICAL CHARACTERISTICS: BROWN-OUT RESET (BOR) DC CHARACTERISTICS Param. No. BO10 Note 1: 2: Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Symbol Characteristics Min.(1) Typical Max. Units Conditions Vbor BOR Event on VDD transition high-to-low(2) 2.0 — 2.3 V — Parameters are for design guidance only and are not tested in manufacturing. Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. TABLE 4-8: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Param. No. Symbol Characteristics Min. Typical Max. Units Comments D321 Cefc External Filter Capacitor Value 8 10 — μF Capacitor must be low series resistance (1 ohm). Typical voltage on the VCAP pin is 1.8V. DS00001885A-page 18 2015 Microchip Technology Inc. SSC7150 4.2 AC Characteristics and Timing Parameters The information contained in this section defines SSC7150 AC characteristics and timing parameters. FIGURE 4-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 CL Pin RL VSS CL Pin RL=464Ω CL=50 pF for all pins VSS TABLE 4-9: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical (1) Max. Units DO56 CIO All I/O pins — — 50 pF DO58 CB I2C_DAx, I2C_CLx — — 400 pF Note 1: Conditions In I2C™ mode Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 4-2: POWER-ON RESET TIMING CHARACTERISTICS Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) SY00 (TPU) (Note 1) CPU Starts Fetching Code Internal Voltage Regulator Enabled Note 1: The power-up period will be extended if the power-up sequence completes before the device exits from BOR (VDD < VDDMIN). 2: Includes interval voltage regulator stabilization delay. 2015 Microchip Technology Inc. DS00001885A-page 19 SSC7150 FIGURE 4-3: EXTERNAL RESET TIMING CHARACTERISTICS Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) MCLR# TMCLR (SY20) BOR TBOR (SY30) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) TABLE 4-10: (TSYSDLY) SY02 RESET TIMING AC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Characteristics (1) Min. Typical (2) Max. Units Conditions SY00 TPU Power-up Period Internal Voltage Regulator Enabled — 400 600 μs — SY02 Tsysdly System Delay Period: Time Required to Reload Device Configuration Fuses plus SYSCLK(3) Delay before First instruction is Fetched. — 1 μs + 8 SYSCLK cycles — — — SY20 Tmclr MCLR# Pulse Width (low) 2 — — μs — SY30 TBOR BOR Pulse Width (low) — 1 — μs — Note 1: 2: 3: These parameters are characterized, but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested. SYSCLK is 48MHz DS00001885A-page 20 2015 Microchip Technology Inc. SSC7150 FIGURE 4-4: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) I2C_CLx IM31 IM34 IM30 IM33 I2C_DAx Stop Condition Start Condition Note: Refer to Figure 4-1 for load conditions. FIGURE 4-5: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 I2C_CLx IM11 IM26 IM10 IM25 IM33 I2C_DAx In IM40 IM40 IM45 I2C_DAx Out Note: Refer to Figure 4-1 for load conditions. 2015 Microchip Technology Inc. DS00001885A-page 21 SSC7150 TABLE 4-11: I2C BUS DATA TIMING REQUIREMENTS (MASTER MODE) AC CHARACTERISTICS Param. Symbol No. IM10 Min.(1) Max. Units Conditions TLO:SCL Clock Low Time 100 kHz mode TPB * (BRG + 2) — μs — 400 kHz mode TPB * (BRG + 2) — μs Clock High Time 100 kHz mode TPB * (BRG + 2) — μs 400 kHz mode TPB * (BRG + 2) — μs IM11 THI:SCL IM20 TF:SCL IM21 IM25 IM26 IM30 IM31 Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C TR:SCL Characteristics I2C_DAx and I2C_CLx Fall Time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns I2C_DAx and I2C_CLx Rise Time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns 100 kHz mode 250 — ns 400 kHz mode 100 — ns TSU:DAT Data Input Setup Time THD:DAT Data Input Hold Time 100 kHz mode 0 — μs 400 kHz mode 0 0.9 μs TSU:STA 100 kHz mode TPB * (BRG + 2) — μs 400 kHz mode TPB * (BRG + 2) — μs 100 kHz mode TPB * (BRG + 2) — μs 400 kHz mode TPB * (BRG + 2) — μs 100 kHz mode TPB * (BRG + 2) — μs Start Condition Setup Time THD:STA Start Condition Hold Time — CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF — — Only relevant for Repeated Start condition After this period, the first clock pulse is generated IM33 TSU:STO Stop Condition Setup Time 400 kHz mode TPB * (BRG + 2) — μs IM34 THD:STO Stop Condition Hold Time 100 kHz mode TPB * (BRG + 2) — ns 400 kHz mode TPB * (BRG + 2) — ns TAA:SCL 100 kHz mode — 3500 ns 400 kHz mode — 1000 ns 100 kHz mode 4.7 — μs 400 kHz mode 1.3 — μs The amount of time the bus must be free before a new transmission can start IM40 IM45 Output Valid from Clock TBF:SDA Bus Free Time — — — IM50 CB Bus Capacitive Loading — 400 pF — IM51 TPGD Pulse Gobbler Delay 52 312 ns See Note 2 Note 1: 2: BRG is the value of the I2C™ Baud Rate Generator. The typical value for this parameter is 104 ns. DS00001885A-page 22 2015 Microchip Technology Inc. SSC7150 FIGURE 4-6: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) I2C_CLx IS34 IS31 IS30 IS33 I2C_DAx Stop Condition Start Condition Note: Refer to Figure 4-1 for load conditions. FIGURE 4-7: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 I2C_CLx IS30 IS26 IS31 IS25 IS33 I2C_DAx In IS40 IS40 IS45 I2C_DAx Out Note: Refer to Figure 4-1 for load conditions. 2015 Microchip Technology Inc. DS00001885A-page 23 SSC7150 I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) TABLE 4-12: AC CHARACTERISTICS Param. No. Symbol IS10 TLO:SCL IS11 THI:SCL IS20 IS21 IS25 TF:SCL TR:SCL TSU:DAT IS26 THD:DAT IS30 TSU:STA IS31 THD:STA IS33 TSU:STO IS34 THD:STO IS40 IS45 IS50 TAA:SCL TBF:SDA CB DS00001885A-page 24 Characteristics Clock Low Time Clock High Time Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Min. Max. Units Conditions 100 kHz mode 4.7 — μs — 400 kHz mode 1.3 — μs — 100 kHz mode 4.0 — μs — 400 kHz mode 0.6 — μs — CB is specified to be from 10 to 400 pF I2C_DAx and I2C_CLx Fall Time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns I2C_DAx and I2C_CLx Rise Time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns Data Input Setup Time 100 kHz mode 250 — ns 400 kHz mode 100 — ns Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 μs Start Condition Setup Time 100 kHz mode 4700 — ns 400 kHz mode 600 — ns Start Condition Hold Time 100 kHz mode 4000 — ns 400 kHz mode 600 — ns Stop Condition Setup Time 100 kHz mode 4000 — ns 400 kHz mode 600 — ns Stop Condition Hold Time 100 kHz mode 4000 — ns 400 kHz mode 600 — ns 0 3500 ns 0 1000 ns 100 kHz mode 4.7 — μs 400 kHz mode 1.3 — μs The amount of time the bus must be free before a new transmission can start — 400 pF — Output Valid from 100 kHz mode Clock 400 kHz mode Bus Free Time Bus Capacitive Loading CB is specified to be from 10 to 400 pF — — Only relevant for Repeated Start condition After this period, the first clock pulse is generated — — — 2015 Microchip Technology Inc. SSC7150 APPENDIX A: TABLE A-1: REVISION HISTORY REVISION HISTORY Revision DS00001885A (01-30-15) 2015 Microchip Technology Inc. Section/Figure/Entry Correction Document Release DS00001885A-page 25 SSC7150 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support DS00001885A-page 26 2015 Microchip Technology Inc. SSC7150 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.(1) - Package Device Series Device: XXX(2) - XXX Sensor Fusion Firmware [X](3) - Tape and Reel Option Example: SSC7150-ML-AB0 = 28-QFN, Bosch 9-axis sensor fusion. SSC7150 (1) Package: ML = 28 pin QFN (2) Sensor Fusion Firmware: AB0 = Bosch 9-axis Sensor Fusion Note 1: Note 2: Tape and Reel Option: Blank = Tray packaging TR = Tape and Reel (3) Note 3: 2015 Microchip Technology Inc. These products meet the halogen maximum concentration values per IEC61249-2-21. All package options are RoHS compliant. For RoHS compliance and environmental information, please visit http://www.microchip.com/pagehandler/en-us/aboutus/ ehs.html . Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. DS00001885A-page 27 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 9781632770073 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == DS00001885A-page 28 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2015 Microchip Technology Inc. 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