FSPL230R, FSPL230F TM Data Sheet Radiation Hardened, SEGR Resistant N-Channel Power MOSFETs Intersil Star*Power Rad Hard MOSFETs have been specifically developed for high performance applications in a commercial or military space environment. Star*Power MOSFETs offer the system designer both extremely low rDS(ON) and Gate Charge allowing the development of low loss Power Subsystems. Star*Power FETs combine this electrical capability with total dose radiation hardness up to 300K RADs while maintaining the guaranteed performance for Single Event Effects (SEE) which the Intersil FS families have always featured. TM The Intersil portfolio of Star*Power FETs includes a family of devices in various voltage, current and package styles. The Star*Power family consists of Star*Power and Star*Power Gold products. Star*Power FETS are optimized for total dose and rDS(ON) performance while exhibiting SEE capability at full rated voltage up to an LET of 37. Star*Power Gold FETs have been optimized for SEE and Gate Charge providing SEE performance to 80% of the rated voltage for an LET of 82 with extremely low gate charge characteristics. This MOSFET is an enhancement-mode silicon-gate power field effect transistor of the vertical DMOS (VDMOS) structure. It is specifically designed and processed to be radiation tolerant. The MOSFET is well suited for applications exposed to radiation environments such as switching regulation, switching converters, power distribution, motor drives and relay drivers as well as other power control and conditioning applications. As with conventional MOSFETs these Radiation Hardened MOSFETs offer ease of voltage control, fast switching speeds and ability to parallel switching devices. June 2000 File Number 4865 Features • 9A, 200V, rDS(ON) = 0.170Ω • UIS Rated • Total Dose - Meets Pre-RAD Specifications to 100K RAD (Si) - Rated to 300K RAD (Si) • Single Event - Safe Operating Area Curve for Single Event Effects - SEE Immunity for LET of 36MeV/mg/cm2 with VDS up to 100% of Rated Breakdown and VGS of 10V Off-Bias • Dose Rate - Typically Survives 3E9 RAD (Si)/s at 80% BVDSS - Typically Survives 2E12 if Current Limited to IAS • Photo Current - 3.0nA Per-RAD (Si)/s Typically • Neutron - Maintain Pre-RAD Specifications for 1E13 Neutrons/cm2 - Usable to 1E14 Neutrons/cm2 Symbol D G S Packaging TO-205AF Reliability screening is available as either TXV or Space equivalent of MIL-S-19500. Formerly available as type TA45210W. Ordering Information RAD LEVEL SCREENING LEVEL PART NUMBER/BRAND 10K Engineering samples FSPL230D1 100K TXV FSPL230R3 100K Space FSPL230R4 300K TXV FSPL230F3 300K Space FSPL230F4 4-1 D G S CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 Star*Power™ is a trademark of Intersil Corporation. FSPL230R, FSPL230F Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified FSPL230R, FSPL230F UNITS 200 200 V V 9 5 29 ±30 A A A V 25 10 0.20 29 9 29 -55 to 150 300 W W W/ oC A A A oC oC 1.0 (Typical) g Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulsed Avalanche Current, L = 100µH (See Test Figure) . . . . . . . . . . . . . . . . . . . . . . . . . IAS Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL (Distance >0.063in (1.6mm) from Case, 10s Max) Weight (Typical) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL Drain to Source Breakdown Voltage Gate Threshold Voltage BVDSS VGS(TH) TEST CONDITIONS ID = 1mA, VGS = 0V VGS = VDS, ID = 1mA Zero Gate Voltage Drain Current IDSS VDS = 160V, VGS = 0V Gate to Source Leakage Current IGSS VGS = ±30V Drain to Source On-State Voltage VDS(ON) Drain to Source On Resistance Turn-On Delay Time rDS(ON)12 td(ON) Rise Time tr Turn-Off Delay Time td(OFF) Fall Time TC = -55oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC VGS = 12V, ID = 9A ID = 5A, VGS = 12V TC = 25oC TC = 125oC VDD = 100V, ID = 9A, RL = 11Ω, VGS = 12V, RGS = 7.5Ω tf Total Gate Charge Qg(12) Gate Charge Source VGS = 0V to 12V Qgs VDD = 100V, ID = 9A MIN TYP MAX UNITS 200 - - V - - 5.5 V 2.0 - 4.5 V 1.0 - - V - - 25 µA - - 250 µA - - 100 nA - - 200 nA - - 1.58 V - 0.145 0.170 Ω - - 0.313 Ω - - 20 ns - - 40 ns - - 35 ns - - 15 ns - 30 33 nC - 10 12 nC Gate Charge Drain Qgd - 8 10 nC Gate Charge at 20V Qg(20) VGS = 0V to 20V - 45 - nC Qg(TH) VGS = 0V to 2V - 3 - nC ID = 9A, VDS = 15V - 6.5 - V VDS = 25V, VGS = 0V, f = 1MHz - 1400 - pF - 230 - pF Threshold Gate Charge Plateau Voltage V(PLATEAU) Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS - 8 - pF Thermal Resistance Junction to Case RθJC - - 5.0 oC/W 4-2 FSPL230R, FSPL230F Source to Drain Diode Specifications PARAMETER Forward Voltage Reverse Recovery Time Reverse Recovery Charge SYMBOL VSD trr QRR TEST CONDITIONS ISD = 9A ISD = 9A, dISD/dt = 100A/µs MIN - MAX 1.5 210 - UNITS V ns µC TC = 25oC, Unless Otherwise Specified Electrical Specifications up to 300K RAD MIN PARAMETER TYP 1.2 SYMBOL TEST CONDITIONS MAX MIN 100K RAD MAX 300K RAD UNITS Drain to Source Breakdown Volts (Note 3) BVDSS VGS = 0, ID = 1mA 200 - 200 Gate to Source Threshold Volts (Note 3) VGS(TH) VGS = VDS, ID = 1mA 2.0 4.5 1.5 V Gate to Body Leakage (Notes 2, 3) IGSS VGS = ±30V, VDS = 0V - 100 Zero Gate Leakage (Note 3) IDSS VGS = 0, VDS = 160V - 25 Drain to Source On-State Volts (Notes 1, 3) VDS(ON) VGS = 12V, ID = 9A - 1.58 - 1.71 V Drain to Source On Resistance (Notes 1, 3) rDS(ON)12 VGS = 12V, ID = 5A - 0.170 - 0.185 Ω 4.5 V 100 nA 50 µA NOTES: 1. Pulse test, 300µs Max. 2. Absolute value. 3. Insitu Gamma bias must be sampled for both VGS = 12V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS . Single Event Effects (SEB, SEGR) Note 4 ENVIRONMENT (NOTE 5) TYPICAL LET (MeV/mg/cm) TYPICAL RANGE (µ) APPLIED VGS BIAS (V) (NOTE 6) MAXIMUM VDS BIAS (V) TEST SYMBOL ION SPECIES Single Event Effects Safe Operating Area SEESOA Br 37 36 -10 200 Br 37 36 -15 160 I 60 32 -2 200 I 60 32 -8 160 Au 82 28 0 160 Au 82 28 -5 120 NOTES: 4. Testing conducted at Brookhaven National Labs. 5. Fluence = 1E5 ions/cm2 (typical), T = 25oC. 6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR). Performance Curves Unless Otherwise Specified LET = 37MeV/mg/cm2, RANGE = 36µ LET = 60MeV/mg/cm2, RANGE = 32µ LET = 82MeV/mg/cm2, RANGE = 28µ LET = 37 BROMINE 200 FLUENCE = 1E5 IONS/cm2 (TYPICAL) 240 TEMP = 25oC 160 VDS 200 VDS (V) 240 160 120 120 80 LET = 82 GOLD 80 40 LET = 60 IODINE 40 0 0 0 0 -4 -8 -12 -16 -20 VGS (V) FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA 4-3 -5 -10 -15 -20 -25 VGS FIGURE 2. TYPICAL SEE SIGNATURE CURVE -30 FSPL230R, FSPL230F Performance Curves Unless Otherwise Specified (Continued) 1E-3 LIMITING INDUCTANCE (HENRY) 10 1E-4 ILM = 10A ID , DRAIN (A) 8 30A 1E-5 100A 300A 6 4 1E-6 2 1E-7 10 30 100 300 0 -50 1000 0 FIGURE 3. TYPICAL DRAIN INDUCTANCE REQUIRED TO LIMIT GAMMA DOT CURRENT TO IAS ID , DRAIN CURRENT (A) 100 50 150 100 TC , CASE TEMPERATURE (oC) DRAIN SUPPLY (V) FIGURE 4. MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE TC = 25oC 12V QG 10 100µs QGS QGD 1ms 1 VG 10ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0.1 1 10 100 1000 CHARGE VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 6. BASIC GATE CHARGE WAVEFORM 2.5 50 ID , DRAIN TO SOURCE CURRENT (A) FIGURE 5. FORWARD BIAS SAFE OPERATING AREA PULSE DURATION = 250ms, VGS = 12V, ID = 5A NORMALIZED rDS(ON) 2.0 1.5 1.0 0.5 0.0 -80 VGS = 14V VGS = 12V VGS = 10V VGS = 8V VGS = 6V 40 30 20 VGS = 6V 10 0 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 7. TYPICAL NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE 4-4 0 2 4 6 8 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 8. TYPICAL OUTPUT CHARACTERISTICS 10 FSPL230R, FSPL230F NORMALIZED THERMAL RESPONSE (ZθJC) Performance Curves Unless Otherwise Specified (Continued) 10 1 0.5 0.1 0.2 0.1 0.05 0.02 0.01 PDM SINGLE PULSE 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC + TC 0.001 10-5 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) t1 t2 100 101 FIGURE 9. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE IAS , AVALANCHE CURRENT (A) 100 STARTING TJ = 25oC 10 STARTING TJ = 150oC 1 IF R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) IF R ≠ 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] 0.1 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms) FIGURE 10. UNCLAMPED INDUCTIVE SWITCHING Test Circuits and Waveforms ELECTRONIC SWITCH OPENS WHEN IAS IS REACHED VDS L BVDSS + CURRENT I TRANSFORMER AS tP - VARY tP TO OBTAIN REQUIRED PEAK IAS VDD DUT tP VDD + 50Ω VGS ≤ 20V 0V VDS IAS 50V-150V 50Ω tAV FIGURE 11. UNCLAMPED ENERGY TEST CIRCUIT 4-5 FIGURE 12. UNCLAMPED ENERGY WAVEFORMS FSPL230R, FSPL230F Test Circuits and Waveforms tON VDD tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% VDS VGS = 12V 10% 10% DUT 0V 90% RGS 50% VGS 50% PULSE WIDTH 10% FIGURE 13. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 14. RESISTIVE SWITCHING WAVEFORMS Screening Information Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table). Delta Tests and Limits (JANTXV Equivalent, JANS Equivalent) TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MAX UNITS Gate to Source Leakage Current IGSS VGS = ±30V ±20 (Note 7) nA Zero Gate Voltage Drain Current IDSS VDS = 80% Rated Value ±25 (Note 7) µA Drain to Source On Resistance rDS(ON) TC = 25oC at Rated ID ±20% (Note 8) Ω Gate Threshold Voltage VGS(TH) ID = 1.0mA ±20% (Note 8) V NOTES: 7. Or 100% of Initial Reading (whichever is greater). 8. Of Initial Reading. Screening Information TEST JANTXV EQUIVALENT JANS EQUIVALENT Unclamped Inductive Switching VGS(PEAK) = 20V, L = 0.1mH; Limit = 29A VGS(PEAK) = 20V, L = 0.1mH; Limit = 29A Thermal Response tH = 10ms; VH = 25V; IH = 1A; LIMIT = 60mV tH = 10ms; VH = 25V; IH = 1A; LIMIT = 60mV Gate Stress VGS = 45V, t = 250µs VGS = 45V, t = 250µs Pind Optional Required Pre Burn-In Tests (Note 9) MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) Steady State Gate Bias (Gate Stress) MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours Interim Electrical Tests (Note 9) All Delta Parameters Listed in the Delta Tests and Limits Table All Delta Parameters Listed in the Delta Tests and Limits Table Steady State Reverse Bias (Drain Stress) MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 160 hours MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours PDA 10% 5% Final Electrical Tests (Note 9) MIL-S-19500, Group A, Subgroup 2 MIL-S-19500, Group A, Subgroups 2 and 3 NOTE: 9. Test limits are identical pre and post burn-in. Additional Tests PARAMETER SYMBOL TEST CONDITIONS MAX UNITS Safe Operating Area SOA VDS = 160V, t = 10ms 0.5 A Thermal Impedance ∆VSD tH = 500ms; VH =25V; IH = 1A 230 mV 4-6 FSPL230R, FSPL230F Rad Hard Data Packages - Intersil Power Transistors TXV Equivalent Class S - Equivalents 1. RAD HARD TXV EQUIVALENT - STANDARD DATA PACKAGE 1. RAD HARD “S” EQUIVALENT - STANDARD DATA PACKAGE A. Certificate of Compliance A. Certificate of Compliance B. Assembly Flow Chart B. Serialization Records C. Preconditioning - Attributes Data Sheet C. Assembly Flow Chart D. Group A - Attributes Data Sheet D. SEM Photos and Report E. Group B - Attributes Data Sheet F. Group C - Attributes Data Sheet G. Group D - Attributes Data Sheet E. Preconditioning - Attributes Data Sheet - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data 2. RAD HARD TXV EQUIVALENT - OPTIONAL DATA PACKAGE A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet - Pre and Post Burn-In Read and Record Data D. Group A - Attributes Data Sheet E. Group B - Attributes Data Sheet - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup B3) - Bond Strength Data (Subgroup B3) - Pre and Post High Temperature Operating Life Read and Record Data (Subgroup B6) F. Group C - Attributes Data Sheet - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup C6) - Bond Strength Data (Subgroup C6) G. Group D - Attributes Data Sheet - Pre and Post RAD Read and Record Data F. Group A G. Group B - Attributes Data Sheet H. Group C - Attributes Data Sheet I. Group D - Attributes Data Sheet 2. RAD HARD MAX. “S” EQUIVALENT - OPTIONAL DATA PACKAGE A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data - X-Ray and X-Ray Report F. Group A - Attributes Data Sheet - Subgroups A2, A3, A4, A5 and A7 Data G. Group B - Attributes Data Sheet - Subgroups B1, B3, B4, B5 and B6 Data H. Group C - Attributes Data Sheet - Subgroups C1, C2, C3 and C6 Data I. Group D 4-7 - Attributes Data Sheet - Attributes Data Sheet - Pre and Post Radiation Data FSPL230R, FSPL230F TO-205AF 3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE INCHES ØD ØD1 SYMBOL P A SEATING PLANE h L Øb e e1 2 e2 1 90o 3 45o j k MIN MILLIMETERS MAX MIN MAX NOTES A 0.160 0.180 4.07 4.57 - Øb 0.016 0.021 0.41 0.53 2, 3 ØD 0.350 0.370 8.89 9.39 - ØD1 0.315 0.335 8.01 8.50 - e 0.095 0.105 2.42 2.66 4 e1 0.190 0.210 4.83 5.33 4 e2 0.095 0.105 2.42 2.66 4 h 0.010 0.020 0.26 0.50 - j 0.028 0.034 0.72 0.86 - k 0.029 0.045 0.74 1.14 - L 0.500 0.560 12.70 14.22 3 P 0.075 - 1.91 - 5 NOTES: 1. These dimensions are within allowable dimensions of Rev. E of JEDEC TO-205AF outline dated 11-82. 2. Lead dimension (without solder). 3. Solder coating may vary along lead length, add typically 0.002 inches (0.05mm) for solder coating. 4. Position of lead to be measured 0.100 inches (2.54mm) from bottom of seating plane. 5. This zone controlled for automatic handling. The variation in actual diameter within this zone shall not exceed 0.010 inches (0.254mm). 6. Lead no. 3 butt welded to stem base. 7. Controlling dimension: Inch. 8. Revision 3 dated 6-94. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 4-8 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369