INTERSIL EL5174

EL5174, EL5374
®
Data Sheet
August 3, 2010
FN7313.7
550MHz Differential Twisted-Pair Drivers
Features
The EL5174 and EL5374 are single and triple high
bandwidth amplifiers with an output in differential form. They
are primarily targeted for applications such as driving
twisted-pair lines in component video applications. The
inputs can be in either single-ended or differential form but
the outputs are always in differential form.
• Fully differential inputs, outputs, and feedback
On the EL5174 and EL5374, two feedback inputs provide
the user with the ability to set the gain of each device (stable
at minimum gain of one). For a fixed gain of two, please see
the EL5173, EL5373 data sheet (FN7312).
The output common mode level for each channel is set by
the associated REF pin, which has a -3dB bandwidth of over
110MHz. Generally, these pins are grounded but can be tied
to any voltage reference.
All outputs are short circuit protected to withstand temporary
overload condition.
The EL5174 is available in a 8 Ld SOIC package and the
EL5374 is available in a 28 Ld QSOP package. All are specified
for operation over the full -40°C to +85°C temperature range.
Ordering Information
PART
NUMBER
PART
MARKING
TEMP.
RANGE
(°C)
• Differential input range ±2.3V
• 550MHz 3dB bandwidth
• 1100V/µs slew rate
• Low distortion at 5MHz
• Single 5V or dual ±5V supplies
• 60mA maximum output current
• Low power - 12.5mA per channel
• Pb-free available (RoHS compliant)
Applications
• Twisted-pair driver
• Differential line driver
• VGA over twisted-pair
• ADSL/HDSL driver
• Single-ended to differential amplification
• Transmission of analog signals in a noisy environment
PACKAGE
PKG.
DWG. #
EL5174IS*
5174IS
-40 to +85 8 Ld SOIC
MDP0027
EL5174ISZ*
(Note)
5174ISZ
-40 to +85 8 Ld SOIC
(Pb-Free)
MDP0027
EL5374IU*
EL5374IU
-40 to +85 28 Ld QSOP M28.15
EL5374IUZ*
(Note)
EL5374IUZ
-40 to +85 28 Ld QSOP M28.15
(Pb-Free)
*Add “-T7” or “-T13” suffix for tape and reel. Please refer to TB347
for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003-2005, 2007, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5174, EL5374
Pinouts
EL5374
(28 LD QSOP)
TOP VIEW
EL5174
(8 LD SOIC)
TOP VIEW
FBP 1
IN+ 2
REF 3
8 OUT+
+
-
FBN 4
NC 1
7 VS-
INP1 2
6 VS+
INN1 3
5 OUT-
REF1 4
+
-
27 FBP1
26 FBN1
25 OUT1B
NC 5
24 VSP
INP2 6
23 VSN
INN2 7
22 OUT2
REF2 8
NC 9
+
-
21 FBP2
20 FBN2
INP3 10
19 OUT2B
INN3 11
18 OUT3
REF3 12
NC 13
EN 14
2
28 OUT1
+
-
17 FBP3
16 FBN3
15 OUT3B
FN7313.7
August 3, 2010
EL5174, EL5374
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Supply Voltage Rate-of-rise (dV/dT) . . . . . . . . . . . . . . . . . . . . 1V/µs
Input Voltage (IN+, IN- to VS+, VS-). . . . . . VS- - 0.3V to VS+ + 0.3V
Differential Input Voltage (IN+ to IN-) . . . . . . . . . . . . . . . . . . . . ±4.8V
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . .
120.40
28 Ld QSOP Package . . . . . . . . . . . . . . . . . . . . . . .
77.61
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RLD = 1kΩ, RF = 0, RG = OPEN, CLD = 2.7pF, unless otherwise
specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Bandwidth
AV = 1, CLD = 2.7pF
550
MHz
AV = 2, RF = 500, CLD = 2.7pF
130
MHz
AV = 10, RF = 500, CLD = 2.7pF
20
MHz
BW
±0.1dB Bandwidth
AV = 1, CLD = 2.7pF
120
MHz
SR
Slew Rate (EL5174)
VOUT = 3VP-P, 20% to 80%
800
1100
V/µs
Slew Rate (EL5374)
VOUT = 3VP-P, 20% to 80%
600
850
V/µs
tSTL
Settling Time to 0.1%
VOUT = 2VP-P
10
ns
tOVR
Output Overdrive Recovery Time
20
ns
GBWP
Gain Bandwidth Product
200
MHz
VREFBW (-3dB) VREF -3dB Bandwidth
AV =1, CLD = 2.7pF
110
MHz
VREFSR+
VREF Slew Rate - Rise
VOUT = 2VP-P, 20% to 80%
134
V/µs
VREFSR-
VREF Slew Rate - Fall
VOUT = 2VP-P, 20% to 80%
70
V/µs
VN
Input Voltage Noise
at 10kHz
21
nV/√Hz
IN
Input Current Noise
at 10kHz
2.7
pA/√Hz
HD2
Second Harmonic Distortion
VOUT = 2VP-P, 5MHz
-95
dBc
VOUT = 2VP-P, 20MHz
-94
dBc
HD3
Third Harmonic Distortion
VOUT = 2VP-P, 5MHz
-88
dBc
VOUT = 2VP-P, 20MHz
-87
dBc
dG
Differential Gain at 3.58MHz
RLD = 300Ω, AV = 2
0.06
%
dθ
Differential Phase at 3.58MHz
RLD = 300Ω, AV = 2
0.13
°
eS
Channel Separation - for EL5374 only
at f = 1MHz
90
dB
INPUT CHARACTERISTICS
VOS
Input Referred Offset Voltage
IIN
Input Bias Current (VIN+, VIN-)
-30
IREF
Input Bias Current (VREF)
0.5
RIN
Differential Input Resistance
150
kΩ
CIN
Differential Input Capacitance
1
pF
(EL5174)
(EL5374)
3
±1.4
±25
mV
±2.2
±25
mV
-14
-7
µA
2.3
4
µA
FN7313.7
August 3, 2010
EL5174, EL5374
Electrical Specifications
VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RLD = 1kΩ, RF = 0, RG = OPEN, CLD = 2.7pF, unless otherwise
specified. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
±2.1
±2.3
±2.5
V
DMIR
Differential Mode Input Range
CMIR+
Common Mode Positive Input Range at VIN+, VIN-
3.4
V
CMIR-
Common Mode Negative Input Range at VIN+, VIN-
-4.3
V
VREFIN +
Positive Reference Input Voltage Range (EL5374)
VREFIN -
Negative Reference Input Voltage Range (EL5374) VIN+ = VIN- = 0V
-3.3
-3
V
VREFOS
Output Offset Relative to VREF (EL5374)
±50
±100
mV
CMRR
Input Common Mode Rejection Ratio (EL5374)
VIN = ±2.5V
65
78
Gain
Gain Accuracy
VIN = 1V (EL5174)
0.980
0.995
1.010
V
VIN = 1V (EL5374)
0.978
0.993
1.008
V
VIN+ = VIN- = 0V
3.4
3.7
V
dB
OUTPUT CHARACTERISTICS
VOUT
Output Voltage Swing
RL = 500Ω to GND (EL5174)
RL = 500Ω to GND (EL5374)
±3.6
±3.8
IOUT(Max)
Maximum Output Current
RL = 10Ω, VIN+ = ±3.2V
±50
±60
ROUT
Output Impedance
±3.4
V
V
±100
mA
130
mΩ
SUPPLY
VSUPPLY
Supply Operating Range
VS+ to VS-
IS(ON)
Power Supply Current - Per Channel
IS(OFF)+
Positive Power Supply Current - Disabled (EL5374) EN pin tied to 4.8V
IS(OFF)-
Negative Power Supply Current - Disabled
(EL5374)
PSRR
Power Supply Rejection Ratio
4.75
10
VS from ±4.5V to ±5.5V
11
V
12.5
14
mA
1.7
10
µA
-200
-120
µA
60
75
dB
ENABLE (EL5374 ONLY)
tEN
Enable Time
130
ns
tDS
Disable Time
1.2
µs
VIH
EN Pin Voltage for Power-Up
VIL
EN Pin Voltage for Shut-Down
IIH-EN
EN Pin Input Current High
At VEN = 5V
IIL-EN
EN Pin Input Current Low
At VEN = 0V
4
VS+ -1.5
VS+ -0.5
V
123
-10
V
-8
150
µA
µA
FN7313.7
August 3, 2010
EL5174, EL5374
Pin Descriptions
EL5174
EL5374
1
PIN NAME
FBP
PIN FUNCTION
Feedback from non-inverting output
2
IN+
Non-inverting input
3
REF
Inverting inputs, note that on EL5174, this pin is also the REF pin
4
FBN
Feedback from inverting output
5
OUT-
Inverting output
6
VS+
Positive supply
7
VS-
Negative supply
8
OUT+
17, 21, 27
FBP3, FBP2, FBP1
Non-inverting output
Feedback from non-inverting outputs
2, 6, 10
INP1, INP2, INP3
Non-inverting inputs
3, 7, 11
INN1, INN2, INN3
Inverting inputs, note that on EL5174, this pin is also the REF pin
16, 20, 26
15, 19, 25
FBN3, FBN2, FBN1
Feedback from inverting outputs
OUT3B, OUT2B, OUT1B Inverting outputs
24
VSP
Positive supply
23
VSN
Negative supply
18, 22, 28
OUT3, OUT2, OUT1
1, 5, 9, 13
NC
No connect; grounded for best crosstalk performance
4, 8, 12
REF1, REF2, REF3
Reference inputs, sets common-mode output voltage
14
EN
5
Non-inverting outputs
ENABLE
FN7313.7
August 3, 2010
Connection Diagrams
RF1
-5V
0Ω
IN+
RG
REF
6
RS1
50Ω
RS1
50Ω
1 FBP
OUT 8
2 INP
VSN 7
3 REF
VSP 6
4 FBN
OUTB 5
RF2
CL1
5pF
OUT
RLD
1kΩ
OUTB
+5V
CL2
5pF
0Ω
FIGURE 1. EL5174
+5V
INN1
REF1
INP2
INN2
REF2
INP3
INN3
REF3
RSP1
50Ω
RSN1
50Ω
RSR1
50Ω
RSP2
50Ω
RSN2
50Ω
RSR2
50Ω
RSP3
50Ω
RSN3
50Ω
RSR3
50Ω
OUT1 28
2 INP1
FBP1 27
3 INN1
FBN1 26
4 REF1
OUT1B 25
5 NC
VSP 24
6 INP2
VSN 23
7 INN2
OUT2 22
8 REF2
FBP2 21
9 NC
FBN2 20
10 INP3
OUT2B 19
11 INN3
OUT3 18
12 REF3
FBP3 17
13 NC
FBN3 16
14 EN
OUT3B 15
RF
RG
FN7313.7
August 3, 2010
FIGURE 2. EL5374
0Ω
RLD1
1kΩ
RF
0Ω
RF
RG
RLD2
1kΩ
0Ω
RF
0Ω
RF
RG
0Ω
RLD3
1kΩ
RF
0Ω
-5V
ENABLE
EL5174, EL5374
INP1
1 NC
CL1
5pF
CL1B
5pF
CL2
5pF
CL2B
5pF
CL3
5pF
CL3B
5pF
EL5174, EL5374
Typical Performance Curves
AV = 1, RLD = 1kΩ, CLD = 2.7pF
3
3
NORMALIZED MAGNITUDE (dB)
4
2
MAGNITUDE (dB)
RLD = 1kΩ, CLD = 2.7pF
4
VOP-P = 200mV
1
0
-1
-2
VOP-P = 1V
-3
-4
-5
-6
1M
10M
100M
2
1
AV = 1
0
-1
-2
-3
AV = 10
-5
FREQUENCY (Hz)
AV = 1, CLD = 2.7pF
3
CLD = 23pF
CLD = 34pF
4
2
0
CLD = 9pF
-2
-4
2
MAGNITUDE (dB)
MAGNITUDE (dB)
6
CLD = 2.7pF
0
-1
-3
-8
-5
100M
RLD = 500Ω
-2
-4
10M
RLD= 1kΩ
1
-6
RLD = 200Ω
-6
1M
1G
FIGURE 5. FREQUENCY RESPONSE vs CLD
AV = 2, CLD = 2.7pF, RF = 750Ω
AV = 2, RLD = 1kΩ, CLD = 2.7pF
10
9
9
RF = 1kΩ
8
7
MAGNITUDE (dB)
MAGNITUDE (dB)
8
6
3
RF = 500Ω
RF = 200Ω
7
5
4
3
2
1
1
10M
100M
FREQUENCY (Hz)
FIGURE 7. FREQUENCY RESPONSE
7
400M
RLD = 1kΩ
6
2
0
1M
1G
FIGURE 6. FREQUENCY RESPONSE vs RLD
10
4
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
5
1G
4
CLD = 50pF
-10
1M
100M
FIGURE 4. FREQUENCY RESPONSE FOR VARIOUS GAIN
AV = 1, RLD = 1kΩ
8
10M
FREQUENCY (Hz)
FIGURE 3. FREQUENCY RESPONSE
10
AV = 2
-4
-6
1M
1G
AV = 5
0
1M
RLD = 500Ω
RLD = 200Ω
10M
100M
400M
FREQUENCY (Hz)
FIGURE 8. FREQUENCY RESPONSE vs RLD
FN7313.7
August 3, 2010
EL5174, EL5374
Typical Performance Curves
(Continued)
5
0
4
-10
-20
2
-30
1
PSRR (dB)
MAGNITUDE (dB)
3
0
-1
-40
-2
-60
-3
-70
-4
-80
-5
100k
1M
10M
-90
10k
100M
PSRR-
-50
PSRR+
FIGURE 10. PSRR vs FREQUENCY
1k
VOLTAGE NOISE (nV/√Hz),
CURRENT NOISE (pA/√Hz)
100
80
CMRR (dB)
100M
10M
FREQUENCY (Hz)
FIGURE 9. FREQUENCY RESPONSE - VREF
60
40
20
0
-20
1k
1M
100k
FREQUENCY (Hz)
10k
1M
100k
10M
100M
100
EN
10
IN
1
10
1G
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 12. VOLTAGE AND CURRENT NOISE vs FREQUENCY
FIGURE 11. CMRR vs FREQUENCY
0
100
-10
-20
IMPEDANCE (Ω)
GAIN (dB)
-30
-40
-50
-60
CH1 <=> CH2, CH2 <=> CH3
-70
-80
10
1.0
CH1 <=> CH3
-90
-100
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 13. CHANNEL ISOLATION (EL5374 ONLY)
8
0.1
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 14. OUTPUT IMPEDANCE vs FREQUENCY
FN7313.7
August 3, 2010
EL5174, EL5374
Typical Performance Curves
(Continued)
VS = ±5V, AV = 2, RLD = 1kΩ
VS = ±5V, AV = 1, RLD = 1kΩ
-40
-40
DISTORTION (dB)
DISTORTION (dB)
-50
HD3 (f = 5MHz)
-50
-60
HD3 (f = 20MHz)
-70
-80
-60
HD3 (f = 20MHz)
-70
5
(f =
HD3
-80
-90
-90
-100
1.0
HD2 (f = 5MHz)
1.5
2.5
2.0
3.0
HD2 (f = 20M
HD2 (f = 20MHz)
3.5
4.5
4.0
5.0
-100
1
2
3
-55
-55
-60
-60
-65
-65
-70
-75
HD2
-90
HD2
-95
-100
100
(f =
20M
Hz)
(f = 5
200
HD3
HD3
(f = 5
MHz
(f = 2
0MH
z
)
)
400
500 600
RLD (Ω)
DISTORTION (dB)
10
HD3 (f = 5MHz)
-75
-80
HD2 (f = 20MHz)
-85
HD2 (f = 5MHz)
700
900 1000
800
-100
200
300
400
500
600 700
RLD (Ω)
800
900
1000
FIGURE 18. HARMONIC DISTORTION vs RLD
VS = ±5V, RLD = 1kΩ, VOP-P, DM = 1V for AV = 1,
VOP-P, DM = 2V for AV = 2
-50
HD3 (AV = 2)
-60
2
HD
-70
(A V
HD3 (A V
-80
HD
-90
-100
9
-70
-90
FIGURE 17. HARMONIC DISTORTION vs RLD
-40
8
HD3 (f = 20MHz)
-95
M Hz)
300
HD2 (f = 5MHz)
VS = ±5V, AV = 2, VOP-P, DM = 2V
-50
DISTORTION (dB)
DISTORTION (dB)
VS = ±5V, AV = 1, VOP-P, DM = 1V
-85
Hz)
FIGURE 16. HARMONIC DISTORTION vs DIFFERENTIAL
OUTPUT VOLTAGE
-50
-80
z)
5
6
7
VOP-P, DM (V)
4
VOP-P, DM (V)
FIGURE 15. HARMONIC DISTORTION vs DIFFERENTIAL
OUTPUT VOLTAGE
MH
0
10
20
30
40
FREQUENCY (MHz)
2(
AV
50
=2
)
= 1)
50mV/DIV
)
=1
60
FIGURE 19. HARMONIC DISTORTION vs FREQUENCY
9
10ns/DIV
FIGURE 20. SMALL SIGNAL TRANSIENT RESPONSE
FN7313.7
August 3, 2010
EL5174, EL5374
Typical Performance Curves
(Continued)
M = 400ns, CH1 = 500mV/DIV, CH2 = 5V/DIV
CH1
0.5V/DIV
CH2
400ns/DIV
10ns/DIV
FIGURE 22. ENABLED RESPONSE
FIGURE 21. LARGE SIGNAL TRANSIENT RESPONSE
M = 400ns, CH1 = 200mV/DIV, CH2 = 5V/DIV
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
POWER DISSIPATION (W)
1.2
CH1
CH2
1.010W
1.0
QSOP28
θJA = +99°C/W
0.8
625mW
0.6
0.4
SO8
θJA = +160°C/W
0.2
0
0
25
400ns/DIV
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 23. DISABLED RESPONSE
POWER DISSIPATION (W)
1.4
FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.2
1.266W
1.0
909mW
QSOP28
θJA = +79°C/W
0.8
0.6
SO8
θJA = +110°C/W
0.4
0.2
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
10
FN7313.7
August 3, 2010
EL5174, EL5374
Simplified Schematic
VS+
R1
IN+
R3
R2
IN-
FBP
R4
R7
R8
FBN
VB1
OUT+
RCD
REF
RCD
VB2
CC
OUT-
R9
R10
CC
R5
R6
VS-
Description of Operation and Application
Information
Product Description
The EL5174 and EL5374 are wide bandwidth, low power
and single/differential ended to differential output amplifiers.
The EL5174 is a single channel differential amplifier. Since
the IN- pin and REF pin are tied together internally, the
EL5174 can be used as a single-ended to differential
converter. The EL5374 is a triple channel differential
amplifier. The EL5374 has a separate IN- pin and REF pin
for each channel. It can be used as single/differential ended
to differential converter. The EL5174 and EL5374 are
internally compensated for closed loop gain of +1 of greater.
Connected in a gain of 1 and driving a 1kΩ differential load,
the EL5174 and EL5374 have a -3dB bandwidth of 550MHz.
Driving a 200Ω differential load at gain of 2, the bandwidth is
about 130MHz. The EL5374 is available with a power-down
feature to reduce the power while the amplifier is disabled.
Input, Output and Supply Voltage Range
The EL5174 and EL5374 have been designed to operate
with a single supply voltage of 5V to 10V or split supplies
with its total voltage from 5V to 10V. The amplifiers have an
input common mode voltage range from -4.3V to 3.4V for
±5V supply. The differential mode input range (DMIR)
between the two inputs is from -2.3V to +2.3V. The input
voltage range at the REF pin is from -3.3V to 3.7V. If the
input common mode or differential mode signal is outside the
above-specified ranges, it will cause the output signal to
become distorted.
The output of the EL5174 and EL5374 can swing from -3.8V
to +3.8V at 1kΩ differential load at ±5V supply. As the load
resistance becomes lower, the output swing is reduced.
Differential and Common Mode Gain Settings
For EL5174, since the IN- pin and REF pin are bound
together as the REF pin in an 8 Ld package, the signal at the
11
REF pin is part of the common mode signal and also part of
the differential mode signal. For the true balance differential
outputs, the REF pin must be tied to the same bias level as
the IN+ pin. For a ±5V supply, just tie the REF pin to GND if
the IN+ pin is biased at 0V with a 50Ω or 75Ω termination
resistor. For a single supply application, if the IN+ is biased
to half of the rail, the REF pin should be biased to half of the
rail also.
The gain setting for EL5174 is expressed in Equation 1:
R F1 + R F2⎞
⎛
V ODM = V IN + × ⎜ 1 + ----------------------------⎟
RG
⎝
⎠
2R F⎞
⎛
V ODM = V IN + = ⎜ 1 + -----------⎟
RG ⎠
⎝
(EQ. 1)
V OCM = V REF = 0V
Where:
VREF = 0V
RF1 = RF2 = RF
The EL5374 has a separate IN- pin and REF pin. It can be
used as a single/differential ended to differential converter.
The voltage applied at REF pin can set the output common
mode voltage and the gain is one.
The gain setting for EL5374 is expressed in Equation 2:
R F1 + R F2⎞
⎛
V ODM = ( V IN + – V IN - ) × ⎜ 1 + ----------------------------⎟
RG
⎝
⎠
2R F⎞
⎛
V ODM = ( V IN + – V IN - ) × ⎜ 1 + -----------⎟
RG ⎠
⎝
(EQ. 2)
V OCM = V REF
Where:
RF1 = RF2 = RF
FN7313.7
August 3, 2010
EL5174, EL5374
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
RF1
FBP
VIN+
VIN-
RG
VREF
Disable/Power-Down (for EL5374 only)
V O+
IN+
INREF
V O-
FBN
RF2
FIGURE 26.
Choice of Feedback Resistor and Gain Bandwidth
Product
For applications that require a gain of +1, no feedback
resistor is required. Just short the OUT+ pin to FBP pin and
OUT- pin to FBN pin. For gains greater than +1, the
feedback resistor forms a pole with the parasitic capacitance
at the inverting input. As this pole becomes smaller, the
amplifier's phase margin is reduced. This causes ringing in
the time domain and peaking in the frequency domain.
Therefore, RF has some maximum value that should not be
exceeded for optimum performance. If a large value of RF
must be used, a small capacitor in the few Pico farad range
in parallel with RF can help to reduce the ringing and
peaking at the expense of reducing the bandwidth.
The bandwidth of the EL5174 and EL5374 depends on the
load and the feedback network. RF and RG appear in parallel
with the load for gains other than +1. As this combination gets
smaller, the bandwidth falls off. Consequently, RF also has a
minimum value that should not be exceeded for optimum
bandwidth performance. For gain of +1, RF = 0 is optimum.
For the gains other than +1, optimum response is obtained
with RF between 500Ω to 1kΩ.
The EL5174 and EL5374 have a gain bandwidth product of
200MHz for RLD = 1kΩ. For gains ≥5, its bandwidth can be
predicted by Equation 3:
(EQ. 3)
Gain × BW = 200MHz
The EL5374 can be disabled and its outputs placed in a high
impedance state. The turn-off time is about 1.2µs and the
turn-on time is about 130ns. When disabled, the amplifier's
supply current is reduced to 1.7µA for IS+ and 120µA for IStypically, thereby effectively eliminating the power
consumption. The amplifier's power-down can be controlled
by standard CMOS signal levels at the EN pin. The applied
logic signal is relative to the VS+ pin. Letting the EN pin float
or applying a signal that is less than 1.5V below VS+ will
enable the amplifier. The amplifier will be disabled when the
signal at the EN pin is above VS+ - 0.5V.
Output Drive Capability
The EL5174 and EL5374 have internal short circuit protection.
Its typical short circuit current is ±60mA. If the output is shorted
indefinitely, the power dissipation could easily increase such
that the part will be destroyed. Maximum reliability is
maintained if the output current never exceeds ±60mA. This
limit is set by the design of the internal metal interconnections.
Power Dissipation
With the high output drive capability of the EL5174 and
EL5374, it is possible to exceed the +135°C absolute
maximum junction temperature under certain load current
conditions. Therefore, it is important to calculate the maximum
junction temperature for the application to determine if the
load conditions or package types need to be modified for the
amplifier to remain in the safe operating area.
The maximum power dissipation allowed in a package is
determined according to Equation 4:
T JMAX – T AMAX
PD MAX = --------------------------------------------Θ JA
Where:
TJMAX = Maximum junction temperature
Driving Capacitive Loads and Cables
TAMAX = Maximum ambient temperature
The EL5174 and EL5374 can drive a 23pF differential
capacitor in parallel with 1kΩ differential load with less than
5dB of peaking at gain of +1. If less peaking is desired in
applications, a small series resistor (usually between 5Ω to
50Ω) can be placed in series with each output to eliminate
most peaking. However, this will reduce the gain slightly. If
the gain setting is greater than 1, the gain resistor RG can
then be chosen to make up for any gain loss, which may be
created by the additional series resistor at the output.
θJA = Thermal resistance of the package
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
12
(EQ. 4)
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or
as expressed in Equation 5:
ΔV O⎞
⎛
PD = i × ⎜ V S × I SMAX + V S × ------------⎟
R LD ⎠
⎝
(EQ. 5)
Where:
VS = Total supply voltage
ISMAX = Maximum quiescent supply current per channel
FN7313.7
August 3, 2010
EL5174, EL5374
ΔVO = Maximum differential output voltage of the
application
capacitor combination should be placed at each supply pin to
ground if split supplies are to be used. In this case, the VS- pin
becomes the negative supply rail.
RLD = Differential load resistance
ILOAD = Load current
i = Number of channels
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLD to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit board
layout is necessary for optimum performance. Lead lengths
should be as short as possible. The power supply pin must be
well bypassed to reduce the risk of oscillation. For normal single
supply operation, where the VS- pin is connected to the ground
plane, a single 4.7µF tantalum capacitor in parallel with a 0.1µF
ceramic capacitor from VS+ to GND will suffice. This same
For good AC performance, parasitic capacitance should be
kept to a minimum. Use of wire-wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
Typical Applications
As the signal is transmitted through a cable, the high frequency
signal will be attenuated. One way to compensate this loss is to
boost the high frequency gain at the receiver side.
RF
FBP
50
TWISTED PAIR
IN+
IN+
RT
RG
INREF
EL5174/
EL5374
50
IN-
ZO = 100Ω
FBN
EL5175/
EL5375
VO
REF
RF
RFR
RGR
FIGURE 27. TWISTED PAIR CABLE RECEIVER
RF
GAIN
(dB)
FBP
RT
75
RGC
VO+
IN+
RG
IN-
CL
REF
VO-
FBN
fL
RF
2R F
DC Gain = 1 + ----------RG
1
f L ≅ ------------------------2πR G C C
2R F
( HF )Gain = 1 + -------------------------R G || R GC
1
f H ≅ ----------------------------2πR GC C C
fH
FREQUENCY
FIGURE 28. TRANSMIT EQUALIZER
13
FN7313.7
August 3, 2010
EL5174, EL5374
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
14
FN7313.7
August 3, 2010
EL5174, EL5374
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
M28.15
N
INDEX
AREA
H
0.25(0.010) M
E
2
SYMBOL
3
0.25
0.010
SEATING PLANE
-A-
INCHES
GAUGE
PLANE
-B1
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
B M
A
D
L
h x 45°
-C-
α
e
A2
A1
B
C
0.10(0.004)
0.17(0.007) M
C A M
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
MIN
MAX
MILLIMETERS
MIN
MAX
NOTES
A
0.053
0.069
1.35
1.75
-
A1
0.004
0.010
0.10
0.25
-
A2
-
0.061
-
1.54
-
B
0.008
0.012
0.20
0.30
9
C
0.007
0.010
0.18
0.25
-
D
0.386
0.394
9.81
10.00
3
E
0.150
0.157
3.81
3.98
4
e
0.025 BSC
0.635 BSC
-
H
0.228
0.244
5.80
6.19
-
h
0.0099
0.0196
0.26
0.49
5
L
0.016
0.050
0.41
1.27
6
N
α
28
0°
28
8°
0°
7
8°
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
Rev. 1 6/04
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch)
per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B”
dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions
are not necessarily exact.
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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15
FN7313.7
August 3, 2010