5 4 3 2 1 D D EVB-LAN9354 Page No. C Schematic Page 1 Title 2 Block Diagram 3 Power Supply & RST 4 LAN9354 (Part1) 5 Copper Mode Interface 6 Fiber - SFP Interface 7 STRAP,GPIO,I2C & FXLOS 8 LAN9354 (Part2) C B B A A Chennai India 5 4 3 2 Part Number: EVB-LAN9354 Size: B Project Name: Date: Tuesday, June 30, 2015 LAN9354 Page: Board Name: TITLE Rev EVB-LAN9354-REV-A Sheet 1 1 of A 8 5 4 3 2 1 D D EVB-LAN9354 Block Diagram 40 Pin MII Connector (Female) 40 Pin MII Connector (Male) RMII I2C EEPROM/ Header Power Supply Module Port 0 Mode Switch C Microchip LAN9354 Straps Jumpers C Reset Switch Crystal Port 1 Port 2 B B Fiber Trasnceiver(SFP) Port 1 10/100 Ethernet Magnetics & RJ45 10/100 Ethernet Magnetics & RJ45 Fiber Trasnceiver(SFP) Port 2 A A Chennai India 5 4 3 2 Part Number: EVB-LAN9354 Size: B Project Name: Date: Friday, June 19, 2015 LAN9354 Page: Board Name: Block Diagram Rev EVB-LAN9354-REV-A Sheet 1 2 of A 8 5 4 3 2 1 D D POWER SUPPLY 3 EN12_1 2A/0.05DCR 2 Switch, SPDT, Slide P/N:1101M2S3CQE2 J1 PJ-002AH 2 1 5V_SW R1 0E C2 10uF 25V VIN ENABLE VOUT TRIM 3_Amp GND C3 4 5 C1 3 OKR-T/3-W12-C 0.1uF R2 1K VOUT_3V3 R3 3.30K 1% R4 470E 1% (Ra) (Rb) R4A 33E 1% C4 C5 10uF 0.1uF 4.7uF DNP 1 3 3V3 U1 FB1 2 A 1 D1 GRN C 5V_EXT 3V3 "3V3 Present" SW1 1 TP2 ORANGE 3.3 V REGULATOR, 3A ( 3V3 fixed when Rb=470E) 5V 2 TP1 RED C C 3V3 3V3 3V3 RESET# RESET D RST# Q1 3 R8 1K 1 G 5 MR# 2 Reset Switch NDS355AN_NMOS 1 2 3V3 VDD 4 5 U2 2 1/10W 1% 3 sw_pb_2P B 1 R7 100 GND SW2 R5 4.75K 1% 0.1uF 2 1 C6 R6 10.0K 1/10W 1% B U3 S 2 4 1 R9 TPS3125 2.2K 74LVC1G14 C 2 D2 RED 1 3 SOT23_5 Threshold = 2.64V Delay = 180ms A "Reset" Reset Generator A A Chennai India 5 4 3 2 Part Number: EVB-LAN9354 Size: B Project Name: Date: Friday, June 19, 2015 LAN9354 Page: Board Name: Power Supply & RESET Rev EVB-LAN9354-REV-A Sheet 1 3 of A 8 5 4 3V3 D 3 2 1 Power Supply Filtering VDD33TXRX1 FB2 3V3 2A/0.05DCR D VDDCR VDD12TX1 VDD12TX2 C20 C21 C22 470pF 0.1uF 0.1uF C19 Low ESR 1uF C18 C17 0.1uF C16 0.1uF 0.1uF C14 C13 C15 0.1uF 0.1uF C12 DNP FB5 2A/0.05DCR BLM18EG221SN1D B 7 49 11 38 8 35 I2C2_SCL I2C2_SDA 37 36 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 42 40 39 29 16 15 13 12 RBIAS RST# IRQ ATEST/FXLOSEN TESTMODE 48 51 VDD12TX1 VDD12TX2 6 22 32 VDDCR_1 VDDCR_2 VDDCR_3 14 18 28 31 41 VDDIO_1 VDDIO_2 VDDIO_3 VDDIO_4 VDDIO_5 REG_EN I2CSCL/EESCL/TCK I2CSDA/EESDA/TMS TXNA TXPA RXNA RXPA TXNB TXPB RXNB RXPB FXSDENB/FXSDB/FXLOSB GPIO0/LED0/TDO/LEDPOL0/MNGT0 GPIO1/LED1/TDI/LEDPOL1 GPIO2/LED2/LEDPOL2/E2PSIZE GPIO3/LED3/LEDPOL3/EEEEN GPIO4/LED4/LEDPOL4/1588EN GPIO5/LED5/LEDPOL5/PHYADD GPIO6 GPIO7 LAN9354_QFN56 FXSDA/FXLOSA 44 45 46 47 TXNA TXPA RXNA RXPA 55 54 53 52 TXNB TXPB RXNB RXPB 10 B FXSDB/FXLOSB GND RST# IRQ TP4 WHITE DNP ATEST/FXLOSEN RBIAS 9 57 12.1K 1% Reserved R10 27 REG_EN 18pF C FXSDENA/FXSDA/FXLOSA INT PORT0 C27 OSCVDD12 OSCI OSCO OSCVSS INT PORT1 1 3V3 3 1 2 4 OSC OSCI OSCO OTHER SIGNALS 25.000MHz 25ppm Y1 I2C 18pF 2 C26 POWER Note: OSCVSS need to connect to Chip gnd. VDD33BIAS VDD33 U4A VDD33TXRX1 VDD33TXRX2 43 56 C 50 5 VDD12TX1 VDD12TX2 0.1uF 0.1uF C25 0.1uF C24 VDD33TXRX1 VDD33TXRX2 BLM18EG221SN1D C23 1.0uF DNP 1.0uF TP3 SMT VDDCR C11 3V3 2A/0.05DCR 2A/0.05DCR 0.1uF 3V3 FB4 FB3 0.1uF 3V3 C9 0.1uF VDD33TXRX2 C10 C8 DNP 1.0uF C7 1.0uF DNP A A Chennai India 5 4 3 2 Part Number: EVB-LAN9354 Size: B Project Name: Date: Friday, June 19, 2015 LAN9354 Page: Board Name: LAN9252 (Part1) Rev EVB-LAN9354-REV-A Sheet 1 4 of A 8 5 4 3 2 R61 LINK/ACT LED2_ANODE PORT1 0E 10 T1 Pulse J0011D01BNL R11 49.9 1/10W 1% TXPA 0E 0E TXNA DNP R18 R19 0E 0E FX_SFP-TXPA R12 49.9 1/10W 1% R13 49.9 1/10W 1% R14 49.9 1/10W 1% R15 0E GRN 1 COP-TXPA 4 FX_SFP-TXNA A C 9 FB6 DNP R16 R17 330E LED2_CATHODE VDD33TXRX1 D 1 2 COP-TXNA RJ45 D XMIT TD+ 75 1 75 TXCT 4&5 TD- 2 Default assembly LED1 (Green) = LINK/ACT DNP C29 10pF 50V 5% DNP C30 10pF 50V 5% DNP C31 10pF 50V 5% C32 0.022uF 7 8 50V 10% 75 7&8 RD- 6 2 kV 1000 pF NC CHS GND 13 C Note: Capacitors C28 through C31 are optional for EMI purposes and are not populated on the EVB9354 evaluation board. These capacitors are required for operation in an EMI constrained environment. 14 GND DNP C28 10pF 50V 5% 75 RXCT YEL C A1 6 12 5 COP-RXNA C1 FX_SFP-RXNA 3 11 0E 0E RD+ MTG1 DNP R22 R23 LED2 (Yellow) = SPEED RCV 3 COP-RXPA MTG FX_SFP-RXPA 16 0E 0E 15 RXNA DNP R20 R21 GND1 RXPA R62 R24 330E LED0_CATHODE 0E LED0_ANODE SPEED RES1210 R63 LINK/ACT FB7 LED5_ANODE 0E 10 T2 Pulse J0011D01BNL B TXPB TXNB R25 49.9 1/10W 1% DNP R30 R31 0E 0E FX_SFP-TXPB DNP R32 R33 0E 0E FX_SFP-TXNB DNP R34 R35 0E 0E FX_SFP-RXPB DNP R36 R37 0E 0E FX_SFP-RXNB R26 49.9 1/10W 1% R27 49.9 1/10W 1% R28 49.9 1/10W 1% A C 9 PORT2 330E LED5_CATHODE VDD33TXRX2 R29 0E GRN 1 COP-TXPB 4 2 COP-TXNB RJ45 B XMIT TD+ 75 75 1 TXCT 4&5 TD- 2 LED1 (Green) = LINK/ACT CHS GND Note: Capacitors C33 through C36 are optional for EMI purposes and are not populated on the EVB9354 evaluation board. These capacitors are required for operation in an EMI constrained environment. YEL A A1 Note: FB6 and FB7 to be zero ohms 12 NC C1 8 6 2 kV 1000 pF 11 50V 10% 7 MTG1 C37 0.022uF MTG DNP C36 10pF 50V 5% 3 7&8 16 DNP C35 10pF 50V 5% GND DNP C34 10pF 50V 5% 75 RD- 15 6 COP-RXNB 75 RXCT GND1 5 DNP C33 10pF 50V 5% A LED2 (Yellow) = SPEED RD+ 14 RXNB 3 COP-RXPB 13 RXPB RCV R64 R38 0E Chennai India 330E LED3_CATHODE LED3_ANODE SPEED RES1210 5 4 3 2 Part Number: EVB-LAN9354 Size: B Project Name: Date: Friday, June 19, 2015 LAN9354 Page: Board Name: Copper Mode Interface Rev EVB-LAN9354-REV-A Sheet 1 5 of A 8 5 4 R39 82 R40 82 R41 49.9 R42 49.9 Note:Place capacitors, and resistors close to FOT 3V3 Fiber Port 1 :SFP Interface R43 82 R44 82 R45 49.9 2 1 Note:Place capacitors, and resistors close to FOT Fiber Port 2 :SFP Interface R46 49.9 Assemble 0E at C38,C40,C42,C44 FX_SFP-RXNA C38 FX_SFP-RXPA C40 C42 FX_SFP-TXPA FX_SFP-TXNA FX_SFP-RXNB C39 0.1uF FX_SFP-RXPB C41 0.1uF FX_SFP-TXPB C43 0.1uF 0.1uF L2 SFP_VCCR 0.1uF DNP R48 100 3V3 SFP_VCCT C47 C48 10uF 16V 0.1uF L4 C45 0.1uF C49 0.1uF R51 130 R52 130 1uH J2 FTLF1217P2 31 30 29 28 27 26 25 24 23 22 21 C54 + 10uF 16V C55 Note:Place 0.1uF resistors close to ASIC J3 FTLF1217P2 R54 4.7K R55 4.7K C 1uH 31 30 29 28 27 26 25 24 23 22 21 31 30 29 28 27 26 25 24 23 22 21 C56 + 10uF 16V C57 0.1uF SFP_VCCT2 B R53 4.7K VeeT1 TDTD+ VeeT2 VccT VccR VeeR2 RD+ RDVeeR3 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 SFP_VCCT VeeT TXFault TX Disable MOD-DEF(2) MOD-DEF (1) MOD-DEF (0) Rate Select LOS VeeR VeeR1 ASIC C53 0.1uF C52 + 10uF 16V 1 2 3 4 5 6 7 8 9 10 resistors close to C51 0.1uF L3 20 19 18 17 16 15 14 13 12 11 VeeT1 TDTD+ VeeT2 VccT VccR VeeR2 RD+ RDVeeR3 Note:Place DNP C50 + 10uF 16V 1uH 20 19 18 17 16 15 14 13 12 11 C + L1 SFP_VCCR2 SFP_TD2SFP_TD2+ SFP_RD+ SFP_RD- SFP_TDSFP_TD+ R50 130 DNP C46 + 10uF 16V 3V3 SFP_VCCT2 1uH FX_SFP-TXNB R49 130 D 0.1uF DNP R47 100 C44 Assemble 0E at C39,C41,C43,C45 0.1uF VeeT TXFault TX Disable MOD-DEF(2) MOD-DEF (1) MOD-DEF (0) Rate Select LOS VeeR VeeR1 D SFP_RD2+ SFP_RD2- 3V3 3 R57 4.7K R56 4.7K FXSDA/FXLOSA R58 4.7K R59 4.7K B R60 4.7K FXSDB/FXLOSB A A Note: Fiber mode related components are Not Populated on EVB (Default) Chennai India 5 4 3 2 Part Number: EVB-LAN9354 Size: B Project Name: Date: Friday, June 19, 2015 LAN9354 Page: Board Name: Fiber-SFP Interface Rev EVB-LAN9354-REV-A Sheet 1 6 of A 8 5 4 3 2 GPIO [0:5] & LED_POL_Strap I2C EEPROM 1 3V3 3V3 3V3 GPIO5 7 1 A0 A1 A2 GPIO0 5 I2C2_SDA 6 I2C2_SCL Note: U5: IC DIP Socket. Different sizes can be mounted I2C EEPROM Lower size Below 16K(2K X 8) I2C EEPROM Higher size Above 16K(2K X 8) [Default-512KBIT] 2 2 GPIO4 D GPIO3 3 1 3 J15 1 1 3 GPIO1 R86 0E J13 3 J14 1 3 GPIO2 R85 0E 2 2 R84 1K J8 1 3 J9 1 J7 C R74 1K 2 2 R73 0E SDA SCL WP 2 2 2 VCC 2 1 2 3 R83 10.0K 24FC512-I/P R72 0E 0.1uF 3 1 3 1 1 3 2 4.7K LED3_CATHODE LED5_CATHODE 2 2 R66 LED3_ANODE LED5_ANODE R82 10.0K LED1_CATHODE LED4_CATHODE 2 LED0_CATHODE LED2_CATHODE R81 10.0K 1 R71 10.0K 1 R70 10.0K J12 2 J10 LED1_ANODE LED4_ANODE 1 1 1 LED0_ANODE LED2_ANODE R69 10.0K 3 1 J11 2 J5 2 J6 2 J4 3 1 3 1 U5 D 2K GPIO3 R67 3V3 GPIO4 2K 3V3 GPIO1 8 3V3 GPIO2 GND 3V3 GPIO0 4 3V3 R68 C58 GPIO5 FX_Los_Strap_1 & 2 C 3V3 Port 1 LEDs LED0_ANODE LED0_CATHODE LED0_ANODE LED0_CATHODE DNP D3 1 GRN A Port 2 LEDs SPEED LED3_ANODE LED3_ANODE 2 C LED3_CATHODE LED3_CATHODE DNP D6 1 GRN A R77 SPEED Poupulate 2 LED1_ANODE LED1_CATHODE D4 1 GRN A FULL DUPLEX / Collision LED4_ANODE 2 LED4_CATHODE C D7 1 GRN A 2 C Poupulate LED2_CATHODE LED2_ANODE LED2_CATHODE LINK/ACT DNP D5 1 GRN A C LED5_ANODE LED5_ANODE 2 LED5_CATHODE LED5_CATHODE Poupulate Function 3V3 Above 2 V selects FX-LOS for ports 1 and 2 1V5 Level of 1.5 V selects FX-LOS for port 1 and FX-SD/copper twisted pair for port 2 further determined by FXSDB R77 10K DNP ATEST/FXLOSEN 1 2 GPIO6 R87 3 10K DNP (Default) LED2_ANODE DNP Ref.Voltage C 3V3 FULL DUPLEX / Collision R79 J16 LINK/ACT DNP 2 D8 1 GRN A C Poupulate (Default) 0 (Default) Level of 0V Selects FX-SD / copper twisted pair for ports A and B further determined by FXSDA and FXSDB. R79 10K 3V3 1 B Strap Name Logic Connector 2 GPIO7 R88 LED Polarity Strap 3 10K B J17 0 J4,J7 (2&3) The LED is set as active high. 1 J4,J7 (1&2) (Default) The LED is set as active low, 0 J5,J8 (2&3) The LED is set as active high. 1 J5,J8 (1&2) (Default) The LED is set as active low, 0 J6,J9 (2&3) The LED is set as active high. EEPROM Size=1K bits (128 x 8) through 16K bits (2K x 8) 1 J6,J9 (1&2) (Default) The LED is set as active low, EEPROM Size=32K bits (4K x 8) through 512K bits (64K x 8) or 4Mbits (512K x 8) (LAN9252 only) 0 J10,J13 (2&3) The LED is set as active high. EEE Disable 1 J10,J13 (1&2) (Default) The LED is set as active low, EEE Enable 0 J11,J14 (2&3) The LED is set as active high. 1588 Disable 1 J11,J14 (1&2) (Default) The LED is set as active low, J12,J15 (2&3) (Default) The LED is set as active high. PHYADD=0,1,2 J12,J15 (1&2) The LED is set as active low, PHYADD =1,2,3 LED0/GPIO0/MNGT0 FX_Mode_Strap_1 & 2 3V3 LED1/GPIO1 LED2/GPIO2/E2PSIZE LED3/GPIO3/EEEEN A LED4/GPIO4/1588EN 0 LED5/GPIO5/PHYADD 1 5 FXSDA/FXLOSA 1 2 3 4 5 6 7 8 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 R75 DNP 10K R76 10K PORT MODE Poupulate DNP Copper (Default) R76 R75 Fiber R75 R76 Copper (Default) R80 R78 Fiber R78 R80 PORT1 3V3 R78 DNP 10K R80 10K PORT2 FXSDB/FXLOSB J18 HEADER 8 A 1588 Enable GPIO0 = LED0/TDO/LEDPOL0/MNGT0 GPIO1 = LED1/TDI/LEDPOL1 GPIO2 = LED2/LEDPOL2/E2PSIZE GPIO3 = LED3/LEDPOL3/EEEEN GPIO4 = LED4/LEDPOL4/1588EN GPIO5 = LED5/LEDPOL5/PHYADD 4 3 Chennai India 2 Part Number: EVB-LAN9354 Size: B Project Name: Date: Monday, June 22, 2015 LAN9354 Page: Board Name: STRAP,GPIO,I2C & FXLOS Rev EVB-LAN9354-REV-A Sheet 1 7 of A 8 5 4 10uF 5V 3 C59 0.1uF C60 P0_OUTD1_MODE2_RES P0_OUTD0_MODE1_RES R89 R90 P0_REF_CLK_MODE0_RES R91 P0_IND0 P0_IND1 P0_SPEED P0_OUTD1_MODE2 P0_OUTD0_MODE1 P0_OUTDV P0_REF_CLK_MODE0 P0_INDV 33 33 33 33 33 R92 R93 P0_DUPLEX P0_MDC P0_MDIO D P0_MDIO P0_MDC P0_OUTD1_MODE2_RES P0_OUTD0_MODE1_RES P0_OUTDV R94 0E MAC_TXCLK0 P0_REF_CLK_MODE0_RES MAC_RXCLK0 P0_INDV P0_IND0 P0_IND1 CRS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 +5V[3] MDIO MDC RXD3 RXD2 RXD1 RXD0 RX_DV RX_CLK RX_ER TX_ER TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 COL CRS +5V[4] +5V[1] COMMON[1] COMMON[2] COMMON[3] COMMON[4] COMMON[5] COMMON[6] COMMON[7] COMMON[8] COMMON[9] COMMON[10] COMMON[11] COMMON[12] COMMON[13] COMMON[14] COMMON[15] COMMON[16] COMMON[17] COMMON[18] +5V[2] 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 U4B Place near to IC MAC 1 J19 2 17 19 20 21 23 24 25 26 30 33 34 3V3 SW3 P0_SPEED P0_OUTD1/P0_MODE2 P0_OUTD0/P0_MODE1 P0_OUTDV P0_REFCLK/P0_MODE0 P0_INDV P0_IND0 P0_IND1 P0_DUPLEX P0_MDC P0_MDIO 2 1 P0_REF_CLK_MODE0_RES R96 P0_MODE0 3 10K JS102011CQN D 3V3 SW4 2 1 P0_OUTD0_MODE1_RES R97 LAN9354_QFN56 P0_MODE1 3 10K JS102011CQN 3V3 3V3 J23 1 J22 2 P0_SPEED R100 R99 Default - Open 1 2 2 P0_DUPLEX 3 10K 10K 3V3 SW5 1 P0_OUTD1_MODE2_RES 3 R98 P0_MODE2 3 10K JS102011CQN Default - Open Note: The P0_SPEED & P0_DUPLEX pins are typically connected to the speed & duplex indication of the external PHY Port 0 Mode strap Mapping Emulated Link Partner Default Advertised Ability for Port 0 C J22 AMP - 6-5174218-2 (P0_DUPLEX) MII_RA MII Male for External MAC Board PORT0 Duplex Strap_0 J23 (P0_SPEED) Speed Strap_0 ADVERTISED LINK PARTNER ABILITY (Bits 8,7,6,5) 1-2 2-3 1 0 10BASE-T full-duplex (0010) 1-2 1-2 1 1 100BASE-X full-duplex (1000) (Default) 2-3 2-3 0 0 10BASE-T half-duplex (0001) 2-3 1-2 0 1 100BASE-X half-duplex (0100) 5V C61 10uF C62 0.1uF P0_MODE2 (SW5) P0_MODE2 (SW4) P0_MODE0 (SW3) 0 Short 1-3 0 Short 1-3 0 Short 1-3 1 Short 1-2 1 Short 1-2 1 Short 1-2 0 Short 1-3 1 Short 1-2 1 Short 1-2 0 Short 1-3 1 Short 1-2 1 Short 1-2 x x 0 Short 1-3 1 Short 1-2 x x 0 Short 2-3 1 Short 1-2 C MODE RMII MAC clock in RMII MAC clock out 12ma RMII MAC clock out 16ma (Default) RMII PHY clock in RMII PHY clock out 12ma RMII PHY clock out 16ma Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa . RMII RX Clock Configurations J20 Chassis2 Chassis1 SW6 B P0_MDIO P0_MDC P0_IND1 P0_IND0 P0_INDV PHY_RXCLK0 P0_REF_CLK_MODE0_RES R95 0E PHY_TXCLK0 P0_OUTDV P0_OUTD0_MODE1_RES P0_OUTD1_MODE2_RES P0_INDV CRS For RMII CRS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2 3 SW7 2 PHY_RXCLK0 3 TP5 TP6 Switch Description Settings Mode SW6 (1-3) Default TX Clock used as a Reference Clock SW6 (1-2) RX Clock used as a Reference Clock 3V3 RMII MAC RMII MAC P0_MDIO 1.5K R101 P0_MDC 10K R102 Reference clock used as a TX clock SW7 (1-3) Default RMII PHY Pullup for MDIO(common for all PHY) signal Reference clock used as a RX clock SW7 (1-2) A RMII PHY Note: 1. For Switches to short 1-3, Knob Position should be at 1-2 and vice versa . 2. External PHY considered LAN8742 Chennai India 3V3 P0_INDV 5 B HEADER 5X2 J21 Default Short 1-3 JS102011CQN PORT0 10K 2 4 6 8 10 PHY_TXCLK0 1 MII Female for External PHY Board R103 1 3 5 7 9 I2C2_SCL I2C2_SDA Default Short 1-3 JS102011CQN 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 FEMALE MII CONN AMP - 749069-4 A Aardvark - I2C Connector MAC_RXCLK0 MAC_TXCLK0 1 4 3 2 Part Number: EVB-LAN9354 Size: B Project Name: Date: Monday, June 22, 2015 LAN9354 Page: Board Name: LAN9354-Part2 Rev EVB-LAN9354-REV-A Sheet 1 8 of A 8