MIC45404 Data Sheet

MIC45404
19V 5A Ultra-Low Profile DC-to-DC Power Module
Features
General Description
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The MIC45404 device is an ultra-low profile, synchronous step-down regulator module, featuring a unique
2.0 mm height. The module incorporates a DC-to-DC
regulator, bootstrap capacitor, high-frequency input
capacitor and an inductor in a single package. The
module pinout is optimized to simplify the Printed
Circuit Board (PCB) layout process.
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Input Voltage Range: 4.5V to 19V
Output Current: Up to 5A
82% Peak Efficiency at 12 VIN, 0.9 VOUT
Pin-Selectable Output Voltages: 0.7V, 0.8V, 0.9V,
1.0V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V
±1% Output Voltage Accuracy
Supports Safe Pre-Biased Start-up
Pin-Selectable Current Limit
Pin-Selectable Switching Frequency
Internal Soft Start
Thermal Shutdown
Hiccup Mode Short-Circuit Protection
Available in a 54-Lead 6 mm x 10 mm QFN
Package
Ultra-Low Profile: 2.0 mm Height
-40°C to +125°C Junction Temperature Range
This highly integrated solution expedites system
design and improves product time to market. The internal MOSFETs and inductor are optimized to achieve
high efficiency at low output voltage. Due to the fully
optimized design, MIC45404 can deliver up to 5A
current with a wide input voltage range of 4.5V to 19V.
The MIC45404 is available in a 54-lead 6 mm x
10 mm x 2.0 mm QFN package with a junction operating temperature range from -40C to +125C, which
makes an excellent solution for systems in which PCB
real-estate and height are important limiting factors,
and air flow is restricted.
Applications
• Servers, Data Storage, Routers and Base Stations
• FPGAs, DSP and Low-Voltage ASIC Power
Typical Application
VDDA
VIN
4.5V to 19V
VIN
VDDA
GND
OUTSNS
GND
VDDA
Frequency
Selection
VDDA
Current Limit
Selection
VOUT
OUT
COMP
FREQ
VDDA
MIC45404
VOSET1
VDDA
ILIM
PG
EN/DLY
Output
Voltage
Selection
VOSET0
Power-Good
Enable
MIC45404 12V 5A DC-to-DC Converter
 2015 Microchip Technology Inc.
DS20005478A-page 1
MIC45404
Package Types
1 OUTSNS
2 SNS
3 VDDA
4 VDDP
5 GND_EXT
6 GND_EXT
7 VIN
8 VIN
9 GND
11 OUT
10 KEEPOUT
12 OUT
13 OUT
14 OUT
15 OUT
16 OUT
17 OUT
18 OUT
19 OUT
MIC45404
6 mm x 10 mm QFN*
(Bottom View)
OUT 20
54 OUTSNS
OUT 21
53 COMP
KEEPOUT 22
52 AGND
MIC45404YMP
GND 23
51 GND
GND_EP
GND 24
50 GND
KEEPOUT 25
49 FREQ
NC 46
VOSET1 45
VOSET0 44
PG 43
BST 42
BST 41
LX 38
LX 39
LX 37
KEEPOUT 40
* Includes Exposed Thermal Pad (EP); see Table 3-1.
LX 36
LX 35
LX 34
LX 33
LX 32
LX 31
47 NC
LX 30
LX 27
LX 28
48 ILIM
LX 29
LX 26
Functional Diagram
VIN
VIN
VDDP
BST
BST
100 nF
GND_EXT
VDDP
LX
OUT
LX
VDDP
VIN
PGND
GND
GND_EP
VDDA
VDDA
LDO
COMP
COMP
47 pF
AGND
PWM
Regulator
PG
EN/DLY
FREQ
ILIM
DS20005478A-page 2
AGND
PG
EN/DLY
OUTSNS
OUTSNS
FREQ
VOSET1
VOSET1
ILIM
VOSET0
VOSET0
 2015 Microchip Technology Inc.
MIC45404
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
VIN to AGND ................................................................................................................................................ -0.3V to +20V
VDDP, VDDA to AGND ..................................................................................................................................... -0.3V to +6V
VDDP to VDDA ............................................................................................................................................ -0.3V to +0.3V
VOSETX, FREQ, ILIM, to AGND .................................................................................................................... -0.3V to +6V
BST to LX..................................................................................................................................................... -0.3V to +6V
BST to AGND .............................................................................................................................................. -0.3V to +26V
EN/DLY to AGND...................................................................................................................... -0.3V to VDDA + 0.3V, +6V
PG to AGND .................................................................................................................................................. -0.3V to +6V
COMP, OUTSNS to AGND ....................................................................................................... -0.3V to VDDA + 0.3V, +6V
AGND to GND ............................................................................................................................................ -0.3V to +0.3V
Junction Temperature .......................................................................................................................................... +150°C
Storage Temperature (TS) ...................................................................................................................... -65°C to +150°C
Lead Temperature (soldering, 10s) ........................................................................................................................ 260°C
ESD Rating(1)
HBM ........................................................................................................................................................................... 2kV
MM ........................................................................................................................................................................... 150V
CDM ....................................................................................................................................................................... 1500V
†
Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Note 1: Devices are ESD-sensitive. Handling precautions are recommended. Human body model, 1.5 k in series
with 100 pF.
Operating Ratings(1)
Supply Voltage (VIN) ..................................................................................................................................... 4.5V to 19V
Externally Applied Analog and Drivers Supply Voltage (VIN = VDDA = VDDP) .............................................. 4.5V to 5.5V
Enable Voltage (EN/DLY)............................................................................................................................... 0V to VDDA
Power Good (PG) Pull-up Voltage (VPU_PG) ................................................................................................ 0V to 5.5V
Output Current ............................................................................................................................................................. 5A
Junction Temperature (TJ) ..................................................................................................................... -40°C to +125°C
Note 1: The device is not ensured to function outside the operating range.
 2015 Microchip Technology Inc.
DS20005478A-page 3
MIC45404
ELECTRICAL CHARACTERISTICS(1)
Electrical Specifications: unless otherwise specified, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
Boldface values indicate -40°C  TJ  +125°C.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
VIN Supply
Input Range
VIN
4.5
—
19
V
Disable Current
IVINQ
—
33
60
µA
EN/DLY = 0V
Operating Current
IVINOp
—
5.35
8.5
mA
EN/DLY > 1.28V,
OUTSNS = 1.15 x VOUT(NOM),
no switching
VDDA
4.8
5.1
5.4
V
EN/DLY > 0.58V,
IVDDA = 0 mA to 10 mA
3.6
3.75
—
V
VIN = 4.5V, EN/DLY > 0.58V,
IVDDA = 10 mA
UVLO_R
3.1
3.5
3.9
V
VDDA Rising, EN/DLY > 1.28V
VDDA UVLO Falling
UVLO_F
2.87
3.2
3.45
V
VDDA Falling, EN/DLY > 1.28V
VDDA UVLO Hysteresis
UVLO_H
—
300
—
mV
EN_LDO_R
—
515
600
mV
Turns on VDDA LDO
LDO Disable Threshold
EN_LDO_F
450
485
—
mV
Turns off VDDA LDO
LDO Threshold Hysteresis
EN_LDO_H
—
30
—
mV
EN/DLY Rising Threshold
EN_R
1.14
1.21
1.28
V
Initiates power stage operation
EN/DLY Falling Threshold
EN_F
—
1.06
—
V
Stops power stage operation
EN/DLY Hysteresis
EN_H
—
150
—
mV
EN/DLY Pull-up Current
EN_I
1
2
3
µA
Programmable
Frequency (High Z)
fSZ
360
400
440
kHz
FREQ = High Z (open)
Programmable Frequency 0
fS0
500
565
630
kHz
FREQ= Low (GND)
Programmable Frequency 1
fS1
700
790
880
kHz
FREQ = High (VDDA)
ILIM_HS0
6.0
7.1
8.1
A
HS Current Limit 1
ILIM_HS1
8.1
9.3
10.3
A
ILIM = High (VDDA)
HS Current Limit High Z
ILIM_HSZ
9.3
10.5
11.9
A
ILIM = High Z (open)
LEB
—
108
—
ns
LS Current Limit 0
ILIM_LS0
3.0
4.6
6.3
A
ILIM = Low (GND)
LS Current Limit 1
ILIM_LS1
4.0
6.2
7.9
A
ILIM = High (VDDA)
A
ILIM = High Z (Open)
VDDA 5V Supply
Operating Voltage
Dropout Operation
VDDA Undervoltage Lockout
VDDA UVLO Rising
EN/DLY Control
LDO Enable Threshold
Switching Frequency
Overcurrent Protection
HS Current Limit 0
Top FET Current Limit
Leading-Edge Blanking Time
LS Current Limit High Z
ILIM_LSZ
5.0
6.8
8.6
OC Events Count for Hiccup
INHICC_DE
—
15
—
Hiccup Wait Time
tHICC_WAIT
—
3 x Soft
Start Time
—
Note 1:
ILIM = Low (GND)
Clock Number of subsequent cycles
Cycles in current limit before entering
hiccup overload protection
Duration of the High Z state on
LX before new soft start.
Specification for packaged product only.
DS20005478A-page 4
 2015 Microchip Technology Inc.
MIC45404
ELECTRICAL CHARACTERISTICS(1) (CONTINUED)
Electrical Specifications: unless otherwise specified, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
Boldface values indicate -40°C  TJ  +125°C.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Pulse-Width Modulation (PWM)
Minimum LX On Time
TON(MIN)
—
26
—
ns
TA = TJ = +25°C
Minimum LX Off time
TOFF(MIN)
90
135
190
ns
VIN = VDDA = 5V, OUTSNS = 3V,
FREQ = Open (400 kHz setting),
VOSET0 = VOSET1 = 0V
(3.3V setting),
TA = TJ = +25°C
Minimum Duty Cycle
DMIN
—
0
—
%
OUTSNS > 1.1 x VOUT(NOM)
GmEA
—
1.4
—
mS
AEA
—
50000
—
V/V
Error Amplifier Source/Sink
Current
ISR_SNK
-400
—
+400
µA
COMP Output Swing High
COMP_H
—
2.5
—
V
COMP Output Swing Low
COMP_L
—
0.8
—
V
COMP-to-Inductor Current
Transconductance
GmPS
—
12.5
—
A/V
Output Voltage Accuracy for
Ranges 1 and 2
OutErr12
-1
—
1
%
4.75V  VIN  19V,
VOUT = 0.7V to 1.8V,
TA = TJ = -40°C to +125°C,
IOUT = 0A
Output Voltage Accuracy for
Range 3
OutErr3
-1.5
—
1.5
%
4.75V  VIN  19V,
VOUT = 2.49V to 3.3V,
TA = TJ = -40°C to +125°C,
IOUT = 0A
Load Regulation
LoadReg
—
0.03
—
%
IOUT = 0A to 5A
Line Regulation
LineReg
—
0.01
—
%
6V < VIN < 19V, IOUT = 2A
SS_SR
—
0.42
—
V/ms
PG Low Voltage
PG_VOL
—
0.17
0.4
V
PG Leakage Current
PG_ILEAK
-1
0.02
1
µA
PG = 5V
PG_R
90
92
95
%
VOUT Rising
Gm Error Amplifier
Error Amplifier
Transconductance
Error Amplifier DC Gain
TA = TJ = +25°C
VOUT = 1.2V, IOUT = 4A
Output Voltage DC Accuracy
Internal Soft Start
Reference Soft Start
Slew Rate
VOUT = 0.7V, 0.8V, 0.9V,
1.0V, 1.2V
Power Good (PG)
PG Rise Threshold
PG Fall Threshold
IPG = 4 mA
PG_F
87.5
90
92.5
%
VOUT Falling
PG Rise Delay
PG_R_DLY
—
0.45
—
ms
VOUT Rising
PG Fall Delay
PG_F_DLY
—
80
—
µs
VOUT Falling
Note 1:
Specification for packaged product only.
 2015 Microchip Technology Inc.
DS20005478A-page 5
MIC45404
ELECTRICAL CHARACTERISTICS(1) (CONTINUED)
Electrical Specifications: unless otherwise specified, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
Boldface values indicate -40°C  TJ  +125°C.
Parameter
Symbol
Min.
Typ.
Max.
Units
Thermal Shutdown
TSHDN
—
160
—
°C
Thermal Shutdown
Hysteresis
TSHDN_HYST
—
25
—
°C
η
—
82
—
%
Test Conditions
Thermal Shutdown
Efficiency
Efficiency
Note 1:
VIN = 12V, VOUT = 0.9V,
IOUT = 2A, fS = fSZ = 400 kHz,
TA = +25°C
Specification for packaged product only.
TEMPERATURE SPECIFICATIONS
Electrical Specifications: unless otherwise specified, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
Boldface values indicate -40°C  TJ  +125°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Temperature Ranges
Operating Ambient Junction Range
TJ
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Maximum Junction Temperature
TJ
-40
—
+150
°C
JA
—
20
—
°C/W
Package Thermal Resistances
Thermal Resistance, 54 Lead,
6 mm x10 mm QFN
DS20005478A-page 6
See “MIC45404 Evaluation
Board User’s Guide”
 2015 Microchip Technology Inc.
MIC45404
2.0
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
35.00
33.00
31.00
29.00
27.00
25.00
23.00
21.00
19.00
17.00
15.00
1.3
Switching
IOUT = 0A
1.25
f = 790 kHz
VOUT = 3.3V
f = 565 kHz
VOUT = 1.8V
f = 400 kHz
VOUT = 1.0V
Enable falling
0.95
8
10
12
VIN (V)
14
16
18
20
Operating Current (IQ) vs.
4.5
5
Current (µA)
4.8
4.6
4.4
4.2
IVDDA = 00 mA
IoutSet
IVDDA = 10
mA
IoutSet
0.01
4
4.5
6.5
8.5
10.5 12.5
VIN (V)
FIGURE 2-2:
Voltage.
14.5
16.5
18.5
VDDA Voltage vs. Input
VOUT = 1.2V
f = 400 kHz
6.5
8.5
FIGURE 2-4:
Voltage.
5.2
VDDA (V)
1.1
1.05
0.9
6
FIGURE 2-1:
Input Voltage.
8
1.15
1
4
8.5
Enable rising
1.2
Enable (V)
IQ (mA)
Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
5
6
7
8
IQ (mA)
IOUT (A)
6.5
ILIM = VDDA
EN/DLY Pull-up Current vs.
Switching
VIN = 12V
IOUT = 0A
f = 790 kHz
VOUT = 3.3V
30
f = 565 kHz
VOUT = 1.8V
25
6
f = 400 kHz
VOUT = 1.0V
20
5.5
18.5
9 10 11 12 13 14 15 16 17 18 19
VIN (V)
7.5
7
16.5
Enable Threshold vs. Input
FIGURE 2-5:
Input Voltage.
35
14.5
EN/DLY = 0V
4
ILIM = high Z
10.5 12.5
VIN (V)
ILIM = GND
5
4.5
5
FIGURE 2-3:
Input Voltage.
5.5
6
8 10
VIN(V)
12
14
16
18
19
Output Current Limit vs.
 2015 Microchip Technology Inc.
15
-40 -25 -10
FIGURE 2-6:
Temperature.
5
20 35 50 65
Temperature (°C)
80
95 110 125
Operating Current (IQ) vs.
DS20005478A-page 7
MIC45404
Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
800
VIN = 12V
400
200
Efficiency (%)
EA Output Current (µA)
600
Sinking
0
Sourcing
-200
-400
-600
-800
-40
-20
0
20
40
60
Temperature(°C)
FIGURE 2-7:
Temperature.
100
120
0.909
1
1.5 2 2.5
IOUT (A)
3
3.5
4
4.5
5
5VIN = 12V
12
VIN = 5V
0.907
0.905
1.6
1.4
1.2
0.903
0.901
0.899
0.897
1
0.895
0.8
0.893
0.6
0.891
-40
-20
0
FIGURE 2-8:
Temperature.
20
40
60
80
Temperature (°C)
100
120
140
EA Transconductance vs.
0
0.5
1
1.5
2 2.5
IOUT (A)
3
3.5
4
4.5
5
FIGURE 2-11:
Output Voltage vs. Output
Current (VOUT = 0.9V).
1.010
100.00%
90.00%
80.00%
70.00%
60.00%
50.00%
40.00%
30.00%
20.00%
10.00%
0.00%
5VIN = 12V
12
VIN = 5V
1.005
0.7V
12
0.8V
12
0.9V
12
12
1.0V
1.2V
12
12
1.5V
12
1.8V
12
2.5V
12
3.3V
0
0.5
1
1.5
2
2.5
IOUT (A)
3
3.5
4
FIGURE 2-9:
Efficiency vs. Output
Current (VIN = 12V).
DS20005478A-page 8
4.5
VOUT (V)
Efficiency (%)
0.5
FIGURE 2-10:
Efficiency vs. Output
Current (VIN = 5V).
EA Output Current vs.
VIN = 12V
VOUT = 1.0V
1.8
50.7V
50.8V
50.9V
51.0V
51.2V
51.5V
51.8V
52.5V
53.3V
0
140
VOUT (V)
EA Transconductance (mS)
2
80
100.00%
90.00%
80.00%
70.00%
60.00%
50.00%
40.00%
30.00%
20.00%
10.00%
0.00%
1.000
0.995
0.990
5
0
0.5
1
1.5
2 2.5
IOUT (A)
3
3.5
4
4.5
5
FIGURE 2-12:
Output Voltage vs. Output
Current (VOUT = 1.0V).
 2015 Microchip Technology Inc.
MIC45404
1.210
1.208
1.206
1.204
1.202
1.200
1.198
1.196
1.194
1.192
1.190
2.500
5VIN = 12V
VIN = 5V
12
2.490
2.485
2.480
0
0.5
1
1.5
2 2.5
IOUT (A)
3
3.5
4
4.5
5
FIGURE 2-13:
Output Voltage vs. Output
Current (VOUT = 1.2V).
0
5VIN = 12V
VIN = 5V
12
VOUT (V)
1.505
1.500
1.495
1.490
0
0.5
1
1.5
2 2.5
IOUT (A)
3
3.5
4
4.5
5
FIGURE 2-14:
Output Voltage vs. Output
Current (VOUT = 1.5V).
1.810
0.5
1
1.5
2 2.5
IOUTt (A)
3
3.5
4
4.5
5
FIGURE 2-16:
Output Voltage vs. Output
Current (VOUT = 2.5V).
1.510
VOUT (V)
5VIN = 12V
VIN = 5V
12
2.495
VOUT (V)
VOUT (V)
Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
3.310
3.308
3.306
3.304
3.302
3.300
3.298
3.296
3.294
3.292
3.290
5VIN = 12V
12
VIN = 5V
0
0.5
1
1.5
2 2.5
IOUT (A)
3
3.5
4
4.5
5
FIGURE 2-17:
Output Voltage vs. Output
Current (VOUT = 3.3V).
5VIN = 12V
VIN = 5V
12
VOUT (V)
1.805
1.800
1.795
1.790
0
0.5
1
1.5
2 2.5
IOUT (A)
3
3.5
4
4.5
5
FIGURE 2-15:
Output Voltage vs. Output
Current (VOUT = 1.8V).
 2015 Microchip Technology Inc.
DS20005478A-page 9
MIC45404
Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
VIN = 12V
VOUT = 1.2V
RLOAD = 0.3
fSW = 400 kHz
VIN
(5V/div)
VOUT
(500 mV/div)
VIN = 12V
VOUT = 1.2V
ROUT = 0.24
fSW = 400 kHz
EN/DLY(2V/div
IOUT(2A/div)
VOUT (500 mV/div)
PG
(5V/div)
PG(5V/div)
Time (2 ms/div)
FIGURE 2-18:
Time (40 µs/div)
VIN Turn-On.
FIGURE 2-21:
VIN = 12V
VOUT = 1.2V
RLOAD = 0.6
fSW = 400 kHz
VIN
(5V/div)
VOUT
(500 mV/div
Enable Turn-Off.
VIN = 12V
VOUT = 1.2V
VPRE-BIAS = 0.6V
fSW = 400 kHz
EN/DLY(2V/div
VOUT (500 mV/div)
PG
(5V/div)
PG(5V/div)
Time (2 ms/div)
FIGURE 2-19:
Time (1 ms/div)
VIN Turn-Off.
VIN = 12V
VOUT = 1.2V
ROUT = 0.24
fSW = 400 kHz
FIGURE 2-22:
Output.
EN/DLY(2V/div
IOUT(2A/div)
Enable Start-up w/Pre-Biased
VIN = 12V
VOUT = 1.2V
VPRE-BIAS = 1.0V
fSW = 400 kHz
EN/DLY(2V/div
VOUT (500 mV/div)
VOUT (500 mV/div)
PG(5V/div)
PG(5V/div)
Time (1 ms/div)
FIGURE 2-20:
DS20005478A-page 10
Enable Turn-On.
Time (1 ms/div)
FIGURE 2-23:
Enable Start-up
w/Pre-Biased Output.
 2015 Microchip Technology Inc.
MIC45404
Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
VIN = 12V
VOUT = 1.2V
fSW = 400 kHz
ILIM = high Z
PG(5V/div)
VIN(5V/div)
VOUT (500 mV/div)
IOUT(5A/div)
VOUT (500 mV/div)
IOUT(2A/div)
PG(5V/div)
Time (1 ms/div)
FIGURE 2-24:
Time (1 ms/div)
Power-up into Short Circuit.
FIGURE 2-27:
(ILIM = High Z).
Output Current Limit
PG(5V/div)
VOUT (500 mV/div)
EN/DLY(2V/div
IOUT(5A/div)
VOUT (500 mV/div)
IOUT(2A/div)
PG(5V/div)
Time (20 ms/div)
Time (1 ms/div)
FIGURE 2-25:
Enable into Short Circuit.
VIN = 12V
VOUT = 1.2V
fSW = 400 kHz
ILIM = 0V
PG(5V/div)
VOUT (500 mV/div)
FIGURE 2-28:
Hiccup Mode Short Circuit
and Output Recovery.
PG(5V/div)
VOUT (500 mV/div)
IOUT(2A/div)
Time (1 ms/div)
FIGURE 2-26:
(ILIM = 0V).
Output Current Limit
 2015 Microchip Technology Inc.
IOUT(2A/div)
Time (200 ms/div)
FIGURE 2-29:
Thermal Shutdown and
Thermal Recovery.
DS20005478A-page 11
MIC45404
Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
VIN = 12V
VOUT = 1.2V
IOUT = 0A
fSW = 400 kHz
SW (5V/div)
VOUT
AC-Coupled
(10 mV/div)
VIN
AC-Coupled
(20 mV/div)
PG (5V/div)
VOUT
AC-Coupled
(100 mV/div)
Time (1 µs/div)
FIGURE 2-30:
(IOUT = 0A).
Time (100 µs/div)
Switching Waveforms
VIN = 12V
VOUT = 1.2V
IOUT = 5A
fSW = 400 kHz
SW (5V/div)
VOUT
AC-Coupled
(10 mV/div)
VIN
AC-Coupled
(100 mV/div)
FIGURE 2-32:
DS20005478A-page 12
Switching Waveforms
Load Transient Response.
VIN
(2V/div)
VOUT
AC-Coupled
(20 mV/div)
PG(5V/div)
Time (1 µs/div)
FIGURE 2-31:
(IOUT = 5A).
VIN = 12V
VOUT = 1.0V
RLOAD = 1 to 0.3
IOUT
(2A/div)
Time (1 ms/div)
FIGURE 2-33:
Line Transient Response.
 2015 Microchip Technology Inc.
MIC45404
3.0
PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MIC45404
Symbol
Pin Function
1, 54
OUTSNS
2
EN/DLY
3
VDDP
MOSFET Drivers Internal Supply Pin
4
VDDA
Internal LDO Output and Analog Supply Pin
5, 6
GND_EXT
Output Sensing Pin
Precision Enable/Turn-On Delay Input Pin
Ground Extension Pins
Input Voltage Pins
7, 8
VIN
9, 23, 24, 50, 51
GND
Power Ground Pins
11, 12, 13, 14, 15, 16, 17, 18,
19, 20, 21
OUT
Output Side Connection Pins
10, 22, 25, 40
KEEPOUT
26, 27, 28, 29, 30, 31, 32, 33,
34, 35, 36, 37, 38, 39
LX
41, 42
BST
Bootstrap Capacitor Pin
43
PG
Power Good Output Pin
44
VOSET0
45
VOSET1
3.1
Depopulated Pin Positions
Switch Node Pins
Output Voltage Selection Pins
46, 47
NC
Not Connected Pins
48
ILIM
Current Limit Selection Pin
49
FREQ
Switching Frequency Selection Pin
52
AGND
Analog Ground Pin
53
COMP
55
GND_EP
Compensation Network Pin
Ground Exposed Pad.
Output Sensing Pins (OUTSNS)
Connect these pins directly to the Buck Converter
output voltage. These pins are the top side terminal of
the internal feedback divider.
3.2
Precision Enable/Turn-On Delay
Input Pin (EN/DLY)
The EN/DLY pin is first compared against a 515 mV
threshold to turn on the on-board LDO regulator. The
EN/DLY pin is then compared against a 1.21V (typical)
threshold to initiate output power delivery. A 150 mV
typical hysteresis prevents chattering when power
delivery is started. A 2 µA (typical) current source pulls
up the EN/DLY pin. Turn-on delay can be achieved by
connecting a capacitor from EN/DLY to ground, while
using an open-drain output to drive the EN/DLY pin.
 2015 Microchip Technology Inc.
3.3
MOSFET Drivers Internal
Supply Pin (VDDP)
Internal supply rail for the MOSFET drivers, fed by the
VDDA pin. An internal resistor (10) between the VDDP
and VDDA pins, and an internal decoupling capacitor
are provided in the module in order to implement an RC
filter for switching noise suppression.
3.4
Internal Regulator Output Pin
(VDDA)
Output of the internal linear regulator and internal
supply for analog control. A 1 µF minimum ceramic
capacitor should be connected from this pin to GND; a
2.2 µF nominal value is recommended.
DS20005478A-page 13
MIC45404
3.5
Ground Extension Pins
(GND_EXT)
These pins are used for the bottom terminal connection
of the internal VIN and VDDP decoupling capacitors.
The GND_EXT pins should be connected to the GND
net, directly at the top layer, using a wide copper
connection.
3.6
Input Voltage Pins (VIN)
Input voltage for the Buck Converter power stage and
input of the internal linear regulator. These pins are the
drain terminal of the internal high-side N-channel
MOSFET. A 10 µF (minimum) ceramic capacitor should
be connected from VIN to GND, as close as possible to
the device.
3.7
Power Ground Pins (GND)
Connect the output capacitors to GND Pins 23 and 24,
as close as possible to the module.
Connect the input capacitors to GND Pin 9, as close as
possible to the module.
3.8
Output-Side Connection Pins
(OUT)
Output side connection of the internal inductor. The
output capacitors should be connected from this pin
group to GND (Pins 23 and 24), as close to the module
as possible.
3.9
Switch Node Pins (LX)
Switch Node: Drain (low-side MOSFET) and source
(high-side MOSFET) connection of the internal power
N-channel FETs. The internal inductor switched side
and the bootstrap capacitor are connected to LX.
Leave this pin floating.
3.10
Bootstrap Capacitor Pin (BST)
Connection to the internal bootstrap capacitor and
high-side power MOSFET drive circuitry. Leave this pin
floating.
DS20005478A-page 14
3.11
Power Good Output Pin (PG)
When the output voltage is within 92.5% of the nominal
set point, this pin will go from logic low to logic high
through an external pull-up resistor. This pin is the drain
connection of an internal N-channel FET.
3.12
Output Voltage Selection Pins
(VOSET0 and VOSET1)
Three-state pin (low, high and High Z) for output voltage programming. Both VOSET0 and VOSET1 define
9 logic values, corresponding to nine output voltage
selections.
3.13
Not Connected Pins (NC)
These pins are not internally connected. Leave them
floating.
3.14
Current Limit Pin (ILIM)
This pin allows the selection of the current limit state:
low, high and High Z.
3.15
Switching Frequency Pin (FREQ)
This pin allows the selection of the frequency state: low,
high and High Z.
3.16
Analog Ground Pin (AGND)
This pin is a quiet ground for the analog circuitry of the
internal regulator and a return terminal for the external
compensation network.
3.17
Compensation Network Pin
(COMP)
Connect a compensation network from this pin to
AGND.
3.18
GND Exposed Pad
Connect to ground plane with thermal vias.
 2015 Microchip Technology Inc.
MIC45404
4.0
FUNCTIONAL DESCRIPTION
The MIC45404 is a pin-programmable, 5A Valley
Current mode controlled power module, with an input
voltage range from 4.5V to 19V.
The MIC45404 requires a minimal amount of external
components. Only two supply decoupling capacitors
and a compensation network are external. The
flexibility in designing the external compensation
allows the user to optimize the design across the entire
input voltage and selectable output voltages range.
4.1
Theory of Operation
Valley Current mode control is a fixed frequency, leading-edge modulated Pulse-Width Modulation (PWM)
Current mode control. Differing from the Peak Current
mode, the Valley Current mode clock marks the turn-off
of the high-side switch. Upon this instant, the
MIC45404 low-side switch current level is compared
against the reference current signal from the error
amplifier. When the falling low-side switch current signal drops below the current reference signal, the
high-side switch is turned on. As a result, the inductor
valley current is regulated to a level dictated by the
output of the error amplifier.
The feedback loop includes an internal programmable
reference and output voltage sensing attenuator, thus
removing the need for external feedback components
and improving regulation accuracy. Output voltage feedback is achieved by connecting the OUTSNS pin directly
to the output. The high-performance transconductance
error amplifier drives an external compensation network
at the COMP pin. The COMP pin voltage represents the
reference current signal. This pin voltage is fed to the
Valley Current mode modulator, which also adds slope
compensation to ensure current loop stability.
Internal inductor, power MOSFETs and internal
bootstrap diode complete the power train.
Overcurrent protection and thermal shutdown protect
the MIC45404 from Faults or abnormal operating
conditions.
4.2
Supply Rails (VIN, VDDA, VDDP)
and Internal LDO
An internal LDO provides a clean supply (5.1V typical)
for the analog circuits at the VDDA pin. The internal LDO
is also powered from VIN, as shown in the Functional
Diagram. The internal LDO is enabled when the
voltage at the EN/DLY pin exceeds about 0.51V, and
regulation takes place as soon as enough voltage has
been established between the VIN and VDDA pins. An
internal Undervoltage Lockout (UVLO) circuit monitors
the level of VDDA. The VDDA pin needs external bypassing to GND by means of a 2.2 µF X5R or X7R ceramic
capacitor, placed as close as possible to the module.
VDDP is the power supply rail for the gate drivers and
bootstrap circuit. This pin is bypassed to GND_EXT by
means of an internal high-frequency ceramic capacitor.
For this reason, the GND_EXT pins should be routed
with a low-inductance path to the GND net. An internal
10 resistor is provided between VDDA and VDDP,
allowing the implementation of a switching noise attenuation RC filter with the minimum amount of external
components. It is possible, although typically not
necessary, to lower the RC time constant by connecting
an external resistor between VDDA and VDDP.
If the input rail is within 4.5V to 5.5V, it is possible to
bypass the internal LDO by connecting VIN, VDDA and
VDDP together. Local decoupling of the VDDA pin is still
recommended.
4.3
Pin-Strapping Programmability
(VOSET0, VOSET1, FREQ, ILIM)
The MIC45404 uses pin strapping to set the output voltage (VOSET0, VOSET1), switching frequency (FREQ)
and current limit (ILIM). No external passives are needed,
therefore, the external component count is minimized.
Each pin is a three-state input (connect to GND for LOW
logic level, connect to VDDA for HIGH logic level or leave
unconnected for High Z). The logic level of the pins is
read and frozen in the internal configuration logic
immediately after the VDDA rail comes up and becomes
stabilized. After this instant, any change of the input logic
level on the pins will have no effect until the VDDA power
is cycled again. The values corresponding to each
particular pin strapping configuration are detailed in
Section 5.0 “Application Information”.
VIN pins represent the power train input. These pins are
the drain connection of the internal high-side MOSFET
and should be bypassed to GND, at least with a X5R or
X7R 10 µF ceramic capacitor, placed as close as
possible to the module. Multiple capacitors are
recommended.
 2015 Microchip Technology Inc.
DS20005478A-page 15
MIC45404
4.4
Enable/Delay (EN/DLY)
The EN/DLY pin is a dual threshold pin that turns the
internal LDO on/off and starts/stops the power delivery
to the output, as shown in Figure 4-1.
Enable LDO
Comparator
VIN
EN_I
2 µA
EN/DLY
EN_R
1.21V
FIGURE 4-1:
Enable Power
Comparator
Enable
150 mV Power
Delivery
EN/DLY Pin Functionality.
The threshold for LDO enable is 515 mV (typical) with
a hysteresis of approximately 30 mV. This hysteresis is
enough because at the time of LDO activation, there is
still no switching activity.
The threshold for power delivery is a precise 1.21V,
±70 mV. A 150 mV typical hysteresis prevents chattering
due to switching noise and/or slow edges.
Inductor (LX, OUT) and Bootstrap
(BST) Pins
The internal inductor is connected across the LX and
OUT pins. The high-side MOSFET driver circuit is powered between BST and LX by means of an internal
capacitor that is replenished from rail VDDP during the
low-side MOSFET on time. The bootstrap diode is
internal.
4.7
EN_LDO_R
515 mV
AGND
4.6
Output Sensing (OUTSNS) and
Compensation (COMP) Pins
OUTSNS should be connected exactly to the desired
Point-of-Load (POL) regulation, avoiding parasitic
resistive drops. The impedance seen into the OUTSNS
pin is high (tens of k or more, depending on the
selected output voltage value), therefore, its loading
effect is typically negligible. OUTSNS is also used by
the slope compensation generator.
The COMP pin is the connection for the external compensation network. COMP is driven by the output of the
transconductance error amplifier. Care must be taken
to return the compensation network ground directly to
AGND.
4.8
Soft Start
A 2 µA typical pull-up current, with ±1 µA accuracy, permits the implementation of a start-up delay by means of
an external capacitor. In this case, it is necessary to use
an open-drain driver to disable the MIC45404 while
maintaining the start-up delay function.
The MIC45404 internal reference is ramped up at a
0.42 V/ms rate. Note that this is the internal reference
soft start slew rate and that the actual slew rate seen at
the output should take into account the internal divider
attenuation, as detailed in the Section 5.0 “Application
Information”.
4.5
4.9
Power Good (PG)
The PG pin is an open-drain output that requires an
external pull-up resistor to a pull-up voltage (VPU_PG),
lower than 5.5V, for being asserted to a logic HIGH
level. The PG pin is asserted with a typical delay of
0.45 ms when the output voltage (OUTSNS) reaches
92.5% of its target regulation voltage. This pin is
deasserted with a typical delay of 80 µs when the
output voltage falls below 90% of its target regulation
voltage. The PG falling delay acts as a deglitch timer
against very short spikes. The PG output is always
immediately deasserted when the EN/DLY pin is below
the power delivery enable threshold (EN_R/EN_F).
The pull-up resistor should be large enough to limit the
PG pin current to below 2 mA.
DS20005478A-page 16
Switching Frequency (FREQ)
The MIC45404 features three different selectable
switching frequencies (400 kHz, 565 kHz and
790 kHz). Frequency selection is tied with a specific
output voltage selection, as described in Section 5.5
“Permissible MIC45404 Settings Combinations”.
4.10
Pre-Biased Output Start-up
The MIC45404 is designed to achieve safe start-up into
a pre-biased output without discharging the output
capacitors.
4.11
Thermal Shutdown
The MIC45404 has a thermal shutdown protection that
prevents operation at excessive temperature. The
thermal shutdown threshold is typically set at +160°C,
with a hysteresis of +25°C.
 2015 Microchip Technology Inc.
MIC45404
4.12
Overcurrent Protection (ILIM) and
Hiccup Mode Short-Circuit
Protection
The MIC45404 features instantaneous cycle-by-cycle
current limit with current sensing, both on the low-side
and high-side switches. It also offers a Hiccup mode for
prolonged overloads or short-circuit conditions.
The low-side cycle-by-cycle protection detects the current level of the inductor current during the low-side
MOSFET on time. The high-side MOSFET turn-on is
inhibited as long as the low-side MOSFET current limit is
above the overcurrent threshold level. The inductor current will continue decaying until the current falls below
the threshold, where the high-side MOSFET will be
enabled again, according to the duty cycle requirement
from the PWM modulator.
The low-side current limit has three different programmable levels (for 3A, 4A and 5A loads) in order to fit
different application requirements. Since the low-side
current limit acts on the valley current, the DC output
current level (IOUT), where the low-side cycle-by-cycle
current limit is engaged, will be higher than the current
limit value by an amount equal to ILPP/2, where ILPP
is the peak-to-peak inductor ripple current.
A Leading-Edge Blanking (LEB) timer (108 ns, typical)
is provided on the high-side cycle-by-cycle current limit
to mask the switching noise and to prevent falsely
triggering the protection. The high-side cycle-by-cycle
current limit action cannot take place before the LEB
timer expires.
Hiccup mode protection reduces power dissipation in
permanent short-circuit conditions. On each clock
cycle, where a low-side cycle-by-cycle current limit
event is detected, a 4-bit up/down counter is incremented. On each clock cycle without a concurrent
low-side current limit event, the counter is decremented
or left at zero. The counter cannot wraparound below
‘0000’ and above ‘1111’. High-side current limit events
do not increment the counter. Only detections from
low-side current limit events trigger the counter.
If the counter reaches ‘1111’ (or 15 events), the high
and low-side MOSFETs become tri-stated, and power
delivery to the output is inhibited for the duration of
three times the soft start time. This digital integration
mechanism provides immunity to momentary overloading of the output. After the wait time, the MIC45404
retries entering operation and initiates a new soft start
sequence.
The high-side current limit is approximately
1.4-1.5 times greater than the low-side current limit
(typical values). The high-side cycle-by-cycle current
limit immediately truncates the high-side on time
without waiting for the off clocking event.
 2015 Microchip Technology Inc.
DS20005478A-page 17
MIC45404
Figure 4-2 illustrates the Hiccup mode short-circuit protection logic flow. Note that Hiccup mode short-circuit
protection is active at all times, including the soft start
ramp.
START
CLEAR
LS OC EVENTS
COUNTER
CLOCK PULSE
(MARKING HS
TURN-OFF,
LS TURN-ON)
IDLE LOOP
IN NORMAL
OPERATION
YES
NO
EVENT
COUNTER = 0
LS OC EVENT
DETECTED?
NO
DECREMENT
EVENT
COUNTER
YES
YES
EVENT COUNTER
FULL?
NO
INITIATE HICCUP
SEQUENCE
INCREMENT
EVENT
COUNTER
STOP SWITCHING
HS AND LS
CYCLE THREE TIMES
INTERNAL SOFT START
CAPACITOR
INITIATE SOFT START
ENABLE SWITCHING
FIGURE 4-2:
DS20005478A-page 18
CLEAR
LS OC EVENTS
COUNTER
Hiccup Mode Short-Circuit Protection Logic.
 2015 Microchip Technology Inc.
MIC45404
5.0
APPLICATION INFORMATION
5.1
Programming Start-up Delay and
External UVLO
The EN/DLY pin allows programming an external
start-up delay. In this case, the driver for the EN/DLY
pin should be an open-drain/open-collector type, as
shown in Figure 5-1.
Enable LDO
Comparator
VIN
EN_I
2 µA
EN_LDO_R
515 mV
EN/DLY
Enable Power
Comparator
CDLY
Off
AGND
FIGURE 5-1:
150 mV
EN_R
1.21V
Enable
Power
Delivery
Programmable Start-up Delay Function.
The start-up delay is the delay time from the off falling
edge to the assertion of the enable power delivery
signal. It can be calculated as shown in Equation 5-1:
The EN/DLY pin can also be used to program a UVLO
threshold for power delivery by means of an external
resistor divider, as described in Figure 5-2.
EQUATION 5-1:
EN_R  C DLY
tSU_DLY = ----------------------------------EN_I
Where:
EN_R = 1.21V
EN_I = 2 µA
CDLY = Delay programming external capacitor
Enable LDO
Comparator
VIN
EN_I
2 µA
R2
EN_LDO_R
515 mV
EN/DLY
R1
AGND
FIGURE 5-2:
Enable Power
Comparator
EN_R
1.21V
150 mV
Enable
Power
Delivery
Programmable External UVLO Function.
 2015 Microchip Technology Inc.
DS20005478A-page 19
MIC45404
The programmed VIN UVLO threshold, VIN_RISE, is
given by:
EQUATION 5-2:
R2
V IN_RISE = EN_R   1 + ------ – EN_I  R 2

R 1
5.3
Setting the Output Voltage
The MIC45404 output voltage can be programmed by
setting pins, VOSET0 and VOSET1, as shown in
Table 5-2.
TABLE 5-2:
OUTPUT VOLTAGE SETTINGS
Where:
VOSET1
VOSET0
Output Voltage
EN_R = 1.21V
EN_I = 2 µA
R1 and R2 = External resistors
0 (GND)
0 (GND)
3.3V
0 (GND)
1 (VDDA)
2.5V (2.49V)
To desensitize the VIN UVLO threshold against variations of the pull-up current, EN_I, it is recommended to
run the R1 – R2 voltage divider at a significantly higher
current level than the EN_I current.
The corresponding VIN UVLO hysteresis, VIN_HYS, is
calculated as follows:
EQUATION 5-3:
R2
V IN_HYS = 150 mV   1 + ------

R 1
Similar calculations also apply to the internal LDO
activation threshold.
5.2
Setting the Switching Frequency
The MIC45404 switching frequency can
programmed using FREQ, as shown in Table 5-1.
TABLE 5-1:
be
SWITCHING FREQUENCY
SETTINGS
FREQ Pin Setting
Frequency
High Z (open)
400 kHz
0 (GND)
565 kHz
1 (VDDA)
790 kHz
The switching frequency setting is not arbitrary, but it
needs to be adjusted according to the particular output
voltage selection due to peak-to-peak inductor
ripple requirements. This is illustrated in Section 5.5
“Permissible MIC45404 Settings Combinations”.
1 (VDDA)
0 (GND)
1.8V
1 (VDDA)
1 (VDDA)
1.5V
0 (GND)
High Z (open)
1.2V
High Z (open)
0 (GND)
1.0V
1 (VDDA)
High Z (open)
0.9V
High Z (open)
1 (VDDA)
0.8V
High Z (open)
High Z (open)
0.7V
To achieve accurate output voltage regulation, the
OUTSNS pin (internal feedback divider top terminal)
should be Kelvin-connected as close as possible to the
point of regulation top terminal. Since both the internal
reference and the internal feedback divider’s bottom
terminal refer to AGND, it is important to minimize
voltage drops between the AGND and the point of
regulation return terminal.
5.4
Setting the Current Limit
The MIC45404’s valley-mode current limit on the
low-side MOSFET can be programmed by means of
ILIM as shown in Table 5-3.
TABLE 5-3:
ILIM
0 (GND)
1 (VDDA)
High Z (open)
CURRENT LIMIT SETTINGS
Valley Current Limit Rated Output
(Typical Value)
Current
4.6 A
6.2 A
6.8 A
3A
4A
5A
Note that the programmed current limit values act as
pulse-by-pulse, current limit thresholds on the valley
inductor current. If the inductor current has not decayed
below the threshold at the time the PWM requires a new
on time, the high-side MOSFET turn-on is either delayed,
until the valley current recovers below the threshold, or
skipped. Each time the high-side MOSFET turn-on is
skipped, a 4-bit up-down counter is incremented. When
the counter reaches the configuration ‘1111’, a hiccup
sequence is invoked in order to reduce power dissipation
under prolonged short-circuit conditions.
The highest current limit setting (6.8A) is intended to
comfortably accommodate a 5A application. Ensure
that the value of the operating junction temperature
does not exceed the maximum rating in high output
power applications.
DS20005478A-page 20
 2015 Microchip Technology Inc.
MIC45404
5.5
Permissible MIC45404 Settings
Combinations
The MIC45404 allowable settings are constrained by
the values in Table 5-4.
TABLE 5-4:
PERMISSIBLE MIC45404
SETTINGS COMBINATIONS
EQUATION 5-7:
 V R,ESR = ESR   I L_PP
The total peak-to-peak output
conservatively estimated as:
ripple
is
then
EQUATION 5-8:
Output Voltage
Frequency
3.3V
790 kHz
 VR   VR,C +  V R,ESR
565 kHz
The output capacitor value and ESR should be chosen
such that VR is within specifications. Capacitor tolerance should be considered for worst-case calculations.
In case of ceramic output capacitors, factor into
account the decrease of effective capacitance versus
applied DC bias.
2.5V (2.49V)
1.8V
1.5V
1.2V
400 kHz
1.0V
0.9V
0.8V
0.7V
5.6
Output Capacitor Selection
Two main requirements determine the size and
characteristics of the output capacitor, CO:
• Steady-state ripple
• Maximum voltage deviation during load transient
For steady-state ripple calculation, both the ESR and
the capacitive ripple contribute to the total ripple amplitude. The MIC45404 utilizes a low loss inductor, whose
nominal value is 1.2 µH. From the switching frequency,
input voltage, output voltage setting and load current,
the peak-to-peak inductor current ripple and the peak
inductor current can be calculated as:
EQUATION 5-4:
 I L_PP
VO
 1 – -------
VIN

= VO   ------------------
 fS  L 


EQUATION 5-5:
 I L_PP
I L,PEAK = I O + ----------------2
The capacitive ripple, Vr,C, and the ESR ripple,
Vr,ESR, are given by:
EQUATION 5-6:
 IL_PP
 VR,C = -------------------------8  fS  CO
 2015 Microchip Technology Inc.
The worst-case load transient for output capacitor calculation is an instantaneous 100% to 0% load release
when the inductor current is at its peak value. In this
case, all the energy stored in the inductor is absorbed
by the output capacitor, while the converter stops
switching and keeps the low-side FET on.
The peak output voltage overshoot (VO) happens
when the inductor current has decayed to zero. This
can be calculated with Equation 5-9:
EQUATION 5-9:
 VO =
2
2
L
VO + -------  I L,PEAK – V O
CO
Equation 5-10 calculates the minimum output
capacitance value (CO(MIN)) needed to limit the output
overshoot below VO.
EQUATION 5-10:
2
L  I L,PEAK
C O  MIN  = -----------------------------------------------2
2
  V O + VO  – VO
The result from the minimum output capacitance value
for load transient is the most stringent requirement
found for capacitor value in most applications. Low
Equivalent Series Resistance (ESR) ceramic output
capacitors, with X5R or X7R temperature ratings, are
recommended.
For low output voltage applications with demanding
load transient requirements, using a combination of
polarized and ceramic output capacitors may be the
most convenient option for smallest solution size.
DS20005478A-page 21
MIC45404
5.7
Input Capacitor Selection
Two main requirements determine the size and
characteristics of the input capacitor:
VIN
OUTSNS
R2
• Steady-State Ripple
• RMS Current
REFDAC
By assuming an ideal input filter (which can be assimilated to a DC input current feeding the filtered buck
power stage) and by neglecting the contribution of the
input capacitor ESR to the input ripple (which is typically
possible for ceramic input capacitors), the minimum
capacitance value, CIN(MIN), needed for a given input
peak-to-peak ripple voltage, Vr, IN, can be estimated as
shown in Equation 5-11:
EQUATION 5-11:
IO  D   1 – D 
= --------------------------------------- Vr,IN  fS
R1
The RMS current, IIN,RMS, of the input capacitor is
estimated as in Equation 5-12:
EQUATION 5-12:
I IN,RMS = I O  D   1 – D 
Note that, for a given output current, IO, worst-case
values are obtained at D = 0.5.
Multiple input capacitors can be used to reduce input
ripple amplitude and/or individual capacitor RMS
current.
5.8
Compensation Design
As a simple first-order approximation, the Valley Current
mode controlled buck power stage can be modeled as a
voltage controlled current source, feeding the output
capacitor and load. The inductor current state variable is
removed and the power stage transfer function from
COMP to the inductor current is modeled as a transconductance (GmPS). The simplified model of the control
loop is shown in Figure 5-3. The power stage transconductance, GmPS, shows some dependence on
current levels and it is also somewhat affected by
process variations, therefore, some design margin is
recommended against the typical value, GmPS = 12.5A/V
(see Section 1.0 “Electrical Characteristics”).
DS20005478A-page 22
Vo
COMP
RL
ESR
CC1
RC1
CC2
FIGURE 5-3:
Simplified Small Signal
Model of the Voltage Regulation Loop.
This simplified approach disregards all issues related
to the inner current loop, like its stability and bandwidth.
This approximation is good enough for most operating
scenarios, where the voltage loop bandwidth is not
pushed to aggressively high frequencies.
Based on the model shown in Figure 5-3, the
control-to-output transfer function is:
EQUATION 5-13:
Where:
D is the duty cycle at the given operating point.
GmEA
VO Range
IL
Co
Vc
The Buck Converter input current is a pulse train with
very fast rising and falling times, so low-ESR ceramic
capacitors are recommended for input filtering because
of their good high-frequency characteristics.
C IN  MIN 
GmPS
Gm Error
Amplifier
G CO  S 
s 
 1 + ---------------
2  fZ
VO  S 
= ------------- = Gm PS  RL  -------------------------------VC  S
s 
 1 + ---------------
2  f P
Where fZ and fP = the frequencies associated with
the output capacitor ESR zero and with the load
pole, respectively:
1
f Z = ------------------------------------2  C O  ESR
1
fP = ------------------------------------------------------2  C O   ESR + RL 
The MIC45404 module uses a transconductance
(GmEA = 1.4 mA/V) error amplifier. Frequency compensation is implemented with a Type-II network (RC1, CC1
and CC2) connected from the COMP to AGND. The
compensator transfer function consists of an integrator
for zero DC voltage regulation error, a zero to boost the
phase margin of the overall loop gain around the
crossover frequency and an additional pole that can
be used to cancel the output capacitor ESR zero, or to
further attenuate switching frequency ripple. In both
cases, the additional pole makes the regulation loop
less susceptible to switching frequency noise. The
additional pole is created by capacitor CC2 (internally
provided, CC2 value is 47 pF). Equation 5-14 details the
compensator transfer function, HC(S) (from OUTSNS to
COMP).
 2015 Microchip Technology Inc.
MIC45404
EQUATION 5-14:
EQUATION 5-17:
R1
1
H C  S  = – ---------------------  GmEA  -------------------------------------------R1 + R2
S   C C1 + C C2 
 1 + S  R C1  CC1 
 -------------------------------------------------------------------C C1  CC2 
 1 + S  R  --------------------------
C1 C

C1 + C C2
2   C O  f XO
R1 + R2
RC1 =  ---------------------  ----------------------------------- R1  GmEA  Gm PS
3.
The overall voltage loop gain, TV(S), is the product of
the control-to-output and the compensator transfer
functions:
EQUATION 5-15:
EQUATION 5-18:
T V  S  = G CO  S   H C  S 
The value of the attenuation ratio, R1/(R1 + R2),
depends on the output voltage selection and can be
retrieved as illustrated in Table 5-5:
TABLE 5-5:
R1/(R1 + R2)
A
(A = 1 + R2/R1)
0.7V-1.2V
1
1
1.5V-1.8V
0.5
2
2.5V(2.49V)-3.3V
0.333
3
The compensation design process is as follows:
1.
Set the TV(s) loop gain crossover frequency, fXO,
in the range of fS/20 to fS/10. Lower values of
fXO allow a more predictable and robust phase
margin. Higher values of fXO would involve additional considerations about the current loop
bandwidth in order to achieve a robust phase
margin. Taking a more conservative approach is
highly recommended.
EQUATION 5-16:
fS
fS
------  fXO  -----20
10
2.
VO
R L = ------IO
EQUATION 5-19:
INTERNAL FEEDBACK
DIVIDER ATTENUATION
VALUES
VO Range
Select RC1 to achieve the target crossover
frequency, fXO, of the overall voltage loop. This
typically happens where the power stage
transfer function, GCO(S), is rolling off at
-20 dB/decade. The compensator transfer function, HC(S), is in the so-called midband gain
region, where CC1 can be considered a DC
blocking short circuit, while CC2 can still be
considered as an open circuit, as calculated in
Equation 5-17:
 2015 Microchip Technology Inc.
Select capacitor CC1 to place the compensator
zero at the load pole. The load pole moves
around with load variations, so to calculate the
load pole use as a load resistance RL, the value
determined by the nominal output current, IO, of
the application, as shown in Equation 5-18 and
Equation 5-19:
C O   ESR + RL 
C C1 = -----------------------------------------RC1
4.
Knowing that an internal CC2 capacitor of 47 pF
is provided already, find out if any additional
capacitance is needed to augment the overall
value of the capacitor, CC2.
The CC2 (total value) is intended for placing the compensator pole at the frequency of the output capacitor
ESR zero and/or achieve additional switching
ripple/noise attenuation.
If the output capacitor is a polarized one, its ESR zero
will typically occur at low enough frequencies to cause
the loop gain to flatten out and not roll off at a
-20 dB/decade slope, around or just after the crossover
frequency, fXO. This causes undesirable scarce
compensation design robustness and switching noise
susceptibility. The compensator pole is then used to
cancel the output capacitor ESR zero and achieve a
well-behaved roll-off of the loop gain above the
crossover frequency.
If the output capacitors are only ceramic, then the ESR
zeros frequencies could be very high. In many cases,
the frequencies could even be above the switching
frequency itself. Loop gain roll-off at -20 dB/decade is
ensured well beyond the crossover frequency, but even
in this case, it is good practice to still make use of the
compensator pole to further attenuate switching noise,
while conserving phase margin at the crossover
frequency.
DS20005478A-page 23
MIC45404
For example, setting the compensator pole at 5 fXO will
limit its associated phase loss at the crossover
frequency to about 11°. Placement at even higher
frequencies, N × fXO (N > 5), will reduce phase loss
even further at the expense of less noise/ripple attenuation at the switching frequency. Some attenuation of
the switching frequency noise/ripple is achieved as
long as N × fXO < fS.
For the polarized output capacitor, compensator pole
placement at the ESR zero frequency is achieved, as
shown in Equation 5-20:
EQUATION 5-20:
1
C C2 = ----------------------------------------R C1
1
------------------------ – ---------C O  ESR C C1
5.9
Output Voltage Soft Start Rate
The MIC45404 features an internal analog soft start,
such that the output voltage can be smoothly increased
to the target regulation voltage. The soft start rate given
in Section 1.0 “Electrical Characteristics” is referred
to the error amplifier reference, and therefore, the
effective soft start rate value, seen at the output of the
module, has to be scaled according to the internal feedback divider attenuation values listed in Table 5-5. To
calculate the effective output voltage soft start slew
rate, SS_SROUT, based on the particular output voltage
setting and the reference soft start slew rate, SS_SR,
use the following formula:
EQUATION 5-23:
SS_SR OUT = A  SS_SR
Where:
For the ceramic output capacitor, compensator pole
placement at N × fXO (N 5, N × fXO < fS) is achieved,
as detailed in Equation 5-21:
A = Amplification
For the value of A, see the right column of Table 5-5.
EQUATION 5-21:
1
CC2 = ---------------------------------------------------------------1
2   R C1  N  fXO – ---------C C1
The MIC45404 already provides an internal CC2 capacitor of 47 pF. Therefore, the external capacitance,
CC2_EXT, that should be added is given by
Equation 5-22:
EQUATION 5-22:
C C2_EXT = max  C C2 – 47 pF, 0 pF 
If the result, CC2 – 47 pF, yields to zero or to a negative
number, no additional external capacitance is needed
for CC2.
DS20005478A-page 24
 2015 Microchip Technology Inc.
MIC45404
6.0
PACKAGING INFORMATION
 2015 Microchip Technology Inc.
DS20005478A-page 25
MIC45404
DS20005478A-page 26
 2015 Microchip Technology Inc.
MIC45404
APPENDIX A:
REVISION HISTORY
Revision A (December 2015)
• Original release of this document.
 2015 Microchip Technology Inc.
DS20005478A-page 27
MIC45404
NOTES:
DS20005478A-page 28
 2015 Microchip Technology Inc.
MIC45404
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
XX
Device
Lead Finish
Package Code
-XX(1)
Tape and Reel
Option
Device:
MIC45404: Ultra-low profile, synchronous step-down
regulator module
Lead Finish:
Y
=
Pb-Free with Industrial Temperature Grade
Package Code
MP
=
Module Package, thickness ≥ 2.0 mm
Examples:
a) MIC45404YMP-TR: Pb-Free, 54 Lead
6 x 10 x 2 mm QFN Package,
Tape and Reel.
Note 1:
Tape and Reel
Option:
TR
= Tape and Reel(1)
 2015 Microchip Technology Inc.
Tape and Reel identifier only appears in the
catalog part number description. This identifier is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
DS20005478A-page 29
MIC45404
NOTES:
DS20005478A-page 30
 2015 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
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•
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•
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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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ISBN: 978-1-5224-0125-4
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DS20005478A-page 31
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