MIC24045 I2C Programmable, 4.5V-19V Input, 5A Step-Down Converter Features General Description • • • The MIC24045 is an I2C-programmable, high-efficiency, wide input range, 5A synchronous step-down regulator. The MIC24045 is perfectly suited for multiple voltage rail application environments, typically found in computing and telecommunication systems. In the MIC24045 various parameters can be programmed via I2C, such as output voltage, switching frequency, soft-start slope, margining, current limit values and start-up delays. The wide switching frequency adjustment range, valley current-mode control technique, high-performance error amplifier and external compensation allow for the best trade-offs between high efficiency and the smallest possible solution size. • • • • • 4.5V to 19V Input Voltage Range 5A (maximum) Output Current I2C Programmable Output Voltage: - 0.64V to 5.25V in 5 mV, 10 mV, 30 mV and 50 mV steps High Efficiency (>95%) I2C Programmability of: - Soft-Start: 0.16, 0.38, 0.76 and 1.5V/ms ramp rates - Switching Frequency: 310 kHz, 400 kHz, 500 kHz, 570 kHz, 660 kHz, 780 kHz, 1 MHz, 1.2 MHz - Current Limits for 2A, 3A, 4A and 5A loads - Output Voltage Margining: -5%, +5% - Start-up delays: 0 ms to 10 ms ±1% Output Voltage Accuracy Over Temperature (0.64V to 1.95V) Supports Safe Start-Up with Pre-Biased Output Extensive Diagnostics through I2C Interface The MIC24045 supports extensive diagnostics and status information through I2C. The MIC24045 pinout is compatible with the MIC24046 pin-strapping programmable regulator pinout, such that I2C-based implementations can be easily converted into pin-programmable ones. The MIC24045 is available in a thermally-efficient, space-saving 20-pin 3 mm x 3 mm FQFN package, with an operating junction temperature range from -40°C to +125°C. Applications • Servers, Data Storage, Routers and Base Stations • FPGAs, DSP and Low-Voltage ASIC Power Typical Application VDDA VIN 4.5V to 19V VIN VINLDO VDDA AGND BST VOUT 0.64V to 5.25V LX PGND OUTSNS VDDP COMP MIC24045 VDDA I2C SDA ADR1 SCL VDDA PGOOD PG ENABLE EN 2016 Microchip Technology Inc. Address Selection ADR0 DS20005568A-page 1 MIC24045 Package Types OUTSNS EN VDDA VDDP VINLDO MIC24045 3 x 3 FQFN* (Top View) 20 19 18 17 16 VIN 1 21 VIN_EP 15 COMP VIN 2 14 AGND PGND 3 22 PGND_EP 13 PGND PGND 4 12 SDA 8 BST PG 9 10 ADR1 7 11 SCL ADR0 6 LX LX 5 23 LX_EP * Includes Exposed Thermal Pad (EP); see Table 3-1. Functional Block Diagram EN VINLDO VDDA Linear Regulator 2 µA 1.21V Reference and DAC UVLO Enable Comparator ADR0 ADR1 SCL SDA VOUT<7:0> POR I2C Interface and Registers VDDA ThSD, ThWrn Thermal Shutdown and Warning 10O SS<1:0> VOUT RANGE Current Limit REFDAC CLK Gm Error Amplifier R1 AGND HS LX LX_EP LS ISENSE R2 Power-Good Comparator VIN_EP PGND PGND_EP SoftStart DS20005568A-page 2 Gate Drive Freq<2:0> DLY VIN UVLO Ilim<1:0> OUTSNS PG BST High-Side Current Limit Control Logic/ Valley Current Mode Modulator REFDAC UVLO VDDP SLOPE Oscillator and Slope Compensation Low-Side ISense Low-Side Current Limit VIN OUTSNS COMP 2016 Microchip Technology Inc. MIC24045 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † VIN, VINLDO, VLX to AGND ........................................................................................................................... -0.3V to +20V VDDP, VDDA to AGND ..................................................................................................................................... -0.3V to +6V VINLDO to VDDA .......................................................................................................................................... -0.3V to +20V VDDP to VDDA ............................................................................................................................................ -0.3V to +0.3V VADRx, VSDA, VSCL to AGND ......................................................................................................................... -0.3V to +6V VBST to VLX .................................................................................................................................................. -0.3V to +6V VBST to AGND ............................................................................................................................................. -0.3V to +26V VEN to AGND .............................................................................................................................. -0.3V to VDDA+0.3V,+6V VPG to AGND ................................................................................................................................................. -0.3V to +6V VCOMP, VOUTSNS to AGND ......................................................................................................... -0.3V to VDDA+0.3V,+6V AGND to PGND ........................................................................................................................................... -0.3V to +0.3V Junction Temperature .......................................................................................................................................... +150°C Storage Temperature (TS) ...................................................................................................................... -65°C to +150°C Lead Temperature (soldering, 10s) ........................................................................................................................ 260°C ESD Rating(1) HBM ....................................................................................................................................................................... 2000V CDM ....................................................................................................................................................................... 2000V † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. Note 1: Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5 k in series with 100 pF. Operating Ratings(1) Supply Voltage (VIN,VINLDO) ......................................................................................................................... 4.5V to 19V Externally Applied Analog and Drivers Supply Voltage (VINLDO = VDDA = VDDP) ........................................ 4.5V to 5.5V Enable Voltage (VEN) ..................................................................................................................................... 0V to VDDA Power-Good (PG) Pull-up Voltage (VPU_PG)................................................................................................... 0V to 5.5V Output Current ............................................................................................................................................................. 5A Junction Temperature (TJ) ..................................................................................................................... -40°C to +125°C Note 1: The device is not ensured to function outside the operating range. 2016 Microchip Technology Inc. DS20005568A-page 3 MIC24045 ELECTRICAL CHARACTERISTICS (Note 1) Electrical Specifications: unless otherwise specified, VIN = VINLDO = 12V; CVDDA = 2.2 µF, CVDDP = 2.2 µF, TA = +25°C. Boldface values indicate -40°C TJ +125°C. Parameter Symbol Min. Typ. Max. Units Test Conditions VIN Supply Input Range VIN 4.5 — 19 V IVINQ — 0.2 2 µA EN = 0V IVINLDOQ — 0.6 1 mA EN = 0V Operating Current IVINOp — 0.3 0.5 mA EN > 1.28V, ILIM<1:0> = 00, OUTSNS = 1.15 x VOUT(NOM), no switching, TA = TJ = +25°C Operating Current IVINLDOOp — 4.5 7 mA EN > 1.28V, OUTSNS = 1.15 x VOUT(NOM), no switching, TA = TJ = +25°C Disable Current Disable Current VDDA 5V Supply Operating Voltage VDDA Dropout Operation 4.8 5.1 5.4 V IVDDA = 0 mA to 10 mA 3.6 4.2 — V VINLDO = 4.5V, IVDDA = 10 mA VDDA Undervoltage Lockout VDDA UVLO Rising UVLO_R 3.1 3.5 3.9 V VDDA Rising, EN > 1.28V VDDA UVLO Falling UVLO_F 2.87 3.2 3.45 V VDDA Falling, EN > 1.28V VDDA UVLO Hysteresis UVLO_H — 300 — mV EN_R 1.14 1.21 1.28 V Initiates power-stage operation Stops power-stage operation EN Control EN Rising Threshold EN Falling Threshold EN_F — 1.07 — V EN Hysteresis EN_H — 135 — mV EN Pull-Down Current EN_I 1 2 3 µA Programmable Frequency 0 fs0 270 310 350 kHz Programmable Frequency 1 fs1 350 400 450 kHz Programmable Frequency 2 fs2 450 500 550 kHz Programmable Frequency 3 fs3 510 570 630 kHz Programmable Frequency 4 fs4 590 660 740 kHz Programmable Frequency 5 fs5 680 780 880 kHz TA = TJ = +25°C Switching Frequency Programmable Frequency 6 fs6 850 970 1100 kHz Programmable Frequency 7 fs7 1050 1200 1350 kHz HS Current Limit 0 ILIM_HS0 4.0 4.7 6.5 A HS Current Limit 1 ILIM_HS1 5.4 6.2 7.6 A HS Current Limit 2 ILIM_HS2 7.6 8.6 10.6 A HS Current Limit 3 ILIM_HS3 8.2 9.4 12.0 A LEB — 108 — ns LS Current Limit 0 ILIM_LS0 2.0 3.25 5.0 A LS Current Limit 1 ILIM_LS1 3.0 4.3 6.0 A LS Current Limit 2 ILIM_LS2 4.0 5.6 7.5 A Overcurrent Protection High Side FET Current-Limit Leading Edge-Blanking Time Note 1: Specification for packaged product only. DS20005568A-page 4 2016 Microchip Technology Inc. MIC24045 ELECTRICAL CHARACTERISTICS (Note 1) Electrical Specifications: unless otherwise specified, VIN = VINLDO = 12V; CVDDA = 2.2 µF, CVDDP = 2.2 µF, TA = +25°C. Boldface values indicate -40°C TJ +125°C. Parameter Symbol Min. Typ. Max. Units ILIM_LS3 5.0 6.2 8.5 A OC Events Count for Hiccup INHICC_DE — 15 — Hiccup Wait Time tHICC_WAIT — 13.5V/ SS_SRx — ms Duration of the high-Z state on LX before new soft-start. SS_SRx = SS_SR0, SS_SR1, SS_SR2, SS_SR3 Low Side FET ON Resistance RLS — 16 21 m VIN = VINLDO = VDDP = VDDA = 5V, VBST-VLX = 5V, TA = TJ = +25°C High Side FET ON Resistance RHS — 38 50 m VIN = VINLDO = VDDP = VDDA = 5V, VBST-VLX = 5V, TA = TJ = +25°C LS Current Limit 3 Test Conditions Clock Number of subsequent cycles in Cycles current limit before entering hiccup overload protection. Power Switches Pulse-Width Modulation (PWM) Minimum LX ON Time TON(MIN) — 26 — ns TA = TJ = +25°C Minimum LX OFF time TOFF(MIN) 90 145 190 ns VIN = VINLDO = VDDA = 5V, VOUTSNS = 3V, 400 kHz setting, VOUT = 3.3V, TA = TJ = +25°C DMIN — 0 — % VOUTSNS > 1.1 x VOUT(NOM) GmEA — 1.4 — mS AEA — 50000 — V/V Error-Amplifier Source Current ISR — 400 — µA Error-Amplifier Sink Current ISNK — 400 — µA Minimum Duty Cycle Gm Error Amplifier Error-Amplifier Transconductance Error-Amplifier DC Gain COMP Output Swing High COMP_H — 2.5 — V COMP Output Swing Low COMP_L — 0.8 — V COMP-to-Inductor Current Transconductance GmPS — 12.5 — A/V Minimum Programmable Output Voltage MinOut — 0.64 — V Maximum Programmable Output Voltage MaxOut — 5.25 — V LSB for range 0.640V to 1.280V LSB1 — 5 — mV LSB for range 1.290V to 1.950V LSB2 — 10 — mV LSB for range 1.980V to 3.42V LSB3 — 30 — mV LSB for range 4.75V to 5.25V LSB4 — 50 — mV OutErr12 -1 — 1 % VOUT = 1.2V, IOUT = 4A Output Voltage DC Accuracy Output Voltage Accuracy for Ranges 1 and 2 Note 1: 4.75V VIN 19V, VOUT = 0.64V to 1.95V TA = TJ = -40°C to +125°C, IOUT = 0A Specification for packaged product only. 2016 Microchip Technology Inc. DS20005568A-page 5 MIC24045 ELECTRICAL CHARACTERISTICS (Note 1) Electrical Specifications: unless otherwise specified, VIN = VINLDO = 12V; CVDDA = 2.2 µF, CVDDP = 2.2 µF, TA = +25°C. Boldface values indicate -40°C TJ +125°C. Parameter Symbol Min. Typ. Max. Units Test Conditions Output Voltage Accuracy for Range 3 and 4 OutErr34 -1.5 — 1.5 % 4.75V VIN 19V for VOUT = 1.98V to 3.42V, 6V VIN 19V for VOUT = 4.75V to 5.25V, TA = TJ = -40°C to +125°C, IOUT = 0A Load Regulation LoadReg — 0.2 — % IOUT = 0A to 5A, VOUT = 3.3V Line Regulation LineReg — 0.1 — % 6V < VIN < 19V, IOUT = 2A Reference Soft-Start Slew Rate 0 SS_SR0 — 0.16 — V/ms VOUT = 0.64 to 1.28V Reference Soft-Start Slew Rate 1 SS_SR1 — 0.38 V/ms VOUT = 0.64 to 1.28V Reference Soft-Start Slew Rate 2 SS_SR2 — 0.76 V/ms VOUT = 0.64 to 1.28V Reference Soft-Start Slew Rate 3 SS_SR3 — 1.5 V/ms VOUT = 0.64 to 1.28V PG Low Voltage PG_VOL — 0.18 0.4 V I(PG) = 4 mA PG Leakage Current PG_ILEAK -1 0.02 1 µA VPG = 5V PG_R 90 92.5 95 % VOUT Rising Internal Soft-Start Power Good (PG) PG Rise Threshold PG_F 87.5 90 92.5 % VOUT Falling PG Rise Delay PG_R_DLY — 0.45 — ms VOUT Rising PG Fall Delay PG_F_DLY — 80 — µs VOUT Falling TSHDN — 160 — °C TSHDN_HYST — 25 — °C TThWrn — 120 — °C η — 82.3 — % VIN = 12V, VOUT = 0.9V, IOUT = 2A, fS = 400 kHz, L = 1.2 µH, TA = +25°C SDA, SCL VIH VIH 2 — — V VDDA = 5V (levels are 3.3V compatible) SDA, SCL VIL VIL — — 1 V VDDA = 5V (levels are 3.3V compatible) SDA, SCL Input High/Low Current IIH, IIL -1 — 1 µA SDA Output Low Voltage VOL — — 0.4 V PG Fall Threshold Thermal Shutdown Thermal Shutdown Thermal-Shutdown Hysteresis Thermal Warning Threshold Efficiency Efficiency I2C Interface Note 1: ISDA = 3 mA Specification for packaged product only. DS20005568A-page 6 2016 Microchip Technology Inc. MIC24045 TEMPERATURE SPECIFICATIONS Electrical Specifications: unless otherwise specified, VIN = VINLDO = 12V; CVDDA = 2.2 µF, CVDDP = 2.2 µF, TA = +25°C. Boldface values indicate -40°C TJ +125°C. Parameters Sym. Min. Typ. Max. Units Junction Temperature TJ -40 — +125 °C Storage Temperature Range TA -65 — +150 °C JA — 29 — °C/W Conditions Temperature Ranges Package Thermal Resistances Thermal Resistance, 20LD 3x3 FQFN 2016 Microchip Technology Inc. DS20005568A-page 7 MIC24045 2.0 TYPICAL CHARACTERISTIC CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Note: Unless otherwise indicated, VIN = 12V, fS = 660 kHz, ILIM = ILIM_LS3, L = 2.2 µH, TA = +25°C. 1.3 fs = 1.2 MHz Enable Thresholds (V) Operating Supply Current (mA) 30 fs = 660 kHz 20 10 fs = 310 kHz VOUT = 1.0V IOUT = 0 mA 0 4 Turn-off 1.1 19 4 9 14 Input Voltage (V) FIGURE 2-4: Voltage. 19 Enable Thresholds vs. Input 30 5.5 Operating Supply Current (mA) IVDDA= 0 mA VDDA Voltage (V) 1.2 1 9 14 Input Voltage (V) FIGURE 2-1: Operating Supply Current vs. Input Voltage, Switching. 5 IVDDA= 10 mA 4.5 4 3.5 4 FIGURE 2-2: 9 14 Input Voltage (V) 19 VDDA vs. Input Voltage. fs = 1.2 MHz 20 fs = 660 kHz 10 0 fs = 310 kHz VOUT = 1.0V IOUT = 0 mA -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 FIGURE 2-5: Operating Supply Current vs. Temperature, Switching. 0.998 8 ILIM_LS3 OUTSNS Voltage (V) Low-side Current Limits (A) Turn-on 6 ILIM_LS2 ILIM_LS1 4 ILIM_LS0 2 fs = 660 kHz VOUT = 1.0V FIGURE 2-3: Input Voltage. DS20005568A-page 8 0.996 0.995 VOUT = 1.0V IOUT = 0 mA fs = 660 kHz 0.994 0 4 0.997 9 14 Input Voltage (V) 19 Low-Side Current Limits vs. -40 -25 -10 FIGURE 2-6: Temperature. 5 20 35 50 65 80 95 110 125 Temperature (°C) OUTSNS Voltage vs. 2016 Microchip Technology Inc. MIC24045 Note: Unless otherwise indicated, VIN = 12V, fS = 660 kHz, ILIM = ILIM_LS3, L = 2.2 µH, TA = +25°C. 60 1.801 Switch RDSON (mΩ) OUTSNS Voltage (V) 1.802 1.8 1.799 1.798 1.797 -40 -25 -10 5 FIGURE 2-7: Temperature. 30 Low Side 10 20 35 50 65 80 95 110 125 Temperature (°C) OUTSNS Voltage vs. -40 -25 -10 20 35 50 65 Temperature (°C) 80 95 110 125 RDS(on) vs. Temperature. 3.303 3.302 3.301 3.3 3.299 VOUT = 3.3V IOUT = 0 mA fs = 660 kHz 3.298 3.297 Err. Amp. Transconductance (mS) 1.5 3.304 1.4 1.3 1.2 1.1 1 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) FIGURE 2-8: vs.Temperature. OUTSNS Voltage 5.014 5.013 5.012 5.011 5.01 5.009 5.008 5.007 5.006 5.005 5.004 5.003 5.002 5.001 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) FIGURE 2-11: Error Amplifier Transconductance vs. Temperature. 600 VOUT = 5.0V IOUT = 0 mA fs = 660 kHz -40 -25 -10 FIGURE 2-9: vs.Temperature. 5 20 35 50 65 80 95 110 125 Temperature (°C) OUTSNS Voltage 2016 Microchip Technology Inc. Error Amp. Output Current (µA) OUTSNS Voltage (V) 5 FIGURE 2-10: 3.305 OUTSNS Voltage (V) High Side 40 20 VOUT = 1.8V IOUT = 0 mA fs = 660 kHz 1.796 50 400 Sinking 200 0 -200 Sourcing -400 -600 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) FIGURE 2-12: Error Amplifier Output Current vs. Temperature. DS20005568A-page 9 MIC24045 Note: Unless otherwise indicated, VIN = 12V, fS = 660 kHz, ILIM = ILIM_LS3, L = 2.2 µH, TA = +25°C. 100 100 95 90 Efficiency (%) Efficiency (%) 90 85 80 Vout=0.8V VOUT = 0.8V 75 VOUT = 1.0V Vout=1.0V 70 VOUT = 1.2V Vout=1.2V 65 VOUT = 1.5V Vout=1.5V 60 VOUT = 1.8V Vout=1.8V 55 Vout=3.3V VOUT = 3.3V 0 1 2 IOUT (A) FIGURE 2-13: 3 4 70 60 50 VIN = 5V fs = 310 kHz 50 80 0 5 90 Efficiency (%) 95 90 Efficiency (%) 100 85 80 75 65 60 Vout=1.2V VOUT = 1.2V VOUT = 1.5V Vout=1.5V Vout=1.8V VOUT = 1.8V Vout=5V VOUT = 5.0V VOUT = 3.3V Vout=3.3V 55 0 1 FIGURE 2-14: 2 3 IOUT (A) 4 VIN = 12V fs = 660 kHz 75 IOUT (A) 3 4 5 Efficiency vs. Load Current. Series1 VOUT = 0.8V Series2 VOUT = 1.0V Series3 VOUT = 1.2V Series4 VOUT = 1.5V Series5 VOUT = 1.8V Series6 VOUT = 3.3V 70 65 50 0 5 100 2 80 55 Efficiency vs. Load Current. 1 85 60 VIN = 12V fs = 310 kHz 50 Vout=3.3V VOUT = 3.3V FIGURE 2-16: 95 VOUT = 1.0V Vout=1.0V VOUT = 1.5V Vout=1.5V Vout=1.8V VOUT = 1.8V 40 100 Vout=0.8V VOUT = 0.8V VOUT = 1.0V Vout=1.0V VOUT = 1.2V Vout=1.2V VOUT = 5.0V Vout=5V Efficiency vs. Load Current. 70 VOUT = 0.8V Vout=0.8V 1 VIN = 5V fs = 1.2 MHz 2 3 4 5 IOUT (A) FIGURE 2-17: Efficiency vs. Load Current. 100 95 90 85 80 Efficiency (%) Efficiency (%) 90 Vout=0.8V VOUT = 0.8V 75 Vout=1.0V VOUT = 1.0V 70 VOUT = 1.2V Vout=1.2V 65 80 70 Vout=0.8V VOUT = 0.8V Vout=1.2V VOUT = 1.2V Vout=1.8V VOUT = 1.8V Vout=5V VOUT = 5.0V 60 VOUT = 1.5V Vout=1.5V 60 50 VOUT = 1.8V Vout=1.8V 55 VIN = 5V fs = 660 kHz Vout=3.3V VOUT = 3.3V 50 0 1 FIGURE 2-15: DS20005568A-page 10 2 IOUT (A) 3 4 Vout=1.0V VOUT = 1.0V Vout=1.5V VOUT = 1.5V Vout=3.3V VOUT = 3.3V VIN = 12V fs = 1.2 MHz 40 5 Efficiency vs. Load Current. 0 FIGURE 2-18: 1 2 IOUT (A) 3 4 5 Efficiency vs. Load Current. 2016 Microchip Technology Inc. MIC24045 Note: Unless otherwise indicated, VIN = 12V, fS = 660 kHz, ILIM = ILIM_LS3, L = 2.2 µH, TA = +25°C. 3.307 0.999 VOUT = 1.0V fs = 660 kHz OUTSNS Voltage (V) OUTSNS Voltage (V) 0.998 0.997 0.996 0.995 0.994 0.993 3.305 3.304 3.303 VOUT = 3.3V fs = 660 kHz 3.302 0 1 FIGURE 2-19: Voltage vs. IOUT. 2 IOUT (A) 3 4 5 Load Regulation: OUTSNS 0 1 FIGURE 2-21: Voltage vs. IOUT. 2 IOUT (A) 3 4 5 Load Regulation: OUTSNS 5.02 1.802 VOUT = 1.8V fs = 660 kHz 5.019 OUTSNS Voltage (V) OUTSNS Voltage (V) 3.306 1.801 1.8 1.799 5.018 5.017 5.016 5.015 5.014 5.013 5.012 5.011 VOUT = 5V fs = 660 kHz 5.01 1.798 0 1 FIGURE 2-20: Voltage vs. IOUT. 2 IOUT (A) 3 4 5 Load Regulation: OUTSNS 2016 Microchip Technology Inc. 0 1 FIGURE 2-22: Voltage vs. IOUT. 2 IOUT (A) 3 4 5 Load Regulation: OUTSNS DS20005568A-page 11 MIC24045 Note: Unless otherwise indicated, VIN = 12V, fS = 660 kHz, ILIM = ILIM_LS3, L = 2.2 µH, TA = +25°C. VIN 5V/div VOUT 500 mV/div PG 5V/div IL 2A/div EN 2V/div VOUT 500 mV/div PG 5V/div IL 2A/div 4 ms/div FIGURE 2-23: VIN Turn-on (EN = VDDA, no I2C programming, registers default values for 2Z version), RLOAD = 0.3. 80 µs/div FIGURE 2-26: EN Turn-off, RLOAD = 0.3. VIN 5V/div EN 2V/div VOUT 500 mV/div VOUT 500 mV/div PG 5V/div PG 5V/div IL 2A/div IL 2A/div 4 ms/div FIGURE 2-24: RLOAD = 0.3. VIN Turn-off (EN = VDDA), EN 2V/div VOUT 500 mV/div PG 5V/div PG 5V/div IL 2A/div IL 2A/div 2 ms/div DS20005568A-page 12 FIGURE 2-27: EN Turn-on into pre-biased output (Vpre-bias = 0.5V). EN 2V/div VOUT 500 mV/div FIGURE 2-25: 2 ms/div EN Turn-on, RLOAD = 0.3. 2 ms/div FIGURE 2-28: EN Turn-on into pre-biased output (Vpre-bias = 0.8V). 2016 Microchip Technology Inc. MIC24045 Note: Unless otherwise indicated, VIN = 12V, fS = 660 kHz, ILIM = ILIM_LS3, L = 2.2 µH, TA = +25°C. VIN 5V/div VOUT 1V/div IL 5A/div AC coupled VOUT 500 mV/div IOUT 5A/div PG 5V/div PG 5V/div IL 2A/div 20 ms/div 10 ms/div FIGURE 2-29: Power-up into Short Circuit, (EN = VDDA, no I2C programming, registers default values for 2Z version). FIGURE 2-32: Hiccup Mode Short Circuit Current Limit Response. EN 2V/div IOUT 500 mA/div VOUT 500 mV/div PG 5V/div PG 5V/div VOUT 1V/div SW 10V/div IL 2A/div 100 ms/div 4 ms/div FIGURE 2-30: Enable into Short Circuit. VOUT 1V/div FIGURE 2-33: Response. IOUT 500 mA/div IL 5A/div AC coupled PG 5V/div IOUT 5A/div VOUT 1V/div PG 5V/div SW 10V/div 10 ms/div 1 ms/div FIGURE 2-31: Threshold. Thermal Shutdown Output Current Limit 2016 Microchip Technology Inc. FIGURE 2-34: Shutdown. Recovery from Thermal DS20005568A-page 13 MIC24045 Note: Unless otherwise indicated, VIN = 12V, fS = 660 kHz, ILIM = ILIM_LS3, L = 2.2 µH, TA = +25°C. Step from 0.5A to 5A PG 5V/div VIN 5V/div IOUT 5A/div VOUT 2 mV/div AC coupled SW 5V/div VOUT 100 mV/div AC coupled IL 1A/div IL 5A/div 1 µs/div FIGURE 2-35: Switching Waveforms fS = 660 kHz, IOUT = 0A. 80 µs/div FIGURE 2-38: Load Transient Response with ILIM = ILIM_LS3. Step from 11.8V to 13.2V VIN 5V/div VIN 2V/div VOUT 2 mV/div AC coupled VOUT 5 mV/div AC coupled IL 2A/div SW 5V/div PG 5V/div 1 µs/div 1 ms/div FIGURE 2-36: Switching Waveforms fS = 660 kHz, IOUT = 5A. Step from 0.2A to 2A FIGURE 2-39: Line Transient Response. PG 5V/div IOUT 2A/div VOUT 50 mV/div AC coupled IL 2A/div 80 µs/div FIGURE 2-37: Load Transient Response with ILIM = ILIM_LS0. DS20005568A-page 14 2016 Microchip Technology Inc. MIC24045 Note: Unless otherwise indicated, VIN = 12V, fS = 660 kHz, ILIM = ILIM_LS3, L = 2.2 µH, TA = +25°C. FIGURE 2-40: Voltage Loop Gain Bode Plot, VOUT = 1.8V, fs = 570 kHz, L = 1.2 µH, COUT = 266 µF, RC1 = 2.55k, CC1 = 10nF, CC2 = 47pF (see Section 7.7, Compensation Design). 2016 Microchip Technology Inc. DS20005568A-page 15 MIC24045 3.0 PIN DESCRIPTION The descriptions of the pins are listed in Table 3-1. TABLE 3-1: 3.1 PIN FUNCTION TABLE MIC24045 Symbol 1, 2 VIN 3, 4, 13 PGND 5, 6 LX 7 BST Pin Function Input Voltage Pin Power Ground Pin Switch Node Pin Bootstrap Capacitor Pin. A bootstrap capacitor is connected between the BST and LX pins. 8 PG 9 ADR0 I2C Address Programming Pin 0 Power Good Open-Drain Output Pin 10 ADR1 I2C Address Programming Pin 1 11 SCL I2C Clock Input Pin 12 SDA I2C Data Input/Output Pin 14 AGND Analog Ground Pin 15 COMP Transconductance Error Amplifier Output Pin. Connect the compensation network from COMP to AGND. 16 OUTSNS Output Sensing Pin 17 EN 18 VDDA Internal Regulator Output Pin Precision Enable Input Pin 19 VDDP MOSFET Drivers Internal Supply Pin 20 VINLDO Internal Regulator Input Pin 21 VIN_EP VIN Exposed Pad. Electrically connected to VIN. 22 PGND_EP 23 LX_EP PGND Exposed Pad. Electrically connected to PGND. LX Exposed Pad. Electrically connected to LX. Input Voltage Pin (VIN) Input Voltage pin for the Buck converter power stage. These pins are the drain terminal of the internal high-side N-channel MOSFET. A 10 µF minimum ceramic capacitor should be connected from VIN to the PGND pins as close as possible to the device. A combination of multiple ceramic capacitors of different sizes is recommended. 3.2 Power Ground Pin (PGND) Low-side MOSFET source terminal and low-side driver return. Connect the ceramic input capacitors to PGND as close as possible to the device. 3.3 Switch Node Pin (LX) Drain (low-side MOSFET) and source (high-side MOSFET) connection of the internal power N-channel FETs. The external inductor (switched side) and bootstrap capacitor (bottom terminal) must be connected to these pins. 3.4 Bootstrap Capacitor Pin (BST) Supply voltage for the driver of the high-side N-channel power MOSFET. Connect the bootstrap capacitor (top terminal) to this pin. 3.5 Power Good Output Pin (PG) When the output voltage is within 92.5% of the nominal set point, this pin will go from logic low to logic high through an external pull-up resistor. This pin is the drain connection of an internal N-channel FET. 3.6 I2C Address Programming Pin 0 (ADR0) Three-state pin (low, high and high-Z) for I2C address programming. Together with ADR1, ADR0 defines nine logic values corresponding to nine I2C addresses. 3.7 I2C Address Programming Pin 1 (ADR1) Three-state pin (low, high and high-Z) for I2C address programming. Together with ADR0, ADR1 defines nine logic values corresponding to nine I2C addresses. DS20005568A-page 16 2016 Microchip Technology Inc. MIC24045 3.8 I2C Clock Input Pin (SCL) The SCL pin is the serial interfaces Serial Clock pin.This pin is connected to the Host Controllers SCL pin. The MIC24045 is a slave device, so its SCL pin accepts only external clock signals. 3.9 I2C Data Input/Output Pin (SDA) The SDA pin is the serial interface Serial Data pin. This pin is connected to the Host Controllers SDA pin. The SDA pin has an open-drain N-channel driver. 3.10 Analog Ground Pin (AGND) This pin is a quiet ground for the analog circuitry of the internal regulator and a return terminal for the external compensation network. 3.11 Transconductance Error Amplifier Output Pin (COMP) 3.15 MOSFET Drivers Internal Supply Pin (VDDP) Internal supply rail for the MOSFET drivers, fed by the VDDA pin. An internal resistor (10) between the VDDP and VDDA pins is provided in the regulator in order to implement an RC filter for switching noise suppression. A 1 µF minimum ceramic capacitor should be connected from this pin to PGND; a 2.2 µF typical value is recommended. 3.16 Internal Regulator Input Pin (VINLDO) This pin is typically connected to the input voltage of the buck converter stage (VIN). If VINLDO and VIN are connected to different voltage rails, individually bypass VINLDO to ground with a 100 nF ceramic capacitor. 3.17 PGND Exposed Pad (PGND_EP) Connect a compensation network from this pin to AGND. Electrically connected to PGND pins. Connect with thermal vias to the ground plane to ensure adequate heat-sinking. See Section 9.0 “Packaging Information”. 3.12 3.18 Output Sensing Pin (OUTSNS) Connect this pin directly to the buck converter output voltage. This pin is the top side terminal of the internal feedback divider. 3.13 Electrically connected to VIN pins. If an input power distribution plane is available, connect with thermal vias to that plane to improve heat-sinking. See Section 9.0 “Packaging Information”. Precision Enable Input Pin (EN) The EN pin is compared to a 1.21V typical threshold to determine the turn-on of the device. After reaching the turn-on threshold, the I2C-programmable turn-on delay counter starts. A 2 µA (typical) current source pulls down the EN pin to prevent unwanted power delivery in case of a floating EN input. A 135 mV typical hysteresis prevents chattering when power delivery is started. 3.14 VIN Exposed Pad (VIN_EX) 3.19 LX Exposed Pad (LX_EP) Electrically connected to LX pins. See Section 9.0 “Packaging Information”. Internal Regulator Output Pin (VDDA) Output of the internal linear regulator and internal supply for analog control. A 1 µF minimum ceramic capacitor should be connected from this pin to AGND; a 2.2 µF typical value is recommended. 2016 Microchip Technology Inc. DS20005568A-page 17 MIC24045 4.0 FUNCTIONAL DESCRIPTION The MIC24045 is a digitally programmable, 5A valley current-mode controlled regulator featuring an input voltage range from 4.5V to 19V. Programmability is achieved by means of an I2C-compatible serial digital interface, which can support Serial Clock (SCL) rates up to 400 kHz (Fast mode). The MIC24045 requires a minimal amount of external components. Only the inductor, supply decoupling capacitors and compensation network are external. The flexibility in the external compensation design allows the user to optimize their design across the entire range of operating parameters such as input voltage, output voltage, switching frequency and load current. 4.1 Theory of Operation Valley current-mode control is a fixed-frequency, leading-edge-modulated PWM current-mode control. Differing from Peak Current mode, in valley current-mode the clock marks the turn-off of the high-side switch. Upon this instant, the MIC24045 low-side switch current level is compared against the reference current signal from the error amplifier. When the falling low-side switch current signal drops below the current reference signal, the high-side switch is turned on. As a result, the inductor valley current is regulated to a level dictated by the output of the error amplifier. As shown in Section 7.7 “Compensation Design”, the feedback loop includes an internal programmable reference (REFDAC) and an output voltage sensing attenuator (R2/R1), which removes the need for external feedback components and improves regulation accuracy. Output voltage feedback is achieved by connecting OUTSNS directly to the output. The high-performance transconductance error amplifier drives an external compensation network at the COMP pin. The COMP pin voltage represents the reference current signal. The COMP pin voltage is fed to the valley current-mode modulator, which also adds slope compensation to ensure current-loop stability. Valley current-mode control requires slope compensation at duty cycles less than 50% for current-loop stability. The slope compensation circuit is internal and it is automatically adapted in amplitude depending upon the frequency, output voltage range and voltage differential (VIN - VOUTSNS). The internal low-RDS(ON) power MOSFETs, the associated adaptive gate driver and the internal bootstrap diode complete the power train. 4.2 Internal LDO, Supply Rails (VIN, VINLDO, VDDA, VDDP) VIN pins represent the power train input. These pins are the drain connection of the internal high-side MOSFET and should be bypassed to PGND with a X5R or X7R 10 µF (minimum) ceramic capacitor, placed as close as possible to the device. A combination of ceramic capacitors of different sizes is recommended. An internal LDO (biased through VINLDO pin) provides a clean supply (5.1V typical) for the analog circuits and the I2C interface at pin VDDA. The internal LDO is typically powered from the same power rail feed at VIN; however, VINLDO can also be higher or lower than VIN and can be connected to any other voltage within its recommended limits. VINLDO and VDDA should be locally bypassed (see Section 3.0 “Pin Description”). A small series resistor (typically 2-10) can be used in combination with the VINLDO bypass capacitor to implement a RC filter for suppression of large high-frequency switching noise. The internal LDO is always enabled and regulation takes place as soon as enough voltage has established between the VINLDO and VDDA pins. If an external 5V±10% is available, it is possible to bypass the internal LDO by connecting VINLDO, VDDA and VDDP together at the external 5V rail, thus improving overall efficiency. The MIC24045 does not require a separate supply for the I2C interface and for the internal logic registers, which are all powered from the VDDA rail. An internal Undervoltage Lock-Out circuit (UVLO) monitors the level of VDDA and resets the interface and the internal registers if the VDDA voltage is below the UVLO threshold. VDDP is the power supply rail for the gate drivers and bootstrap circuit. This pin is subject to high-current spike with high-frequency content. To prevent these from polluting the analog VDDA supply, a separate capacitor is needed for VDDP pin bypassing. An internal 10 resistor is provided between pins VDDA and VDDP, allowing a switching noise attenuation RC filter with the minimum amount of external components to be implemented. It is possible, although typically not necessary, to lower the RC time constant by connecting an external resistor between pins VDDA and VDDP. Overcurrent protection and thermal shutdown protect the MIC24045 from faults or abnormal operating conditions. DS20005568A-page 18 2016 Microchip Technology Inc. MIC24045 4.3 Enable (EN) The EN pin starts/stops the power delivery to the output. It does not turn off the internal LDO. The EN pin does not act as a Reset signal for the I2C registers, only the VDDA UVLO circuit does. Rising threshold is a precise 1.21V±70 mV. A 135 mV typical hysteresis prevents chattering due to switching noise and/or slow edges. A 2 µA typical pull-down current with ±1 µA accuracy prevents unwanted start-ups if the EN pin is momentarily floating. To achieve automatic turn-on as soon as enough voltage is present, connect EN to VDDA. 4.4 Power Good (PG) PG is an open-drain output. For asserting a logic HIGH level, PG requires an external resistor connected to a pull-up voltage (VPU_PG), which should not exceed 5.5V. PG is asserted with a typical delay of 0.45 ms when the output voltage (OUTSNS) reaches 92.5% of its target regulation voltage. PG is de-asserted with a typical delay of 80 µs when the output voltage falls below 90% of its target regulation voltage. The PG falling delay acts as a de-glitch timer against very short spikes. The PG output is always immediately de-asserted when the EN pin is below the power delivery enable threshold (EN_R/EN_F). The pull-up resistor should be large enough to limit the PG pin current to below 2 mA. The PG is in a defined state once the VDDA voltage is greater than about 1V, but with reduced current sinking capability. The PG is also immediately de-asserted (with no delay) whenever an undervoltage condition on VDDA is detected, or in thermal shutdown. 4.5 Inductor (LX) and Bootstrap (BST) The external inductor is connected to LX. The high-side MOSFET driver circuit is powered between BST and LX by means of an external capacitor (typically 100 nF) that is replenished from rail VDDP during the low-side MOSFET ON-time. The bootstrap diode is internal. 4.6 Output Sensing (OUTSNS) and Compensation (COMP) OUTSNS should be connected exactly to the desired point-of-load regulation, avoiding parasitic resistive drops. The impedance seen into OUTSNS is high (tens of k or more, depending on the selected output voltage value), therefore its loading effect is typically negligible. OUTSNS is also used by the slope compensation generator. 4.7 Soft-Start The MIC24045 features four different I2C-selectable soft-start slew-rate values (0.16V/ms, 0.38V/ms, 0.76V/ms and 1.5V/ms). See the section Section 5.0 “Registers Maps and I2C Programmability” for the value vs. code mapping. The internal reference is ramped up at the selected rate. Note that this is the internal reference soft-start slew rate and that the actual slew rate seen at the output should take into account the internal divider attenuation, as detailed in the Section 7.0 “Application Information”. 4.8 Start-Up Delay The MIC24045 features eight different I2C-selectable start-up delays (from 0 ms to 10 ms). These represent the added delays from the EN rising edge to the beginning of the power delivery (soft-start). See the section Section 5.0, Registers Maps and I2C Programmability for the value vs. code mapping. 4.9 Switching Frequency The MIC24045 features eight different I2C-selectable switching frequencies from 310 kHz to 1200 kHz. See Section 5.0 “Registers Maps and I2C Programmability” for the value vs. code mapping. Also pay attention to voltage conversion ratio limitations due to minimum TON and TOFF, as stated in Section 7.0 “Application Information”. 4.10 Pre-Biased Output Start-Up The MIC24045 is designed to achieve safe start-up into a pre-biased output without discharging the output capacitors. 4.11 Thermal Warning and Thermal Shutdown The MIC24045 has a thermal shutdown protection that prevents operation at excessive temperature. The thermal shutdown threshold is typically set at +160°C with a hysteresis of +25°C. The MIC24045 features a Thermal Warning flag that is readable through the I2C interface (register polling is needed). The Thermal Warning flag signals the approaching of thermal shutdown, so that appropriate system-level countermeasures can be undertaken. Note that a thermal shutdown event will not disable the internal VDDA linear regulator, but only the power stage. In this way, the I2C interface remains powered and can still be read throughout the duration of the thermal shutdown. COMP is the connection for the external compensation network. COMP is driven by the output of the transconductance error amplifier. Care must be taken to return the compensation network ground directly to AGND. 2016 Microchip Technology Inc. DS20005568A-page 19 MIC24045 4.12 Overcurrent Protection The MIC24045 features instantaneous cycle-by-cycle current limit with current sensing both on the low-side and high-side switches. It also offers a Hiccup mode for prolonged overloads or short-circuit conditions. Low-side cycle-by-cycle protection detects the current level of the inductor current during the low-side MOSFET ON time. The high-side MOSFET turn-on is inhibited as long as the low-side MOSFET current limit is above the low-side current-limit threshold level. The inductor current will continue decaying until the current falls below the threshold, then the high-side MOSFET will be enabled again according to the duty cycle requirement from the PWM modulator. The mechanism is illustrated in Figure 4-1. IL LS OC Detected HS Turn-on Inhibited LS Current OK HS Turn-on is Enabled LS OC Detected HS Turn-on Inhibited ¨ILpp IOUT Low-Side Current-Limit Threshold Resulting Duty Cycle Required Duty Cycle Valley CM clock (HS OFF, LS ON) FIGURE 4-1: Low-Side Cycle-by-Cycle Current-Limit Action. The low-side current limit is programmable at four different levels (for 2A, 3A, 4A and 5A loads) in order to optimize inductor size for different application requirements. These levels are listed in Section 5.0 “Registers Maps and I2C Programmability”. Since the low-side current limit acts on the valley current, the DC output current level (IOUT), where the low-side cycle-by-cycle current limit is engaged, will be higher than the current limit value by an amount equal to ILPP/2, where ILPP is the peak-to-peak inductor ripple current. The high-side current limit is approximately 1.4 – 1.5 times greater than the low-side current limit (typical values). The high-side cycle-by-cycle current limit immediately truncates the high-side ON time without waiting for the OFF clocking event. A leading edge blanking (LEB) timer (108 ns, typical) is provided on the high-side cycle-by-cycle current limit to mask the switching noise and to prevent falsely triggering the protection. High-side cycle-by-cycle current limit action cannot take place before the LEB timer expires. Hiccup mode protection reduces power dissipation in permanent short-circuit conditions. On each clock cycle, where a low-side cycle-by-cycle current-limit event is detected, a 4-bit up/down counter is incremented. On each clock cycle, without a concurrent low-side current limit event, the counter is decremented or left at zero. The counter cannot wrap-around below DS20005568A-page 20 Time 0000 and above 1111. High-side current limit events do not increment the counter. Only detections from low-side current limit events trigger the counter. If the counter reaches 1111 (or 15 events), the high and low-side MOSFETs become tri-stated and power delivery to the output is inhibited for a duration which is dependent on the soft-start rate and can be calculated with the following equation: EQUATION 4-1: 13.5V Inhibited Time = -----------------SS_SRx Where SS_SRx = selected soft-start rate (SS_SRx = SS_SR0, SS_SR1, SS_SR2 or SS_SR3). See Electrical Characteristics table. This digital integration mechanism provides immunity to the momentary overloading of the output. After the wait time, the MIC24045 retries entering operation and initiates a new soft-start sequence. Note that Hiccup mode short-circuit protection is active at all times, including the soft-start ramp. In case of very large output capacitors, consider slowing down the soft-start slew rate to prevent start-up problems, especially if the load is completely discharging the output capacitor during the hiccup wait time. 2016 Microchip Technology Inc. MIC24045 START CLEAR LS OC EVENTS COUNTER CLOCK PULSE (MARKING HS TURN-OFF, LS TURN-ON) IDLE LOOP IN NORMAL OPERATION YES NO EVENT COUNTER = 0 LS OC EVENT DETECTED? NO DECREMENT EVENT COUNTER YES YES EVENT COUNTER FULL? NO INITIATE HICCUP SEQUENCE INCREMENT EVENT COUNTER STOP SWITCHING HS AND LS WAIT INHIBITED TIME INITIATE SOFT-START ENABLE SWITCHING FIGURE 4-2: CLEAR LS OC EVENTS COUNTER Hiccup Short-Circuit Protection Flowchart. 2016 Microchip Technology Inc. DS20005568A-page 21 MIC24045 5.0 REGISTERS MAPS AND I2C PROGRAMMABILITY The MIC24045 internal registers are summarized in Table 5-1, below. TABLE 5-1: MIC24045 REGISTER MAP Register Register Address Name 0h Status Type B7 B6 B5 B4 B3 RO OCF ThSDF ThWrnF Reserved EnS B2 B1 Reserved Reserved B0 PGS 1h Setting 1 RW ILIM1 ILIM0 Freq2 Freq1 Freq0 2h Setting 2 RW Reserved SUDly2 SUDly1 SUDly0 Mrg1 Mrg0 SS1 SS0 3h VOUT RW VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 VOUT0 4h Command RW DS20005568A-page 22 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ClFF 2016 Microchip Technology Inc. MIC24045 5.1 STATUS Register In the read-only STATUS registers, diagnostic information is provided. Bits can be F = latched (Flag) or S = non-latched (Status). Flag bits are set when the corresponding Fault condition has occurred and do not return-to-zero once the Fault condition has ceased. Flags can only be cleared by writing ‘1’ in Bit 0 of the COMMAND register 4h, or REGISTER 5-1: by power cycling. Status bits are set when the corresponding Fault condition has occurred and return to zero automatically once the Fault condition has ceased. Default bits value at power-up is zero, except for Bit 2 (which will always be read as ‘1’) and Bit 1, which is ‘1’ if no Fault conditions are detected. STATUS – STATUS REGISTER (ADDRESS 0h) R-0 R-0 R-0 R’0’ R-0 R’1’ R-1 R-0 OCF ThSDF ThWrnF Reserved EnS Reserved Reserved PGS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown RC = Read-then-clear bit bit 7 OCF: Over-Current Flag bit. OCF is set high whenever an over-current event occurs. Latched. bit 6 ThSDF: Thermal Shut-down Flag bit. ThSDF is set high whenever a Thermal Shutdown occurs. Latched. bit 5 ThWrnF: Thermal Warning Flag bit. ThWrnF is set high whenever a Thermal Warning occurs. Latched. bit 4 Reserved: Flag bit. Always read as zero. bit 3 EnS: Enable Pin Status bit. EnS reflects the logic value present on pin EN. Non-latched. bit 2 Reserved: Status bit. Always read as ‘1’. bit 1 Reserved: Default status at POR is ‘1’ (no faults detected). bit 0 PGS: Power-Good Status bit. PGS reflects the logic value present on pin PG. Non-latched. REGISTER 5-2: SETTING 1 – SETTING 1 REGISTER (ADDRESS 1h) RW-V RW-V RW-V RW-V RW-V U-0 U-0 U-0 ILIM1 ILIM0 Freq2 Freq1 Freq0 Reserved Reserved Reserved bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared RC = Read-then-clear bit V = factory-programmed POR value(1) Note 1: 2: x = Bit is unknown Default Status settings at power-up can be changed at the factory. Standard selections are described in Section 6.0 “MIC24045 Default Settings Values at Power-Up”. Overwriting default settings by I2C has no permanent effect and values will return to factory default values upon power cycling. Changing Setting 1 Register values while power delivery is enabled is not recommended. To change settings by I2C, set EN pin low first, then write the new configuration, and finally, set EN pin high again to resume power delivery. 2016 Microchip Technology Inc. DS20005568A-page 23 MIC24045 REGISTER 5-2: bit 7-6 SETTING 1 – SETTING 1 REGISTER (ADDRESS 1h) (CONTINUED) ILIM<1:0>: MOSFET Current Limit bit. See the Current Limit selection in table below: ILIM1 ILIM0 bit 5-3 TYP Low-Side TYP High-Side Nominal Load Current Limit (A) Current Limit (A) Current (A) 0 0 3.25 4.7 2 0 1 4.3 6.2 3 1 0 5.6 8.6 4 1 1 6.2 9.4 5 Freq0 (Switching Frequency): See the Switching Frequency selection in table below: Freq2 Freq1 Freq0 bit 2-0 Frequency (kHz) 0 0 0 310 0 0 1 400 0 1 0 500 0 1 1 570 1 0 0 660 1 0 1 780 1 1 0 970 1 1 1 1200 Reserved: Unimplemented bit. Read as ‘0’. Note 1: 2: Default Status settings at power-up can be changed at the factory. Standard selections are described in Section 6.0 “MIC24045 Default Settings Values at Power-Up”. Overwriting default settings by I2C has no permanent effect and values will return to factory default values upon power cycling. Changing Setting 1 Register values while power delivery is enabled is not recommended. To change settings by I2C, set EN pin low first, then write the new configuration, and finally, set EN pin high again to resume power delivery. DS20005568A-page 24 2016 Microchip Technology Inc. MIC24045 REGISTER 5-3: SETTING 2 – SETTING 2 REGISTER (ADDRESS 2h) U-0 RW-V RW-V RW-V RW-0 RW-0 RW-V RW-V Reserved SUDly2 SUDly1 SUDly0 Mrg1 Mrg0 SS1 SS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown (1) RC = Read-then-clear bit V = factory-programmed POR value bit 7 Reserved: Unimplemented bit. Read as ‘0’. Writing to this bit has no effect. bit 6-4 SUDly<2:0>: Start-Up Delay bit. Delay to start power delivery from the rising edge of the EN signal. See the Start-up Delay selection in table below: SUDly2 SUDly1 SUDly0 Start-Up Delay (ms) bit 3-2 0 0 0 0 0 0 1 0.5 0 1 0 1 0 1 1 2 1 0 0 4 1 0 1 6 1 1 0 8 1 1 1 10 Mrg<1:0>: Voltage Margins bit. These bits can be changed at any time during power delivery. See the Voltage Margining selection in table below: Mrg1 Mrg0 Change to nominal VOUT Setting (%) 0% 0 0 0 1 -5% 1 0 +5% 1 1 +5% Default at power-up is <0:0> bit 1-0 SS1<1:0>: Soft-Start Ramp Rate bit. See the Soft-Start Tamp Rates selection in table below: SS1 SS0 Soft-Start Slope (V/ms) Note 1: 2: 0 0 0.16 0 1 0.38 1 0 0.76 1 1 1.5 For all bits (except Margining bits Mrg<1:0>) the Default Status at power-up can be changed at the factory. Standard selections are described in Section 6.0 “MIC24045 Default Settings Values at Power-Up”. Overwriting default settings by I2C has no permanent effect and values will return to factory default settings upon power cycling. Default power-up status for Mrg<1:0> is <0:0>. With the exception of Margining Bits Mrg<1:0>, changing Setting 2 register values while power delivery is enabled is not recommended. To change settings by I2C, set EN pin low first, then write the new configuration, and finally, set EN pin high again to resume power delivery. 2016 Microchip Technology Inc. DS20005568A-page 25 MIC24045 REGISTER 5-4: VOUT – VOUT REGISTER (ADDRESS 3h) RW-V RW-V RW-V RW-V RW-V RW-V RW-V RW-V VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 VOUT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared RC = Read-then-clear bit bit 7-0 x = Bit is unknown (1) V = factory-programmed POR value VOUT<7:0>: VOUT register bits can be changed at any time during power delivery, provided that transitions from one code to another: • are done step-by-step, by small VOUT increments. The speed of the transition is left to the user and limited by the I2C writing interface speed. • code transition shall take place only within the same VOUT Range. Crossing boundaries of resolution ranges may cause VOUT glitches and it is not recommended. See VOUT selection in table below: VOUT Range Step Size Codes-decimal (hex) Note 1: 2: 0.640V to 1.280V 5 mV 0 (00h) to 128 (80h) 1.290V to 1.950V 10 mV 129 (81h) to 195 (C3h) 1.980V to 3.420V 30 mV 196 (C4h) to 244 (F4h) 4.750V to 5.250V 50 mV 245 (F5h) to 255 (FFh) Default Status settings at power-up can be changed at the factory. Standard selections are described in Section 6.0 “MIC24045 Default Settings Values at Power-Up”. Overwriting default settings by I2C has no permanent effect and values will return to factory default values upon power cycling. The functionality of the MIC24045 at any output voltage selection is subject to limitations described in Section 7.0 “Application Information”. REGISTER 5-5: COMMAND – COMMAND REGISTER (ADDRESS 4h) RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved ClFF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown RC = Read-then-clear bit bit 7-1 Reserved<7:1>: Writing to these bits has no effect to the device operation. bit 0 ClFF: Clear Fault Flags bit. Writing ‘1’ to bit 0 will clear all Fault Flags. The ClFF bit is self-clearing and it returns to ‘0’ as soon as the Fault Flags have been cleared. DS20005568A-page 26 2016 Microchip Technology Inc. MIC24045 6.0 MIC24045 DEFAULT SETTINGS VALUES AT POWER-UP Part number MIC24045-XXYFL also designates different default settings values at power-up, before any I2C writing operation takes place. These values are programmed at factory. Different default settings are obtained by burning an OTP memory (fuses). The XX code corresponds to a certain combination of output voltage, switching frequency, nominal load current and soft-start ramp rate. Start-up delay and voltage margining always default to 0 ms and 0%. The blank (all zeros) OTP memory option has a special code (2Z). The standard default settings are as shown in Table 6-1. For availability of other default settings, contact the nearest Microchip Sales Office. TABLE 6-1: STANDARD DEFAULT SETTINGS Full Part Number Code VOUT (V) Frequency Load Current Reference Soft-Start Rate MIC24045-2ZYFL 2Z 0.64 310 kHz 2A 0.16V/ms MIC24045-DIYFL DI 1.0 780 kHz 5A 0.38V/ms MIC24045-EIYFL EI 1.2 780 kHz 5A 0.38V/ms MIC24045-JFYFL JF 3.3 570 kHz 5A 0.38V/ms MIC24045-KDYFL KD 5.0 570 kHz 3A 0.38V/ms When power is cycled, the MIC24045 user-programmable registers return to the factory-programmed default settings values, regardless of any prior settings through I2C bus. Note that the EN pin does NOT act as a Reset signal for the user-programmable registers, only the internal POR (Power-on Reset) based on the VDDA voltage UVLO does (see Functional Block Diagram). 2016 Microchip Technology Inc. DS20005568A-page 27 MIC24045 7.0 APPLICATION INFORMATION 7.1 Programming External UVLO The EN pin can be used to program an automatic turn-on of the MIC24045 when the VIN (or VINLDO) power rails have exceeded a desired threshold. This programmable UVLO function is achieved as described in Figure 7-1. Enable Comparator EN EN_I 2 µA AGND FIGURE 7-1: UVLO Function. 135 mV EN_R 1.21V Enable Power Delivery Programmable External The programmed VIN UVLO threshold VIN_RISE is given by: EQUATION 7-1: R2 V IN_RISE = EN_R 1 + ------- + EN_I R2 R1 where: EN_R = 1.21V EN_I = 2 µA RI, R2 = External resistors To desensitize the VIN UVLO threshold against variations of the pull-up current EN_I, it is recommended to run the R1-R2 voltage divider at a significantly higher current level than the EN_I current. The corresponding VIN UVLO hysteresis, VIN_HYS, is calculated as follows: EQUATION 7-2: R2 V IN_HYS = 135 mV 1 + ------- R1 DS20005568A-page 28 VOUT On-The-Fly Changes It is possible to change the output voltage on-the-fly during power delivery by writing a different value to Register 5-4 (Address 3h). Note that VOUT changes are possible only within each VOUT range, as specified in the VOUT selection table in Register 5-4. VINLDO R2 Output Voltage Sensing To achieve accurate output voltage regulation, the OUTSNS pin (internal feedback divider top terminal) should be Kelvin-connected as close as possible to the point-of-regulation top terminal. Since both the internal reference and the internal feedback divider’s bottom terminal refer to AGND, it is important to minimize voltage drops between the AGND and the point-of-regulation return terminal. 7.3 VIN R1 7.2 The transition from one particular VOUT value to another is under control of the I2C interface. The number of steps from one code to another and the speed of the transition are left to the end user. Single Write instructions separated by a Repeated START (Sr) can be used to update Register 5-4 multiple subsequent times, without releasing the I2C bus. Please refer to section Section 8.5.2 “Single Write with Repeated Start (Sr)” for more details. The minimum tSU_STA specification (set-up time for a repeated START condition), the SCL frequency and the length of the Single Write message (3 bytes) dictate a limitation on the maximum update rate of the VOUT code at Register 5-4. Ramping down the output voltage at no or light load implies inductor current reversal (i.e., the MIC24045 will be sinking current from the output capacitor). The larger the output capacitor value, the larger the reverse inductor current will be for a given negative VOUT variation.The voltage steps and the ramping step rate should be small enough to maintain a safe level of reverse current magnitude. This is especially important when using large output capacitors. 7.4 Inductor Selection and Slope Compensation When selecting an inductor, it is important to consider the following factors: • • • • • Inductance Rated Current value Size requirements DC Resistance (DCR) Core losses 2016 Microchip Technology Inc. MIC24045 The inductance value is critical to the operation of MIC24045. Since the MIC24045 is a valley current-mode regulator, it needs a slope compensation for the stable current loop operation where duty cycles are below 50%. Slope compensation is internally programmed according to the frequency, output voltage and nominal load current selection, assuming there is a minimum inductance value for the given operating condition. TABLE 7-1: Nominal IOUT Table 7-1 lists the assumed minimum inductor values recommended for stable current-loop operation. Note that the minimum suggested inductance values should be met when taking into account the inductor tolerance and its change with current level. MINIMUM RECOMMENDED INDUCTANCE VALUES VOUT Minimum Inductance LMIN (µH) 3A-4A-5A 0.64V-1.28V 1.27 0.97 0.78 0.68 0.58 0.49 0.39 0.29 3A-4A-5A 1.29V-1.95V 1.96 1.51 1.21 1.06 0.91 0.76 0.61 0.45 3A-4A-5A 1.98V-3.42V 3.14 2.42 1.94 1.70 1.46 1.21 0.97 0.73 3A-4A-5A 4.57V-5.25V 3.69 2.36 2.27 1.99 1.70 1.42 1.14 0.85 2A 0.64V-1.28V 2.52 1.94 1.55 1.36 1.16 0.97 0.78 0.58 2A 1.29V-1.95V 4.07 3.13 2.50 2.18 1.87 1.56 1.25 0.94 2A 1.98V-3.42V 6.53 5.03 4.01 3.52 3.02 2.52 2.01 1.51 2A 4.57V-5.25V 9.14 6.99 5.60 4.91 4.18 3.49 2.80 2.10 310 400 500 570 660 780 970 1200 The slope compensation is also internally adapted to the input-output voltage differential. In practical implementations of valley current-mode control, slope compensation is also added to any duty cycle larger than 50% as part of improving current loop stability and noise immunity for all input and output voltage ranges. Consequently, the MIC24045 adds internal slope compensation signal up to 80% duty cycle. Above this, no slope compensation is added. For this reason, the PWM modulator gain exhibits an abrupt change when the duty cycle exceeds 80%, possibly leading to some increase in jitter and noise susceptibility. If operation around and above 80% duty cycle is considered, a more conservative design of the compensation loop might help in reducing jitter and noise sensitivity. Inductor current ratings are generally stated as permissible DC current and saturation current. Permissible DC current can be rated for a +20°C to +40°C temperature rise. Saturation current can be rated for a 10% to 30% loss in inductance. Ensure that the nominal current of the application is well within the permissible DC current ratings of the inductor, depending on the allowed temperature rise. Note that the inductor permissible DC current rating typically does not include inductor core losses. These are very important contributors of total inductor core loss and temperature increase in high-frequency DC/DC converters because core losses increase rapidly with the excitation frequency. When saturation current is specified, make sure that there are enough design margins so the peak current does not cause the inductor to enter deep saturation. 2016 Microchip Technology Inc. Pay attention to the inductor saturation characteristic in current limit. The inductor should not heavily saturate, even in current limit operation. If there is heavy saturation, the current may instantaneously run away and reach potentially destructive levels. Typically, ferrite-core inductors exhibit an abrupt saturation characteristic, while powdered-iron or composite inductors have a soft-saturation characteristic. Peak current can be calculated with Equation 7-3. EQUATION 7-3: 1 – VOUT VIN I L,PEAK = I OUT + V OUT ----------------------------------- 2 fs L As shown in Equation 7-3, the peak inductor current decreases with the switching frequency and the inductance. At a given IOUT load current, the lower the switching frequency or inductance, the higher the peak current. As input voltage increases, the peak current also increases. 7.5 Output Capacitor Selection Two main requirements determine the size and characteristics of the output capacitor COUT: • Steady-state ripple • Maximum voltage deviation during load transient For steady-state ripple calculation, both the ESR and the capacitive ripple contribute to the total ripple amplitude. DS20005568A-page 29 MIC24045 From the switching frequency, input voltage, output voltage setting, and load current, the peak-to-peak inductor current ripple and the peak inductor current can be calculated as: Equation 7-10 calculates the minimum output capacitance value (COUT(MIN)) needed to limit the output overshoot below VOUT. EQUATION 7-10: EQUATION 7-4: I L_PP 2 1 – VOUT VIN = V OUT ----------------------------------- fS L C OUT(MIN) EQUATION 7-5: I L_PP I L,PEAK = I OUT + ---------------2 The capacitive ripple VR,C and the ESR ripple VR,ESR are given by: EQUATION 7-6: I L_PP V R,C = --------------------------------8 fS C OUT L I L,PEAK = ------------------------------------------------------------------2 2 V OUT + V OUT – V OUT The result from the minimum output capacitance value for load transient is the most stringent requirement found for capacitor value in most applications. Low equivalent series resistance (ESR) ceramic output capacitors, with X5R or X7R temperature characteristics, are recommended. For low-output voltage applications with demanding load transient requirements, using a combination of polarized and ceramic output capacitors may be most convenient for smallest solution size. 7.6 Input Capacitor Selection Two main requirements determine the size and characteristics of the input capacitor: EQUATION 7-7: • Steady-state ripple • RMS current V R,ESR = ESR I L_PP The total peak-to-peak output conservatively estimated as: ripple is then EQUATION 7-8: V R V R,C + VR,ESR The output capacitor value and the ESR should be chosen so that VR is within specifications. Capacitor tolerance should be considered for worst-case calculations. In the case of ceramic output capacitors, factor into account the decrease of effective capacitance versus applied DC bias. The worst-case load transient for output capacitor calculation is an instantaneous 100% to 0% load release when the inductor current is at its peak value. In this case, all the energy stored in the inductor is absorbed by the output capacitor while the converter stops switching and keeps the low-side FET ON. The buck converter input current is a pulse train with very fast rising and falling times so low-ESR ceramic capacitors are recommended for input filtering, because of their good high-frequency characteristics. For ideal input filtering (assuming a DC input current feeding the filtered buck power stage) and by neglecting the capacitor ESR contribution to the input ripple (typically possible for ceramic input capacitors), the minimum capacitance value CIN(MIN) needed for a given input peak-to-peak ripple voltage Vr,IN can be estimated as shown in Equation 7-11: EQUATION 7-11: I OUT D 1 – D CIN(MIN) = ---------------------------------------------- V r,IN f S where: D = the duty cycle at the given operating point The peak output voltage overshoot (VOUT) happens when the inductor current has decayed to zero. This can be calculated with Equation 7-9: EQUATION 7-9: VOUT = 2 2 L VOUT + -------------- I – V OUT C OUT L,PEAK DS20005568A-page 30 2016 Microchip Technology Inc. MIC24045 The RMS current IIN,RMS of the input capacitor is estimated as in Equation 7-12: 7.7 As a simple first-order approximation, the valley current-mode controlled buck power stage can be modeled as a voltage-controlled current-source feeding the output capacitor and the load. The inductor current state-variable is removed and the power-stage transfer function from COMP to the inductor current is modeled as a transconductance (GmPS). The simplified model of the control loop is shown in Figure 7-2. The power-stage transconductance GmPS shows some dependence on current levels and it is also somewhat affected by process variations, therefore some design margin is recommended against the typical value GmPS = 12.5A/V (see Electrical Characteristics). EQUATION 7-12: I IN, RMS = I OUT D 1 – D Note that, for a given output current IOUT, the worst-case values are obtained at D = 0.5. Multiple input capacitors can be used to reduce input ripple amplitude and/or individual capacitor RMS current. VIN R2 Compensation Design IL GmPS COUT Gm Error Amplifier RL ESR VC COMP REFDAC R1 FIGURE 7-2: GmEA VOUT Range Based on the model shown in Figure 7-2, the control-to-output transfer function is: EQUATION 7-13: where: CC1 CC2 RC1 Simplified Small-Signal Model of the Voltage Regulation Loop. This simplified approach disregards all issues related to the inner current loop, like its stability and bandwidth. This approximation is good enough for most operating scenarios, where the voltage-loop bandwidth is not pushed to aggressively high frequencies. G CO S VOUT s 1 + -------------- 2 f z VOUT S = -------------------- = Gm PS R L -------------------------------VC S s 1 + --------------- 2 f p fZ, fP = The frequencies associated with the output capacitor ESR zero and with the load pole, respectively: 1 f Z = -------------------------------------------2 C OUT ESR 1 f P = -------------------------------------------------------------2 COUT ESR + RL 2016 Microchip Technology Inc. The MIC24045 uses a transconductance (GmEA = 1.4 mA/V) error amplifier. Frequency compensation is implemented with a Type-II network (RC1, CC1 and CC2) connected from COMP to AGND. The compensator transfer function consists of an integrator for zero DC voltage regulation error, a zero to boost the phase margin of the overall loop gain around the crossover frequency and an additional pole that can be used to cancel the output capacitor ESR zero, or to further attenuate switching frequency ripple. In both cases, the additional pole makes the regulation loop less susceptible to switching frequency noise. The additional pole is created by capacitor CC2. Equation 7-14 details the compensator transfer function HC(S) (from OUTSNS to COMP). EQUATION 7-14: R1 1 H C S = – --------------------- Gm EA ----------------------------------------R1 + R2 S CC1 + C C2 1 + S R C1 CC1 CC1 C C2 1 + S R -------------------------- C1 C C1 + C C2 X -------------------------------------------------------------------- DS20005568A-page 31 MIC24045 The overall voltage loop gain TV(S) is the product of the control-to-output and the compensator transfer functions: 3. EQUATION 7-15: T V S = G CO S H C S The value of the attenuation ratio R1/(R1 + R2) depends on the output voltage selection and can be retrieved as illustrated in Table 7-2: TABLE 7-2: INTERNAL FEEDBACK DIVIDER ATTENUATION VALUES VOUT Range 0.640V – 1.280V A R1/(R1 + R2) (A = 1 + R2/R1) 1 0.5 2 1.980V – 3.420V 0.333 3 4.750V – 5.250V 0.2 4 The compensation design process is as follows: 1. Set the TV(S) loop gain crossover frequency fXO in the range fS/20 to fS/10. Lower values of fXO allow a more predictable and robust phase margin. Higher values of fXO would involve additional considerations about the current loop bandwidth in order to achieve a robust phase margin. Taking a more conservative approach is highly recommended. EQUATION 7-16: fS fXO -----20 2. Select RC1 to achieve the target crossover frequency fXO of the overall voltage loop. This typically happens where the power stage transfer function GCO(S) is rolling off at -20 dB/dec. The compensator transfer function HC(S) is in the so-called mid-band gain region where CC1 can be considered a DC-blocking short circuit while CC2 can still be considered as an open circuit, as calculated in Equation 7-17: EQUATION 7-17: 2 C OUT f XO R1 + R2 RC1 = --------------------- ----------------------------------------- R1 Gm EA Gm PS DS20005568A-page 32 EQUATION 7-18: V OUT R L = ------------I OUT EQUATION 7-19: C OUT ESR + R L C C1 = -------------------------------------------------RC1 1 1.290V – 1.950V Select capacitor CC1 to place the compensator zero at the load pole. The load pole moves around with load variations, so, to calculate the load pole, use as a load resistance RL the equivalent value that yields the nominal output current IOUT of the application at the output voltage VOUT, as shown in: Equation 7-18 and Equation 7-19: 4. Select capacitor CC2 to place the compensator pole at the output capacitor ESR zero frequency fZ, or at 5 fXO, whichever is lower. The CC2 is intended for placing the compensator pole at the frequency of the output capacitor ESR zero, and/or achieve additional switching ripple/noise attenuation. If the output capacitor is a polarized one, its ESR zero will typically occur at low enough frequencies to cause the loop gain to flatten out and not roll-off at a -20 dB/decade slope around, or just after the crossover frequency fXO. This causes undesirable scarce compensation design robustness and switching noise susceptibility. The compensator pole is then used to cancel the output capacitor ESR zero and achieve a well-behaved roll-off of the loop gain above the crossover frequency. If the output capacitors are only ceramic, then the ESR zeroes frequencies could be very high. In many cases, the frequencies could even be above the switching frequency itself. Loop gain roll-off at -20 dB/decade well beyond the crossover frequency is ensured, but even in this case, it is good practice to still make use of the compensator pole to further attenuate switching noise, while conserving phase margin at the crossover frequency. For example, setting the compensator pole at 5 fXO, will limit its associated phase loss at the crossover frequency to about 11°. Placement at even higher frequencies N × fXO (N > 5) will reduce phase loss even further, at the expense of less noise/ripple attenuation at the switching frequency. Some attenuation of the switching frequency noise/ripple is achieved as long as N × fXO < fS. 2016 Microchip Technology Inc. MIC24045 For polarized output capacitor, compensator pole placement at the ESR zero frequency is achieved, as shown in Equation 7-20 below: EQUATION 7-20: 1 CC2 = -----------------------------------------------R C1 1 ------------------------------- – ---------C OUT ESR C C1 For ceramic output capacitor, compensator pole placement at N × fXO (N 5, N × fXO < fS) is achieved, as detailed in Equation 7-21: EQUATION 7-21: 1 CC2 = ---------------------------------------------------------------1 2 R C1 N fXO – ---------C C1 7.9 Minimum TON and Minimum TOFF Limitations The valley current-mode control method utilized in the MIC24045 allows very small minimum controllable ON time (around 26 ns), so that it is possible to convert from 19V down to very low voltages at high frequency. Note that the high-side current limit circuit may not be able to detect an overcurrent event if the ON time is below the high side switch current limit leading edge blanking time (LEB, see Electrical Characteristics). Conversely, some minimum OFF time is needed for valley current-mode modulator operation. This TOFF(MIN) specification (see Electrical Characteristics) may dictate a limit on the maximum attainable output voltage for a given VIN voltage. The maximum attainable output voltage (at no load) is calculated as follows: EQUATION 7-23: 7.8 Output Voltage Soft-Start Rate The MIC24045 features internal, I2C programmable soft-start, such that the output voltage can be smoothly increased to the target regulation voltage. The soft-start rate given in the Electrical Characteristics refers to the error amplifier reference, and therefore the effective soft-start rate value seen at the output of the module has to be scaled according to the internal feedback divider attenuation values listed in Table 7-2. To calculate the effective output voltage soft-start slew rate SS_SROUT, based on the particular output voltage setting and the reference soft-start slew rate SS_SRx (x = 0, 1, 2, 3 depending on selection), use the following formula: V OUT,max = V IN 1 – fS T OFF(MIN) It is advisable to use a safe headroom margin against the calculated value of VOUT,max for DC load and good dynamic performance. EQUATION 7-22: SS_SROUT = A SS_SRx where: A = amplification (see Table 7-2 for A values.) 2016 Microchip Technology Inc. DS20005568A-page 33 MIC24045 8.0 I2C INTERFACE DESCRIPTION The I2C bus is for 2-way, 2-line communication between different ICs or modules. The two lines are: a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. MIC24045 is a slave-only device (i.e., it cannot generate a SCL signal and does not have SCL clock stretching capability). Every data transfer to and from the MIC24045 must be initiated by a master device which drives the SCL line. The MIC24045 is a Fast mode device, supporting data transfers at up to 400 Kbit/s. The MIC24045 device assumes that the I2C logic levels on the bus are generated by a device operating from a nominal supply voltage of 3.3V (with +/-10% tolerance). Therefore, VIH and VIL are not related to the VDDA value of the MIC24045. The SDA and SCL lines must not be pulled up to the VDDA voltage of the MIC24045, but to the I2C master interface supply voltage (3.3V nominal). SDA SCL Data line stable; data valid FIGURE 8-1: 8.1 Change of data allowed Bit Transfer. Bit Transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. 8.2 START and STOP Conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START (S) or repeated START (Sr) condition. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. SDA SDA SCL S START condition FIGURE 8-2: DS20005568A-page 34 P SCL STOP condition START and STOP Conditions. 2016 Microchip Technology Inc. MIC24045 8.3 Device Address The MIC24045 device uses a 7-bit address, which is set in hardware, using three-state pins ADR0 and ADR1 (HIGH, LOW, or high-Z). These two three-state pins allow for nine different addresses, as described in Table 8-1 below. MIC24045 I2C ADDRESS SETTING TABLE 8-1: ADR1 ADR0 I2C Address 0 0 101 0000 0 1 101 0001 1 0 101 0010 1 1 101 0011 0 high-Z 101 0100 high-Z 0 101 0101 1 high-Z 101 0110 high-Z 1 101 0111 high-Z high-Z 101 1000 8.4 A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter, except on the last received byte. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave 2 3 4 5 6 7 8 S A 0 0 R/W ACK from Slave The data to port is the 8-bit data that needs to be written to the selected register. This is followed by the acknowledge from the slave and then the STOP condition. The Write command is as follows and it is illustrated in the timing diagram below: 1. 2. 3. 4. 5. 6. 7. 8. 9. Send START sequence Send 7-bit slave address Send the R/W bit - 0 to indicate a write operation Wait for acknowledge from the slave Send the command byte – address that needs to be written Wait for acknowledge from the slave Receive the 8-bit data from the master and write it to the slave register indicated in step 5 starting from MSB Acknowledge from the slave Send STOP sequence Data to port A ACK from Slave DATA 1 A P ACK from Slave DATA 1 VALID Data out from port FIGURE 8-3: SINGLE WRITE Command byte 0 START condition 8.5.1 9 Slave address SDA Bus transactions Command byte is a data byte which selects a register on the device. The Least Significant six bits of the command byte determine the address of the register that needs to be written. The number of data bytes transferred between the START and the STOP conditions, from transmitter to receiver, is not limited. Each byte of eight bits is followed by one Acknowledge bit. The Acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge-related clock pulse. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse; setup and hold times must be taken into account. 1 8.5 The first seven bits of the first byte make up the slave address. The eighth bit is the LSB (Least Significant bit). It determines the direction of the message (R/W). A ‘zero’ in the least significant position of the first byte means that the master will write information to a selected slave. A ‘1’ in this position means that the master will read information from the slave. When an address is sent, each device in a system compares the first seven bits after the START condition with its address. If they match, the device considers itself addressed by the master as a slave-receiver or slave-transmitter, depending on the R/W bit. Acknowledge SCL transmitter. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Single Write Timing Diagram. 2016 Microchip Technology Inc. DS20005568A-page 35 MIC24045 Note: 8.5.2 Writing to a non-existing register location will generate a reject action (NACK) by the MIC24045 after the command byte. 6. 7. SINGLE WRITE WITH REPEATED START (Sr) 8. 2 In multi-master I C systems, this bus transaction is the recommended method to execute VOUT on-the-fly changes in multiple steps. 9. 10. 11. 12. 13. The sequence is the same as for the previous Single Write transaction, except that at the end the master issues a Repeated START (Sr) instead of a STOP (P), and another (or more) Single Write operation takes place until the master releases the bus with a STOP. This way the master does not release the bus after the first Single Write and can accomplish the VOUT on-the-fly change in multiple steps, without interference from other master devices. 14. 15. 16. The Single Write with Repeated Start (Sr) command is as follows and it is illustrated in the timing diagram of Figure 8-4 below: 1. 2. 3. 4. 5. These steps (steps 9 through 16) can continue as many times as needed to write to the same register (or another valid writable register as indicated in steps 5 and 13) without sending a STOP sequence. The master will conclude the data transfer on the last write operation by generating a STOP condition. Send START sequence Send 7-bit slave address Send the R/W bit - 0 to indicate a write operation Wait for acknowledge from the slave Send the command byte – address that needs to SCL 1 2 3 4 5 6 7 8 9 Slave address SDA Command byte S 0 1 A 0 0 2 3 4 5 6 7 8 0 Repeated START 1 A 0 0 3 4 5 6 7 8 Sr ACK from Slave Register Address A DATA 2 ACK from Slave A ACK from Slave Command byte 0 Repeated START A 9 Slave address SDA ACK from Slave R/W ACK from Slave 2 DATA 1 Command byte Sr SCL A 9 Slave address SDA Register address R/W ACK from Slave START SCL be written Wait for acknowledge from the slave Receive the 8-bit data – DATA 1 from the master and write it to the slave register indicated in step 5, starting from MSB Acknowledge from the slave – The register is updated with DATA 1 Send START sequence Send 7-bit slave address Send the R/W bit - 0 to indicate a write operation Wait for acknowledge from the slave Send the command byte – address that needs to be written Wait for acknowledge from the slave Receive the 8-bit data – DATA 2 from the master and write it to the slave register indicated in step 13, starting from MSB Acknowledge from the slave – The register is updated with DATA 2 A 0 0 R/W ACK from Slave Register Address A ACK from Slave DATA N A P ACK from Slave STOP FIGURE 8-4: Note: Single Write with Repeated Start Timing Diagram. Writing to a non-existing register location will generate a reject action (NACK) by the MIC24045 after the command byte. DS20005568A-page 36 2016 Microchip Technology Inc. MIC24045 8.5.3 SINGLE READ 7. This reads a single byte from a device, from a designated register. The register is specified through the command byte. The Read command is as follows and it is illustrated in the timing diagram of Figure 8-5 below. 1. 2. 3. 4. 5. 6. Send START sequence Send 7-bit slave address Send the R/W bit - 0 to indicate a write operation Wait for acknowledge from the slave Send the register address that needs to be read Wait for acknowledge from the slave 12. 13. Slave address SDA 8. 9. 10. 11. Send START sequence again (Repeated START condition) Send the 7-bit slave address Send R/W bit - 1 to indicate a read operation Wait for acknowledge from the slave Receive the 8-bit data from the slave starting from MSB Acknowledge from the master. On the received byte, the master receiver issues a NACK in place of ACK to signal the end of the data transfer. Send STOP sequence Command byte S 0 A START condition R/W A (cont.) *** ACK from Slave ACK from Slave Slave address (cont.) *** Data from register Sr 1 (repeated) START condition R/W A ACK from Slave FIGURE 8-5: Note: DATA (first byte) A P STOP condition At this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter Single Read Timing Diagram. Attempts to read from a non-existing register location will generate a reject action (NACK) by the MIC24045 after the command byte. 2016 Microchip Technology Inc. DS20005568A-page 37 MIC24045 8.5.4 BLOCK READ (AUTO INCREMENT MODE) 5. This command reads a block of bytes, starting from a designated register that is specified through the command byte. Bit<6> of the command byte indicates the Auto-Increment mode. If this bit is set, the address gets incremented by one automatically and the registers are read in order, starting from the address provided by the command byte. 6. 7. 8. 9. 10. 11. The Block/Auto-Increment Read command is as follows and it is illustrated in the timing diagram of Figure 8-6. 1. 2. 3. 4. 12. Send START sequence Send 7-bit slave address Send the R/W bit - 0 to indicate a write operation Wait for acknowledge from the slave Slave address SDA 13. 14. Send the command byte – address that needs to be read with Bit<6> set high to indicate the Auto-Increment Read mode. Wait for acknowledge from the slave Send START sequence again Send the 7-bit slave address Send R/W bit - 1 to indicate a read operation Wait for acknowledge from the slave Receive the 8-bit data from the slave register indicated in step 5, starting from MSB Acknowledge from the master receiver. On the last byte, master receiver issues a NACK in place of ACK to signal the end of the data transfer. Repeat steps 11 and 12 until last byte STOP sequence is sent Command byte S 0 START condition R/W 1 A A (cont.) *** ACK from Slave ACK from Slave Slave address Data from register X Sr 1 (repeated) START condition R/W *** A ACK from Slave FIGURE 8-6: Note: DATA (first byte) Data from register X+n Data from register X+1 A DATA (first byte) A (cont.) *** DATA (first byte) A P STOP condition At this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter Block Read Timing Diagram. If the master is using a non-existing register location in the command byte, a reject (NACK) will be generated by the MIC24045. In Block Read Auto-Increment mode, the master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. If the master keeps reading beyond the valid user-accessible register locations, the content of internal test registers will be streamed out until location 15 (Fh) is reached. After that, the read operation wraps-around and restarts from register location 0h and so on, until the master stops reading. DS20005568A-page 38 2016 Microchip Technology Inc. MIC24045 8.5.5 BLOCK WRITE (AUTO-INCREMENT MODE) 4. 5. This command writes data to the designated register and to all the following registers that are specified through the command byte. Bit<6> of the command byte indicates the Auto-Increment mode. If this bit is set, the address gets incremented by one automatically and the registers are written in order, starting from the address provided by the command byte. The Block/Auto-Increment Write command is as follows and it is illustrated in the timing diagram of Figure 8-7 below. 1. 2. 3. Wait for acknowledge from the slave Send the command byte – address that needs to be written with Bit<6> set high to indicate the Auto-Increment Write mode. 6. Wait for acknowledge from the slave. 7. Receive the 8-bit data from the master and write it to the slave register indicated in step 5, starting from MSB. 8. Acknowledge from the slave 9. Repeat steps 7 and 8 until the entire data is sent 10. Send STOP sequence Send START sequence Send 7-bit slave address Send the R/W bit - 0 to indicate a write operation SCL 1 2 3 4 5 6 7 8 9 Slave address SDA S 0 START condition Data to port Command byte A 0 1 R/W ACK from Slave A DATA 1 ACK from Slave A ACK from Slave DATA 1 VALID Data out from port FIGURE 8-7: Note: Data to port DATA 1 Data to port A ACK from Slave DATA 2 VALID DATA 1 STOP condition A P ACK from Slave DATA n VALID Block Write Timing Diagram. If the master is using a non-existing register location, a reject (NACK) will be generated. 2016 Microchip Technology Inc. DS20005568A-page 39 MIC24045 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 20-Pin FQFN (3 x 3 mm) 2Z 24045 1612 XX 24045 YYWW Legend: XX...X Y YY WW NNN e3 * Note: DS20005568A-page 40 Example Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2016 Microchip Technology Inc. MIC24045 2016 Microchip Technology Inc. DS20005568A-page 41 MIC24045 NOTES: DS20005568A-page 42 2016 Microchip Technology Inc. MIC24045 APPENDIX A: REVISION HISTORY Revision A (May 2016) • Original release of this document. 2016 Microchip Technology Inc. DS20005568A-page 43 MIC24045 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -XX X XX Device Default settings Lead Finish Package Code Device: Examples: a) MIC24045-2ZYFL: 2Z default settings option, Pb-Free, 20-pin 3 x 3 mm FQFN Package. MIC24045: I2C-programmable, high-efficiency, wide input range, 5A synchronous step-down regulator XX = device code for default settings (see Table 6-1) Lead Finish Y = Pb-Free with Industrial Temperature Grade Package FL = Flip-chip QFN, 0.85 mm thickness DS20005568A-page 44 2016 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2016 Microchip Technology Inc. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. 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