TLE4997 - Programming Guide

Application Note, Rev 1.09, April 2009
TLE4997
User Programming Description
Sensors
N e v e r
s t o p
t h i n k i n g .
Edition 2009-04
Published by Infineon Technologies AG,
Am Campeon 1-12,
85579 Neubiberg, Germany
© Infineon Technologies AG 2009.
All Rights Reserved.
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Terms of delivery and rights to technical change reserved.
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Information
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be endangered.
TLE4997-Programming Guide
1
1.1
1.2
1.3
1.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
2.2
2.3
2.4
Interface Access Details - Part I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Detailed Command Frame Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Detailed Data Frame Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Interface parity calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
3.1
3.2
3.3
Interface Access Details - Part II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing and Electrical Parameters for Interface Access . . . . . . . . . . . . . . .
Timing and Electrical Parameters for Programming . . . . . . . . . . . . . . . . .
11
11
11
12
4
4.1
4.2
4.3
4.4
4.5
4.6
Interface Access Details - Part III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Complete Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic EEPROM Access and Programming Procedure . . . . . . . . . . . . . . .
DATA Access Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temporary Overwrite of EEPROM Data . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC Setup Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
17
21
25
26
27
5
Application Circuit for Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Application Note
1
3
3
3
4
5
Rev 1.09, 2009-04
TLE4997-Programming Guide
Revision history
Status:
Date/Version:
2009-04
Rev 1.09
Previous Version: V 1.07
Page
Subjects (major changes since last revision)
3
Chap. 1.1/ General Information adapted
11
Table 5/ Temperature specification unified acc. to Infineon guidelines
12
Table 6/ Vdd clock high level adapted
14
Table 8/ Threshold voltage for ’0’ adjusted, footnote 3) adapted, 4) added
14
Table 8/ Vdd slope for margin adapted, footnote 4) deleted
20
Chap. 4.2.9/ EEPROM description adapted, table 10/ TT-register address
added
21
Chap. 4.3/ Detail six added
Previous Version: V1.08
19
Figure 16: Test register adapted
General
Grammar, typing errors
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Application Note
2
Rev 1.09, 2009-04
User Programming Description
TLE4997
TLE4997-Programming Guide
1
Overview
1.1
General Information
•
•
•
•
•
•
This document is valid for all TLE4997 products and derivatives
It is intended as addon to the current available TLE4997x target and/or data sheets
It gives an overview of the internal signal processing capabilities
It contains basic information about accessing the device using the digital interface
It describes how to access internal registers and parameters stored in the EEPROM
Furthermore it shows how to apply the programming voltage for the EEPROM and
how to verify the programming
• The herein given electrical specification has to be understood directly on the sensor
interface. Additional effects concerning the external circuitry, the attached
programming equipment or any degradation e.g. in combination with EMC is not
considerd
1.2
Block Diagram
Figure 1 shows a simplified block diagram.
VDD
Interface
Supply
Bias
HALL
EEPROM
A
enable
D
D
VDD
DSP
Temp.
Sense
A
D
OBD
ROM
firmware
Figure 1
OUT
A
GND
Block Diagram
Application Note
3
Rev 1.09, 2009-04
TLE4997-Programming Guide
Overview
The device can be accessed using a two-wire synchronous interface. The device supply
pin (Vdd pin) acts as clock line and the ratiometric output pin (OUT pin) is used as
bidirectional serial data line and to apply the required programming voltage.
This method allows connection of several devices to a single supply while accessing
each device separately or in parallel. Using the parallel access all or only some of the
devices can be accessed with the same timeframe as a single device. This is especially
important for time-consuming operations like programming the EEPROMs in multidevice setups.
1.3
Pin Configuration
Figure 2 shows the location of the three pins of the package.
Top View
1
2
Figure 2
Pin Configuration
Table 1
Pin Definitions and Functions
3
Pin No.
Symbol
Function
1
VDD
Supply voltage / programming interface (clock)
2
GND
Ground
3
OUT
Output voltage / programming interface (I/O data, Vprog)
More information regarding location of branding, Hall probe etc. can be found in the
corresponding target and or data sheet.
Application Note
4
Rev 1.09, 2009-04
TLE4997-Programming Guide
Overview
1.4
Signal Flow
Figure 3 shows a the signal flow diagram including important internal data values.
Range
LP
H_ADC
V_DAC
Limiter
Gain
(Clamp)
Hall
Sensor
A
Temperature
Sensor
T_ADC
A
D
P
P
D
+
D
A
TC 2
+
out
LPDAC
Offset
DAC_SET
H_CAL
X
X
1
+
X
TC1
-T0
X
X
Stored in
EEPROM
Memory
P
T_CAL
Temperature
Compensation
Figure 3
Block Diagram
Table 2
Internal data values
internal device
pre-calibration
Address.
Symbol
Function
0x05
H_CAL
Calibrated Hall value 1)
0x06
T_CAL
Calibrated temperature value, incl. reference-temp. T0 1)
0x07
V_DAC
Calculated DAC value, incl. clamping 1)
0x0A
H_ADC
Uncalibrated Hall ADC value 1)2)
0x0B
T_ADC
Uncalibrated temperature ADC value 1)2)
0x20
DAC_SET
Direct setup of DAC value 1)3)
1) requires special debug mode and activated interface - access possible only with unlocked devices
2) please note, this value does not include any compensation - this are just the internal “raw” ADC values
3) additionally requires special test mode - when leaving the interface, this value is replaced by V_DAC again
Application Note
5
Rev 1.09, 2009-04
TLE4997-Programming Guide
Interface Access Details - Part I
2
Interface Access Details - Part I
2.1
Functional Interface Description
All internal data is organized in a memory-like setup. Each data value or EEPROM
parameter is located at a specific address. The data width is always 16bit.
The interface uses specific frames for information exchange. Frames have two special
purposes:
• command frames containing a specific task (like read/write data, select EEPROM
programming etc.) and a corresponding address sent to the device
• data frames containing a 16bit data value sent to or received from the device - these
frames can only follow a proper command frame for reading or writing data
A valid frame has this properties:
•
•
•
•
•
•
A frame consists always of 21 bits
A bit is shifted in or out via the output line with an rising clock edge on the supply line.
A frame always starts and ends with a '1' (frame bits)
The LSB of a frame to transmit is shifted in first
The LSB of a result frame is shifted out first
The whole frame sent to the device, including frame bits, is protected with an even
positional and odd positional parity bit.
The first frame sent must be always a valid command to activate the interface mode. As
additional protection, the device does not deactivate the output stage during this
transmission (using 21 clock pulses) as shown in Figure 4. This means that the external
interface needs to overwrite the internal driver of the device.
VDD
Vout
power up
LSB
interface
activated
MSB
during first transmission, the buffer is still switched on
Figure 4
First frame transmission to the device
Note: Overwriting of Vout needs a strong driver, as Vout works ratiometric to Vdd but must
be driven to a very low level near ground for any “0” bit to enter the interface mode
correctly.
Application Note
6
Rev 1.09, 2009-04
TLE4997-Programming Guide
Interface Access Details - Part I
Later, to avoid additional power consumption in the output stage of the device, the
internal driver is deactivated with a first clock pulse, followed by the frame itself (using
again 21 clock pulses). This is illustrated in Figure 5.
VDD
interface
active
LSB
MSB
during transmission the buffer is switched off
internal buffer on
Figure 5
interface
active
Vout
internal buffer on
Further frame transmission to the device
In case the command or data frame is wrong, the interface is immediately locked and the
device falls back to its normal application mode. As long as the device is in the interface
mode, selected test modes stay activated, too.
Special transmission modes based on this frames, used for programming of the
EEPROM, will be explained in the EEPROM programming section.
When data is sent by the device, the output buffer is switched into a special I/O mode to
deliver directly binary voltage levels. The transmission is still triggered by clock pulses
on the supply line as shown in figure Figure 6.
VDD
Vout
LSB
internal buffer on
Figure 6
MSB
digital data readout, buffer in I/O mode
internal buffer on
Frame reception from the device
Application Note
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Rev 1.09, 2009-04
TLE4997-Programming Guide
Interface Access Details - Part I
2.2
Detailed Command Frame Description
As already described, the data transmission is performed by command frames. This
command frames are supported by following data frames, if required.
A general command frame is shown in Figure 7. Additionally, the available commands
are described in Table 3.
MSB
1
LSB
1
P
O
P
E
0
0
ADDR (6bit)
Figure 7
Command Frame
Table 3
List of available device commands
1
0
CMD (6bit)
1
CMD No.
Bits1)
Function
0x0
Leave interface mode 2)
0x1
“000000”
“000001”
0x3
“000011”
Read data incrementally from given address until address
reaches “xxx111” (block read) 4)
0x9
“001001”
Write data to given address 3)
0xB
“001011”
Write data incrementally to given address until address
reaches “xxx111” (block write) 4)
0xC
“001100”
Enable EEPROM write mode (programs one bits) 2)5)
0xD
Enable EEPROM erase mode (programs zero bits) 2)5)
0xE
“001101”
“001110”
0xF
“001111”
Enable EEPROM refresh (update EEPROM registers) 2)
Read data from given address 3)
Enable EEPROM margin mode (program level check) 2)6)
1) Left is MSB, right is LSB
2) No data frame must follow
3) Exactly one data frame must follow
4) One or more data frames must follow until address reaches block boundary (“xxx111”)
5) A program pulse must follow after the frame (output stage is kept disabled)
6) A margin voltage level must follow before the last Vdd clock pulse falling edge (this edge is used for refreshing
the EEPROM registers using the margin voltage)
Available addresses are sumarized again later based on address maps.
Application Note
8
Rev 1.09, 2009-04
TLE4997-Programming Guide
Interface Access Details - Part I
The parity bits PE (bit 17) and PO (bit 18) needs to be set in a way that these conditions
are met (bit 0 is the LSB, bit 20 is the MSB):
• bit0 XOR bit2 XOR bit4 XOR …. XOR bit20 = 0
• bit1 XOR bit3 XOR bit5 XOR …. XOR bit19 = 0
2.3
Detailed Data Frame Description
A general data frame sent to the device is shown in Figure 8.
MSB
1
LSB
0
Figure 8
P
O
P
E
DATA (16bit)
1
Data Frame (to device)
The parity bits PE (bit 17) and PO (bit 18) needs to be set (in the same way as for the
command frame) that these conditions are met (bit 0 is the LSB, bit 20 is the MSB):
• bit0 XOR bit2 XOR bit4 XOR …. XOR bit20 = 0
• bit1 XOR bit3 XOR bit5 XOR …. XOR bit19 = 0
See Chapter 2.4 for a source code example of a parity generator.
A general data frame received from the device is shown in Figure 9.
MSB
1
LSB
ADR (3 LSBs)
Figure 9
DATA (16bit)
1
Data Frame (from device)
Instead of a zero bit followed by two parity bits, the least 3 bits of the address used for
readout is transmitted together with the data. This ensures a correct readout of the
required data.
Application Note
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Rev 1.09, 2009-04
TLE4997-Programming Guide
Interface Access Details - Part I
2.4
Interface parity calculation
An example parity generator is shown using a pseudo code. The array “framedatabits”
contain the data bits to transmit including the framebits, its index corresponds to 0 ... LSB
and 20 ... MSB.
This parity calculation is valid for command and data frame transmissions:
// count framedatabits from 0 (LSB) to 20 (MSB) - this are 21 bits
// bit 0 and 20 are always '1' (framebits)
pe = framedatabit(19);
po = 0;
for (i=1; i<17; i++) // go through all data bits
{ // handle even/odd separately
if ((i&1)==1) {
if (framedatabit(i)==1) { if (pe) pe=0; else pe=1; }//toggle pe
} else {
if (framedatabit(i)==1) { if (po) po=0; else po=1; }//toggle po
}
}
framedatabit(17) = pe;
framedatabit(18) = po;
For example, a command 0x03 using address 0x02 should be transmitted (this
command triggers a block readout for addresses 0x02 to 0x07):
Table 4
Command frame example
Bitcount
20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Descr. of
CMD-frame
1
0
C
5
C
4
C
3
C
2
C
1
C
0
1
Descr. of
DATA-frame
1
D
5
D
4
D
3
D
2
D
1
D
0
1
Bits for PO
P
O
P
E
0
A
1
A
0
1
MSB
P
O
P
E
D D D D D D D
15 14 13 12 11 10 9
D
8
D
7
X
X
0
X
Bits for PE
CMD-frame
1
MSB
1
Application Note
1
X
X
1
0
0
A
5
X
X
0
A
4
0
A
3
X
X
0
A
2
0
X
X
0
0
10
X
X
1
D
6
0
X
X
1
0
X
X
0
0
X
X
0
0
LSB
LSB
X
X
1
1
1
Rev 1.09, 2009-04
TLE4997-Programming Guide
Interface Access Details - Part II
3
Interface Access Details - Part II
3.1
General Operation Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the TLE4997 during programming and debugging. All parameters specified
in the following sections refer to these operating conditions, unless otherwise noticed.
Table 5
Operating Range1)
Parameter
Symbol Limit Values
Unit
Notes
min.
max.
4.5
5.5
V
47
1000
nF
from Vdd to GND 2) 3)
Load capacitance
VDD
CS
CL
0.0 4)
210
nF
from OUT to GND 3)
Ambient temperature
Ta
10
30
°C
at programming 5)
Supply voltage
Supply buffer cap.
1) Keeping signal levels within the limits specified in this table, ensures correct setup and programming.
2) Prevents severe supply drops causing a device reset during interface access. For high reliability use the
capacitance must be soldered to the device to avoid contact failures.
3) Please be aware that the driving circuits of Vdd and Vout need also additionally proper driving strength for these
capacitors.
4) >47nF soldered to the device required in case that connectivity failures can influence the programming voltage.
5) IF readouts are also possible at higher and lower temperatures (altough not explicitly tested and guaranteed),
but applying the programming- or margin- voltage outside this room temperature range is strictly forbidden.
3.2
Timing and Electrical Parameters for Interface Access
For accessing the interface, the supply pin and output pin must be proper accessed, the
timing parameters correspond to Figure 10.
tch
tdel
tcl
tsu thld
thlm
Vout
LSB
MSB
init
frame
Figure 10
tmin
VDD
tset
tset
LSB
data read
frame
Frame timing
Application Note
11
Rev 1.09, 2009-04
TLE4997-Programming Guide
Interface Access Details - Part II
3.3
Table 6
Timing and Electrical Parameters for Programming
Electrical levels and interface timing
Parameter
Symbol
Limit Values
min.
typ.
Unit Notes
max.
Vdd,CLKHI
8.8
9.4
Vdd clock low level
Vdd,CLKLOW 4.8
5.0
OUT data out high level VO,OHIGH
Vdd - 2 -
10
V
1)
5.2
V
this is Vdd1)
OUT data out low level VO,OLOW
0
-
2.0
V
VO,IHIGH
OUT data in low level VO,ILOW
OUT data input current IO
Vdd clock high time
tCH
Vdd clock low time
tCL
Buffer off delay
tDEL
Data in setup time
tSU
Data in hold time
tHLD
Data out settling time
tSET
Time between frames tMIN
Buffer on delay
tHLM
3.0
Vdd
Vdd+0.1
V
-0.2
0.0
0.1
V
-50
-
50
mA
2)
2.4
5.0
100
µs
5k...250kBit/s3)
1.6
4.0
100
µs
5k...250kBit/s3)
10.0
25.0
-
µs
4)
1.5
2.0
-
µs
to rising Vdd
2.3
3.0
-
µs
after rising Vdd
-
1.0
1.7
µs
after rising Vdd
10.0
-
-
µs
5)
-
5.0
10.0
µs
4)6)
Vdd clock high level
OUT data in high level
Vdd,CLKHI V
OUT follows Vdd
if ’high’
1) prevent over-/ underswing during Vdd switching to avoid unexpected sensor behavior (e.g. undervoltage
sensor reset).
2) capability of external driver, especially during initial interface access (to overwrite ratiometric device output).
3) excact bitrates depend also on several further conditions, like length of cables (inductors) and the electrical
behavior of the used programming device/setup. Furthermore the desired customer margins for the timing and
voltage levels may limit the bitrate even more. In case of problems try the typical recommended bitrate first
(see Table 7 and Figure 11) and optimize the timing based on measurements using the given system. Also
temperatures outside the allowed temperature range for the EEPROM programming are not considered in the
above recommendation.
4) to reduce collisions with the ext. driver, it must be switched on slower than tDEL min. and switched off faster
than tHLM max. ;
charge/ discharge behavior on VOUT depends also on capacitive output load.
5) in interface mode, EMC influences or Vdd drops during and between frames may cause internally to stop the
interface mode due to safety reasons; a power cycle is needed to allow interface access again.
6) to reach again a valid and stable ratiometric Vout signal state, please check the power-on time in the data sheet.
Application Note
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Interface Access Details - Part II
Table 7
Bitrate at given capacitive load
Load capacitance CL
nF
0
1
10
47
100
200
210
Typical bitrate
kbit/s
250
200
20
4.2
2
1
0.9
Maximum bitrate
kbit/s
250
238.8 79.6
21.2
10.3
5.2
5
recommended bitrate at given CL
(no pullup/down R, Vdd=5V, no influence of cables etc.)
log. bitrate [kBit/s]
1000
100
max. recommended
10
typ. recommended
1
0,1
0
50
100
150
200
load capacitance [nF]
Figure 11
Bitrate at given capacitive load
Additionally, for programming Figure 12 shows a general Vprog pulse timing:
tdel
VDD
tmin
thld
tmin
Vout
MSB
erase or write
command frame(buffer stays off)
Figure 12
VO,PROG/t
(rise)
LSB
tPROG,WR or tPROG,ER
Vprog pulse
VO,PROG/t
(fall)
next command
frame
Program pulse timing
A margin readout needs a special behavior (Figure 13) at the end of a command frame:
Application Note
13
Rev 1.09, 2009-04
TLE4997-Programming Guide
Interface Access Details - Part II
VDD
Vdd/t
(fall)
tmin tMARG
Vout
tmin
tmin
thld
MSB
LSB
margin
command frame(buffer stays off)
apply VO,MARG and
capture EEPROM data
Figure 13
Margin setup timing
Table 8
Electrical levels and interface timing
Parameter
Symbol
Limit Values
min.
typ.
next command
frame
Unit
Notes
max.
IO
OUT margin level
VO,MARG
Threshold margin level VTH
0
20
mA
1)
-0.1
7
V
2)
2.23
4.5
0.4
V
V
check ’1’3)
check ’0’4)
tMARG
Vdd slope for margin
Vdd/t
OUT program level
VO,PROG
OUT prog. slope (rise) VO,PROG/t
OUT prog. slope (fall) VO,PROG/t
OUT write time
tPROG,WR
OUT erase time
tPROG,ER
200
OUT input current
Margin setup time
µs
5
10
150
mV/µs falling edge
19.2
19.3
19.4
V
low tolerance!2)
5)
2
V/µs
7)
-10
6)
V/µs
7)
9.9
10.0
10.1
ms
79.2
80.0
80.8
ms
1) when Vo,prog or Vo,marg is applied
2) proper command must be applied first to switch off internal output stage of device
3) level range within programmed EEPROM bits start to flip from ones to zeros - to be checked after programming
- a too low value could be given by too short programming pulse or a too low programming voltage
- a too high value could be given by a too long programming pulse or a too high programming voltage
To check the programmed “1” threshold levels, the “Margin zero on” bit needs to be set to “0” in the test register
4) To check the programmed “0” threshold levels, the “Margin zero on” bit needs to be set to “1” in the test register
5) Time to reach VO,PROG min. must not exceed 50µs
6) Time to reach 1V max. must not exceed 50µs
7) ramp up/down needs to be assured by the programming hardware - especially faster slopes when applying the
programming voltage may damage the EEPROM cell
Application Note
14
Rev 1.09, 2009-04
TLE4997-Programming Guide
Interface Access Details - Part II
Due to this specification for the programming pulse, either a linear programming ramp or
a exponential ramp (using an R/C circuit) may be applied as shown in Figure 14.
Figure 14
Example slopes for VO,PROG
Application Note
15
Rev 1.09, 2009-04
TLE4997-Programming Guide
Interface Access Details - Part III
4
Interface Access Details - Part III
4.1
Complete Memory Map
Table 9
memory map
Address.
Symbol
Function
0x05
H_CAL
Calibrated Hall value
0x06
T_CAL
Calibrated temperature value, incl. reference-temp. T0
0x07
V_DAC
Calculated DAC value, incl. clamping
0x0A
H_ADC
Uncalibrated Hall ADC value
0x0B
T_ADC
Uncalibrated temperature ADC value
0x0F
STATUS
Chip status register
0x10...0x19
EEPROM
EEPROM map 1)
0x20
DAC_SET
Direct setup of DAC value 1)
0x21
TEST
Test mode register 1)
1) this addresses allow also write access
• H_CAL, T_CAL, V_DAC, H_ADC, T_ADC, DAC_SET
This registers correspond to the signal flow diagram shown in Chapter 1.4.
• STATUS
This register contains internal status information as well as the chip version.
• EEPROM
This registers contain the EEPROM based parameter set of the device.
• TEST
This register activates several test modes necessary for accessing internals of the
device.
Note: To access the registers (except STATUS, H_ADC, T_ADC, V_DAC, DAC_SET
and TEST) the internal digital signal processor must be deactivated as it has
priority over interface read and write commands. Please check out the TEST
register content how to disable the DSP.
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Interface Access Details - Part III
4.2
Register Details
4.2.1
H_ADC
This register contains a 16bit signed value. When read as unsigned value and this value
is larger than 32767, it is necessary to subtract 65536 to get an signed value again:
0111111111111111
0100111000100000
0000000000000001
0000000000000000
1111111111111111
1011000111100000
1000000000000000
(unsigned
(unsigned
(unsigned
(unsigned
(unsigned
(unsigned
(unsigned
dec.
dec.
dec.
dec.
dec.
dec.
dec.
32767)
20000)
1)
0)
65535)
45536)
32768)
the (theoretical) max. pos. field
the max. allowed positive field
is a growing positive field
is the zero field (without offset error)
is a growing negative field (-1)
the max. allowed negative field (-20000)
the (theoretical) max. neg. field (-32768)
For valid usage of the device, the H_ADC value must be always in a range of +/- 20000
decimal, which corresponds to approximately 2/3 of the theoretical integer range.
Otherwise the used magnetic flux density is too high and the ADC might be saturated.
4.2.2
T_ADC
This register contains a 15bit unsigned value. This value is not important for the usage
of the IC. Just for information this value is roughly in a range of 22000 to 29000 decimal
for temperatures between -50°C and 150°C.
4.2.3
H_CAL
This register contains a 16bit signed value similar to the H_ADC value and is required to
calculate the output DAC value for a specific magnetic value. This value is at a given
magnetic range (for a calibrated device) in the range of +/- 30000 (approx. 1.5 times of
H_ADC) when the max. positive or negative field is applied.
4.2.4
T_CAL
This register contains a 16 bit signed value and delivers the current junction temperature
of the device. This value includes the programmed reference temperature T0. To retreive
the actual temperature in °C, the register value needs to be divided by 16 and the T0
value must be read from the EEPROM and accordingly added or subtracted.
4.2.5
V_DAC
This value is the 12 bit unsigned decimal result applied to the internal DAC for the
ratiometric output stage. It includes the clamping limits if programmed. The value range
is from 0 to 4095 decimal and corresponds to 0% to 100% of Vdd.
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4.2.6
DAC_SET
This register contains a 12 bit unsigned decimal value similar to the V_DAC register. It
can be written via the interface. When the DAC test bit is set in the TEST register, the
value of this register is used on the ratiometric output, as long as the device stays in the
interface mode. This allows an direct, accurate and easy calibration of the output.
4.2.7
STATUS
The content of the status register is shown in Figure 15.
LSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ROMSIG4
ROMSIG3
ROMSIG2
ROMSIG1
ROMSIG0
HWver2
HWver1
HWver0
perr_col
perr_more
perr_adr3
perr_adr2
perr_adr1
perr_adr0
LOCKED
CRC ok
Figure 15
15
Status register
• CRCok must be ’1’, otherwise the DSP BIST failed and the device is defective.
• LOCKED must be ’0’ as long as the lockbits are not programmed. After setting the
lockbits the lock can be verified by refreshing the EEPROM content and checking this
bit before the supply of the device is removed or the interface is closed.
• perr_adr must be on address 0xF (=”1111”) otherwise it shows the first EEPROM
address (=line) where the internal parity check failed.
• perr_more must be ’0’, otherwise more than one EEPROM addresses (=lines) have a
parity error.
• perr_col must be ’0’, otherwise one or more EEPROM columns have a parity error.
• HWver contains the actual silicon revision starting with 0 (=”000”). The latest version
from 6’ manufacturing line is version 1 (=”001”, availability from end 2005), the latest
version from 8’ manufacturing line is version 3 (=”011”, availability from mid 2006 and
released for productive use).
• ROMSIG must be 0x1F (=”11111”) otherwise the DSP ROM is not valid and the device
itself is defective.
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4.2.8
TEST
The content of the test register is shown in Figure 16.
MSB
LSB
3
2
1
0
0
4
0
5
0
0
6
0
REF off
7
0
8
Margin zero on
9
FEC off
10
0
11
DSP off
DAC test
12
DSP stop
0
Figure 16
13
0
14
0
15
Test register
All bits are ’0’ after reset. All bits not described or used must kept at ’0’.
• “FEC off” switches off the error correction of the EEPROM. This bit should be set when
reading the EEPROM content to ensure to retreive the real data stored in the
EEPROM (address range 0x10 to 0x19)
• “REF off” switches off the automatic (cyclic) refresh performed by the DSP to actualize
the EEPROM registers from the eeprom cells. When writing new values to the
EEPROM registers this bit must be set, otherwise these values will be always
overwritten by the EEPROM content.
• “DSP off” switches off the signal processor immediately. This bit must be set prior to
access the internal register values via the interface (H_CAL, T_CAL and EEPROM).
• “DSP stop” should be set prior (as a separate step before switching the DSP off) when
reading out the calculated data H_CAL and T_CAL. This allows the DSP to finish the
calculation of the current sample and all values in the RAM are consistent.
• “DAC test” switches from the DSP DAC value to the DAC_SET value. This allows
setup of any DAC value directly to measure the output voltage for a given DAC value
for calibration purposes.
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4.2.9
EEPROM
The content of the EEPROM setup registers is shown in Table 10. Please refer to the
product data sheets for all parameter details.
Table 10
ADR
EEPROM registers
Description
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0x10
Parity of each row
0x11
IC lock (high locks), USER Pl
bits, Clamping low value
0x12
TR value, Clamping high
value
Pl TR - reg.
0x13
Gain setting
Pl G - register (bit 14...0)
0x14
Offset setting
Pl OS - register (bit 14...0)
0x15
TQ value, (TT value,
precal)
Pl TQ - register (bit 7...0)
0x16
Lowpass value, Range, TL
value, IC lock (low locks)
Pl LP - reg.
0x17
precal
Pl precal area - do not modify
0x18
precal
Pl precal area - do not modify
0x19
precal
Pl precal area - do not modify
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Pl Pc Pc Pc Pc Pc Pc Pc Pc Pc Pc Pc Pc P c Pc Pc
L
H
USER
CL - register (bit 11...0)
CH - register (bit 11...0)
(bit 2...0)
(bit 0,2,1)1)
precal area - do not modify
TT -register (bit 6...0)
R reg. TL - register (bit 8...0)
(b. 1,0)
L
L
1) LP-register bit 0 is mapped to EEP bit 11 (together with R-register bit 1) in HW version 0 and 1. In HW version
2 and above it is mapped to EEP bit 14. LP-register bits 2/1 are always mapped to EEP bit 13/12.
The red marked parameters set the sensor hardware, the yellow marked parameters are
used by the DSP algorithms, the blue values are used to detemine the condition of the
parameters by an external programming software (user defined) and the magenta/cyan
values correspond to the parity setup for the internal forward error correction (FEC). All
parameters are unsigned integer values. The white areas must not be changed.
• The parity Pc of each column (including the precalibration ranges) must be even for
even bit positions (bit0=LSB, bit2, bit4, ... bit14) and the parity Pc for all odd columns
(bit1, bit3, ... bit15=MSB) must be odd. The parity Pl of every EEPROM line (address
0x10 ... 0x19) needs to be calculated so that the sum of bits is always odd
• The two USER bits can be free used by the customer
• LH and LL are lock bits (LH locked if '1', LL locked if '0'). As soon as either LH, LL or
both are set to locked state, the interface mode cannot be accessed anymore.
Therefore, LH and LL can be used to lock the interface and avoid that the interface is
accessed and registers changed by mistake after final programming
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Interface Access Details - Part III
• All other parameters (G, OS, etc.) are defined and explained in the datasheet
Note: Don’t forget to switch of the FEC during access of the EEPROM to read the data
actually stored in the EEPROM cells to detect possible faults.
4.3
Basic EEPROM Access and Programming Procedure
Following steps are required to setup the EEPROM and to program new values,
assuming additional external memory called EEP_NEW (new EEP values), EEP_PROG
(for intermediate values) and EEP_OLD (current EEP values).
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Interface Access Details - Part III
EEPROM
programming
Vdd = 5V
INIT-CMD:
cmd=0x01
adr=0x0F
READ DATA
Is
0xF93D or
0xFB3D ?
ILLEGAL
STATUS:
analyse
problem
NO
CMD (write):
cmd=0x09
adr=0x21
DAT: 0x0640
(DSP, FEC,
REF off)
CMD (b read)
cmd=0x03
adc=0x10
RD. B-DATA
CMD (read)
cmd=0x01
adc=0x18
READ DATA
CMD (read)
cmd=0x01
adc=0x19
READ DATA
Create erase
pattern for
programming
> EEP_OLD <
Store this initial
dataset (allows
later restore)
10x 16bit
User input, TC
setup algorithm or
2P calibration
algorithm setup
> EEP_NEW <
Given by TC
setup and/or 2P
algorithms etc.
EEP_OLD
2x 10x 16bit
EEP_NEW
For each line I from 0x10 to 0x19:
EEP_PROG[i] = INVERT ((EEP_OLD[i] XOR EEP_NEW[i]) AND EEP_OLD[i])
EEP_PROG (as precal areas must not be changed, the bits in this areas must remain ‚1')
CMD (bwrite)
cmd=0x0b
adc=0x10
WR. B-DATA
CMD (write)
cmd=0x09
adc=0x18
WR. DATA
CMD (write)
cmd=0x09
adc=0x19
WR. DATA
2x 10x 16bit
CMD (erase):
cmd=0x0D
adr=0x00
Vprog PULSE
Create write
pattern for
programming
EEP_PROG
EEP_OLD
EEP_NEW
For each line I from 0x10 to 0x19:
EEP_PROG[i] = (EEP_OLD[i] XOR EEP_NEW[i]) AND EEP_NEW[i]
(as precal areas must not be changed, the bits in this areas must remain ‚0')
CMD (write):
cmd=0x0C
adr=0x00
Vprog PULSE
CMD(marg.):
cmd=0x0E
adr=0x00
Readout could be looped for several
margin voltages (starting from a very
high voltage e.g. 5V) to find the margin
level of the EEPROM
Vmarg+V dd-ramp
see above (like complete
readout procedure for
EEP_OLD)
CMDs (read)
cmd=0x03/01
adc=0x10/8/9
READ DATA
content =
EEP_NEW ?
Optionally do a last status
readout (adr. 0x0F) to check
the IF mode is still active
and the device is ok.
NO
margin higher
required limit ?
NO
ILLEGAL
MARGIN
READ:
analyse
problem
Vdd = 0V (off)
FINISHED
Figure 17
Basic EEPROM programming flow
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Interface Access Details - Part III
Description of the flowchart shown in Figure 17:
1. Switch on the device
2. Send an inital command (status line readout)
- read the status,check that the device is valid and the EEPROM content is valid
- if it is not correct, do not continue and check for the failure
3. Set the test register bits FECoff=1, DSPoff=1, REFoff=1 (allows EEPROM access)
4. Read out the EEPROM content to the array EEP_OLD (store also for reference
purposes and for traceability of programming)
- Parallel task: prepare the data necessary to program as array EEP_NEW (see
application notes for calculation of TC parameters and how to do a 2-point calibration).
5. Calculate the bits to be cleared from EEP_OLD to EEP_NEW as EEP_PROG array
6. Write the EEPROM content from the EEP_PROG array to the EEPROM registers
7. Send the EEPROM erase command
- Apply an erase programming pulse on the output pin (see electrical specification)
8. Calculate the bits to be set from EEP_OLD to EEP_NEW as EEP_PROG array
9. Write the EEPROM content from the EEP_PROG array to the EEPROM registers
10.Send the EEPROM write command
- Apply an program porgramming pulse on the output pin (see electrical specification)
11.Send a margin command
- During the last falling edge of the margin command, apply VO,MARG on the output (see
electrical specification
12.Read out the EEPROM content to the array EEP_PROG
13.Verify the EEP_PROG data against EEP_NEW to check the programming (no/all bits
flipped)
- Optionally the item 11. to 13. might be looped to find the exact VTH EEPROM level.
- If the acquired VTH level is too low, do not continue and check for the failure
14.Finally it is recommended send a read command to check the status register again to
check if the sensor is still running in the interface mode before switching off the device
Detail one: How to set the TEST register:
1. Send a write command (TEST register set: CMD=0x09, ADR=0x21)
2. Send the new data word for the TEST register
Detail two: How to readout the EEPROM content:
1. Send a block command (EEPROM data readout: CMD=0x03, ADR=0x10)
2. Read the first 8 data words of the EEPROM and store it in an array
3. Send a read command (EEPROM data readout: CMD=0x01, ADR=0x18)
4. Read the 9th data word of the EEPROM and store it in an array
5. Send a read command (EEPROM data readout: CMD=0x01, ADR=0x19)
6. Read the 10th data word of the EEPROM and store it in an array
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Detail three: How to set the EEPROM content:
1. Send a block command (EEPROM data writeout: CMD=0x0B, ADR=0x10)
2. Send the first 8 data words from the array to the EEPROM
3. Send a write command (EEPROM data write: CMD=0x09, ADR=0x18)
4. Send the 9th data word from the array to the EEPROM
5. Send a write command (EEPROM data write: CMD=0x09, ADR=0x19)
6. Send the 10th data word from the array to the EEPROM
Detail four: How to calculate the bits to be clared from EEP_OLD to EEP_NEW:
1. For each data word i in the arrays calculate:
2. EEP_PROG[i] = INVERT ((EEP_OLD[i] XOR EEP_NEW[i]) AND EEP_OLD[i])
Example of a calculated erase mask:
EEP_OLD: 0101010101010101
EEP_NEW: 0101110001010101
EEP_PROG: 1111111011111111
Detail five: How to calculate the bits to be set from EEP_OLD to EEP_NEW:
1. For each data word i in the arrays calculate:
2. EEP_PROG[i] = (EEP_OLD[i] XOR EEP_NEW[i]) AND EEP_NEW[i]
Example of a calculated program mask:
EEP_OLD: 0101010101010101
EEP_NEW: 0101110001010101
EEP_PROG: 0000100000000000
Detail six: How to determine the EEPROM margin voltages
The threshold voltage of EEPROM cells is dependent on the programming voltage and
programming pulse length. For reliable programming the programming pulse has to be
kept within the specification (Table 8) at the sensor interface. The margin command can
be used to check the threshold voltages of the programmed cells: A voltage VO,MARG is
applied after the margin mode command (CMD No. 0xE, see timing diagram in
Figure 13). For EEPROM cells with a threshold voltage smaller than the applied
VO,MARG, a '0' will be stored to the EEPROM registers, for those with a higher threshold
voltage, a '1' will be written. By sweeping the applied VO,MARG, the effective threshold
voltages of each EEPROM cell can be identified. The threshold voltages of cells
programmed to ‘1’ can be found in this way.
In order to check the threshold voltages of EEPROM cells programmed to ’0’, it is
necessary to activate the “Margin zero on” bit in the test register (Figure 16). The
Application Note
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Interface Access Details - Part III
smallest possible VO,MARG is 0V, and it is therefore not possible to determine the
threshold voltages below 0V.
Note: This routine can be merged with other (exemplary shown) routines. In that case
only one initial frame (the very first interface access) is required after power-on.
4.4
DATA Access Example
Following steps are required to readout other internal data like the calibrated
temperature and Hall value (as shown below). Of couse this routines can be used for an
EEPROM access (in that case also FECoff should be set to ’1’).
EEPROM
programming
Vdd = 5V
INIT-CMD:
cmd=0x01
adr=0x0F
READ DATA
Is
0xF93D or
0xFB3D ?
NO
ILLEGAL
STATUS:
analyse
problem
CMD (write):
cmd=0x09
adr=0x21
DAT: 0x0800
(DSP stop)
CMD (write):
cmd=0x09
adr=0x21
DAT: 0x0C00
(DSP stop,
DSP off)
CMD (read)
cmd=0x01
adr=0x05
READ DATA
Optionally do a last status
readout (adr. 0x0F) to check
the IF mode is still active
and the device is ok.
Like reading out H_CAL,
also all other RAM and
EEPROM registers can
be read out here in a loop.
Vdd = 0V (off)
FINISHED
Figure 18
Basic data access flow
Description of the above flowchart:
1. Switch on the device
2. Send an inital command (status register readout)
3. Read the status data,check that the device is valid and the EEPROM content is valid
4. Set the test register: DSP stop=1 (see previous chapter)
5. Set the test register: DSP stop=1 DSP off=1 (see previous chapter)
6. Send a read command (H_CAL)
- Read the data word
- This readout might be looped for reading out also other parameters (like T_CAL)
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7. Finally it is recommended send a read command to check the status register again to
check if the sensor is still running in the interface mode before switching off the device
Note: This routine can be merged with other (exemplary shown) routines. In that case
only one initial frame (the very first interface access) is required after power-on.
4.5
Temporary Overwrite of EEPROM Data
Following steps are required to readout other internal data like the calibrated
temperature and Hall value (as shown below). As the error correction stay disabled, it is
not necessary to use correct parity values for this temporary setup. In case the parity is
always corrected (and it is desired to check the complete behavior and correct EEPROM
array calculation), the “FECoff” bit could be switched off again after the temprary
EEPROM write, too.
EEPROM
programming
Vdd = 5V
INIT-CMD:
cmd=0x01
adr=0x0F
READ DATA
Is
0xF93D or
0xFB3D ?
NO
ILLEGAL
STATUS:
analyse
problem
CMD (write):
cmd=0x09
adr=0x21
DAT: 0x0640
(DSP, FEC,
REF off)
CMD (write)
cmd=0x09
adr=0x10..19
WR. DATA
Optionally do a last status
readout (adr. 0x0F) to check
the IF mode is still active
and the device is ok.
All o t h e r EEPR OM
r egi s ter s c an be
written here in a loop
(as required).
CMD (write):
cmd=0x09
adr=0x21
DAT: 0x0250
(FEC, REF
off)
Vdd = 0V (off)
Here the output should
show (temporarily) the
desired result (before
s wi tc hi ng off the
supply, of course).
FINISHED
Figure 19
Basic (temporary) EEPROM register overwrite flow
Description of the above flowchart:
1. Switch on the device
2. Send an inital command (status register readout)
3. Read the status data,check that the device is valid and the EEPROM content is valid
4. Set the test register: DSP off=1 FEC off=1 REF off=1 (see previous chapter)
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5. Send a write command (for any EEPROM register)
Send the data words (in 16bit format, MSBs containing the parity may be kept ’0’)
6. Set the test register: FEC off=1 REF off=1 (see previous chapter)
- The device is now temporarily working with the new EEPROM setting.
7. Finally it is recommended send a read command to check the status register again to
check if the sensor is still running in the interface mode before switching off the device
Note: This routine can be merged with other (exemplary shown) routines. In that case
only one initial frame (the very first interface access) is required after power-on.
4.6
DAC Setup Example
To find the exact DAC value for a desired output voltage (e.g. to set up the clamping
low/high registers with the best available accuracy), it is possible to set the DAC value
directly and to measure the result on the output pin.
EEPROM
programming
Vdd = 5V
INIT-CMD:
cmd=0x01
adr=0x0F
READ DATA
Is
0xF93D or
0xFB3D ?
NO
ILLEGAL
STATUS:
analyse
problem
CMD (write):
cmd=0x09
adr=0x21
DAT: 0x4000
(DAC test)
CMD (write)
cmd=0x09
adr=0x20
WR. DATA
Wait 10ms and
evaluate the
response on
the Vout -pin
Optionally do a last status
readout (adr. 0x0F) to check
the IF mode is still active
and the device is ok.
Se t a ll re q u ire d D AC
values in a loop
Vdd = 0V (off)
FINISHED
Figure 20
Basic (temporary) DAC setup flow
Description of the flow as shown above:
1. Switch on the device
2. Send an inital command (status data readout)
3. Read the status data,check that the device is valid and the EEPROM content is valid
4. Set the test register: “DAC Test”=1 (see previous chapter)
- The output immediately shows the content given by the DAC_SET register.
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5. Send a write command (DAC_SET register)
- Send the data word for the desired 12bit DAC value (in 16bit format, MSBs are ’0’)
- The output changes accordingly to the new DAC value in DAC_SET
6. After 10ms (max. output setup time), measure Vout
- Repeat writing a new DAC value (continue at step 5) until the response of all desired
DAC values are measured
7. Finally it is recommended send a read command to check the status register again to
check if the sensor is still running in the interface mode before switching off the device
Note: This routine can be merged with other (exemplary shown) routines. In that case
only one initial frame (the very first interface access) is required after power-on.
Application Note
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Application Circuit for Programming
5
Application Circuit for Programming
Figure 21 shows the connection of multiple sensors to a programmer.
application module
VDD
V DD
TLE out
4997x
47nF
GND
I/O 1
47nF
GND
optional
VDD
TLE out
4997x
47nF
GND
PROGRAMMER
I/O2
47nF
TLE4997_PROGRAMMING_CIRCUIT
Figure 21
Application Circuit
Note: For calibration and programming, the interface has to be connected directly to the
output pin.
Application Note
29
Rev 1.09, 2009-04
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG