SMM151/152 Single-channel Voltage/Current Monitors and Voltage Marginers FEATURES & APPLICATIONS INTRODUCTION • Capable of margining supplies with trim inputs using either positive or negative trim pin control • Wide Margin range of 0.3V to VDD with internal reference • Differential Voltage Sensing of the DC-DC converter output voltage • Supply-side current monitoring (10-bit ADC) 2 • 10-bit ADC readout of supply voltage over I C bus • Margining Controlled Via: 2 I C Command Input Pins (MUP, MDN) • Two programmable general purpose sensor inputs (COMP1/2) – UV/OV with FAULT Output • Programmable glitch filters (COMP1/2) • Programmable internal COMP1/2 VREF: 0.5V or 1.25V • Operates from 2.7V to 5.5V supply • Current sensing from 4.0V to 15V supply • Programmable, general purpose I/Os (SMM152) • General Purpose 256-Byte EEPROM with Write Protect 2 • I C 2-wire serial bus for programming configuration and monitoring status • 28-lead 5x5 QFN The SMM151/152 are highly accurate power supply voltage/current supervisors and monitors with provisions for voltage margining of the monitored supply. The parts include an internal voltage reference to accurately monitor and margin the supply to within ±1%. The SMM151/152 have the capability to margin over a wide range from 0.3V to VDD using the internal reference and can read the differential voltage of the supply and voltage drop of the current sense resistor over the I2C bus using an on-chip 10-bit ADC. The margin levels are set using the I2C serial bus. The devices initiate margining via the 2 I C bus or by using the MUP or MDN inputs. Once the preprogrammed margin target voltage is reached, the SMM151/152 hold the converter at this voltage until receiving an I2C command or de-asserting the margin input pin. When the SMM151/152 are not margining, the TRIM output pin is held in a high impedance state allowing the converter to operate at its nominal set point. Two general purpose input pins are provided for sensing under or over-voltage conditions. A programmable glitch filter associated with these inputs allows the user to ignore spurious noise signals. A FAULT# pin is asserted once either input set point is exceeded. The SMM152 also provides four programmable general-purpose inputs/outputs. Using the I2C interface, a host system can communicate with the SMM151/152 status register and utilize 256-bytes of nonvolatile memory. Applications • • • In-system test and control of Point-of-Load (POL) Power Supplies for Multi-voltage Processors, DSPs and ASICs Routers, Servers, Storage Area Networks TYPICAL APPLICATION 4.0V-15V 2.7V-5.5V RS CAPC VDD GND VDD_CAP COMP1 CS- V1 CS+ Margin Commands Status Outputs MUP VREF FAULT# READY SDA I2 C Interface COMP2 MDN SMM151 (SMM152) VIN VOUT+ SEN+ TRIM TRIM SCL CAPM+ A0-A2 WP VOUTSEN- DC-DC Converter (GPIO0) CAPM- (GPIO1) VM+ (GPIO2) (GPIO3) VM- Figure 1 – Application with the SMM151/152 used to Monitor and Margin a DC/DC Converter. Notes: RS must be Kelvin sensed for maximum current sensing accuracy.This is an applications example only. Some components and values are not shown. © SUMMIT Microelectronics, Inc. 2007 • 757 N. Mary Avenue • Sunnyvale CA 94085 • Phone 408 523-1000 • FAX 408 523-1266 http://www.summitmicro.com/ 2131 3.0 1/20/2010 1 SMM151/152 GENERAL DESCRIPTION The SMM151 and SMM152 sense converter input current using a Kelvin connected sense resistor in series with the converter supply whose terminals are connected to the CS+ and CS- pins. The internal ADC, also used for measuring the converter’s output voltage, is used to measure the converter’s input current using the voltage dropped across the current sense resistor RS (see Figure 1). The SMM151 and SMM152 are capable of margining the DC output voltage of LDOs or DC/DC converters that use a trim/adjust pin. The Margin function is programmable over a standard 2-wire I2C serial data interface and is used to set the margin low/high DC output voltages. The devices are also capable of monitoring the differential output voltage and the input current of DC/DC converters, thereby providing real-time power information to the system. The SMM151/152 have two additional input pins and one additional output pin. The input pins, COMP1 and COMP2, are high impedance inputs, each connected to a comparator and compared against the internal reference (VREF: 0.5V or 1.25V). Each comparator can be independently programmed to monitor for UV or OV. When either of the COMP1 or COMP2 inputs are in fault the open-drain FAULT# output will be pulled low. A configuration option exists to disable the FAULT# output during margining. In margining mode the user communicates with the SMM151/152 via the I2C serial data bus to select the desired values for margining. This allows the part to margin the supplies up or down to these set values either through asserting the MUP and MDN pins or by writing to the margin register directly. The margin high and margin low voltage settings can range from 0.3V to VDD around the converter’s nominal output voltage setting depending on the specified margin range of the DC-DC converter and/or system components, usually ±10%. The SMM151/152 also feature a margin nominal command and set-point. This can be used to set the converter's nominal output voltage to a more accurate value than is attainable without margining due to inaccuracy of the standalone converter and its voltage setting components. The SMM152 also provides four programmable generalpurpose inputs/outputs. The power-on state of these I/Os is determined via non-volatile (NV) memory. Volatile programming allows the user to select the logic level (HIGH or LOW) of each I/O, which can also be read via a status register. Programming of the SMM151/152 is performed over the industry standard I2C 2-wire serial data interface. A status register is available to read the state of the part and a Write Protect (WP) pin is available to prevent writing to the configuration registers and EE memory. When the SMM151/152 receive the command to margin, the TRIM output will begin adjusting the supply to the selected margin voltage. This is accomplished by incrementing (or decrementing) an internal counter based on the digital comparison between the voltage margin target value and that read by the ADC from the VM+ - VM- differential input. This operation is repeated until the 2 values are equal, after which the SMM151/152 hold the TRIM output pin at the voltage required to maintain the margin setting. An I2C command or de-assertion of the MUP/MDN pin will return the TRIM output pin to a high impedance state thus allowing the converter to return to its nominal operating voltage. Summit Microelectronics, Inc 2131 3.0 1/20/2010 2 SMM151/152 INTERNAL BLOCK DIAGRAM VREF READY FAULT# VDD COMP1 OV/UV VREF VDD_CAP GND Output Control VREF = 1.25V 0.5V/1.25V Glitch Filter OV/UV COMP2 50kΩ Up/Dn MUP Margin Target MDN Digital Comparator Control Logic Halt SW1 50kΩ Clock A0 A1 A2 SCL SDA WP 10Bit ADC I 2C Interface SW2 MUX CAPM+ CAPM- 25kΩ GPIO0 GPIO1 GPIO2 GPIO3 TRIM 8-bit DAC Control Logic 25kΩ VM+ EE Configuration Registers & Memory VMCAPC SMM152 CS+ 250kΩ DIFF AMP CS- Figure 2 – SMM151 and SMM152 Controller Internal Block Diagram. PACKAGE AND PIN DESCRIPTION Summit Microelectronics, Inc 2131 3.0 1/20/2010 3 SMM151/152 PIN DESCRIPTIONS Pin Number Pin Type Pin Name 28 I/O SDA I2C Bi-directional data line 1 I SCL I2C clock input. 2 I A2 4 I A1 6 I A0 I/O GPIO0,1,2,3 NC NC I WP 10, 13 CAP CAPM+, - 20 O TRIM 14 I VM+ 15 I VM- 18 I CS+ 17 I CS- 26 PWR VREF 16 O CAPC 21 PWR VDD 23 PWR VDD_CAP 7 GND GND 24 I MUP 25 I MDN 19 I COMP1 12 I COMP2 11 O FAULT# 3, 9, 22, 27 8 Summit Microelectronics, Inc Pin Description The address pins are biased either to VDD, GND or left floating. This allows for a total of 21 distinct device addresses. When communicating with the SMM151/2 over the 2-wire bus these pins provide a mechanism for assigning a unique bus address. SMM152: General purpose inputs/outputs. SMM151: No Connect. Programmable Write Protect active high/low input. When asserted, writes to the configuration registers and general purpose EE are not allowed. The WP input is internally tied to VDD with a 50KΩ resistor. External capacitor inputs used to filter the VM+/VM- inputs, 0.22μF. Output voltage used to control and/or margin converter voltages. Connect to the converter trim input. Voltage monitor input. Connect to the DC-DC converter positive sense line or its +Vout pin. Voltage monitor input. Connect to the DC-DC converter negative sense line or its -Vout pin. Current monitor input + side. Kelvin connect to the input supply side of the current sense resistor. Current monitor input - side. Kelvin connect to the load side of the current sense resistor. Internal reference voltage of 1.25V. Connect to GND through a 0.1uF capacitor to improve noise immunity. External capacitor input used to filter the CS+/CS- input. Typical value: 1uF. Power supply of the part. External capacitor input used to filter the internal VDD supply rail. Ground of the part. The SMM151/2 ground pin should be connected to the ground of the device under control or to a star point ground. PCB layout should take into consideration ground drops. Margin up command input. Asserted high. The MUP input is internally tied to VDD with a 50KΩ resistor. Margin down command input. Asserted high. The MDN input is internally tied to VDD with a 50KΩ resistor. COMP1 and COMP2 are high impedance inputs, each connected internally to a comparator and compared against the internally programmable VREF voltage. Each comparator can be independently programmed to monitor for UV or OV. The monitor level is set externally with a resistive voltage divider. When either of the COMP1 or COMP2 inputs are in fault the open-drain FAULT# output will be pulled low. A configuration option exists to disable the FAULT# output while the device is margining. 2131 3.0 1/20/2010 4 SMM151/152 PIN DESCRIPTIONS (CONTINUED) 5 I/O READY 29 GND GND Programmable active high/low open drain output indicates that VM+ - VMis at its set point. When programmed as an active high output, READY can also be used as an input. When pulled low, it will latch the state of the comparator inputs. GND. The bottom side metal plate (Pad 29) should be connected on the PCB to GND for optimized noise performance. SDA (GPIO3) VREF MDN MUP VDD_CAP (GPIO2) PIN CONFIGURATION Pin 1 28 27 26 25 24 23 22 28-Pad 5x5 QFN Top View () applies on SMM152 SCL A2 (GPIO0) A1 READY A0 GND 1 21 2 20 3 19 SMM150 4 17 6 16 7 15 9 10 11 12 13 14 WP (GPIO1) CAPM+ FAULT# COMP2 CAPMVM+ 8 Summit Microelectronics, Inc 18 5 2131 3.0 1/20/2010 5 VDD TRIM COMP1 CS+ CSCAPC VM- SMM151/152 ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Temperature Range (Industrial)..................... –40°C to +85°C (Commercial) ..................... 0°C to +70°C CS+, CS- ............................................................. 4.0V to 15V VDD Supply Voltage ........................................... 2.7V to 5.5V Inputs..................................................................GND to VDD Temperature Under Bias .................................-55°C to 125°C Storage Temperature QFN ..............................-65°C to 150°C Terminal Voltage with Respect to GND: VDD Supply Voltage .................................. -0.3V to 6.0V All Others ....................................... -0.3V to VDD + 0.7V FAULT#…………………………….………. GND to 15.0V CS+, CS-...………………………………… -0.3V to 16.0V Output Short Circuit Current ........................................ 100mA Reflow Solder Temperature (10 secs) .......….………....240°C Junction Temperature.........................…….....………....150°C Human Body ESD Rating per JEDEC……..…………....2000V Machine Model ESD Rating per JEDEC……..…………..200V Latch-Up testing per JEDEC………..……...……….…±100mA Package Thermal Resistance (θJA) 28-Pad QFN (Thermal pad connected to PCB)………37.2oC/W 28-Pad QFN (Thermal pad not connected to PCB).…66.5oC/W Moisture Classification Level 3 (MSL 3) per J-STD- 020 RELIABILITY CHARACTERISTICS Data Retention……………………………..………….…20 Years Endurance……………………….………………...100,000 Cycles Note - The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions outside those listed in the operational sections of the specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Devices are ESD sensitive. Handling precautions are recommended. DC OPERATING CHARACTERISTICS TA= 0°C to +70°C, VDD = 2.7V to 5.5V, VCS = 4.0V to 15V, unless otherwise noted. All voltages are relative to GND. Note 6. Symbol Parameter VDD Supply Voltage VMRange Sense Voltage Common Mode Range Notes Min. Typ. Max Unit 2.7 3.3 5.5 V VM+ pin voltage range, Note 5 -0.3 VDD V VM- pin voltage range, Note 5 -0.3 +0.5 V 4.0 15 V CSRange Current Sense Common Mode Voltage Range CS+, CS- pin voltage range IDD Supply Current from VDD TRIM pin floating ITRIM Max. TRIM output current through 100Ω to 1.0V VTRIM TRIM output voltage range ITRIM ±1.5mA, Note 5 VADOC Margin Range Depends on Converter Trim range VIH Input High Voltage SDA, SCL, WP, MUP, MDN Input Low Voltage SDA, SCL, WP, MUP, MDN VDD = 2.7V 0.1xVDD VDD = 5.0V 0.3xVDD VIL VOL Open Drain Output FAULT#, GPIOx, READY VAIH Address Input High Voltage, A2, A1, A0 VAIL Address Input Low Voltage, A2, A1, A0 Summit Microelectronics, Inc 3 mA TRIM Sourcing Current, Note 5 1.5 mA TRIM Sinking Current, Note 5 -1.5 mA GND 2.5 V 0.3 VDD V VDD = 2.7V 0.9xVDD VDD VDD = 5.0V 0.7xVDD VDD ISINK = 1mA 0.2 0.9xVDD VDD VDD = 5.0V, Rpullup≤300kΩ 0.7xVDD VDD VDD = 2.7V, Rpulldown≤300kΩ 0.1xVDD VDD = 5.0V, Rpulldown≤300kΩ 0.3xVDD 6 V V VDD = 2.7V, Rpullup≤300kΩ 2131 3.0 1/20/2010 V V V SMM151/152 DC OPERATING CHARACTERISTICS (CONTINUED) TA= 0°C to +70°C, VDD = 2.7V to 5.5V, VCS = 4.0V to 15V, unless otherwise noted. All voltages are relative to GND. Note 6. Symbol Parameter IAIT Address Input Tristate Maximum Leakage – High Z OV/UV Monitor Voltage Range COMP1 and COMP2 pins VHYST COMP1/2 DC Hysteresis COMP1 and COMP2 pins, VTH-VTL (see Note 1) 10 mV RPull-Up Input Pull-Up Resistors See Pin Descriptions, Note 5 50 kΩ VREF Internal COMP1/2 Reference MARGACC Margin Accuracy Notes Min. Typ. Max Unit -3.0 +3.0 μA 0 VDD V VREF=1.25V 1.24 1.25 1.26 VREF=0.5V 0.495 0.500 0.505 VM+ - VM- = 1.2V, Note 4 -1.0 ±0.75 +1.0 % VM+ - VM- = 2.5V, Note 4 -1.0 ±0.75 +1.0 % VDD V V Voltage Monitor ADC Measure Range VM+ - VM- RVM VM+, VM- Input Resistance Note 5 50 kΩ CMRRVM Voltage Sense Common Mode Rejection Ratio VCM (VM+, VM-) = 0.5V – VDD, Note 5 62 dB CSADC Current Monitor ADC Measure Range Minimum CS+ - CS- voltage 0 Maximum CS+ - CS- voltage 100 VMADC CSACC CMRRCS Current Sense Accuracy Current Sense Common Mode Rejection Ratio 0 mV CSADC ≥ 50mV, Note 2 -2 +2 % CSADC < 50mV, Note 2 -1 +1 mV VCM (CS+, CS-) = 5.0V, Note 5 100 VCM (CS+, CS-) = 12V, Note 5 80 dB Note 1: VHYST is measured with a 1.25V external voltage and is determined by subtracting Threshold Low from Threshold High, VTH-VTL while monitoring the FAULT# pin state. Actual DC Hysteresis is derived from the equation: (VIN(COMP1/2)/VREF)(VHYST). For example, if VIN(COMP1/2)/=2.5V and VREF=1.25V then Actual DC Hysteresis= (2.5V/1.25V)(0.003V)=6mV. Note 2: Current sense accuracy depends on the current sense resistor tolerance. Kelvin sensing of the voltage drop across this resistor must be used to guarantee accuracy. Accuracy at the low range of the current monitor ADC will be adversely impacted by offset errors. Note 3: It is recommended that ADC reads occur with a frequency of not more than 250Hz. Note 4: Voltage accuracy is only guaranteed for factory-programmed settings. Changing voltage from the value reflected in the customer specific CSIR code may result in inaccuracies exceeding those specified above. Note 5: Not 100% Production tested. Guaranteed by Design and/or Characterization. Note 6: All electrical parameters are guaranteed to function over the stated VDD, VCS and temperature range. Electrical parameters not specified as "guaranteed by design" are tested with a VDD voltage required of the specific application. For example, if the device is to be operated at 3.3V and VCS supply of 12V, it is tested with a VDD supply of 3.3V, +-10% and a VCS supply of 12V, +-10%. Summit Microelectronics, Inc 2131 3.0 1/20/2010 7 SMM151/152 AC OPERATING CHARACTERISTICS TA= 0°C to +70°C, VDD = 2.7V to 5.5V unless otherwise noted. All voltages are relative to GND. Symbol Parameter Notes tADC_DAC Monitor sampling/conversion period Update period for ADC conversion and DAC update 1.8 ms tMARG_I/D Margin single bit increment or decrement time TMARG_UPDATE = (X)(1.8ms) where: X=step number of possible 256 steps and 1 step=10mV 1.8 ms tGLITCH_MU/D Margin Up/Down glitch filter tGLITCH_COMP tMARGIN 70 Programmable COMP1 & COMP2 glitch filter times Programmable Margin Delay Times Summit Microelectronics, Inc Min. Typ. 100 Max 130 Unit μs 0 ms 10 ms 20 ms 40 ms 80 ms 100 ms 120 ms 140 ms 2.5 ms 5 ms 10 ms 17.5 ms See Figure 4 2131 3.0 1/20/2010 8 SMM151/152 I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100kHz TA= 0°C to +70°C, VDD = 2.7V to 5.5V unless otherwise noted. All voltages are relative to GND. See Figure 3 Timing Diagram. Note 6. Symbol Description fSCL SCL Clock Frequency Conditions Min Typ tLOW Clock Low Period 4.7 μs tHIGH Clock High Period 4.0 μs tBUF Bus Free Time 4.7 μs tSU:STA Start Condition Setup Time 4.7 μs tHD:STA Start Condition Hold Time 4.0 μs tSU:STO Stop Condition Setup Time 4.7 tAA Clock Edge to Data Valid SCL low to valid SDA (cycle n) 0.2 tDH Data Output Hold Time SCL low (cycle n+1) to SDA change 0.2 tR SCL and SDA Rise Time Note 5 1000 ns tF SCL and SDA Fall Time Note 5 300 ns tSU:DAT Data In Setup Time tHD:DAT Data In Hold Time TI Noise Filter SCL and SDA tWR Write Cycle Time 0 Before New Transmission, Note 5 Max Units 100 KHz μs 3.5 μs 250 ns 0 Noise suppression μs ns 100 ns 5 ms Note 5: Not 100% Production tested. Guaranteed by Design and/or Characterization. Note 6: All electrical parameters are guaranteed to function over the stated VDD, VCS and temperature range. Electrical parameters not specified as "guaranteed by design" are tested with a VDD voltage required of the specific application. For example, if the device is to be operated at 3.3V and VCS supply of 12V, it is tested with a VDD supply of 3.3V, +-10% and a VCS supply of 12V, +-10%. TIMING DIAGRAMS tR tF tSU:STA tHD:STA tWR (For Write Operation Only) tHIGH tLOW SCL tHD:DAT tSU:DAT tSU:STO SDA (IN) tAA tDH SDA (OUT) Figure 3. Basic I2C Serial Interface Timing Summit Microelectronics, Inc 2131 3.0 1/20/2010 9 tBUF SMM151/152 APPLICATIONS INFORMATION the actual converter output voltage. The voltage on the TRIM output will continue increasing or decreasing until the converter’s output voltage equals the target margin voltage. This voltage adjustment allows the SMM151 and SMM152 to control the margined output voltage of the power supply converter to within ±1.0% in an open-loop manner. The converter is held at the margin voltage until the SMM151 receives an I2C command or the respective MUP/MDN pin is de-asserted. When not margining, the TRIM pin on the SMM151/152 is in a high impedance state. The voltage on the TRIM pin is buffered and applied to the ADC at the beginning of a margin cycle to ensure the converter is margined from its nominal setpoint. This allows a smooth transition from the converter’s nominal voltage to the SMM151/152 controlling that margin voltage to the margin target setting. After margining high, low or nominal, issuing a margin Off command will cause the trim pin to go high impedance. The part margin time from Off to High or Off to Low is specified as a typical according to the equation: DEVICE OPERATION POWER SUPPLY The SMM151 and SMM152 can be powered by a 2.7V to 5.5V input to the VDD pin (Figure 1). See Figure 6 as an example. VOLTAGE REFERENCE The SMM151/152 use an internal voltage reference, VREF with a level of 1.25V. Total accuracy of VREF is ±1.0% over temperature and supply variations. MODES OF OPERATION The SMM151/152 have four basic modes of operation: under-voltage (UV) and over-voltage (OV) monitoring mode, differential output voltage sensing mode, input current monitoring mode and supply margining mode. A detailed description of each mode and feature follows and can also be found in Application Note 68. A flow diagram is shown in Figure 5. MARGIN MODE The SMM151/152 can control margining of a DC/DC converter that has a trim pin or any regulator having access to its feedback node. The TRIM pin on the SMM151 is connected to the trim input pin on the power supply converter. Sense lines from the converter’s point-of-load connects to the VM+ and VMinputs. The margin function begins upon an I2C command or assertion of the MUP/MDN pins. The TRIM pin is driven by a DAC whose input is incremented or decremented every 200µs based on the digital comparison of the margin target value and TMARG_UPDATE = (X)(1.8ms) where: X=number of possible steps (256) and 1 step = 10mV The Active Margin Command Delay Time using the MUP and MDN pins is shown in Figure 4. DC/DC Supply Margin N/H/L GND TMARGIN_UPDATE Turn on Time SMM151 Total Margin Delay Time MPU/D/EN tMARGIN - Internal Programmable Active Margin Delay Time tADC_DAC ADC/DAC tADC_DAC ADC/DAC Sample/ Sample/ Conversion time Conversion time 1.8ms 1.8ms Figure 4 – Margin Delay Time Summit Microelectronics, Inc 2131 3.0 1/20/2010 10 SMM151/152 APPLICATIONS INFORMATION (CONTINUED) MARGINING OPERATION NO POWER OK? YES INPUT VTRIM TO ADC DUMP ADC INTO DAC DAC DRIVES BRICK (TRIM OUTPUT LO-Z) INPUT VOUT TO ADC ADC EQUAL TARGET? NO INCREMENT/ DECREMENT DAC YES 1. HOLD DAC 2. CLEAR STATUS REGISTER 3. WAIT FOR NEXT COMMAND Figure 5 - SMM151/152 Margin Flow Chart Summit Microelectronics, Inc 2131 3.0 1/20/2010 11 SMM151/152 APPLICATIONS INFORMATION (CONTINUED) from bit 0 of registers 34h, 35h, 36h or 37h with 0=Low and 1=High. Additionally, the I/Os have a command bit that when written overrides the NV setting and sets the pin either high or low. The I/Os also have status bits to read the state of the pin as high or low. The command/status register for each I/O is addressed separately alleviating the need for the host controller to remember the state of the other I/Os when writing commands. More information can be found in Application Note 69. When measuring the margin delay time external to the device, ADC sample time and Update Trim time (≅ 3.6 ms) must be added to the internally programmed delay time as shown: Spec Actual measurement 2.5 ms 6.1 ms 5 ms 8.6 ms 10 ms 13.6 ms 17.5 ms 21.1 ms MONITOR The SMM151/152 monitor the COMP1 and COMP2 pins. COMP1 and COMP2 are high impedance inputs, each connected internally to a comparator and compared against the programmable internal reference voltage. Each comparator can be independently programmed to monitor for either an UV or an OV event. The monitor level may be set externally with a resistive voltage divider. The COMPx pins can be connected to Vin, Vout or any voltage that needs to be monitored. The internal comparators COMP1/2 are compared to VREF, so the voltage dividers are set above or below the programmed VREF level depending on whether monitoring UV or OV. As an example, with VREF set to 1.25V, to monitor an OV of 1.7V on COMP1 and a UV of 1.3V on COMP2, the voltage divider resistors are: STATUS REGISTER A status register exists for I2C polling of the status of the COMP1 and COMP2 inputs. Two bits in this status register reflect the current state of the inputs (1 = fault, 0 = no fault). Two additional bits show the state of the inputs latched by one of two events programmed in the configuration. More information can also be found in Application Note 69. The first event option is the FAULT# output going active. The second event option is the READY pin going low. The READY pin is an I/O. As an output, the READY output pin goes active when the DC controlled voltages are at their set point. As an input programmed to active high, it can be pulled low externally and latch the state of the COMP inputs. This second event option allows the state of the COMP inputs on multiple devices to be latched at the same time while a host monitors their FAULT# outputs. For OV, RUpper = 1.37k, 1% RLower = 3.83k, 1%. For UV, RUpper = 1.02k, 1% RLower = 25.5k, 1%. MARGINING The SMM151/152 have three additional control voltage settings: margin high, margin nominal, and margin low. The margin high and margin low settings can be as much as ±15% of the nominal setting depending on the converter manufacturer. The margin high and margin low voltage settings can range from 0.3V to VDD around the converters’ nominal output voltage setting depending on the specified margin range of the DC-DC converter. These settings are stored in the configuration registers and are loaded as control voltage settings by margin commands issued via the I2C bus. The margin command registers contain two bits that decode the commands to margin high or margin low. Once the SMM151/152 receive the command to margin the supply voltage, it begins adjusting the supply voltage to move toward the desired setting. When this voltage setting is reached, a bit is set in the margin status registers and the READY signal becomes active. Note: Configuration writes or reads of registers 00HEX to 03HEX should not be performed while the SMM151 or SMM152 is margining. The parts can be programmed to trigger the FAULT# pin when either COMPx comparator has exceeded the UV or OV setting. The READY and FAULT# outputs of the SMM151/152 are active as long as the triggering limit remains in a fault condition. The READY pin is a programmable active high/low open drain output indicates that VM+ - VM- is at its’ set point. When programmed as an active high output, READY can also be used as an input. When pulled low, it will latch the state of the comparator inputs. When either of the COMP1 or COMP2 inputs are in fault, the opendrain FAULT# output will be pulled low. A configuration option exists to disable the FAULT# output while the device is in margining mode. GENERAL-PURPOSE INPUTS/OUTPUTS The GPIOs are open drain type outputs. The pins should be pulled up externally to voltages ranging from 2.0V to 12V. Each I/O has non-volatile (NV) memory setting associated with it that determines the power-on state of the pin. The status (High/Low) is read Summit Microelectronics, Inc 2131 3.0 1/20/2010 12 SMM151/152 APPLICATIONS INFORMATION (CONTINUED) For example, writing 59HEX will allow writes to the configuration register but not to the memory, while writing 35HEX will allow writes to the memory but not to the configuration registers. The SMM151/152 also feature a Write Protect pin (WP input) which, when asserted, prevents writing to the configuration registers and EE memory. In addition to these two forms of write protection there is a configuration register lock bit which, once programmed, does not allow the configuration registers to be changed. A2, A1, A0 The address bits A[2:0] can be hard wired High or Low or may be left open (High-Z) to allow for a total of 21 distinct device addresses. When floating, the inputs can tolerate the amount of leakage as described by the specification IAIT. An external 100k pull-up or pull down resistor is sufficient to set a High or Low logic level. CS+, CSSelect a resistor value that will drop no more than 100mV (full scale) when full load is drawn by the converter or circuit being sensed by the resistor RS (Figure 1). To obtain highest accuracy current-sensing, provide a Kelvin connection from the resistor to the CS+ and CS- pins. Do not allow the main current path circuit traces to inadvertently become a part of the current sense resistor. Kelvin connect directly at the resistor and follow the manufacturer’s instructions for exact positioning of the traces for Kelvin sensing. FAULTS When either of the COMP1 or COMP2 inputs are in fault, the open-drain FAULT# output will be pulled low. A configuration option exists to disable the FAULT# output while the device is margining. If “Fault Output Disabled while Margining” is selected, Faults are disabled for all margining except when margining to the ‘Off’ and ‘Nominal’ states. Also, the programmable feature ‘Fault Holds Off and Shutdown Control’ is enabled only for the Nominal margin state. Please note that if "Fault Output Disabled” is selected and the device has margined to LOW and HIGH and then returns to the OFF state without going through NOMINAL, the Status Register will read a fault (if there is one) but the FAULT Output Pin will be disabled until such time that the NOMINAL setting is activated. To avoid this condition it is recommended that the device always return to OFF from the NOMINAL state. Fault Latched by a Fault Condition: The “Fault Latched by a Fault Condition” programmable option is triggered only on the leading edge of a Fault. That is, a latched fault can be cleared while the Fault yet exists. Fault Latched by Ready I/O Pin: Fault Latched by Ready I/O pin functions on the margin transitions from Off to Hi/Low/Nominal or from Nominal to Hi/Low or Hi/Low to Nominal but not from Hi/Low/Nominal to Off. WRITE PROTECTION Write protection for the SMM151/152 is located in a volatile register where the power-on state is defaulted to write protect. There are separate write protect modes for the configuration registers and memory. In order to remove write protection, the code 55HEX is written to the write protection register.Other codes will enable write protection. Summit Microelectronics, Inc 2131 3.0 1/20/2010 13 SMM151/152 APPLICATIONS INFORMATION (CONTINUED) READY +VIN 2.7V- 5.5V FAULT# 12VIN MUP VDD R6 MDN VDD 0.01, 1% VDD C1 0.01uF C2 0.1uF C3 10uF U2 DC-DC SIE 6 4 2 8 VMTrim 16 3 92227 NCNCNCNC C4 0.47uF VDD_CAP Gnd CAPM+ VOUT = 1.5V R7 R Load Trim C12 C Load R5 10 2.5k 20 26 10 C6 0.22uF CAPM- 4 3 14 R1 R2 R3 R4 25.5K, 1% 7 1 2 C7 0.1uF 1.02K, 1% VREF -Vout -Sense 15 3.83K, 1% A0 A1 A2 WP# C11 0.01uF +Vout +Sense 12 1.37K, 1% I2C VM+ 13 23 2 4 6 8 10 SMM151 CAPC Gnd SCL Gnd3 SDA Rsrv5 MR +10V Rsrv8 +5V Rsrv10 SCL SDA C10 0.1uF 19 +Vin +Vin Enable +Vin Gnd Gnd 17 Comp2 1 28 J1 1 3 5 7 9 CS- 18 5 11 Comp1 DIODE D1 7 8 11 9 5 6 MDN MUP CS+ 25 24 Fault# 21 1 U1 VDD Programming Supply Ready 2 VDD C5 1uF C8 0.01uF C9 0.01uF Figure 6 – Typical application schematic shows the SMM151 controlling a 12V in/1.5V out DC/DC converter. This example, using the 1.25V VREF, also shows the COMP1/2 pins monitoring the DC/DC converter VOUT set to an OV of 1.7V on COMP1 and a UV of 1.3V on COMP2, the voltage divider resistors are: For OV, R1 = 1.37k, 1% R3 = 3.83k, 1%, For UV, R2 = 1.02k, 1% R4 = 25.5k, 1%. The Programming Supply jumper can be used to supply the SMM151 VDD voltage from the SMX3202 programmer when the device is programmed with board power off and the controlled supply unloaded. Summit Microelectronics, Inc 2131 3.0 1/20/2010 14 SMM151/152 APPLICATIONS INFORMATION (CONTINUED) Maximizing Accuracy Maximum margining accuracy is obtained by placing a resistor between the SMM151/152 TRIM output and the TRIM input of the converter. From the manufacturer’s data sheet obtain the value of the internal voltage reference and equivalent TRIM input series resistance. Figure 7 below displays the internal trimming circuit for a typical isolated DC-DC converter. In this example, the converter uses positive trimming, i.e., an increase in voltage at the TRIM pin causes an increase in output voltage. V+ VREF +S L O A D R1 DC-DC Converter RTRIM TRIM SMM151/152 TRIM Pin R2 V- VREF -S Figure 7 - Simplified TRIM circuit of an isolated DC-DC converter connects to SMM151/152 TRIM output For this example RTRIM is found: The next example applies to most non-isolated DC-DC converters, LDO’s and in-system designed converters using monolithic PWM controllers. Figure 8 is a simplified schematic showing the resistor divider network used to close the loop from the output to the circuit’s feedback node. These type circuits employ negative trimming, meaning any decrease in voltage into the feedback node cause an increase in output voltage. ⎡ (VREF ×k ) -0.3 ⎤ R 2× ⎢ ⎥ ⎣ (VREF -0.3) ⎦ RTRIM = ( k×VREF -0.3) 1(VREF -0.3) Where: RTRIM = VLow k= VNom k= 0.3 = SMM151/152 TRIM output saturation voltage VLow = Margin Low target voltage VNom = Nominal (non-trimmed output voltage) VREF = Converter internal reference voltage Summit Microelectronics, Inc R1× (VREF -0.3) VNom× ( k -1) VHigh VNom 0.3 = SMM151/152 TRIM output saturation voltage VHIGH = Margin Low target voltage VNom = Nominal (non-trimmed output voltage) VREF = Converter internal reference voltage 2131 3.0 1/20/2010 15 SMM151/152 APPLICATIONS INFORMATION (CONTINUED) VOUT RTRIM R1 SMM151/152 TRIM Pin To FB node (VREF) R2 Figure 8 - Simplified TRIM circuit of a non-isolated DC-DC converter connects to SMM151/152 TRIM output Summit Microelectronics, Inc 2131 3.0 1/20/2010 16 SMM151/152 APPLICATIONS INFORMATION (CONTINUED) The Windows GUI software will generate the data and send it in I2C serial bus format so that it can be directly downloaded to the SMM151/152 via the programming Dongle and cable. An example of the connection interface is shown in Figure 9. The end user can obtain the Summit SMX3202 programming system for device prototype development. The SMX3202 system consists of a programming Dongle, cable and WindowsTM GUI software. It can be ordered on the website or from a local representative. The latest revisions of all software and an application brief describing the SMX3202 is available from the website (www.summitmicro.com). When design prototyping is complete, the software can generate a HEX data file that should be transmitted to Summit for approval. Summit will then assign a unique customer ID to the HEX code and program production devices before the final electrical test operations. This will ensure proper device operation in the end application. The SMX3202 programming Dongle/cable interfaces directly between a PC’s USB port and the target application. The device is then configured on-screen via an intuitive graphical user interface employing dropdown menus. Top view of straight 0.1" x 0.1 closed-side connector. SMX3202 interface cable connector. D1 Positive Supply Jumper Pin 10, Reserved Pin 8, Reserved Pin 6, MR# Pin 4, SDA Pin 2, SCL 1N4148 VDD SMM151 SMM152 WP SDA SCL 10 8 6 4 2 9 7 5 3 1 Pin 9, 5V Pin 7, 10V Pin 5, Reserved Pin 3, GND Pin 1, GND C1 0.1μF GND Common Ground Figure 9– SMX3202 Programmer I2C serial bus connections to program the SMM151/152. The SMM151/152 have a Write Protect pin (WP input) which, when asserted, prevents writing to the configuration registers and EE memory. In addition, there is a configuration register lock bit, which, once programmed, does not allow the configuration registers to be changed. Summit Microelectronics, Inc 2131 3.0 1/20/2010 17 SMM151/152 I2C PROGRAMMING INFORMATION WRITE Writing to the memory or configuration registers is illustrated in Figures 10, 11, 12, 14, 15 and 17. A Start condition followed by the address byte is provided by the host I2C controller; the SMM151 responds with an Acknowledge; the host then responds by sending the memory address pointer or configuration register address pointer; the SMM151/152 respond with an acknowledge; the host then clocks in one byte of data. For memory and configuration register writes, up to 15 additional bytes of data can be clocked in by the host to write to consecutive addresses within the same page. After the last byte is clocked in and the host receives an Acknowledge, a Stop condition must be issued to initiate the nonvolatile write operation. READ The address pointer for the configuration registers, memory, command and status registers and ADC registers must be set before data can be read from the SMM151. This is accomplished by issuing a dummy write command, which is simply a write command that is not followed by a Stop condition. The dummy write command sets the address from which data is read. After the dummy write command is issued, a Start command followed by the address byte is sent from the host. The host then waits for an Acknowledge and then begins clocking data out of the slave device (SMM151/2). The first byte read is data from the address pointer set during the dummy write command. Additional bytes can be clocked out of consecutive addresses with the host providing an Acknowledge after each byte. After the data is read from the desired registers, the read operation is terminated by the host holding SDA high during the Acknowledge clock cycle and then issuing a Stop condition. Refer to Figures 13, 16 and 18 for an illustration of the read sequence. WRITE PROTECTION The SMM151/152 power up into a write protected mode. Writing a code to the volatile write protection register (write only) can disable the write protection. The write protection register is located at address 38HEX. Writing to the write protection register is shown in Figure 10. Writing 0101BIN to bits [7:4] of the write protection register allows writes to the general-purpose memory while writing 0101BIN to bits [3:0] allow writes to the configuration registers. Write protection isre-enabled by writing other codes (not 0101BIN) to the write protection register. SERIAL INTERFACE Access to the configuration registers, general-purpose memory and command and status registers is carried out over an industry standard 2-wire serial interface (I2C). SDA is a bi-directional data line and SCL is a clock input. Data is clocked in on the rising edge of SCL and clocked out on the falling edge of SCL. All data transfers begin with the most significant bit (MSB). During data transfers SDA must remain stable while SCL is high. Data is transferred in 8-bit packets with an intervening clock period in which an Acknowledge is provided by the device receiving data (SMM151). The SCL high period (tHIGH) is used for generating Start and Stop conditions that precede and end most transactions on the serial bus. A high-to-low transition of SDA while SCL is high is considered a Start condition while a low-to-high transition of SDA while SCL is high is considered a Stop condition. The interface protocol allows operation of multiple devices and types of devices on a single bus through unique device addressing. The address byte is comprised of a 4-bit device type identifier (slave address) and a unique (three-state) 3-bit bus address. The remaining bit indicates either a read or a write operation. Refer to Table 1 for a description of the address bytes used by the SMM151/152. Refer to Table 2 for an example of the unique address handling of the SMM151/152. The device type identifier for the memory array, the configuration registers and the command and status registers are accessible with the same slave address. It can be set using the address pins as described in Table 2. The bus address bits A[2:0] are hard wired only through address pins 2, 4 and 6 (A2, A1 and A0 respectively) or may be left open (Z) to allow for a total of 21 distinct device addresses. The bus address accessed in the address byte of the serial data stream must match the setting on the SMM151 address pins. Summit Microelectronics, Inc 2131 3.0 1/20/2010 18 SMM151/152 I2C PROGRAMMING INFORMATION (CONTINUED) CONFIGURATION REGISTERS COMMAND AND STATUS REGISTERS The majority of the configuration registers are grouped Writes and reads of the command and status registers with the general-purpose memory. Writing and reading are shown in Figures 17 and 18. the configuration registers is shown in Figures 11, 12 GRAPHICAL USER INTERFACE (GUI) and 13. Device configuration utilizing the Windows based Note: Configuration writes or reads of registers 00 to SMM151/152 graphical user interface (GUI) is strongly 03HEX must not be performed while the SMM151/152 is recommended. The software is available from the margining. Summit website (www.summitmicro.com). Using the GENERAL-PURPOSE MEMORY GUI in conjunction with this datasheet simplifies the process of device prototyping and the interaction of The 256-byte general-purpose memory is located at the various functional blocks. A programming Dongle any slave address. The bus address bits are hard (SMX3202) is available from Summit to communicate wired by the address pins A2, A1 and A0. They can be with the SMM151/152. See Figure 9 and the SMX3202 tied low, high or left floating, (Hi-Z). Memory writes and Data Sheet (www.summitmicro.com). reads are shown in Figures 14, 15 and 16. Slave Address Bus Address Register Type 10XX A2 A1 A0 Configuration Registers are located in 00 HEX thru 05HEX and 30 HEX thru 3EHEX General-Purpose Memory is located in 40 HEX thru FF HEX Table 1 - Address bytes used by the SMB151/152. Slave Address programmed as 10XX (Z = Hi-Z state) A2 0 0 0 0 0 0 0 Pins A[2:0] A1 0 0 0 1 1 1 Z A0 0 1 Z 0 1 Z X Slave Address 1000 1000 1000 1000 1000 1000 1000 Bus Address 000 001 010 100 101 110 011 1 1 1 1 1 1 1 0 0 0 1 1 1 Z 0 1 Z 0 1 Z X 1001 1001 1001 1001 1001 1001 1001 000 001 010 100 101 110 011 Z Z Z Z Z Z Z 0 0 0 1 1 1 Z 0 1 Z 0 1 Z X 1010 1010 1010 1010 1010 1010 1010 000 001 010 100 101 110 011 Table 2 – Example device addresses allowed by the SMM151. Summit Microelectronics, Inc 2131 3.0 1/20/2010 19 SMM151/152 I2C PROGRAMMING INFORMATION (CONTINUED) Master S T A R T Configuration Register Address = 38HEX Bus Address 1 S A 1 0 S A 0 A 1 A 2 A 0 W 0 0 A C K Slave 1 1 1 0 3HEX S T O P Data = 55HEX 0 0 0 1 0 1 0 1 0 1 A C K 8HEX A C K Write Protection Register Address 5HEX Unlocks General Purpose EE 5HEX Unlocks Configuration Registers Figure 10 – Write Protection Register Write Master S T A R T Configuration Register Address Bus Address 1 S A 1 0 S A 0 A 2 A 1 A 0 C 7 W C 6 C 5 C 4 C 3 Data C 2 C 1 C 0 D 7 A C K Slave S T O P D 6 D 5 D 4 D 3 D 2 D 1 D 0 A C K A C K Figure 11 – Configuration Register Byte Write Master S T A R T Configuration Register Address Bus Address 1 0 S A 1 S A 0 A 2 A 1 A 0 C 6 C 5 C 4 C 3 C 2 C 1 C 0 A C K Slave D 7 D 6 D 7 D 6 D 5 D 4 D 3 D 5 D 3 D 2 D 1 D 0 A C K S T O P Data (16) D 2 D 1 D 0 D 7 D 6 D 5 D 2 A C K D 1 D 0 D 7 D 6 D 5 D 4 A C K Figure 12 – Configuration Register Page Write Summit Microelectronics, Inc D 4 A C K Data (2) Master Slave C 7 W Data (1) 2131 3.0 1/20/2010 20 D 3 D 2 D 1 D 0 A C K SMM151/152 I2C PROGRAMMING INFORMATION (CONTINUED) Master S T A R T Configuration Register Address Bus Address 1 S A 1 0 S A 0 A 2 A 1 S T A R T A 0 C 6 C 7 W C 5 C 4 C 3 C 2 C 1 S A 3 C 0 A C K Slave D 7 D 6 D 5 D 4 D 3 D 2 D 1 S A 2 S A 0 A 2 A 1 A 0 R A C K A C K D 0 S A 1 A C K A C K Data (1) Master Bus Address D 7 D 6 D 5 D 2 D 1 N A C K Data (n) D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 S T O P D 0 Slave Figure 13 - Configuration Register Read Master S T A R T Configuration Register Address Bus Address 1 S A 1 0 S A 0 A 2 A 1 A 0 C 6 C 7 W C 5 C 4 C 3 Data C 2 C 1 C 0 D 7 A C K Slave S T O P D 6 D 5 D 4 D 3 D 2 D 1 D 0 A C K A C K Figure 14 – General Purpose Memory Byte Write Master S T A R T Configuration Register Address Bus Address 1 0 S A 1 S A 0 A 2 A 1 A 0 C 6 C 5 C 4 C 3 C 2 C 1 C 0 A C K Slave Master D 7 D 6 D 6 D 5 D 4 D 3 D 5 D 3 D 2 D 1 D 0 A C K S T O P Data (16) D 2 D 1 D 0 D 7 D 6 D 5 D 2 A C K D 1 D 0 D 7 D 6 D 5 D 4 A C K Figure 15 - General Purpose Memory Page Write Summit Microelectronics, Inc D 4 A C K Data (2) D 7 Slave C 7 W Data (1) 2131 3.0 1/20/2010 21 D 3 D 2 D 1 D 0 A C K SMM151/152 I2C PROGRAMMING INFORMATION (CONTINUED) Master S T A R T Configuration Register Address Bus Address 1 0 S A 1 S A 0 A 2 A 1 A 0 S T A R T C 7 W C 6 C 5 C 4 C 3 C 2 C 1 Master D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 S A 0 S A 1 A 2 A 1 A 0 R A C K A C K D 7 S A 2 A C K A C K Data (1) S A 3 C 0 A C K Slave Bus Address D 6 D 5 D 2 D 1 D 0 N A C K Data (n) D 7 D 6 D 5 D 4 D 3 D 2 D 1 S T O P D 0 Slave Figure 16 - General Purpose Memory Read Master S T A R T Command and Status Register Address Bus Address 1 0 S A 1 S A 0 A 2 A 1 A 0 C 7 W C 6 C 5 C 4 C 3 C 2 Data C 1 C 0 A C K Slave S T O P D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 A C K A C K Figure 17 – Command and Status Register Write Master S T A R T Command and Status Register Address Bus Address 1 0 S A 1 S A 0 A 2 A 1 A 0 S T A R T C 7 W C 6 C 5 C 4 C 3 C 2 C 1 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 S A 0 A 2 A 1 A 0 D 6 D 5 D 2 D 1 D 0 D 7 D 6 D 5 D 4 Figure 18 - Command and Status Register Read 2131 3.0 1/20/2010 22 N A C K Data (n) Slave Summit Microelectronics, Inc S A 1 R A C K A C K D 7 S A 2 A C K A C K Data (1) Master S A 3 C 0 A C K Slave Bus Address D 3 D 2 D 1 D 0 S T O P SMM151/152 PACKAGE OUTLINES 28-Pad QFN Summit Microelectronics, Inc 2131 3.0 1/20/2010 23 SMM151/152 PART MARKING SUMMIT Summit Part Number SMM151N Subject to Change Status Tracking Code (Blank, MS, ES, 01, 02,...) (Summit Use) SS nnnn L AYYWW Date Code (YYWW) Pin 1 Lot tracking code (Summit use) 100% Sn, RoHS compliant Part Number suffix (Contains Customer specific ordering requirements) Drawing not to scale ORDERING INFORMATION Summit Part Number SMM151 N C nnnn L L: Lead-Free Attribute for QFN package Part Number Suffix SMM151 or SMM152 Temp Range Package N=28 Pad QFN C=Commercial Blank=Industrial Customer specific requirements are contained in the suffix such as Hex code, Hex code revision, etc. (Default CSIRs: SMM151=786, SMM152=957) NOTICE NOTE 1 - This is a final data sheet that describes a Summit product currently in production. SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. Revision 3.0 - This document supersedes all previous versions. www.summitmicro.com for data sheet updates. © Copyright 2008 SUMMIT MICROELECTRONICS, Inc. Please check the Summit Microelectronics Inc. web site at PROGRAMMABLE POWER FOR A GREEN PLANET™ I2C is a trademark of Philips Corporation Summit Microelectronics, Inc 2131 3.0 1/20/2010 24