INTERSIL ISL90840WIV2027Z

ISL90840
®
Quad Digitally Controlled Potentiometers (XDCP™)
Data Sheet
July 27, 2005
FN8086.0
Low Noise, Low Power I2C® Bus, 256 Taps
Features
The ISL90840 integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
circuit.
• Four potentiometers in one package
• 256 resistor taps - 0.4% resolution
• I2C serial interface
- Three address pins, up to eight devices/bus
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. Each potentiometer has an associated
Wiper Register (WR) that can be directly written to and read
by the user. The contents of the WR controls the position of
the wiper.
• Wiper resistance: 70Ω typical @ 3.3V
• Standby current <5µA max
• Power supply: 2.7V to 5.5V
• 50kΩ, 10kΩ total resistance
The DCPs can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• 20 Lead TSSOP
• Pb-free plus anneal available (RoHS compliant)
Pinout
ISL90840
(20 LEAD TSSOP)
TOP VIEW
Ordering Information
PART NUMBER
PACKAGE
TEMP
RANGE
(°C)
RESISTANCE
OPTION
(Ω)
ISL90840UIV2027
20 Ld TSSOP
-40 to +85
50K
ISL90840UIV2027Z
(Notes 1 & 2)
20 Ld TSSOP
(Pb-Free)
-40 to +85
50K
ISL90840WIV2027
20 Ld TSSOP
-40 to +85
10K
ISL90840WIV2027Z
(Notes 1 & 2)
20 Ld TSSOP
(Pb-Free)
-40 to +85
10K
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
RH3
1
20
RW0
RL3
2
19
RL0
RW3
3
18
RH0
A2
4
17
D.N.C.
SCL
5
16
VCC
SDA
6
15
A1
GND
7
14
A0
RW2
8
13
RH1
RL2
9
12
RL1
RH2
10
11
RW1
2. Contact factory for availability.
Functional Diagram
VCC
RH0
RH1
RH2
RH3
SCL
SDA
A0
I2C
INTERFACE
A1
A2
GND
1
RL0
RW0
RL1
RW1
RL2
RW2
RL3
RW3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL90840
Block Diagram
VCC
SDA
I2C INTERFACE
SCL
POWER-UP,
INTERFACE,
CONTROL
AND STATUS
LOGIC
WR3
DCP3
RH3
RW3
RL3
WR2
DCP2
RH2
RW2
RL2
WR1
DCP1
RH1
RW1
RL1
WR0
DCP0
RH0
RW0
RL0
A2
A1
A0
GND
Pin Descriptions
TSSOP PIN
SYMBOL
1
RH3
“High” terminal of DCP3
2
RL3
“Low” terminal of DCP3
3
RW3
“Wiper” terminal of DCP3
4
A2
5
SCL
I2C interface clock
6
SDA
Serial data I/O for the I2C interface
7
GND
Device ground pin
8
RW2
“Wiper” terminal of DCP2
9
RL2
“Low” terminal of DCP2
10
RH2
“High” terminal of DCP2
11
RW1
“Wiper” terminal of DCP1
12
RL1
“Low” terminal of DCP1
13
RH1
“High” terminal of DCP1
14
A0
Device address for the I2C interface
15
A1
Device address for the I2C interface
16
VCC
17
D.N.C.
18
RH0
“High” terminal of DCP0
19
RL0
“Low” terminal of DCP0
20
RW0
“Wiper” terminal of DCP0
2
DESCRIPTION
Device address for the I2C interface
Power supply pin
Do not connect
FN8086.0
July 27, 2005
ISL90840
Absolute Maximum Ratings
Recommended Operating Conditions
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at any digital interface pin
with respect to GND . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Voltage at any DCP pin with
respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC
Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300°C
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level B at +85°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2kV Human Body Model
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Power rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW
Wiper current of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Specifications
SYMBOL
RTOTAL
Over recommended operating conditions unless otherwise stated.
PARAMETER
RH to RL resistance
TEST CONDITIONS
CH/CL/CW
ILkgDCP
Wiper resistance
MAX
UNIT
10
kΩ
U option
50
kΩ
-20
VCC = 3.3V @ 25°C, wiper current =
VCC/RTOTAL
70
Potentiometer capacitance (Note 15)
Leakage on DCP pins (Note 15)
TYP
(NOTE 1)
W option
RH to RL resistance tolerance
RW
MIN
+20
%
200
Ω
10/10/25
Voltage at pin from GND to VCC
0.1
pF
1
µA
-1
1
LSB
(Note 2)
-0.5
0.5
LSB
(Note 2)
LSB
(Note 2)
VOLTAGE DIVIDER MODE (0V @ RLi; VCC @ RHi; measured at RWi, unloaded; i = 0, 1, 2, or 3)
INL
(Note 6)
Integral non-linearity
DNL
(Note 5)
Differential non-linearity
Monotonic over all tap positions
ZSerror
(Note 3)
Zero-scale error
W option
0
1
7
U option
0
0.5
2
FSerror
(Note 4)
Full-scale error
W option
-7
-1
0
U option
-2
-1
0
VMATCH
(Note 7)
DCP to DCP matching
Any two DCPs at same tap position, same
voltage at all RH terminals, and same voltage
at all RL terminals
-2
TCV
(Note 8)
Ratiometric temperature coefficient
DCP register set to 80 hex
2
±4
LSB
(Note 2)
LSB
(Note 2)
ppm/°C
RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected. i = 0, 1, 2 or 3)
RINL
(Note 12)
Integral non-linearity
RDNL
(Note 11)
Differential non-linearity
Roffset
(Note 10)
Offset
DCP register set between 20 hex and FF
hex; monotonic over all tap positions
1
MI
(Note 9)
-0.5
0.5
MI
(Note 9)
W option
0
1
7
MI
(Note 9)
U option
0
0.5
2
MI
(Note 9)
-2
2
MI
(Note 9)
RMATCH
(Note 13)
DCP to DCP matching
Any two DCPs at the same tap position with
the same terminal voltages
TCR
(Note 14)
Resistance temperature coefficient
DCP register set between 20 hex and FF hex
3
-1
±45
ppm/°C
FN8086.0
July 27, 2005
ISL90840
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
ICC1
ISB
ILkgDig
tDCP
(Note 15)
PARAMETER
TEST CONDITIONS
MIN
TYP
(NOTE 1)
MAX
UNIT
VCC supply current (volatile
write/read)
fSCL = 400kHz; SDA = Open; (for I2C, active,
read and write states)
1
mA
VCC current (standby)
VCC = +5.5V, I2C interface in standby state
5
µA
VCC = +3.6V, I2C interface in standby state
2
µA
10
µA
1
µs
Leakage current, at pins A0, A1, A2,
SDA, and SCL
Voltage at pin from GND to VCC
DCP wiper response time
SCL falling edge of last bit of DCP data byte
to wiper change
-10
SERIAL INTERFACE SPECS
VIL
A2, A1, A0, SDA, and SCL input buffer
LOW voltage
-0.3
0.3*VCC
V
VIH
A2, A1, A0, SDA, and SCL input buffer
HIGH voltage
0.7*VCC
VCC+0.3
V
Hysteresis
(Note 15)
SDA and SCL input buffer hysteresis
0.05*
VCC
VOL
(Note 15)
SDA output buffer LOW voltage,
sinking 4mA
Cpin
(Note 15)
fSCL
0
V
0.4
V
A2, A1, A0, SDA, and SCL pin
capacitance
10
pF
SCL frequency
400
kHz
tIN
(Note 15)
Pulse width suppression time at SDA
and SCL inputs
Any pulse narrower than the max spec is
suppressed
50
ns
tAA
(Note 15)
SCL falling edge to SDA output data
valid
SCL falling edge crossing 30% of VCC, until
SDA exits the 30% to 70% of VCC window
900
ns
tBUF
(Note 15)
Time the bus must be free before the
start of a new transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC
during the following START condition
1300
ns
tLOW
Clock LOW time
Measured at the 30% of VCC crossing
1300
ns
tHIGH
Clock HIGH time
Measured at the 70% of VCC crossing
600
ns
tSU:STA
START condition setup time
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
600
ns
tHD:STA
START condition hold time
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
600
ns
tSU:DAT
Input data setup time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
100
ns
tHD:DAT
Input data hold time
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
0
ns
tSU:STO
STOP condition setup time
From SCL rising edge crossing 70% of VCC,
to SDA rising edge crossing 30% of VCC
600
ns
tHD:STO
STOP condition hod time for read, or
volatile only write
From SDA rising edge to SCL falling edge;
both crossing 70% of VCC
600
ns
tDH
(Note 15)
Output data hold time
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC
window
0
ns
tR
(Note 15)
SDA and SCL rise time
From 30% to 70% of VCC
4
20 +
0.1 * Cb
250
ns
FN8086.0
July 27, 2005
ISL90840
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(NOTE 1)
MAX
UNIT
tF
(Note 15)
SDA and SCL fall time
From 70% to 30% of VCC
20 +
0.1 * Cb
250
ns
Cb
(Note 15)
Capacitive loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu
(Note 15)
SDA and SCL bus pull-up resistor off- Maximum is determined by tR and tF
chip
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ
1
kΩ
tSU:A
A2, A1 and A0 setup time
Before START condition
600
ns
tHD:A
A2, A1 and A0 hold time
After STOP condition
600
ns
SDA vs SCL Timing
tF
tHIGH
SCL
tLOW
tR
tSU:DAT
tSU:STA
tHD:DAT
tHD:STA
SDA
(INPUT TIMING)
tSU:STO
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
A0, A1, and A2 Pin Timing
STOP
START
SCL
CLK 1
SDA IN
tSU:A
tHD:A
A0, A1, OR A2
5
FN8086.0
July 27, 2005
ISL90840
NOTES:
1. Typical values are for TA = 25°C and 3.3V supply voltage.
2. LSB: [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
3. ZS error = V(RW)0/LSB.
4. FS error = [V(RW)255 – VCC]/LSB.
5. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting.
6. INL = V(RW)i – i - LSB – V(RW) for i = 1 to 255.
7. VMATCH = [V(RWx)i – V(RWy)i]/LSB, for i = 0 to 255, x = 0 to 3 and y = 0 to 3.
Max ( V ( RW ) i ) – Min ( V ( RW ) i )
10 6
8. TC V = ---------------------------------------------------------------------------------------------- × ----------------- for i = 16 to 240 decimal, T = -40°C to 85°C. Max( ) is the maximum value of the wiper
[ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] ⁄ 2 125°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.
9. MI = |R255 – R0|/255. R255 and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively.
10. Roffset = R0/MI, when measuring between RW and RL.
Roffset = R255/MI, when measuring between RW and RH.
11. RDNL = (Ri – Ri-1)/MI, for i = 32 to 255.
12. RINL = [Ri – (MI • i) – R0]/MI, for i = 32 to 255.
13. RMATCH = (Ri,x – Ri,y)/MI, for i = 0 to 255, x = 0 to 3 and y = 0 to 3.
6
[ Max ( Ri ) – Min ( Ri ) ]
10
14. TC R = ---------------------------------------------------------------- × ----------------- for i = 32 to 255, T = -40°C to 85°C. Max( ) is the maximum value of the resistance and Min ( ) is the
[ Max ( Ri ) + Min ( Ri ) ] ⁄ 2 125°C minimum value of the resistance over the temperature range.
15. This parameter is not 100% tested.
Typical Performance Curves
1.8
160
VCC=2.7, T=-40°C
120
100
80
60
40
1.4
1.2
-40°C
1
0.8
+85°C
0.6
0.4
20
0
1.6
VCC=2.7, T=+25°C
STANDBY ICC (µA)
WIPER RESISTANCE (Ω)
140
VCC=2.7, T=+85°C
VCC=5.5, T=-40°C
0
50
VCC= 5.5, T=+85°C
VCC=5.5, T=+25°C
100
150
200
TAP POSITION (DECIMAL)
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[I(RW) = VCC / RTOTAL] FOR 50kΩ (U)
6
250
0.2
0
2.7
+25°C
3.2
3.7
4.2
4.7
5.2
VCC (V)
FIGURE 2. STANDBY ICC vs VCC
FN8086.0
July 27, 2005
ISL90840
Typical Performance Curves
0.2
0.3
VCC=5.5, T=-40°C
0.15
(Continued)
VCC=2.7, T=-40°C
VCC=2.7, T=-40°C
VCC=2.7, T=+25°C
VCC=5.5, T=-40°C
0.2
VCC=5.5, T=+85°C
0.1
0.1
INL (LSB)
DNL (LSB)
0.05
0
-0.05
VCC=2.7, T=+25°C
-0.1
-0.1
VCC=5.5, T=+25°C
-0.15
-0.2
0
0
50
-0.2
VCC=5.5, T=+85°C
VCC=2.7, T=+85°C
100
150
200
VCC=2.7, T=+85°C
0.3
250
0
50
0.4
0
0.35
-0.2
0.3
2.7V
0.25
0.15
-40
0
20
-0.6
VCC=2.7V
-0.8
40
60
-1
-40
80
-20
20
0
40
60
80
TEMPERATURE (°C)
FIGURE 5. ZSerror vs TEMPERATURE FOR 50kΩ (W)
FIGURE 6. FSerror vs TEMPERATURE FOR 50kΩ (W)
0.5
0.3
VCC=2.7, T=+25°C
VCC=2.7, T=+25°C
VCC=5.5, T=+25°C
0.3
VCC=5.5, T=-40°C
0.1
INL (LSB)
DNL (LSB)
250
VCC=5.5V
TEMPERATURE (°C)
0.2
200
-0.4
5.5V
-20
150
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10kΩ (W)
FSerror (LSB)
ZSerror (LSB)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10kΩ (W)
0.2
100
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
0
VCC=5.5, T=+85°C
0.1
VCC=2.7, T=+85°C
-0.1
-0.1
VCC=5.5, T=+85°C
-0.2
-0.3
32
VCC=2.7, T=-40°C
VCC=2.7, T=+85°C
VCC=5.5, T=-40°C
82
132
182
232
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR
50kΩ (U)
7
-0.3
-0.5
32
VCC=2.7,
T=-40°C
VCC=5.5, T=+25°C
82
132
182
232
TAP POSITION (DECIMAL)
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR
50kΩ (U)
FN8086.0
July 27, 2005
ISL90840
Typical Performance Curves
(Continued)
20
1
0.5
2.7V
0
5.5V
10
TC (ppm/°C)
END TO END RTOTAL CHANGE (%)
1.5
-0.5
0
-10
-1
-1.5
-40
-20
20
0
40
60
80
TEMPERATURE (°C)
-20
32
82
132
182
232
TAP POSITION (DECIMAL)
FIGURE 9. END TO END RTOTAL % CHANGE vs
TEMPERATURE FOR 50kΩ (W)
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm FOR
50kΩ (W)
35
TC (ppm/°C)
25
INPUT
15
5
OUTPUT
-5
-15
-25
32
82
132
182
232
TAP POSITION = MID POINT
RTOTAL=9.4K
TAP POSITION (DECIMAL)
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm FOR 50kΩ (W)
SIGNAL AT WIPER (WIPER UNLOADED)
FIGURE 12. FREQUENCY RESPONSE (2.2MHz)
SCL
SIGNAL AT WIPER
(WIPER UPLOADED
MOVEMENT FROM
ffh TO 00h
WIPER MOVEMENT MID POINT
FROM 80h TO 7fh
FIGURE 13. MIDSCALE GLITCH, CODE 80h TO 7Fh (WIPER 0)
8
FIGURE 14. LARGE SIGNAL SETTLING TIME
FN8086.0
July 27, 2005
ISL90840
Principles of Operation
The ISL90840 is an integrated circuit incorporating four
DCPs with their associated registers, and an I2C serial
interface providing direct communication between a host
and the potentiometers.
DCP Description
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL90840 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 15). A START condition is ignored during the powerup of the device.
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of each DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WR). Each DCP has its own WR.
When the WR of a DCP contains all zeroes (WR<7:0>: 00h),
its wiper terminal (RW) is closest to its “Low” terminal (RL).
When the WR of a DCP contains all ones (WR<7:0>: FFh),
its wiper terminal (RW) is closest to its “High” terminal (RH).
As the value of the WR increases from all zeroes (00h) to all
ones (255 decimal), the wiper moves monotonically from the
position closest to RL to the closest to RH. At the same time,
the resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 15). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.
While the ISL90840 is being powered up, all four WRs are
reset to 80h (128 decimal), which locates RW roughly at the
center between RL and RH.
A valid Identification Byte contains 0101 as the four MSBs,
and the following three bits matching the logic values
present at pins A2, A1, and A0. The LSB is the Read/Write
bit. Its value is “1” for a Read operation, and “0” for a Write
operation (See Table 1).
The WRs can be read or written to directly using the I2C
serial interface as described in the following sections. The
I2C interface Address Byte has to be set to 00h, 01h, 02h,
and 03h to access the WR of DCP0, DCP1, DCP2, and
DCP3 respectively
I2C Serial Interface
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 16).
The ISL90840 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL90840 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
TABLE 1. IDENTIFICATION BYTE FORMAT
Logic values at pins A2, A1, and A0 respectively
0
The ISL90840 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL90840
operates as a slave device in all applications.
(MSB)
1
0
1
A2
A1
A0
R/W
(LSB)
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 15). On power-up of the ISL90840 the SDA pin is in
the input mode.
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ISL90840
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
S
T
A
R
T
IDENTIFICATION
BYTE
ADDRESS
BYTE
0 1 0 1 A2 A1 A0 0
0 0 0 0 0 0
SIGNALS FROM
THE ISL90840
S
T
O
P
DATA
BYTE
A
C
K
A
C
K
A
C
K
FIGURE 17. BYTE WRITE SEQUENCE
SIGNALS
FROM THE
MASTER
S
T
A
R
T
SIGNAL AT SDA
IDENTIFICATION
BYTE WITH
R/W=0
ADDRESS
BYTE
0 1 0 1 A2 A1 A0 0
A
C
K
S
T
O
P
A
C
K
0 1 0 1 A2 A1 A0 1
0 0 0 0 0 0
A
C
K
SIGNALS FROM
THE SLAVE
S
T
A IDENTIFICATION
R
BYTE WITH
T
R/W=1
A
C
K
A
C
K
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 18. READ SEQUENCE
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ISL90840
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL90840 responds with an ACK. At this time, the device
enters its standby state (See Figure 17).
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 18). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL90840 responds with an ACK. Then the ISL90840
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the read operation (issuing a
STOP condition) following the last bit of the last Data Byte
(See Figure 18).
The Data Bytes are from the registers indicated by an
internal pointer. This pointer initial value is determined by the
Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 03h, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
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Packaging Information
20-Lead Plastic, TSSOP, Package Code V20
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.252 (6.4)
.260 (6.6)
.041 (1.05)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: All dimensions in inches (in parentheses in millimeters).
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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