ISL90727, ISL90728 ® Single Volatile 128-Tap XDCP Data Sheet August 2, 2006 Digitally Controlled Potentiometer (XDCP™) Features The Intersil ISL90727 and ISL90728 are digitally controlled potentiometers (XDCP). Each device consists of a resistor array, wiper switches, and a control section. The wiper position is controlled by an I2C interface. • I2C Serial Bus Interface FN8247.4 • Volatile Solid-State Potentiometer The potentiometer is implemented by a resistor array composed of 127 resistive elements and a wiper switching network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the SDA and SCL inputs. • DCP Terminal Voltage, 2.7V to 5.5V • Low Tempco - Rheostat - 45 ppm/°C typical - Divider - 15 ppm/°C typical • 128 Wiper Tap Points - Wiper resistance 70Ω typ at VCC = 3.3V • Low Power CMOS - Active current, 200µA max - Standby current, 500nA max The device can be used in a wide variety of applications including: • Mechanical potentiometer replacement • Available RTOTAL Values = 50kΩ, 10kΩ • Transducer adjustment of pressure, temperature, position, chemical, and optical sensors • Power on Preset to Midscale • Direct Replacement for AD5247 • RF amplifier biasing • Packaging - 6 Ld SC-70 • LCD brightness and contrast adjustment • Gain control and offset adjustment • Pb-Free Plus Anneal Available (RoHS Compliant) Pinout ISL90727, ISL90728 (6 LD SC-70) TOP VIEW VDD 1 6 RH GND 2 5 RW SCL 3 4 SDA Ordering Information PART NUMBER (See Notes 1, 2) PART MARKING RTOTAL (kΩ) TEMP RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL90727WIE627Z-TK ANH 10 -40 to +85 6 Ld SC-70 P6.049 ISL90727UIE627Z-TK ANI 50 -40 to +85 6 Ld SC-70 P6.049 ISL90728WIE627Z-TK CCF 10 -40 to +85 6 Ld SC-70 P6.049 NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 2. ISL90727 has an I2C address 5Ch and ISL90728 has an I2C address 7Ch 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL90727, ISL90728 Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1 VDD Supply Voltage 2 GND Ground 3 SCL Open drain Serial Clock input 4 SDA Open drain Serial Data I/O 5 RW Potentiometer Wiper Terminal 6 RH Potentiometer High Terminal Block Diagram VDD SCL SDA RH I2C INTERFACE RW WIPER REGISTER RL GND 2 FN8247.4 August 2, 2006 ISL90727, ISL90728 Absolute Maximum Ratings Recommended Operating Conditions Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage at any Digital Interface Pin with Respect to VSS . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V Voltage at any DCP Pin with Respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level B at 85°C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2kV Human Body Model Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Power Rating of Each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Analog Specifications SYMBOL RTOTAL Over recommended operating conditions unless otherwise stated. PARAMETER RH to RL Resistance TEST CONDITIONS MIN CH/CL/CW ILkgDCP Wiper Resistance UNIT 10 kΩ U option 50 kΩ -20 VCC = 3.3V @ 25°C 85 Potentiometer Capacitance Leakage on DCP Pins MAX W option RH to RL Resistance Tolerance RW TYP (Note 3) Voltage at pin from GND to VCC +20 % 200 Ω 10/10/ 25 pF 0.1 µA VOLTAGE DIVIDER MODE INL Integral Non-linearity DNL Differential Non-linearity ZSerror (Note 5) Zero-scale Error FSerror (Note 6) Full-scale Error TCV (Note 12) Ratiometric Temperature Coefficient -1 ±0.2 1 LSB (Note 4) W option -1 ±0.1 1 LSB (Note 4) U option -1 ±0.1 1 LSB (Note 4) W option 0 1 3 U option 0 0.5 1 LSB (Note 4) W option -3 -1 0 U option -1 -0.5 0 Monotonic over all tap positions DCP Register set to 80 hex ±15 LSB (Note 4) ppm/°C RESISTOR MODE RINL (Note 10) Integral Non-linearity DCP register set between 20 hex and FF hex. Monotonic over all tap positions RDNL (Note 9) Differential Non-linearity DCP register set between 20 hex and FF hex. Monotonic over all tap positions Roffset (Note 8) Offset TCR Resistance Temperature Coefficient (Notes 11, 12) 3 -2 ±0.25 2 MI (Note 7) W option -1 ±0.1 1 MI (Note 7) U option -1 ±0.1 1 MI (Note 7) W option 0 1 3 MI (Note 7) U option 0 0.5 1 MI (Note 7) DCP register set between 20 hex and FF hex ±45 ppm/°C FN8247.4 August 2, 2006 ISL90727, ISL90728 Operating Specifications SYMBOL ICC1 ISB IComLkg PARAMETER TEST CONDITIONS MIN TYP (Note 3) MAX UNIT VCC Supply Current (Volatile write/read) fSCL = 400kHz; SDA = Open; (for I2C, Active, Read and Volatile Write States only) 200 µA VCC Current (standby) VCC = +5.5V, I2C Interface in Standby State 500 nA Common-Mode Leakage Voltage at SDA pin to GND or VCC 3 µA tDCP (Note 12) DCP Wiper Response Time VCCRamp VCC Ramp Rate tD Power-up Delay SCL falling edge of last bit of DCP Data Byte to wiper change 500 ns 0.2 VCC above Vpor, to DCP Initial Value Register recall completed, and I2C Interface in standby state V/ms 3 ms SERIAL INTERFACE SPECIFICATIONS VIL SDA, and SCL Input Buffer LOW Voltage -0.3 0.3* VCC V VIH SDA, and SCL Input Buffer HIGH Voltage 0.7* VCC VCC+ 0.3 V SDA and SCL Input Buffer Hysteresis 0.05* VCC Hysteresis VOL SDA Output Buffer LOW Voltage, Sinking 4mA 0 Cpin (Note 14) SDA, and SCL Pin Capacitance fSCL SCL Frequency tIN Pulse Width Suppression Time at SDA and SCL Inputs tAA SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of VCC, until SDA Valid exits the 30% to 70% of VCC window. Any pulse narrower than the max spec is suppressed. V 0.4 V 10 pF 400 kHz 50 ns 900 ns tBUF Time the Bus Must be Free Before the SDA crossing 70% of VCC during a STOP Start of a New Transmission condition, to SDA crossing 70% of VCC during the following START condition. 1300 ns tLOW Clock LOW Time Measured at the 30% of VCC crossing. 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VCC crossing. 600 ns tSU:STA START Condition Setup Time SCL rising edge to SDA falling edge. Both crossing 70% of VCC. 600 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC. 600 ns tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC 100 ns tHD:DAT Input Data Hold Time From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window. 0 ns tSU:STO STOP Condition Setup Time From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC. 600 ns tHD:STO STOP Condition Hold Time for Read, or Volatile Only Write From SDA rising edge to SCL falling edge. Both crossing 70% of VCC. 600 ns Output Data Hold Time From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window. 0 ns SDA and SCL Rise Time From 30% to 70% of VCC tDH tR (Note 14) 4 20 + 0.1 * Cb 250 ns FN8247.4 August 2, 2006 ISL90727, ISL90728 Operating Specifications SYMBOL (Continued) PARAMETER TEST CONDITIONS MIN TYP (Note 3) MAX UNIT tF (Note 14) SDA and SCL Fall Time From 70% to 30% of VCC 20 + 0.1 * Cb 250 ns Cb (Note 14) Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF Maximum is determined by tR and tF. For Cb = 400pF, max is about 2~2.5kΩ. For Cb = 40pF, max is about 15~20kΩ 1 Rpu (Note 14) SDA and SCL Bus Pull-up Resistor Off-chip kΩ SDA vs SCL Timing tHIGH tF SCL tLOW tR tSU:DAT tSU:STA tHD:DAT tSU:STO tHD:STA SDA (INPUT TIMING) tAA tDH tBUF SDA (OUTPUT TIMING) NOTES: 3. Typical values are for TA = 25°C and 3.3V supply voltage. 4. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 5. ZS error = V(RW)0/LSB. 6. FS error = [V(RW)127 – VCC]/LSB. 7. MI = |R127 – R0|/127. R127 and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. Roffset = R0/MI, when measuring between RW and RL. 8. Roffset = R127/MI, when measuring between RW and RH. 9. RDNL = (Ri – Ri-1)/MI - 1, for i = 32 to 127. 10. RINL = [Ri – (MI • i) – R0]/MI, for i = 32 to 127. 6 [ Max ( Ri ) – Min ( Ri ) ] 10 11. TC R = ---------------------------------------------------------------- × ----------------- for i = 32 to 127, T = -40°C to 85°C. Max( ) is the maximum value of the resistance and Min ( ) is the [ Max ( Ri ) + Min ( Ri ) ] ⁄ 2 125°C minimum value of the resistance over the temperature range. 12. This parameter is not 100% tested. 13. VIL = 0V, VIH = VCC. 14. These are I2C-specific parameters and are not directly tested. However, they are used in the device testing to validate specifications. Principles of Operation The ISL90727 and ISL90728 are integrated circuits incorporating one DCP with its associated registers and an I2C serial interface providing direct communication between a host and the potentiometer. DCP Description The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of the DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by a 7-bit volatile Wiper Register (WR). The DCP has its own WR. When the WR of the DCP contains all zeroes (WR<6:0> = 00h), its wiper 5 terminal (RW) is closest to its “Low” terminal (RL). When the WR of the DCP contains all ones (WR<6:0> = 7Fh), its wiper terminal (RW) is closest to its “High” terminal (RH). As the value of the WR increases from all zeroes (00h) to all ones (127 decimal), the wiper moves monotonically from the position closest to RL to the position closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. RL is connected to the GND pin of the device, so the wiper movement will always be relative to RL. While the ISL90727 and ISL90728 are being powered up, the WR is reset to 40h (64 decimal), which locates RW roughly at the center between RL and RH. FN8247.4 August 2, 2006 ISL90727, ISL90728 The WR and IVR can be read or written directly using the I2C serial interface as described in the following sections. I2C Serial Interface The ISL90727 and ISL90728 support bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL90727 and ISL90728 operate as slave devices in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first. Protocol Conventions Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 1). On power-up of the ISL90727 and ISL90728, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL90727 and ISL90728 continuously monitor the SDA and SCL lines for the START condition and do not respond to any command until this condition is met (See Figure 1). A START condition is ignored during the power-up sequence and during internal non-volatile write cycles. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (See Figure 1). An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 2). . TABLE 1. IDENTIFICATION BYTE FORMAT ISL90727 0 1 0 1 1 1 0 R/W ISL90728 0 1 1 1 1 1 0 R/W MSB LSB Write Operation A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL90727 and ISL90728 respond with an ACK. At this time, the device enters its standby state (See Figure 3). Data Protection A valid Identification Byte, Address Byte, and total number of SCL pulses act as a protection of both volatile and non-volatile registers. During a Write sequence, the Data Byte is loaded into an internal shift register as it is received. If the Address Byte is 0, the Data Byte is transferred to the Wiper Register (WR) at the falling edge of the SCL pulse that loads the last bit (LSB) of the Data Byte. If an address other than 00h or an invalid slave address is sent, then the device will respond with no ACK. Read Operation A Read operation consist of a three byte instruction followed by one or more Data Bytes (See Figure 4). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL90727 and ISL90728 respond with an ACK. Then the ISL90727 and ISL90728 transmit the Data Byte as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master then terminates the read operation (issuing a STOP condition) following the last bit of the Data Byte (See Figure 4). The ISL90727 and ISL90728 respond with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL90727 and ISL90728 also respond with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. A valid Identification Byte contains 0101110 as the seven MSBs for the ISL90727 and 0111110 as the seven MSBs for the ISL90728. The LSB in the Read/Write bit. Its value is “1” for a Read operation, and “0” for a Write operation (See Table 1) 6 FN8247.4 August 2, 2006 ISL90727, ISL90728 SCL SDA START DATA STABLE DATA CHANGE DATA STABLE STOP FIGURE 1. VALID DATA CHANGES, START AND STOP CONDITIONS SCL FROM MASTER 1 8 9 SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START ACK FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER WRITE SIGNALS FROM THE MASTER SIGNAL AT SDA S T A R T IDENTIFICATION BYTE ADDRESS BYTE 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 SIGNALS FROM THE ISL23711 A C K A C K A C K S T O P DATA BYTE FIGURE 3. BYTE WRITE SEQUENCE (ISL90727 VERSION SHOWN) S T A R T SIGNALS FROM THE MASTER SIGNAL AT SDA SIGNALS FROM THE SLAVE IDENTIFICATION BYTE WITH R/W=0 S T A IDENTIFICATION R BYTE WITH T R/W=1 ADDRESS BYTE 0 1 0 1 1 1 0 0 0 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 A C K S T O P A C K A C K DATA BYTE FIGURE 4. READ SEQUENCE (ISL90727 VERSION SHOWN) 7 FN8247.4 August 2, 2006 ISL90727, ISL90728 Small Outline Transistor Plastic Packages (SC70-6) 0.20 (0.008) M P6.049 VIEW C C 6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE CL INCHES e b SYMBOL 6 5 4 CL CL E1 E 1 2 3 e1 C D CL A A2 SEATING PLANE A1 -C- WITH b PLATING b1 c c1 MILLIMETERS MAX MIN MAX NOTES A 0.031 0.043 0.80 1.10 - A1 0.000 0.004 0.00 0.10 - A2 0.031 0.039 0.00 1.00 - b 0.006 0.012 0.15 0.30 - b1 0.006 0.010 0.15 0.25 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.009 0.08 0.20 6 D 0.073 0.085 1.85 2.15 3 E 0.071 0.094 1.80 2.40 - E1 0.045 0.053 1.15 1.35 3 e 0.0256 Ref 0.65 Ref - e1 0.0512 Ref 1.30 Ref - L 0.10 (0.004) C MIN 0.010 0.018 0.26 0.46 L1 0.017 Ref. 0.420 Ref. L2 0.006 BSC 0.15 BSC N 6 6 4 5 R 0.004 - 0.10 - R1 0.004 0.010 0.15 0.25 α 0o 8o 0o 8o Rev. 2 9/03 NOTES: BASE METAL 1. Dimensioning and tolerance per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO203AB. 4X θ1 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. 5. “N” is the number of terminal positions. R GAUGE PLANE SEATING PLANE L C L1 α L2 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only 4X θ1 VIEW C All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 FN8247.4 August 2, 2006