MCP6421/2/4 4.4 µA/Amplifier, 90 kHz Op Amp Features: Description: • Low Quiescent Current: - 4.4 µA/amplifier (typical) • Low Input Offset Voltage: - ±1.0 mV (maximum) • Enhanced EMI Protection: - Electromagnetic Interference Rejection Ratio (EMIRR) at 1.8 GHz: 97 dB • Supply Voltage Range: 1.8V to 5.5V • Gain Bandwidth Product: 90 kHz (typical) • Rail-to-Rail Input/Output • Slew Rate: 0.05 V/µs (typical) • Unity Gain Stable • No Phase Reversal • Small Packages: - Singles in SC70-5, SOT-23-5 - Dual in MSOP-8, SOIC-8 - Quad in SOIC-14, TSSOP-14 The Microchip Technology Inc. MCP6421/2/4 family of operational amplifiers operate with a single supply voltage as low as 1.8V, while drawing low quiescent current per amplifier (5.5 µA, maximum). This family also has low-input offset voltage (±1.0 mV, maximum) and rail-to-rail input and output operation. In addition, the MCP6421/2/4 family is unity gain stable and has a gain bandwidth product of 90 kHz (typical). This combination of features supports battery-powered and portable applications. The MCP6421/2/4 family has enhanced EMI protection to minimize any electromagnetic interference from external sources. This feature makes it well suited for EMI sensitive applications such as power lines, radio stations, and mobile communications, etc. The MCP6421/2/4 family is offered in single (MCP6421), dual (MCP6422) and quad (MCP6424) packages. All devices are designed using an advanced CMOS process and fully specified in extended temperature range from -40°C to +125°C. • Extended Temperature Range: - -40°C to +125°C Typical Application VDD R+¨R R-¨R Applications: • • • • • • Portable Medical Instruments Safety Monitoring Battery-Powered Systems Remote Sensing Supply Current Sensing Analog Active Filters - Va Vb VDD - R-¨R R+¨R + R3 MCP6421 100k R1 1k + Design Aids: • • • • • VDD VDD VOUT - + R2 1k MCP6421 MCP6421 R5 100k 100k VOUT = Va – V b ---------------1k Strain Gauge SPICE Macro Models FilterLab® Software Microchip Advanced Part Selector (MAPS) Analog Demonstration and Evaluation Boards Application Notes Package Types MCP6421 SC70-5, SOT-23-5 VOUT 1 5 VDD VSS 2 VIN+ 3 4 VIN– 2013 Microchip Technology Inc. MCP6424 SOIC, TSSOP MCP6422 MSOP, SOIC VOUTA 1 VINA– 2 VINA+ 3 VSS 4 8 7 6 5 VDD VOUTB VINB– VINB+ 1 2 3 4 VINB+ 5 VINB– 6 VOUTB 7 VOUTA VINA– VINA+ VDD 14 13 12 11 10 9 8 VOUTD VIND– VIND+ VSS VINC+ VINC– VOUTC DS20005165B-page 1 MCP6421/2/4 NOTES: DS20005165B-page 2 2013 Microchip Technology Inc. MCP6421/2/4 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † VDD – VSS ..................................................................................................................................................................6.5V Current at Analog Input Pins (VIN+, VIN-)................................................................................................................±2 mA Analog Inputs (VIN+, VIN-)††.....................................................................................................VSS – 1.0V to VDD + 1.0V All Other Inputs and Outputs ....................................................................................................VSS – 0.3V to VDD + 0.3V Difference Input Voltage .................................................................................................................................|VDD – VSS| Output Short-Circuit Current .......................................................................................................................... Continuous Current at Input Pins ...............................................................................................................................................±2 mA Current at Output and Supply Pins ...................................................................................................................... ±30 mA Storage Temperature ..............................................................................................................................-65°C to +150°C Maximum Junction Temperature (TJ) .................................................................................................................... +150°C ESD Protection on All Pins (HBM; MM) 4 kV; 400V ESD Protection on All Pins (HBM; MM) (Dual and Quad) 4 kV; 300V † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. †† See Section 4.1.2 “Input Voltage Limits”. 1.2 Specifications TABLE 1-1: DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS= GND, VCM = VDD/2, VOUT = VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 30 pF (refer to Figure 1-1). Parameters Sym. Min. Typ. Max. Units Conditions VOS -1.0 — 1.0 mV VDD = 3.0V; VCM = VDD/4 Input Offset Drift with Temperature VOS/TA — ±3.0 — µV/°C Power Supply Rejection Ratio PSRR 75 90 — dB IB — ±1 50 pA Input Offset Input Offset Voltage TA= -40°C to +125°C, VCM = VSS VCM = VSS Input Bias Current and Impedance Input Bias Current — 20 — pA TA = +85°C — 800 — pA TA = +125°C Input Offset Current IOS — ±1 — pA Common Mode Input Impedance ZCM — 1013||12 — ||pF Differential Input Impedance ZDIFF — 1013||12 — |pF Common Mode Input Voltage Range VCMR VSS – 0.3 — VDD + 0.3 V Common Mode Rejection Ratio CMRR 75 90 — dB VDD = 5.5V VCM = -0.3V to 5.8V 70 85 — dB VDD = 1.8V VCM = -0.3V to 2.1V Common Mode 2013 Microchip Technology Inc. DS20005165B-page 3 MCP6421/2/4 TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS= GND, VCM = VDD/2, VOUT = VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 30 pF (refer to Figure 1-1). Parameters Sym. Min. Typ. Max. Units Conditions AOL 95 115 — dB 0.3 < VOUT < (VDD –0.3V) VCM= VSS VDD = 5.5V Open-Loop Gain DC Open-Loop Gain (Large Signal) Output High-Level Output Voltage Low-Level Output Voltage Output Short-Circuit Current VOH VDD – 4 VDD – 1 — mV VDD = 1.8V VDD – 5 VDD – 1 — mV VDD = 5.5V — VSS + 1 VSS + 4 mV VDD = 1.8V — VSS + 1 VSS + 5 mV VDD = 5.5V — ±6 — mA VDD = 1.8V — ±22 — mA VDD = 5.5V VDD 1.8 — 5.5 V IQ 3 4.4 5.5 µA VOL ISC Power Supply Supply Voltage Quiescent Current per Amplifier TABLE 1-2: IO = 0, VCM = VDD/4 AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS= GND, VCM = VDD/2, VOUT = VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 30 pF (refer to Figure 1-1). Parameters Sym. Min. Typ. Max. Units Conditions AC Response Gain Bandwidth Product GBWP — 90 — kHz Phase Margin PM — 55 — ° Slew Rate SR — 0.05 — V/µs G = +1 V/V Noise Input Noise Voltage Eni — 15 — µVP-P Input Noise Voltage Density eni — 95 — nV/Hz — 90 — nV/Hz f = 10 kHz Input Noise Current Density ini — 0.6 — fA/Hz f = 1 kHz Electromagnetic Interference Rejection Ratio EMIRR — 77 — dB — 92 — VIN = 100 mVPK, 900 MHz — 97 — VIN = 100 mVPK, 1800 MHz — 99 — VIN = 100 mVPK, 2400 MHz DS20005165B-page 4 f = 0.1 Hz to 10 Hz f = 1 kHz VIN = 100 mVPK, 400 MHz 2013 Microchip Technology Inc. MCP6421/2/4 TABLE 1-3: TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND. Parameters Sym. Min. Typ. Max. Units Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Conditions Temperature Ranges Note 1 Thermal Package Resistances Thermal Resistance, 5L-SC70 JA — 331 — °C/W Thermal Resistance, 5L-SOT-23 JA — 221 — °C/W Thermal Resistance, 8L-MSOP JA — 211 — °C/W Thermal Resistance, 8L-SOIC JA — 150 — °C/W Thermal Resistance, 14L-SOIC JA — 95 — °C/W Thermal Resistance, 14L-TSSOP JA — 100 — °C/W Note 1: 1.3 The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C. Test Circuits The circuit used for most DC and AC tests is shown in Figure 1-1. This circuit can independently set VCM and VOUT (see Equation 1-1). Note that VCM is not the circuit’s Common mode voltage ((VP + VM)/2), and that VOST includes VOS plus the effects (on the input offset error, VOST) of the temperature, CMRR, PSRR and AOL. EQUATION 1-1: CF 6.8 pF RG 100 k VP VDD VIN+ CB1 100 nF MCP6421 G DM = RF RG VDD/2 CB2 1 µF VIN– V CM = V P + V DD 2 2 VM V OST = VIN– – VIN+ V OUT = V DD 2 + V P – V M + VOST 1 + G DM Where: GDM = Differential Mode Gain (V/V) VCM = Op Amp’s Common Mode Input Voltage (V) VOST = Op Amp’s Total Input Offset Voltage (mV) 2013 Microchip Technology Inc. RF 100 k RG 100 k RL 100 k RF 100 k CF 6.8 pF VOUT CL 30 pF VL FIGURE 1-1: AC and DC Test Circuit for Most Specifications. DS20005165B-page 5 MCP6421/2/4 NOTES: DS20005165B-page 6 2013 Microchip Technology Inc. MCP6421/2/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 1000 800 600 400 0 200 -200 -400 -600 -800 1253Samples VDD = 3.0V VCM = VDD/4 -1000 entage of Occurences Perce 48% 44% 40% 36% 32% 28% 24% 20% 16% 12% 8% 4% 0% Inputt Offset Voltage (μV) Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS= GND, VCM = VDD/2, VOUT = VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 30 pF. Input Offset Voltage (μV) FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage. 8% 6% 4% 2% 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 Inputt Offset Voltage (μV) Percentage of Occurances 10% 346 Samples VDD = 3.0V VCM = VDD/4 TA = -40°C to +125°C 1000 TA = +125°C 800 TA = +85°C 600 TA = +25°C TA = -40°C 400 200 0 -200 -400 VDD = 5 5.5V 5V -600 Representative Part -800 -1000 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Common Mode Input Voltage (V) 0% 1000 800 TA = +125°C 600 TA = +85°C T A = +25°C 400 TA = -40°C 200 0 -200 -400 -600 VDD = 1.8V -800 Representative Part -1000 -0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 Common Mode Input Voltage (V) FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage. 2013 Microchip Technology Inc. VDD = 1.8V 0.5 1 FIGURE 2-5: Output Voltage. 1.5 2 2.5 3 3.5 4 Output Voltage (V) 4.5 5 5.5 Input Offset Voltage vs. 1000 Input O Offset Voltage (μV) Inputt Offset Voltage (μV) Input Offset Voltage Drift. VDD = 5.5V 0 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 Input Offset Voltage Drift (μV/°C) FIGURE 2-2: Representative Part 800 Representative Part 600 400 200 0 -200 -400 -600 -800 TA = +125°C 125 C TA = +85°C TA = +25°C TA = -40°C -1000 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 Power Supply Voltage (V) FIGURE 2-6: Input Offset Voltage vs. Power Supply Voltage. DS20005165B-page 7 MCP6421/2/4 90 140 80 130 70 120 CM MRR, PSRR (dB) 60 50 40 30 20 10 90 80 CMRR @ VDD = 5.5V @ VDD = 1.8V 60 FIGURE 2-7: Input Noise Voltage Density vs. Common Mode Input Voltage. 10,000 50 -50 -25 0 25 50 75 100 Ambient Temperature (°C) FIGURE 2-10: Temperature. 1000 1n Input Bias and Offset Currents (A) 125 CMRR, PSRR vs. Ambient VDD = 5.5V 100 100p 1,000 100 1p 1 0.1p 0.1 Input Offset Current FIGURE 2-8: vs. Frequency. 1.E+5 100k Ambient Temperature (°C) Input Noise Voltage Density Representative Part 70 PSRR- 50 PSRR+ 40 30 20 10 10 100 100 FIGURE 2-9: Frequency. DS20005165B-page 8 1000 1k Frequency (Hz) TA = +125°C Input B Bias Current (pA) CMRR 80 60 FIGURE 2-11: Input Bias, Offset Current vs. Ambient Temperature. 1000 900 800 700 600 500 400 300 200 100 0 -100 100 10000 10k CMRR, PSRR vs. 100000 100k 125 10k 115 1.E+4 105 1.E+2 1.E+3 10 100 1k Frequency (Hz) 95 1.E+1 85 1 75 1.E+0 65 0.1 25 1.E-1 55 0.01p 0.01 10 90 Input Bias Current 10p 10 45 Input No oise Voltage Density (nV/¥Hz) 110 100 70 f = 10 kHz VDD = 5.5 V 0 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Common Mode Input Voltage (V) CMR RR, PSRR (dB) PSRR 35 Input No oise Voltage Density (nV/¥Hz) Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS= GND, VCM = VDD/2, VOUT = VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 30 pF. TA = +85°C TA = +25°C VDD = 5.5 V 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Input Voltage (V) 5.5 FIGURE 2-12: Input Bias Current vs. Common Mode Input Voltage. 2013 Microchip Technology Inc. MCP6421/2/4 Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS= GND, VCM = VDD/2, VOUT = VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 30 pF. 6 VDD = 5.5V VDD = 1.8V 5 Ou uiescent Current (μA/Amplifier) Quiescent Current (μA/Amplifier) 6 4 3 2 5 4 3 2 1 1 0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) 0 -50 -25 0 25 50 75 100 Ambient Temperature (°C) 125 FIGURE 2-13: Quiescent Current vs. Ambient Temperature. VDD = 5.5V G = +1 V/V FIGURE 2-16: Quiescent Current vs. Common Mode Input Voltage. 6 120 0 4 3 TA = +125°C TA = +85°C TA = +25°C 25°C TA = -40°C 2 1 0 -60 Open-Loop Phase 60 -90 40 -120 20 -150 0 -180 1.0E+00 1 1.0E+01 1.0E+02 1.0E+03 10 100 1k Frequency (Hz) 1.0E+04 10k -210 1.0E+05 100k Open-Loop Gain, Phase vs. 140 DC Open-Loop Gain (dB) Ou uiescent Current (μA/Amplifier) 80 FIGURE 2-17: Frequency. 6 5 4 3 2 1 -30 -201.0E-02 1.0E-01 0.01 0.1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Power Supply Voltage (V) FIGURE 2-14: Quiescent Current vs. Power Supply Voltage. 100 Open n-Loop Phase (°) 5 Open n-Loop Gain (dB) Quiescent Q Current (μA/Amplifier) Open-Loop Gain VDD = 1.8V G = +1 V/V 0 -0.5 -0.2 0.1 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 Common Mode Input Voltage (V) FIGURE 2-15: Quiescent Current vs. Common Mode Input Voltage. 2013 Microchip Technology Inc. VDD = 5.5V 130 120 VDD = 1.8V 110 100 90 80 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) FIGURE 2-18: DC Open-Loop Gain vs. Ambient Temperature. DS20005165B-page 9 MCP6421/2/4 Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS= GND, VCM = VDD/2, VOUT = VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 30 pF. Output Short Circuit Current (mA) DC--Open Loop Gain (dB) 150 140 130 120 110 100 VDD = 5.5V VDD = 1.8V 90 80 70 0.00 0.05 0.10 0.15 0.20 0.25 0.30 40 20 10 0 -10 -30 -40 0 FIGURE 2-19: DC Open-Loop Gain vs. Output Voltage Headroom. 180 120 Gain Bandwidth Product 100 80 60.0 60 50.0 VDD = 5.5V 12V 40 Phase Margin 20 30.0 0 180 140 80.0 120 70.0 Gain Bandwidth Product 100 80 60.0 60 50.0 Phase Margin 40.0 VDD = 1.8V 30.0 Phase Margin (°) 160 90.0 40 20 0 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) FIGURE 2-21: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. DS20005165B-page 10 5 5.5 VDD = 1.8V 1 1000 10000 10k Frequency (Hz) 1k FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. 100.0 1.5 2 2.5 3 3.5 4 4.5 Power Supply Voltage (V) VDD = 5.5V 0.1 -25 0 25 50 75 100 125 Ambient Temperature (°C) FIGURE 2-23: Frequency. Output Voltage V Headroom (mV) -50 Gain B Bandwidth Product (MHz) Outputt Voltage Swing (VP-P) 140 80.0 1 10 160 90.0 0.5 FIGURE 2-22: Output Short Circuit Current vs. Power Supply Voltage. Ph hase Margin (°) Gain B Bandwidth Product (MHz) 100.0 40.0 Isc-@ TA = +125°C TA = +85°C 85°C TA = +25°C TA = -40°C 20 -20 Output Voltage Headroom (V) VDD - VOH or VOL - VSS 70.0 Isc+@ TA = +125°C TA = +85°C TA = +25°C TA = -40°C 30 100000 100k Output Voltage Swing vs. 1000 VDD = 1.8V 100 VDD - VOH 10 VOL - VSS 1 0.1 0.001 0.01 0.1 1 10 Output Current (mA) 100 FIGURE 2-24: Output Voltage Headroom vs. Output Current. 2013 Microchip Technology Inc. MCP6421/2/4 1000 0.09 VDD = 5.5V 100 VDD - VOH 10 VOL - VSS 1 0.06 0.05 0.04 0.03 Falling Edge, VDD = 1.8V Rising Ri i Edge, Ed VDD = 1.8V 1 8V 0.02 0.00 0.1 1 10 Output Current (mA) -50 100 -25 0 25 50 75 100 125 Ambient Temperature (°C) FIGURE 2-25: Output Voltage Headroom vs. Output Current. FIGURE 2-28: Temperature. Slew Rate vs. Ambient 0.9 0.8 Outputt Voltage (20 mV/div) Output Voltage V Headroom (mV) 0.07 0.01 0.1 0.01 VDD - VOH 0.7 0.6 0.5 VOL - VSS 0.4 0.3 0.2 0.1 VDD = 1.8V 0 -50 -25 0 25 50 75 Ambient Temperature (°C) 100 VDD = 5.5V 5 5V G = +1 V/V 125 Time (25 μs/div) FIGURE 2-26: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Pulse Response. Small Signal Non-Inverting 1.2 Output Voltage (20 mV/div) Output Voltage V Headroom (mV) Falling Edge, VDD = 5.5V Rising Edge, VDD = 5.5V 0.08 Slew S Rate (V/μs) Output Voltage V Headroom (mV) Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS= GND, VCM = VDD/2, VOUT = VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 30 pF. VOL - VSS 1 0.8 VDD - VOH 0.6 0.4 0.2 VDD = 5.5V VDD = 5.5 V G = -1 V/V 0 -50 -25 0 25 50 75 Ambient Temperature (°C) 100 125 FIGURE 2-27: Output Voltage Headroom vs. Ambient Temperature. 2013 Microchip Technology Inc. Time (25 μs/div) FIGURE 2-30: Response. Small Signal Inverting Pulse DS20005165B-page 11 MCP6421/2/4 10000 Ou utput Voltage (V) 5 Clos sed Loop Output Im mpedance (:) 6 1000 4 3 2 VDD = 5.5 55V G = +1 V/V 100 GN: 101 V/V 11 V/V 1 V/V 10 1 1 0 1.0E+00 1 Time (0.1 ms/div) Large Signal Non-Inverting 6 100μ 5 10μ 4 VDD = 5.5 V G = -1 V/V 3 10 1.0E+02 10n 1.0E+05 100k TA = +125°C TA = +85°C TA = +25°C TA = -40°C 1n -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0 VIN (V) Time (0.1 ms/div) FIGURE 2-32: Response. Large Signal Inverting Pulse FIGURE 2-35: Measured Input Current vs. Input Voltage (below VSS). 6 5 VOUT 4 EMIRR (dB) Input, Output Voltages (V) 10k 1μ 1 VIN 2 1 0 1.0E+04 100n 2 3 1.0E+03 100 1k Frequency (Hz) FIGURE 2-34: Closed Loop Output Impedance vs. Frequency. -IIN (A) Output Voltage (V) O FIGURE 2-31: Pulse Response. 1.0E+01 VDD = 5.5V G = +2V/V 120 110 100 90 80 70 60 50 40 30 20 10 0 VIN = 100 mVPK VDD = 5.5V 100k -1 FIGURE 2-33: The MCP6421/2/4 Device Shows No Phase Reversal. DS20005165B-page 12 1M 10M 100M 1G 10G Frequency (Hz) Time (1 ms/div) FIGURE 2-36: EMIRR vs. Frequency. 2013 Microchip Technology Inc. MCP6421/2/4 Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS= GND, VCM = VDD/2, VOUT = VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 30 pF. 120 EMIRR (dB) 100 80 60 EMIRR @ 2400 MHz EMIRR @ 1800 MHz EMIRR @ 900 MHz EMIRR @ 400 MHz 40 20 0 0.01 0.1 1 RF Input Peak Voltage Voltage (VPK) FIGURE 2-37: to-Peak Voltage. EMIRR vs. RF Input Peak- Channel-to-Channel Separation (dB) 140 130 Input Referred 120 110 100 90 80 70 100.00 100 1000.00 1k 10000.00 100000.00 10k 100k Frequency (Hz) 1000000.00 1M FIGURE 2-38: Channel-to-Channel Separation vs. Frequency. 2013 Microchip Technology Inc. DS20005165B-page 13 MCP6421/2/4 NOTES: DS20005165B-page 14 2013 Microchip Technology Inc. MCP6421/2/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6421 MCP6422 MCP6424 SC70-5, SOT-23-5 MSOP, SOIC SOIC, TSSOP Symbol 1 1 1 VOUT, VOUTA Analog Output (op amp A) 3.1 Description 4 2 2 VIN–, VINA– Inverting Input (op amp A) 3 3 3 VIN+, VINA+ Non-inverting Input (op amp A) 5 8 4 VDD — 5 5 VINB+ Non-inverting Input (op amp B) — 6 6 VINB– Inverting Input (op amp B) — 7 7 VOUTB Analog Output (op amp B) — — 8 VOUTC Analog Output (op amp C) Positive Power Supply — — 9 VINC– Inverting Input (op amp C) — — 10 VINC+ Non-inverting Input (op amp C) Negative Power Supply 2 4 11 VSS — — 12 VIND+ Non-inverting Input (op amp D) — — 13 VIND– Inverting Input (op amp D) — — 14 VOUTD Analog Output (op amp D) Analog Outputs The output pin is a low-impedance voltage source. 3.2 Analog Inputs The non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents. 3.3 Power Supply Pins (VSS, VDD) The positive power supply (VDD) is 1.8V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are at voltages between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors. 2013 Microchip Technology Inc. DS20005165B-page 15 MCP6421/2/4 NOTES: DS20005165B-page 16 2013 Microchip Technology Inc. MCP6421/2/4 4.0 APPLICATION INFORMATION The MCP6421/2/4 op amps are manufactured using Microchip’s state-of-the-art CMOS process. This op amp is unity gain stable and suitable for a wide range of general purpose applications. In some applications, it may be necessary to prevent excessive voltages from reaching the op amp inputs; Figure 4-2 shows one approach to protecting these inputs. VDD 4.1 Rail-to-Rail Input 4.1.1 D1 PHASE REVERSAL The MCP6421/2/4 op amps are designed to prevent phase reversal, when the input pins exceed the supply voltages. Figure 2-33 shows the input voltage exceeding the supply voltage with no phase reversal. 4.1.2 INPUT VOLTAGE LIMITS In order to prevent damage and/or improper operation of the amplifier, the circuit must limit the voltages at the input pins (see Section 1.1, Absolute Maximum Ratings †). The Electrostatic Discharge (ESD) protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors against many, but not all, over-voltage conditions, and to minimize the input bias current (IB). VDD Bond Pad VIN+ Bond Pad VSS Input Stage Bond V – IN Pad Bond Pad FIGURE 4-1: Structures. D2 V1 VOUT MCP642X V2 FIGURE 4-2: Inputs. Protecting the Analog A significant amount of current can flow out of the inputs when the Common mode voltage (VCM) is below ground (VSS); see Figure 2-35. 4.1.3 INPUT CURRENT LIMITS In order to prevent damage and/or improper operation of the amplifier, the circuit must limit the currents into the input pins (see Section 1.1, Absolute Maximum Ratings †). Figure 4-3 shows one approach to protecting these inputs. The resistors R1 and R2 limit the possible currents in or out of the input pins (and the ESD diodes, D1 and D2). The diode currents will go through either VDD or VSS. VDD D1 D2 V1 The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go well above VDD; their breakdown voltage is high enough to allow normal operation, but not low enough to protect against slow over-voltage (beyond VDD) events. Very fast ESD events that meet the spec are limited so that damage does not occur. 2013 Microchip Technology Inc. VOUT R1 Simplified Analog Input ESD MCP642X V2 R2 min(R1,R2) > VSS – min(V1, V2) 2 mA min(R1,R2) > max(V1,V2) – VDD 2 mA FIGURE 4-3: Inputs. Protecting the Analog DS20005165B-page 17 MCP6421/2/4 NORMAL OPERATION The input stage of the MCP6421/2/4 op amps uses two differential input stages in parallel. One operates at a low Common mode input voltage (VCM), while the other operates at a high VCM. With this topology, the device operates with a VCM up to 300 mV above VDD and 300 mV below VSS. The input offset voltage is measured at VCM = VSS – 0.3V and VDD + 0.3V, to ensure proper operation. 100000 Reco ommended R ISO (Ω) 4.1.4 1000 Capacitive Loads 1 10p 100p 1n 10n 0.1μ 1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 Normalized Load Capacitance; CL/GN (F) After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Modify RISO’s value until the response is reasonable. Bench evaluation and simulations with the MCP6421/2/4 SPICE macro model are very helpful. Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases, and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. While a unity-gain buffer (G = +1 V/V) is the most sensitive to the capacitive loads, all gains show the same general behavior. 4.4 When driving large capacitive loads with the MCP6421/2/4 op amps (e.g., > 60 pF when G = +1 V/V), a small series resistor at the output (RISO in Figure 4-5) improves the feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitance load. 4.5 – VIN MCP642X + 10 FIGURE 4-5: Recommended RISO Values for Capacitive Loads. Rail-to-Rail Output The output voltage range of the MCP6421/2/4 op amps is 0.001V (typical) and 5.499V (typical) when RL = 100 k is connected to VDD/2 and VDD = 5.5V. Refer to Figures 2-24 and 2-26 for more information. 4.3 GN: 1 V/V 2 V/V ≥ 5 V/V 100 The transition between the input stages occurs when VCM is near VDD – 0.6V (see Figures 2-3 and 2-4). For the best distortion performance and gain linearity, with non-inverting gains, avoid this region of operation. 4.2 VDD = 5.5 V RL = 100 kȍ 10000 RISO VOUT CL Supply Bypass The MCP6421/2/4 op amps’ power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good high frequency performance. It can use a bulk capacitor (i.e., 1 µF or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other analog parts. Unused Op Amps An unused op amp in a quad package (MCP6424) should be configured as shown in Figure 4-6. These circuits prevent the output from toggling and causing crosstalk. Circuit A sets the op amp at its minimum noise gain. The resistor divider produces any desired reference voltage within the output voltage range of the op amp, and the op amp buffers that reference voltage. Circuit B uses the minimum number of components and operates as a comparator, but it may draw more current. ¼ MCP6424 (A) ¼ MCP6424 (B) VDD FIGURE 4-4: Output Resistor, RISO Stabilizes Large Capacitive Loads. Figure 4-5 gives the recommended RISO values for the different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). R1 VDD VDD R2 R2 V REF = VDD -------------------R1 + R2 FIGURE 4-6: DS20005165B-page 18 VREF Unused Op Amps. 2013 Microchip Technology Inc. MCP6421/2/4 4.6 PCB Surface Leakage 4.7 In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow, which is greater than the MCP6421/2/4 family’s bias current at +25°C (±1 pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-7. Electromagnetic Interference Rejection Ratio (EMIRR) Definitions The electromagnetic interference (EMI) is the disturbance that affects an electrical circuit due to either electromagnetic induction or electromagnetic radiation emitted from an external source. The parameter which describes the EMI robustness of an op amp is the Electromagnetic Interference Rejection Ratio (EMIRR). It quantitatively describes the effect that an RF interfering signal has on op amp performance. Internal passive filters make EMIRR better compared with older parts. This means that, with good PCB layout techniques, your EMC performance should be better. EMIRR is defined as: Guard Ring VIN– VIN+ VSS EQUATION 4-1: V RF EMIRR dB = 20 log ------------- V OS Where: FIGURE 4-7: for Inverting Gain. 1. 2. VRF = Peak Amplitude of RF Interfering Signal (VPK) Example Guard Ring Layout Non-inverting Gain and Unity-Gain Buffer: a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b) Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the Common mode input voltage. Inverting Gain and Transimpedance Gain Amplifiers (convert current to voltage, such as photo detectors): a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface. VOS = Input Offset Voltage Shift (V) 4.8 4.8.1 Application Circuits CARBON MONOXIDE GAS SENSOR A carbon monoxide (CO) gas detector is a device which detects the presence of carbon monoxide gas level. Usually this is battery powered and transmits audible and visible warnings. The sensor responds to CO gas by reducing its resistance proportionaly to the amount of CO present in the air exposed to the internal element. On the sensor module, this variable is part of a voltage divider formed by the internal element and potentiometer R1. The output of this voltage divider is fed into the noninverting inputs of the MCP6421 op amp. The device is configured as a buffer with unity gain and is used to provide a non-loaded test point for sensor sensitivity. Because this sensor can be corrupted by parasitic electromagnetic signals, the MCP6421 op amp can be used for conditioning this sensor. 2013 Microchip Technology Inc. DS20005165B-page 19 MCP6421/2/4 In Figure 4-8, the variable resistor is used to calibrate the sensor in different environments. . VDD VREF VDD - + R1 FIGURE 4-8: 4.8.2 VOUT MCP6421 CO Gas Sensor Circuit. PRESSURE SENSOR AMPLIFIER The MCP6421/2/4 op amps are well suited for conditioning sensor signals in battery-powered applications. Many sensors are configured as Wheatstone bridges. Strain gauges and pressure sensors are two common examples. Figure 4-9 shows a strain gauge amplifier, using the MCP6421/2/4 Enhanced EMI protection device. The difference amplifier with EMI robustness op amp is used to amplify the signal from the Wheatstone bridge. The two op amps, configured as buffers and connected at outputs of pressure sensors, prevents resistive loading of the bridge by resistor R1 and R2. Resistors R1,R2 and R3,R5 need to be chosen with very low tolerance to match the CMRR. VDD R+¨R R-¨R - The MCP6421/2/4 op amps’ Common Mode Input Range, which goes 0.3V beyond both supply rails, supports their use in high-side and low-side battery current sensing applications. The low quiescent current helps prolong battery life, and the rail-to-rail output supports detection of low currents. Figure 4-10 shows a high side battery current sensor circuit. The 10 resistor is sized to minimize power losses. The battery current (IDD) through the 10 resistor causes its top terminal to be more negative than the bottom terminal. This keeps the Common mode input voltage of the op amp below VDD, which is within its allowed range. The output of the op amp will also be below VDD, within its Maximum Output Voltage Swing specification. VDD VDD VOUT 10 IDD VDD - + MCP6421 VSS 1.8V to 5.5V 100 k 1 M V DD – V OUT I DD = ----------------------------------------- 10 V/V 10 High-Side Battery Current Sensor Battery Current Sensing. R3 MCP6421 100k R1 1k Vb R-¨R R+¨R BATTERY CURRENT SENSING FIGURE 4-10: VDD + Va 4.8.3 VDD - + R2 1k MCP6421 VOUT MCP6421 R5 100k 100k VOUT = Va – V b ---------------1k Strain Gauge FIGURE 4-9: DS20005165B-page 20 Pressure Sensor Amplifier. 2013 Microchip Technology Inc. MCP6421/2/4 5.0 DESIGN AIDS Microchip provides the basic design tools needed for the MCP6421/2/4 op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6421/2/4 op amp is available on the Microchip web site at www.microchip.com. The model was written and tested in the official OrCAD (Cadence®) owned PSpice®. For the other simulators, translation may be required. 5.4 Analog Demonstration and Evaluation Boards Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you achieve faster time to market. For a complete listing of these boards and their corresponding user’s guides and technical information, visit the Microchip web site at www.microchip.com/analogtools. Some boards that are especially useful are: The model covers a wide aspect of the op amp's electrical specifications. Not only does the model cover voltage, current and resistance of the op amp, but it also covers the temperature and the noise effects on the behavior of the op amp. The model has not been verified outside of the specification range listed in the op amp data sheet. The model behaviors under these conditions cannot ensure it will match the actual op amp performance. • • • • • • Moreover, the model is intended to be an initial design tool. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. The following Microchip Analog Design Note and Application Notes are available on the Microchip web site at www.microchip.com/appnotes, and are recommended as supplemental reference resources. 5.2 FilterLab® Software Microchip’s FilterLab software is an innovative software tool that simplifies analog active filter design using op amps. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate the actual filter performance. 5.3 Microchip Advanced Part Selector (MAPS) MAPS is a software tool that helps semiconductor professionals efficiently identify the Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/ maps, the MAPS is an overall selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool, you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for data sheets, purchase and sampling of Microchip parts. 2013 Microchip Technology Inc. MCP6XXX Amplifier Evaluation Board 1 MCP6XXX Amplifier Evaluation Board 2 MCP6XXX Amplifier Evaluation Board 3 MCP6XXX Amplifier Evaluation Board 4 Active Filter Demo Board Kit 5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2 5.5 Application Notes • ADN003 – “Select the Right Operational Amplifier for your Filtering Circuits”, DS21821 • AN722 – “Operational Amplifier Topologies and DC Specifications”, DS00722 • AN723 – “Operational Amplifier AC Specifications and Applications”, DS00723 • AN884 – “Driving Capacitive Loads With Op Amps”, DS00884 • AN990 – “Analog Sensor Conditioning Circuits – An Overview”, DS00990 • AN1177 – “Op Amp Precision Design: DC Errors”, DS01177 • AN1228 – “Op Amp Precision Design: Random Noise”, DS01228 • AN1297 – “Microchip’s Op Amp SPICE Macro Models”, DS01297 • AN1332: “Current Sensing Circuit Concepts and Fundamentals”’ DS01332 • AN1494: “Using MCP6491 Op Amps for Photodetection Applications”’ DS01494 These application notes and others are listed in the design guide: • “Signal Chain Design Guide”, DS21825 DS20005165B-page 21 MCP6421/2/4 NOTES: DS20005165B-page 22 2013 Microchip Technology Inc. MCP6421/2/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 5-Lead SC70 (MCP6421 only) Example: DS25 5-Lead SOT-23 (MCP6421 only) XXNN 8-Lead MSOP (3x3 mm) (MCP6422 only) Example: 3H25 Example 6422E 330256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2013 Microchip Technology Inc. DS20005165B-page 23 MCP6421/2/4 8-Lead SOIC (150 mil.) (MCP6422 only) NNN 14-Lead SOIC (3.90 mm) (MCP6424 only) Example MCP6422E 3 SN e^^1330 256 Example MCP6424 E/SL 1330256 14-Lead TSSOP (4.4 mm) (MCP6424 only) XXXXXXXX YYWW NNN DS20005165B-page 24 Example 6424E/ST 1330 256 2013 Microchip Technology Inc. MCP6421/2/4 5-Lead Plastic Small Outine Transistor (LTY) [SC70] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: D b 3 1 2 E1 E 4 5 e A e A2 c A1 L ) + -0 1 *++*%, *- - -. / ! 1 .'3 4 2!"# 5 16%6 4 5 5 .'7 4 167 ! ! 8! .'+ 4 ! 9 + + 2 +%6 4 5 2 +7 0 ! 5 ! "#$ " % &' (( Microchip Technology Drawing % & ( # C04-083B :2" 2013 Microchip Technology Inc. DS20005165B-page 25 MCP6421/2/4 5-Lead Plastic Small Outine Transistor (LTY) [SC70] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005165B-page 26 2013 Microchip Technology Inc. MCP6421/2/4 9 6(< 16 $==((( =6 b N E E1 3 2 1 e e1 D A2 A c φ A1 L L1 ) + -0 1 *++*%, *- -. / - ! +1 ;!"# .+1 .'3 ; 5 16%6 4; 5 8 5 ! .'7 5 8 167 8 5 4 .'+ 5 8 ;"# ! 9 + + 5 2 9 + 8! 5 4 9 > 5 8> +%6 4 5 2 +7 0 5 ! ! "#$ " % &' (( % & ( # :;" 2013 Microchip Technology Inc. DS20005165B-page 27 MCP6421/2/4 \ Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005165B-page 28 2013 Microchip Technology Inc. MCP6421/2/4 \ Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013 Microchip Technology Inc. DS20005165B-page 29 MCP6421/2/4 \ Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005165B-page 30 2013 Microchip Technology Inc. MCP6421/2/4 \ Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013 Microchip Technology Inc. DS20005165B-page 31 MCP6421/2/4 \ Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005165B-page 32 2013 Microchip Technology Inc. MCP6421/2/4 \ Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013 Microchip Technology Inc. DS20005165B-page 33 MCP6421/2/4 \ !"#$%&'*+, 9 6(< 16 $==((( =6 DS20005165B-page 34 2013 Microchip Technology Inc. MCP6421/2/4 \ Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013 Microchip Technology Inc. DS20005165B-page 35 MCP6421/2/4 \ Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005165B-page 36 2013 Microchip Technology Inc. MCP6421/2/4 \ 9 6(< 16 $==((( =6 2013 Microchip Technology Inc. DS20005165B-page 37 MCP6421/2/4 \ Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005165B-page 38 2013 Microchip Technology Inc. MCP6421/2/4 \ Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013 Microchip Technology Inc. DS20005165B-page 39 MCP6421/2/4 \ Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005165B-page 40 2013 Microchip Technology Inc. MCP6421/2/4 APPENDIX A: REVISION HISTORY Revision B (August 2013) The following is the list of modifications: 1. 2. 3. 4. 5. 6. 7. 8. 9. Added two new devices to the family: dual version MCP6422 (in 8L-MSOP and 8L-SOIC packages) and quad version MCP6424 (in 15L-SOIC and 14L-TSSOP packages). Added related information throughout the document. Updated Package Types drawing with the new devices’ pinouts. Added ESD Protection on all pins (HBM; MM) (Dual and Quad) in the Section 1.1, Absolute Maximum Ratings †. Added the new package temperatures in Table 1-3. Updated Figures 2-2 and 2-37 in Section 2.0, Typical Performance Curves. Added new Figure 2-38. Updated Section 3.0, Pin Descriptions with pin list and information. Added new Section 4.5, Unused Op Amps. Updated Section 6.0, Packaging Information with markings and package specification drawings. Updated Product Identification System. Revision A (March 2013) • Original Release of this Document. 2013 Microchip Technology Inc. DS20005165B-page 41 MCP6421/2/4 NOTES: DS20005165B-page 42 2013 Microchip Technology Inc. MCP6421/2/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X Examples: /XX Device Temperature Package Range Device: MCP6421T: MCP6422: MCP6422T: MCP6424: MCP6424T: Temperature Range: E Package: LTY* MS OT SL SN ST Single Op Amp (Tape and Reel) (SC70, SOT-23) Dual Op Amp (MSOP, SOIC) Dual Op Amp (Tape and Reel) (MSOP, SOIC) Quad Op Amp (SOIC, TSSOP) Quad Op Amp (Tape and Reel) (SOIC, TSSOP) = -40°C to +125°C (Extended) = Plastic Package (SC70), 5-lead = Plastic Micro Small Outline Package (MSOP), 8-lead = Plastic Small Outline Transistor (SOT-23), 5-lead = Plastic Small Outline - Narrow, 3.90 mm Body, 14-lead = Plastic Small Outline - Narrow, 3.90 mm Body, 8-lead = Plastic Thin Shrink Small Outline - 4.4 mm Body, 14-lead * Y = Nickel palladium gold manufacturing designator. Only available on the TDFN package. 2013 Microchip Technology Inc. a) MCP6421T-E/LTY: Tape and Reel, Extended Temperature, 5LD SC-70 package Tape and Reel, Extended Temperature, 5LD SOT-23 package b) MCP6421T-E/OT: a) MCP6422-E/MS: b) MCP6422T-E/MS: c) MCP6422-E/SN: Extended Temperature, 8LD SOIC package d) MCP6422T-E/SN: Tape and Reel, Extended Temperature, 8LD SOIC package a) MCP6424-E/SL: b) MCP6424T-E/SL: Extended Temperature, 14LD SOIC package Tape and Reel, Extended Temperature, 14LD SOIC package c) MCP6424-E/ST: Extended Temperature, 14LD TSSOP package d) MCP6424T-E/ST: Tape and Reel, Extended Temperature, 14LD TSSOP package Extended Temperature, 8LD MSOP package Tape and Reel, Extended Temperature, 8LD MSOP package DS20005165B-page 43 MCP6421/2/4 NOTES: DS20005165B-page 44 2013 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. 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Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62077-382-6 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2013 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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