MICROCHIP MCP6H02

MCP6H01/2/4
1.2 MHz, 16V Op Amps
Features:
Description:
•
•
•
•
•
•
Microchip’s MCP6H01/2/4 family of operational amplifiers (op amps) has a wide supply voltage range of 3.5V
to 16V and rail-to-rail output operation. This family is
unity gain stable and has a gain bandwidth product of
1.2 MHz (typical). These devices operate with a
single-supply voltage as high as 16V, while only
drawing 135 µA/amplifier (typical) of quiescent current.
•
•
•
•
•
Input Offset Voltage: ±0.7 mV (typical)
Quiescent Current: 135 µA (typical)
Common Mode Rejection Ratio: 100 dB (typical)
Power Supply Rejection Ratio: 102 dB (typical)
Rail-to-Rail Output
Supply Voltage Range:
- Single-Supply Operation: 3.5V to 16V
- Dual-Supply Operation: ±1.75V to ±8V
Gain Bandwidth Product: 1.2 MHz (typical)
Slew Rate: 0.8V/µs (typical)
Unity Gain Stable
Extended Temperature Range: -40°C to +125°C
No Phase Reversal
The MCP6H01/2/4 family is offered in single
(MCP6H01), dual (MCP6H02) and quad (MCP6H04)
configurations. All devices are fully specified in
extended temperature range from -40°C to +125°C.
Package Types
MCP6H01
SC70-5, SOT 23-5
Applications:
•
•
•
•
VOUT 1
Automotive Power Electronics
Industrial Control Equipment
Battery Powered Systems
Medical Diagnostic Instruments
VIN+ 3
MCP6H01
SOIC
Design Aids:
•
•
•
•
•
SPICE Macro Models
FilterLab® Software
MAPS (Microchip Advanced Part Selector)
Analog Demonstration and Evaluation Boards
Application Notes
Typical Application
R1
VREF
VDD
MCP6H01
V2
R1
R2
Difference Amplifier
VOUT
4 VIN–
MCP6H02
SOIC
NC 1
8 NC
VOUTA 1
8 VDD
VIN– 2
7 VDD
6 VOUT
5 NC
VINA– 2
VINA+ 3
7 VOUTB
VIN+ 3
VSS 4
MCP6H02
2x3 TDFN
NC 1
8 NC
VOUTA 1
VIN– 2
7 VDD
VINA– 2
VSS 4
EP
9
6 VINB–
5 VINB+
VSS 4
MCP6H01
2x3 TDFN
VIN+ 3
R2
V1
5 VDD
VSS 2
6 VOUT VINA+ 3
5 NC
8 VDD
EP
9
VSS 4
7 VOUTB
6 VINB–
5 VINB+
MCP6H04
SOIC, TSSOP
VOUTA 1
14 VOUTD
VINA– 2
13 VIND–
VINA+ 3
VDD 4
12 VIND+
11 VSS
VINB+ 5
10 VINC+
VINB– 6
9 VINC–
8 VOUTC
VOUTB 7
* Includes Exposed Thermal Pad (EP); see Table 3-1.
 2010-2011 Microchip Technology Inc.
DS22243D-page 1
MCP6H01/2/4
NOTES:
DS22243D-page 2
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
1.0
ELECTRICAL CHARACTERISTICS
1.1
Absolute Maximum Ratings †
Output Short-Circuit Current...................................continuous
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Current at Output and Supply Pins ..............................±65 mA
†† See 4.1.2 “Input Voltage Limits”.
VDD – VSS..........................................................................17V
Current at Input Pins......................................................±2 mA
Analog Inputs (VIN+, VIN-)††.............VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ............VSS – 0.3V to VDD + 0.3V
Difference Input Voltage..........................................VDD – VSS
Storage Temperature.....................................-65°C to +150°C
Maximum Junction Temperature (TJ)...........................+150°C
ESD protection on all pins (HBM; MM) 2 kV; 200V
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +3.5V to +16V, VSS = GND, TA = +25°C,
VCM = VDD/2 – 1.4V, VOUT  VDD/2, VL = VDD/2 and RL = 10 kto VL. (Refer to Figure 1-1).
Parameters
Sym
Min
Typ
Max
Units
VOS
-3.5
±0.7
+3.5
mV
VOS/TA
—
±2.5
—
PSRR
87
102
—
dB
IB
—
10
—
pA
Conditions
Input Offset
Input Offset Voltage
Input Offset Drift with Temperature
Power Supply Rejection Ratio
µV/°C TA = -40°C to +125°C
Input Bias Current and Impedance
Input Bias Current
IB
—
600
—
pA
TA = +85°C
IB
—
10
25
nA
TA = +125°C
Input Offset Current
IOS
—
±1
—
pA
Common Mode Input Impedance
ZCM
—
1013||6
—
||pF
Differential Input Impedance
ZDIFF
—
1013||6
—
||pF
Common Mode Input Voltage Range
VCMR
VSS  0.3
—
VDD  2.3
V
Common Mode Rejection Ratio
CMRR
78
93
—
dB
VCM = -0.3V to 1.2V,
VDD = 3.5V
82
98
—
dB
VCM = -0.3V to 2.7V,
VDD = 5V
84
100
—
dB
VCM = -0.3V to 12.7V,
VDD = 15V
95
115
—
dB
0.2V < VOUT <(VDD –
0.2V)
Common Mode
Open-Loop Gain
DC Open-Loop Gain (Large Signal)
 2010-2011 Microchip Technology Inc.
AOL
DS22243D-page 3
MCP6H01/2/4
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, VDD = +3.5V to +16V, VSS = GND, TA = +25°C,
VCM = VDD/2 – 1.4V, VOUT  VDD/2, VL = VDD/2 and RL = 10 kto VL. (Refer to Figure 1-1).
Parameters
Sym
Min
Typ
Max
Units
Conditions
VOH
3.490
3.495
—
V
VDD = 3.5V
0.5V input overdrive
4.985
4.993
—
V
VDD = 5V
0.5V input overdrive
14.970
14.980
—
V
VDD = 15V
0.5V input overdrive
—
0.005
0.010
V
VDD = 3.5V
0.5 V input overdrive
—
0.007
0.015
V
VDD = 5V
0.5 V input overdrive
—
0.020
0.030
V
VDD = 15V
0.5 V input overdrive
—
±27
—
mA
VDD = 3.5V
—
±45
—
mA
VDD = 5V
—
±50
—
mA
VDD = 15V
Output
High-Level Output Voltage
Low-Level Output Voltage
Output Short-Circuit Current
VOL
ISC
Power Supply
Supply Voltage
Quiescent Current per Amplifier
VDD
IQ
3.5
—
16
V
Single-supply operation
±1.75
—
±8
V
Dual-supply operation
—
125
175
µA
IO = 0, VDD = 3.5V
VCM = VDD/4
—
130
180
µA
IO = 0, VDD = 5V
VCM = VDD/4
—
135
185
µA
IO = 0, VDD = 15V
VCM = VDD/4
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +3.5V to +16V, VSS = GND,
VCM = VDD/2 - 1.4V, VOUT  VDD/2, VL = VDD/2, RL = 10 kto VL and CL = 60 pF. (Refer to Figure 1-1).
Parameters
Sym
Min
Typ
Max
Units
Conditions
AC Response
Gain Bandwidth Product
GBWP
—
1.2
—
MHz
Phase Margin
PM
—
57
—
°C
Slew Rate
SR
—
0.8
—
V/µs
G = +1V/V
Noise
Input Noise Voltage
Eni
—
12
—
µVp-p
f = 0.1 Hz to 10 Hz
Input Noise Voltage Density
eni
—
35
—
nV/Hz
f = 1 kHz
—
30
—
nV/Hz
f = 10 kHz
Input Noise Current Density
ini
—
1.9
—
fA/Hz
f = 1 kHz
DS22243D-page 4
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +3.5V to +16V and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
TA
-40
—
+125
°C
TA
-65
—
+150
°C
Conditions
Temperature Ranges
Operating Temperature Range
Storage Temperature Range
Note 1
Thermal Package Resistances
Thermal Resistance, 5L-SC70
JA
—
331
—
°C/W
Thermal Resistance, 5L-SOT-23
JA
—
256
—
°C/W
Thermal Resistance, 8L-2x3 TDFN
JA
—
41
—
°C/W
Thermal Resistance, 8L-SOIC
JA
—
149.5
—
°C/W
Thermal Resistance, 14L-SOIC
JA
—
95.3
—
°C/W
Thermal Resistance, 14L-TSSOP
JA
—
100
—
°C/W
Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C.
1.2
Test Circuits
The circuit used for most DC and AC tests is shown in
Figure 1-1. This circuit can independently set VCM and
VOUT (refer to Equation 1-1). Note that VCM is not the
circuit’s common mode voltage ((VP + VM)/2), and that
VOST includes VOS plus the effects (on the input offset
error, VOST) of temperature, CMRR, PSRR and AOL.
CF
6.8 pF
RG
100 k
RF
100 k
VP
VDD
VIN+
EQUATION 1-1:
G DM = RF  RG
CB1
100 nF
MCP6H0X
V CM =  V P + V DD  2   2
VOUT =  V DD  2  +  V P – V M  + V OST   1 + G DM 
Where:
GDM = Differential Mode Gain
(V/V)
VCM = Op Amp’s Common Mode
Input Voltage
(V)
 2010-2011 Microchip Technology Inc.
CB2
1 µF
VIN–
VOST = VIN– – VIN+
VOST = Op Amp’s Total Input Offset
Voltage
VDD/2
(mV)
VM
RG
100 k
RL
10 k
RF
100 k
CF
6.8 pF
VOUT
CL
60 pF
VL
FIGURE 1-1:
AC and DC Test Circuit for
Most Specifications.
DS22243D-page 5
MCP6H01/2/4
NOTES:
DS22243D-page 6
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +3.5V to +16V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT  VDD/2,
VL = VDD/2, RL = 10 kto VL and CL = 60 pF.
2550 Samples
18%
Input Offset Voltage (µV)
Percentage of Occurences
21%
15%
12%
9%
6%
3%
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-3.0
-2.5
0%
Input Offset Voltage (mV)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Input Offset Voltage vs.
Common Mode Input Voltage.
2550 Samples
TA = - 40°C to +125°C
Input Offset Voltage (µV)
Percentage of Occurences
35%
30%
1000
TA = +125°C
800
TA = +85°C
600
TA = +25°C
TA = -40°C
400
200
0
-200
-400
VDD = 5V
-600
Representative Part
-800
-1000
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Common Mode Input Voltage (V)
25%
20%
15%
10%
5%
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
16
0%
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
-0.5
Input Offset Voltage Drift (µV/°C)
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
-0.5
Input Offset Voltage Drift.
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
VDD = 3.5V
Representative Part
0.0
0.5
1.0
1.5
2.0
Common Mode Input Voltage (V)
FIGURE 2-3:
Input Offset Voltage vs.
Common Mode Input Voltage.
 2010-2011 Microchip Technology Inc.
2.5
VDD = 15V
Representative Part
1.5 3.5 5.5 7.5 9.5 11.5 13.5 15.5
Common Mode Input Voltage (V)
FIGURE 2-5:
Input Offset Voltage vs.
Common Mode Input Voltage.
Input Offset Voltage (µV)
Input Offset Voltage (µV)
FIGURE 2-2:
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
1000
800
600
Representative Part
VDD = 15V
400
200
0
VDD = 5V
-200
-400
-600
-800
VDD = 3.5V
-1000
0
2
FIGURE 2-6:
Output Voltage.
4
6
8
10
12
Output Voltage (V)
14
16
Input Offset Voltage vs.
DS22243D-page 7
MCP6H01/2/4
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
120
TA =
TA =
TA =
TA =
CMRR, PSRR (dB)
+125°C
+85°C
+25°C
-40°C
Representative Part
0
2
4
6
8
10 12 14
Power Supply Voltage (V)
16
70
60
50
40
30
10
10
100
100
1k
10k
1000
10000
Frequency (Hz)
100k 1000000
1M
100000
CMRR, PSRR vs.
130
PSRR
120
CMRR, PSRR (dB)
100
110
100
90
CMRR @ VDD = 15V
@ VDD = 5V
@ VDD = 3.5V
80
70
60
50
11
10
10
FIGURE 2-8:
vs. Frequency.
100
1k
100
1000
Frequency (Hz)
-50
10k 100k
10000
100000
Input Noise Voltage Density
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-11:
Temperature.
CMRR, PSRR vs. Ambient
100000
100n
Input Bias and Offset Currents
(A)
50
45
VDD = 15V
10000
10n
40
35
30
Input Bias Current
1000
1n
100
100p
15
FIGURE 2-9:
Input Noise Voltage Density
vs. Common Mode Input Voltage.
DS22243D-page 8
Ambient Temperature (°C)
125
3
5
7
9
11
13
Common Mode Input Voltage (V)
115
1
105
-1
Input Offset Current
1
1p
95
10
10
10p
85
15
75
20
65
f = 1 kHz
VDD = 16V
55
25
45
10
25
Input Noise Voltage Density
(nV/Hz)
PSRR-
FIGURE 2-10:
Frequency.
1,000
Input Noise Voltage Density
(nV/ Hz)
Representative Part
CMRR
90
80
20
18
FIGURE 2-7:
Input Offset Voltage vs.
Power Supply Voltage.
PSRR+
110
100
35
Input Offset Voltage (µV)
Note: Unless otherwise indicated, TA = +25°C, VDD = +3.5V to +16V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT  VDD/2,
VL = VDD/2, RL = 10 kto VL and CL = 60 pF.
FIGURE 2-12:
Input Bias, Offset Currents
vs. Ambient Temperature.
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +3.5V to +16V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT  VDD/2,
VL = VDD/2, RL = 10 kto VL and CL = 60 pF.
120
10n
10000
Open-Loop Gain (dB)
Input Bias Current (A)
TA = +125°C
1n
1000
100p
100
TA = +85°C
10p
10
VDD = 15V
100
1p
1
2
4
6
8
10
12
14
Common Mode Input Voltage (V)
FIGURE 2-13:
Input Bias Current vs.
Common Mode Input Voltage.
60
200
190
180
170
160
150
140
130
120
110
100
90
80
-90
40
-120
20
-150
0
-180
0.1
1.0E+00
1.0E+01
1
10
FIGURE 2-16:
Frequency.
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
-210
1.0E+07
100 1k 10k 100k 1M 10M
Frequency (Hz)
Open-Loop Gain, Phase vs.
160
DC-Open Loop Gain (dB)
Quiescent Current
(µA/Amplifier)
-60
Open-Loop Phase
1.0E-01
16
-30
80
-20
0
VDD = 15V
VDD = 5V
VDD = 3.5V
150
140
130
120
110
100
VSS + 0.2V < VOUT < VDD - 0.2V
90
80
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
3
125
FIGURE 2-14:
Quiescent Current vs.
Ambient Temperature.
5
7
9
11
13
Power Supply Voltage (V)
15
17
FIGURE 2-17:
DC Open-Loop Gain vs.
Power Supply Voltage.
150
200
180
160
140
120
100
80
60
40
20
0
DC-Open Loop Gain (dB)
Quiescent Current
(µA/Amplifier)
0
Open-Loop Gain
Open-Loop Phase (°)
100n
100000
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0
2
4
6
8
10
12
Power Supply Voltage (V)
130
120
14
16
VDD = 15V
VDD = 5V
VDD = 3.5V
110
100
90
80
0.00
FIGURE 2-15:
Quiescent Current vs.
Power Supply Voltage.
 2010-2011 Microchip Technology Inc.
140
0.05
0.10
0.15
0.20
0.25
0.30
Output Voltage Headroom (V)
VDD - VOH or VOL - VSS
FIGURE 2-18:
DC Open-Loop Gain vs.
Output Voltage Headroom.
DS22243D-page 9
MCP6H01/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +3.5V to +16V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT  VDD/2,
VL = VDD/2, RL = 10 kto VL and CL = 60 pF.
Output Short Circuit Current
(mA)
140
120
100
80
Input Referred
40
100
100
1k
10k
1000
10000
Frequency (Hz)
1.8
180
1.6
160
Gain Bandwidth Product
140
1.2
120
1.0
100
Phase Margin
0.8
0.6
80
60
0.4
40
VDD = 3.5V
0.2
0.0
-50
140
1.2
120
100
Phase Margin
0.8
0.6
80
60
0.4
40
VDD = 15V
0.2
0.0
-50
Phase Margin (°)
Gain Bandwidth Product
(MHz)
160
1.4
1.0
20
0
-25
0
25
50
75 100 125
Ambient Temperature (°C)
FIGURE 2-21:
Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
DS22243D-page 10
30
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
20
10
0
2
4
6
8
10
12
14
16
Power Supply Voltage (V)
VDD = 15V
10
VDD = 5V
VDD = 3.5V
1
0.1
100
100
180
Gain Bandwidth Product
40
0
0
-25
0
25
50
75 100 125
Ambient Temperature (°C)
FIGURE 2-20:
Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
1.6
50
100
20
1.8
60
FIGURE 2-22:
Output Short Circuit Current
vs. Power Supply Voltage.
Phase Margin (°)
Gain Bandwidth Product
(MHz)
FIGURE 2-19:
Channel-to-Channel
Separation vs. Frequency (MCP6H02 only).
1.4
70
100k
100000
Output Voltage Swing (VP-P)
60
FIGURE 2-23:
Frequency.
Output Voltage Headroom (mV)
Channel to Channel
Separation (dB)
160
1k
1000
10k
100k
10000
100000
Frequency (Hz)
1M
1000000
Output Voltage Swing vs.
10000
VDD = 15V
1000
VDD - VOH
100
10
1
0.01
VOL - VSS
0.1
1
10
Output Current (mA)
100
FIGURE 2-24:
Output Voltage Headroom
vs. Output Current.
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
1000
VDD = 5V
100
VDD - VOH
10
VOL - VSS
1
0.1
0.01
0.1
1
10
Output Current (mA)
VDD = 3.5V
100
VOL - VSS
1
VDD - VOH
0.1
0.1
1.0
Output Current (mA)
5
2
6
VOL - VSS
17
VDD = 15V
16
100
125
VDD - VOH
5
4
VOL - VSS
3
VDD = 3.5V
2
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-29:
Output Voltage Headroom
vs. Ambient Temperature.
0.9
18
0
25
50
75
Ambient Temperature (°C)
7
1.0
19
-25
8
21
VDD - VOH
VDD = 5V
3
22
20
VOL - VSS
4
-50
Slew Rate (V/µs)
Output Voltage Headroom (mV)
6
FIGURE 2-28:
Output Voltage Headroom
vs. Ambient Temperature.
10.0
FIGURE 2-26:
Output Voltage Headroom
vs. Output Current.
VDD - VOH
-50
Output Voltage Headroom (mV)
Output Voltage Headroom (mV)
1000
0.0
7
100
FIGURE 2-25:
Output Voltage Headroom
vs. Output Current.
10
8
Output Voltage Headroom (mV)
Output Voltage Headroom (mV)
Note: Unless otherwise indicated, TA = +25°C, VDD = +3.5V to +16V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT  VDD/2,
VL = VDD/2, RL = 10 kto VL and CL = 60 pF.
0.8
0.7
0.6
Falling Edge, VDD = 15V
Rising Edge, VDD = 15V
0.5
0.4
0.3
15
0.2
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-27:
Output Voltage Headroom
vs. Ambient Temperature.
 2010-2011 Microchip Technology Inc.
-50
-25
FIGURE 2-30:
Temperature.
0
25
50
75
Ambient Temperature (°C)
100
125
Slew Rate vs. Ambient
DS22243D-page 11
MCP6H01/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +3.5 V to +16 V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT  VDD/2,
VL = VDD/2, RL = 10 kto VL and CL = 60 pF.
1.6
16
Falling Edge, VDD = 5V
Rising Edge, VDD = 5V
1.2
14
Output Voltage (V)
Slew Rate (V/µs)
1.4
1.0
0.8
0.6
Falling Edge, VDD = 3.5V
Rising Edge, VDD = 3.5V
0.4
0.2
12
10
8
6
VDD = 15V
G = +1V/V
4
2
0.0
-50
-25
FIGURE 2-31:
Temperature.
0
25
50
75
Ambient Temperature (°C)
100
0
125
Slew Rate vs. Ambient
Time (20 µs/div)
FIGURE 2-34:
Pulse Response.
Large Signal Non-Inverting
14
VDD = 15V
G = +1V/V
Output Voltage (V)
Output Voltage (20 mv/div)
16
10
8
6
4
2
0
Time (2 µs/div)
FIGURE 2-32:
Pulse Response.
VDD = 15V
G = -1V/V
12
Small Signal Non-Inverting
Time (20 µs/div)
FIGURE 2-35:
Response.
Large Signal Inverting Pulse
VDD = 15V
G = -1V/V
15
Output Voltage (V)
Output Voltage (20 mv/div)
17
VOUT
13
11
VIN
9
7
5
3
VDD = 15V
G = +2V/V
1
-1
Time (2 µs/div)
FIGURE 2-33:
Response.
DS22243D-page 12
Small Signal Inverting Pulse
Time (0.1 ms/div)
FIGURE 2-36:
The MCP6H01/2/4 Shows
No Phase Reversal.
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +3.5 V to +16 V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT  VDD/2,
VL = VDD/2, RL = 10 kto VL and CL = 60 pF.
1m
1000
1.00E-03
100µ
1.00E-05
1µ
100
1.00E-06
-IIN (A)
Closed Loop Output
Impedance (Ω)
1.00E-04
10µ
10
100n
1.00E-07
10n
1.00E-08
1n
G N:
101V/V
11V/V
1V/V
1.00E-09
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
100p
1.00E-10
10p
1.00E-11
1p
1
1.00E-12
1.0E+01
10
1.0E+02
100
1.0E+03
1.0E+04
1k
10k
Frequency (Hz)
1.0E+05
100k
FIGURE 2-37:
Closed Loop Output
Impedance vs. Frequency.
 2010-2011 Microchip Technology Inc.
1.0E+06
1M
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
VIN (V)
FIGURE 2-38:
Measured Input Current vs.
Input Voltage (below VSS).
DS22243D-page 13
MCP6H01/2/4
NOTES:
DS22243D-page 14
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP6H01
SC70-5,
SOT-23-5
3.1
MCP6H02
SOIC 2x3 TDFN
MCP6H04
SOIC
2x3 TDFN
SOIC,
TSSOP
Symbol
1
6
6
1
1
1
VOUT, VOUTA
Analog Output (op amp A)
4
2
2
2
2
2
VIN–, VINA–
Inverting Input (op amp A)
3
3
3
3
3
3
VIN+, VINA+
Non-inverting Input (op amp A)
5
7
7
8
8
4
VDD
Non-inverting Input (op amp B)
Positive Power Supply
—
—
—
5
5
5
VINB+
—
—
—
6
6
6
VINB–
Inverting Input (op amp B)
—
—
—
7
7
7
VOUTB
Analog Output (op amp B)
—
—
—
—
—
8
VOUTC
Analog Output (op amp C)
—
—
—
—
—
9
VINC–
Inverting Input (op amp C)
—
—
—
—
—
10
VINC+
Non-inverting Input (op amp C)
Negative Power Supply
2
4
4
4
4
11
VSS
—
—
—
—
—
12
VIND+
Non-inverting Input (op amp D)
—
—
—
—
—
13
VIND–
Inverting Input (op amp D)
—
—
—
—
—
14
VOUTD
Analog Output (op amp D)
—
1, 5, 8
1, 5, 8
—
—
—
NC
No Internal Connection
—
—
9
—
9
—
EP
Exposed Thermal Pad (EP); must
be connected to VSS.
Analog Outputs
The output pins are low-impedance voltage sources.
3.2
Description
Analog Inputs
The non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
3.3
Power Supply Pins
The positive power supply (VDD) is 3.5V to 16V higher
than the negative power supply (VSS). For normal
operation, the other pins are at voltages between VSS
and VDD.
Typically, these parts can be used in single-supply
operation or dual-supply operation. Also, VDD will need
bypass capacitors.
3.4
Exposed Thermal Pad (EP)
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the VSS pin; they must
be connected to the same potential on the Printed
Circuit Board (PCB).
 2010-2011 Microchip Technology Inc.
DS22243D-page 15
MCP6H01/2/4
NOTES:
DS22243D-page 16
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
4.0
APPLICATION INFORMATION
The MCP6H01/2/4 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process and
is specifically designed for low-power, high-precision
applications.
4.1
VDD
D1
D2
V1
Inputs
4.1.1
MCP6H0X
V2
PHASE REVERSAL
The MCP6H01/2/4 op amps are designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 2-36 shows the input voltage
exceeding the supply voltage without any phase
reversal.
4.1.2
INPUT VOLTAGE LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1 “Absolute Maximum
Ratings †”).
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors against many (but not all)
over-voltage conditions, and to minimize the input bias
current (IB).
FIGURE 4-2:
Inputs.
Protecting the Analog
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS), see Figure 2-38.
4.1.3
INPUT CURRENT LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1 “Absolute
Maximum Ratings †”).
Figure 4-3 shows one approach to protecting these
inputs. The resistors R1 and R2 limit the possible
currents in or out of the input pins (and the ESD diodes,
D1 and D2). The diode currents will go through either
VDD or VSS.
VDD Bond
Pad
VDD
D1
Bond
VIN+
Pad
VOUT
Input
Stage
Bond
VIN–
Pad
D2
V1
R1
MCP6H0X
VOUT
V2
R2
VSS Bond
Pad
FIGURE 4-1:
Structures.
R3
Simplified Analog Input ESD
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages that go well above VDD. Their
breakdown voltage is high enough to allow normal
operation, but not low enough to protect against slow
overvoltage (beyond VDD) events. Very fast ESD
events (that meet the specification) are limited so that
damage does not occur.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs;
Figure 4-2 shows one approach to protecting these
inputs.
 2010-2011 Microchip Technology Inc.
VSS – (minimum expected V1)
2 mA
VSS – (minimum expected V2)
R2 >
2 mA
R1 >
FIGURE 4-3:
Inputs.
4.1.4
Protecting the Analog
NORMAL OPERATION
The inputs of the MCP6H01/2/4 op amps connect to a
differential PMOS input stage. It operates at a low
common mode input voltage (VCM), including ground.
With this topology, the device operates with a VCM up
to VDD – 2.3V and 0.3V below VSS (refer to Figure 2-3
through 2-5). The input offset voltage is measured at
VCM = VSS – 0.3V and VDD – 2.3V to ensure proper
operation.
DS22243D-page 17
MCP6H01/2/4
For a unity gain buffer, VIN must be maintained below
VDD – 2.3V for correct operation.
Rail-to-Rail Output
The output voltage range of the MCP6H01/2/4 op amps
is 0.020V (typical) and 14.980V (typical) when
RL = 10 k is connected to VDD/2 and VDD = 15V.
Refer to Figures 2-24 through 2-29 for more
information.
4.3
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = + 1V/V), a small series
resistor at the output (RISO in Figure 4-4) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will generally be lower than the bandwidth
with no capacitance load.
–
MCP6H0X
+
RISO
VOUT
CL
FIGURE 4-4:
Output Resistor, RISO
Stabilizes Large Capacitive Loads.
Figure 4-5 gives the recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1 + |Signal Gain| (e.g., -1V/V gives GN = +2V/V).
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP6H01/2/4 SPICE macro
model are helpful.
VDD = 16V
RL = 10 kΩ
100
GN:
1 V/V
2 V/V
 5 V/V
10
1
10p
100p
1n
10n
0.1µ 1.E-06
1µ
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
Normalized Load Capacitance; CL/GN (F)
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. While a unity-gain buffer (G = +1V/V) is the
most sensitive to capacitive loads, all gains show the
same general behavior.
VIN
Recommended R ISO (Ω)
4.2
1000
1k
FIGURE 4-5:
Recommended RISO Values
for Capacitive Loads.
4.4
Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It can use a bulk
capacitor (i.e., 1 µF or larger) within 100 mm to provide
large, slow currents. This bulk capacitor can be shared
with other analog parts.
4.5
Unused Op Amps
An unused op amp in a quad package (MCP6H04)
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. Circuit A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp, and the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
¼ MCP6H04 (A)
VDD
R1
VDD
VDD
R2
VREF
R2
V REF = VDD  -------------------R1 + R2
FIGURE 4-6:
DS22243D-page 18
¼ MCP6H04 (B)
Unused Op Amps.
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
4.6
PCB Surface Leakage
4.7
In applications where low input bias current is critical,
PCB surface leakage effects need to be considered.
Surface leakage is caused by humidity, dust or other
contamination on the board. Under low-humidity conditions, a typical resistance between nearby traces is
1012. A 15V difference would cause 15 pA of current
to flow; which is greater than the MCP6H01/2/4 family’s
bias current at +25°C (10 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-7.
Guard Ring
VIN– VIN+
VSS
4.7.1
Application Circuits
DIFFERENCE AMPLIFIER
The MCP6H01/2/4 op amps can be used in current
sensing applications. Figure 4-8 shows a resistor
(RSEN) that converts the sensor current (ISEN) to
voltage, as well as a difference amplifier that amplifies
the voltage across the resistor while rejecting common
mode noise. R1 and R2 must be well matched to obtain
an acceptable Common Mode Rejection Ratio
(CMRR). Moreover, RSEN should be much smaller than
R1 and R2 in order to minimize the resistive loading of
the source.
To ensure proper operation, the op amp common mode
input voltage must be kept within the allowed range.
The reference voltage (VREF) is supplied by a
low-impedance source. In single-supply applications,
VREF is typically VDD/2.
.
R1
R2
VREF
VDD
FIGURE 4-7:
for Inverting Gain.
1.
2.
Example Guard Ring Layout
Non-inverting Gain and Unity-Gain Buffer:
a. Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b. Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
Inverting Gain and Trans-impedance Gain
Amplifiers (convert current to voltage, such as
photo detectors):
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b. Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
 2010-2011 Microchip Technology Inc.
RSEN
MCP6H01
ISEN
R1
VOUT
R2
RSEN << R1, R2
R2
VOUT =  V1 – V 2   ------ + V REF
 R 1
FIGURE 4-8:
High Side Current Sensing
Using Difference Amplifier.
DS22243D-page 19
MCP6H01/2/4
4.7.2
TWO OP AMP INSTRUMENTATION
AMPLIFIER
The MCP6H01/2/4 op amps are well suited for
conditioning sensor signals in battery-powered
applications. Figure 4-9 shows a two op amp
instrumentation amplifier using the MCP6H02, which
works well for applications requiring rejection of
common mode noise at higher gains.
To ensure proper operation, the op amp common mode
input voltage must be kept within the allowed range.
The reference voltage (VREF) is supplied by a lowimpedance source. In single-supply applications, VREF
is typically VDD/2.
RG
VREF R1
R2
R2
4.7.3
PHOTODETECTOR AMPLIFIER
The MCP6H01/2/4 op amps can be used to easily
convert the signal from a sensor that produces an
output current (such as a photo diode) into voltage (a
trans-impedance amplifier). This is implemented with a
single resistor (R2) in the feedback loop of the
amplifiers shown in Figure 4-10. The optional capacitor
(C2) sometimes provides stability for these circuits.
A photodiode configured in Photovoltaic mode has a
zero voltage potential placed across it. In this mode,
the light sensitivity and linearity is maximized, making it
best suited for precision applications. The key amplifier
specifications for this application are: low input bias
current, common mode input voltage range (including
ground), and rail-to-rail output.
C2
R1
R2
VOUT
V2
½
MCP6H02
VOUT
½
MCP6H02
V1
ID1
–
Light
D1
MCP6H01
+
R 1 2R1
V OUT =  V1 – V 2   1 + ------ + --------- + VREF
R2 RG
FIGURE 4-9:
Two Op Amp
Instrumentation Amplifier.
VDD
VOUT = ID1*R2
FIGURE 4-10:
Photodetector Amplifier.
To obtain the best CMRR possible, and not limit the
performance by the resistor tolerances, set a high gain
with the RG resistor.
DS22243D-page 20
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
5.0
DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP6H01/2/4 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP6H01/2/4
op amp is available on the Microchip web site at
www.microchip.com. The model was written and tested
in PSPICE owned by Orcad (Cadence). For other
simulators, it may require translation.
The model covers a wide aspect of the op amp’s
electrical specifications. Not only does the model cover
voltage, current and resistance of the op amp, but it
also covers the temperature and noise effects on the
behavior of the op amp. The model has not been
verified outside the specification range listed in the op
amp data sheet. The model behaviors under these conditions cannot be guaranteed to match the actual op
amp performance.
Moreover, the model is intended to be an initial design
tool. Bench testing is a very important part of any
design and cannot be replaced with simulations. Also,
simulation results using this macro model need to be
validated by comparing them to the data sheet
specifications and characteristic curves.
5.2
FilterLab Software
Microchip’s FilterLab software is an innovative software
tool that simplifies analog active filter (using op amps)
design. Available at no cost from the Microchip web site
at www.microchip.com/filterlab, the FilterLab design
tool provides full schematic diagrams of the filter circuit
with component values. It also outputs the filter circuit
in SPICE format, which can be used with the macro
model to simulate actual filter performance.
5.3
MAPS (Microchip Advanced Part
Selector)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip web site at www.microchip.com/
maps, MAPS is an overall selection tool for Microchip’s
product portfolio that includes analog, memory, MCUs
and DSCs. Using this tool, you can define a filter to sort
features for a parametric search of devices and export
side-by-side technical comparison reports. Helpful links
are also provided for data sheets, purchases and
sampling of Microchip parts.
 2010-2011 Microchip Technology Inc.
5.4
Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are designed
to help you achieve faster time to market. For a complete listing of these boards and their corresponding
user’s guides and technical information, visit the
Microchip web site: www.microchip.com/analogtools.
Some boards that are especially useful include:
• MCP6XXX Amplifier Evaluation Board 1
• MCP6XXX Amplifier Evaluation Board 2
• MCP6XXX Amplifier Evaluation Board 3
• MCP6XXX Amplifier Evaluation Board 4
• Active Filter Demo Board Kit
• 5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
5.5
Application Notes
The following Microchip analog design note and application notes are available on the Microchip web site at
www.microchip.com/appnotes, and are recommended
as supplemental reference resources.
• ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits”, DS21821
• AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
• AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
• AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
• AN990: “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
• AN1177: “Op Amp Precision Design: DC Errors”,
DS01177
• AN1228: “Op Amp Precision Design: Random
Noise”, DS01228
• AN1297: “Microchip’s Op Amp SPICE Macro
Models”’ DS01297
• AN1332: “Current Sensing Circuit Concepts and
Fundamentals”’ DS01332
These application notes and others are listed in:
• “Signal Chain Design Guide”, DS21825
DS22243D-page 21
MCP6H01/2/4
NOTES:
DS22243D-page 22
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
5-Lead SC-70 (MCP6H01)
Example
Device
MCP6H01
Code
DH25
DHNN
Note: Applies to 5-Lead SC-70.
5-Lead SOT-23 (MCP6H01)
Example:
Device
XXNN
MCP6H01
Code
2A25
XXNN
2ANN
Note: Applies to 5-Lead SOT-23.
8-Lead SOIC (150 mil) (MCP6H01, MCP6H02)
Example:
MCP6H01E
e3 1103
SN^^
256
XXXXXXXX
XXXXYYWW
NNN
8-Lead 2x3 TDFN (MCP6H01, MCP6H02)
Example:
AAL
103
25
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2010-2011 Microchip Technology Inc.
DS22243D-page 23
MCP6H01/2/4
Package Marking Information
14-Lead SOIC (150 mil) (MCP6H04)
Example:
MCP6H04
e3
E/SL^^
1103256
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
14-Lead TSSOP (MCP6H04)
XXXXXXXX
YYWW
NNN
DS22243D-page 24
Example:
6H04E/ST
1103
256
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
.
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 2010-2011 Microchip Technology Inc.
DS22243D-page 25
MCP6H01/2/4
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DS22243D-page 26
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
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 2010-2011 Microchip Technology Inc.
DS22243D-page 27
MCP6H01/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22243D-page 28
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2010-2011 Microchip Technology Inc.
DS22243D-page 29
MCP6H01/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22243D-page 30
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
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 2010-2011 Microchip Technology Inc.
DS22243D-page 31
MCP6H01/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22243D-page 32
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2010-2011 Microchip Technology Inc.
DS22243D-page 33
MCP6H01/2/4
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DS22243D-page 34
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2010-2011 Microchip Technology Inc.
DS22243D-page 35
MCP6H01/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22243D-page 36
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
.
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 2010-2011 Microchip Technology Inc.
DS22243D-page 37
MCP6H01/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22243D-page 38
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2010-2011 Microchip Technology Inc.
DS22243D-page 39
MCP6H01/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22243D-page 40
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
APPENDIX A:
REVISION HISTORY
Revision D (December 2011)
The following is the list of modifications:
1.
Added the SC70-5 and SOT-23-5 packages for
the MCP6H01 device and updated all related
information throughout the document.
Revision C (March 2011)
The following is the list of modifications:
1.
2.
Added new device MCP6H04.
Updated Table 3-1 with MCP6H04 pin names
and details.
Revision B (October 2010)
The following is the list of modifications:
1.
Updated Section 4.1 “Inputs”.
Revision A (March 2010)
• Original Release of this Document.
 2010-2011 Microchip Technology Inc.
DS22243D-page 41
MCP6H01/2/4
NOTES:
DS22243D-page 42
 2010-2011 Microchip Technology Inc.
MCP6H01/2/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
-X
/XX
Device
Temperature
Range
Package
Device:
MCP6H01T:
MCP6H01:
MCP6H01T:
MCP6H02:
MCP6H02T:
MCP6H04:
MCP6H04T:
Temperature Range:
E
Package:
LT =
OT =
MNY *
SN =
SL =
ST =
Single Op Amp (Tape and Reel)
(SC-70, SOT-23)
Single Op Amp
Single Op Amp (Tape and Reel)
(SOIC and 2x3 TDFN)
Dual Op Amp
Dual Op Amp (Tape and Reel)
(SOIC and 2x3 TDFN)
Quad Op Amp
Quad Op Amp (Tape and Reel) (SOIC
and TSSOP)
= -40°C to +125°C
Examples:
a)
MCP6H01T-E/LT:
b)
MCP6H01T-E/OT:
c)
d)
MCP6H01-E/SN:
MCP6H01T-E/SN:
e)
MCP6H01T-E/MNY:
f)
g)
MCP6H02-E/SN:
MCP6H02T-E/SN:
h)
MCP6H02T-E/MNY:
i)
j)
MCP6H04-E/SL:
MCP6H04T-E/SL:
k)
l)
MCP6H04-E/ST:
MCP6H04T-E/ST:
Tape and Reel,
5LD SC70 pkg
Tape and Reel,
5LD SOT-23 pkg
8LD SOIC pkg
Tape and Reel,
8LD SOIC pkg
Tape and Reel,
8LD 2x3 TDFN pkg
8LD SOIC pkg
Tape and Reel,
8LD SOIC pkg
Tape and Reel
8LD 2x3 TDFN pkg
14LD SOIC pkg
Tape and Reel,
14LD SOIC pkg
14LD SOIC pkg
Tape and Reel,
14LD TSSOP pkg
Plastic Package (SC-70), 5-lead
Plastic Small Outline Transistor (SOT-23), 5-lead
= Plastic Dual Flat, No Lead, (2x3 TDFN) 8-lead
Lead Plastic Small Outline (150 mil Body), 8-lead
Plastic Small Outline, (150 mil Body), 14-lead
Plastic Thin Shrink Small Outline (150 mil Body),
14-lead
* Y = Nickel palladium gold manufacturing designator. Only
available on the TDFN package.
 2010-2011 Microchip Technology Inc.
DS22243D-page 43
MCP6H01/2/4
NOTES:
DS22243D-page 44
 2010-2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-927-4
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
 2010-2011 Microchip Technology Inc.
DS22243D-page 45
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DS22243D-page 46
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11/29/11
 2010-2011 Microchip Technology Inc.