X9271
®
Single Supply/Low Power/256-Tap/SPI Bus
Data Sheet
March 31, 2005
Single Digitally-Controlled (XDCP™)
Potentiometer
FN8174.1
DESCRIPTION
The X9271 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
FEATURES
• 256 Resistor Taps
• SPI Serial Interface for write, read, and transfer
operations of the potentiometer
• Wiper Resistance, 100Ω typical @ VCC = 5V
• 16 Nonvolatile Data Registers
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position on
Power-up.
• Standby Current < 3µA Max
• VCC: 2.7V to 5.5V Operation
• 50kΩ, 100kΩ versions of End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes per Bit per
Register
• 14-Lead TSSOP
• Low Power CMOS
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and a four
nonvolatile Data Registers that can be directly written to
and read by the user. The contents of the WCR controls
the position of the wiper on the resistor array though the
switches. Powerup recalls the contents of the default
data register (DR0) to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
VCC
SPI
Bus
Interface
Address
Data
Status
RH
Write
Read
Transfer
Inc/Dec
Wiper Counter
Register (WCR)
Bus
Interface
and Control
Control
VSS
1
50kΩ and 100kΩ
256-taps
Power-on Recall
POT
Data Registers
16 Bytes
RW
RL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9271
DETAILED FUNCTIONAL DIAGRAM
VCC
Bank 0 Power-on Recall
R0 R1
HOLD
CS
SCK
SO
SI
A0
A1
R2 R3
INTERFACE
AND
CONTROL
CIRCUITRY
50kΩ and 100kΩ
256-taps
WIPER
COUNTER
REGISTER
(WCR)
RH
RL
RW
DATA
WP
Control
Bank 1
Bank 2
Bank 3
R0 R1
R0 R1
R0 R1
R2 R3
R2 R3
R2 R3
12 additional nonvolatile registers
3 Banks of 4 registers x 8-bits
VSS
CIRCUIT LEVEL APPLICATIONS
SYSTEM LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Adjust the contrast in LCD displays
• Provide programmable dc reference voltages for
comparators and detectors
• Control the power level of LED transmitters in
communication systems
• Control the volume in audio circuits
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Control the gain in audio and home entertainment
systems
• Provide the variable DC bias for tuners in RF
wireless systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
• Provide a control variable (I, V, or R) in feedback
circuits
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March 31, 2005
X9271
PIN CONFIGURATION
TSSOP
S0
1
A0
2
NC
14
VCC
13
RL
3
12
RH
CS
SCK
4
11
RW
5
10
HOLD
SI
6
VSS
7
9
8
WP
X9271
A1
PIN ASSIGNMENTS
TSSOP
Symbol
1
SO
Serial Data Output.
2
A0
Device Address.
3
NC
No Connect.
4
CS
Chip Select.
5
SCK
Serial Clock.
6
SI
Serial Data Input.
7
VSS
System Ground.
8
WP
Hardware Write Protect.
9
A1
Device Address.
10
HOLD
Device select. Pause the serial bus.
11
RW
Wiper Terminal of the Potentiometer.
12
RH
High Terminal of the Potentiometer.
13
RL
Low Terminal of the Potentiometer.
14
VCC
3
Function
System Supply Voltage.
FN8174.1
March 31, 2005
X9271
PIN DESCRIPTIONS
Potentiometer Pins
Bus Interface Pins
RH, RL
SERIAL OUTPUT (SO)
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
RW
SERIAL INPUT
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.
Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (VSS)
The VCC pin is the system supply voltage. The VSS
pin is the system ground.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the
X9271.
Other Pins
HOLD (HOLD)
HARDWARE WRITE PROTECT INPUT (WP)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause the
serial communication with the controller without resetting
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH at
all times. CMOS level input.
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
NO CONNECT.
No connect pins should be left floating. This pins are
used for Intersil manufacturing and testing purposes.
DEVICE ADDRESS (A1 - A0)
The address inputs are used to set the the 8-bit slave
address. A match in the slave address serial data
stream must be made with the address input in order
to initiate communication with the X9271.
CHIP SELECT (CS)
When CS is HIGH, the X9271 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9271, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
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FN8174.1
March 31, 2005
X9271
series. The physical ends of each array are equivalent
to the fixed terminals of a mechanical potentiometer
(RH and RL inputs).
PRINCIPLES OF OPERATION
Device Description
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(RW) output. Within each individual array only one
switch may be turned on at a time.
SERIAL INTERFACE
The X9271 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
POWER-UP AND DOWN RECOMMENDATIONS.
There are no restrictions on the power-up or powerdown conditions of VCC and the voltages applied to
the potentiometer pins provided that VCC is always
more positive than or equal to VH, VL, and VW, i.e.,
VCC ≥ VH, VL, VW. The VCC ramp rate specification is
always in effect.
ARRAY DESCRIPTION
The X9271 is comprised of a resistor array (See
Figure 1). The array contains the equivalent of 255
discrete resistive segments that are connected in
Figure 1. Detailed Potentiometer Block Diagram
SERIAL DATA PATH
RH
SERIAL
BUS
INPUT
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
REGISTER 1
(DR1)
8
8
BANK_0 Only
REGISTER 2
(DR2)
IF WCR = 00[H] THEN RW = RL
IF WCR = FF[H] THEN RW = RH
REGISTER 3
(DR3)
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR)
C
O
U
N
T
E
R
D
E
C
O
D
E
INC/DEC
LOGIC
UP/DN
MODIFIED SCK
UP/DN
CLK
RL
RW
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FN8174.1
March 31, 2005
X9271
DEVICE DESCRIPTION
Wiper Counter Register (WCR)
The X9271 contains a Wiper Counter Register for the
DCP potentiometer. The Wiper Counter Register can
be envisioned as a 8-bit parallel and serial load
counter with its outputs decoded to select one of 256
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written
directly by the host via the Write Wiper Counter
Register instruction (serial load); it may be written
indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register
instruction (parallel load); it can be modified one step
at a time by the Increment/ Decrement instruction.
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9271 is powereddown. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Power-up guidelines are recommended to ensure
proper loadings of the R0 value into the WCR. The
DR0 value of Bank 0 is the default value.
Data Registers (DR3–DR0)
The potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Bits [7:0] are used to store one of the 256 wiper
positions or data (0 ~255).
Status Register (SR)
This 1-bit Status Register is used to store the system
status.
WIP: Write In Progress status bit, read only.
– When WIP=1, indicates that high-voltage write cycle
is in progress.
– When WIP=0, indicates that no high-voltage write
cycle is in progress
Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
V
V
V
V
V
V
V
V
(MSB)
(LSB)
Table 2. Data Register, DR (8-bit), DR[7:0]: Used to store wiper positions or data (Nonvolatile, NV).
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NV
NV
NV
NV
NV
NV
NV
NV
MSB
LSB
Table 3. Status Register, SR (WIP is 1-bit)
WIP
(LSB)
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FN8174.1
March 31, 2005
X9271
Banks 1, 2, and 3 are additional banks of registers (12
total) that can be used for SPI write and read
operations. The data registers in Banks 1, 2, and 3
cannot be used for direct read/write operations
between the Wiper Counter Register.
DEVICE DESCRIPTION
Instructions
IDENTIFICATION BYTE (ID AND A)
The first byte sent to the X9271 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier. The ID[3:0]
bits is the device id for the X9271; this is fixed as
0101[B] (refer to Table 4).
The A1 - A0 bits in the ID byte is the internal slave
address. The physical device address is defined by the
state of the A1 - A0 input pins. The slave address is
externally specified by the user. The X9271 compares
the serial data stream with the address input state; a
successful compare of both address bits is required for
the X9271 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A1 - A0 inputs
can be actively driven by CMOS input signals or tied to
VCC or VSS.
INSTRUCTION BYTE (I[3:0])
The next byte sent to the X9271 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode (I[3:0]). The RB and RA bits point to one of the
four Data Registers. P0 is the POT selection; since the
X9271 is single POT, the P0=0. The format is shown in
Table 5.
Register Selection (DR0 to DR3) Table
Register
RB
0
0
1
1
RA Selection
Operations
0
0
Data Register Read and Write;
Wiper Counter Register
Operations
1
1
Data Register Read and Write;
Wiper Counter Register
Operations
0
2
Data Register Read and Write;
Wiper Counter Register
Operations
1
3
Data Register Read and Write;
Wiper Counter Register
Operations
Register Bank Selection (Bank 0 to Bank 3) Table
Bank
P1
0
0
1
1
P0 Selection
Operations
0
0
Data Register Read and Write;
Wiper Counter Register
Operations
1
1
Data Register Read and Write
Only
0
2
Data Register Read and Write
Only
1
3
Data Register Read and Write
Only
REGISTER BANK SELECTION (R1, R0, P1, P0)
There are 16 registers organized into four banks. Bank
0 is the default bank of registers. Only Bank 0 registers
can be used for data register to Wiper Counter
Register operations.
Table 4. Identification Byte Format
Device Type
Identifier
Set to 0
for proper operation
ID3
ID2
ID1
ID0
0
1
0
1
(MSB)
0
0
Internal
Slave Address
A1
A0
(LSB)
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FN8174.1
March 31, 2005
X9271
Table 5. Instruction Byte Format
P1 and P0 are used also for register Bank Selection
for SPI Register Write and Read operations
Instruction Opcode
I3
I2
I1
Pot Selection (WCR Selection)
Set to P0=0 for potentiometer operations
Register Selection
P0
RB
(MSB)
RA
P1
P0
(LSB)
DEVICE DESCRIPTION
Instructions
Five of the eight instructions are three bytes in length.
These instructions are:
– Read Wiper Counter Register – read the current
wiper position of the potentiometer;
– Write Wiper Counter Register – change current
wiper position of the potentiometer;
– Read Data Register – read the contents of the
selected Data Register;
– Write Data Register – write a new value to the
selected Data Register.
– Read Status - This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between all potentiometers and
one associated register. The Read Status Register
instruction is the only unique format (See Figure 4).
8
Two instructions require a two-byte sequence to
complete (Figure 2). These instructions transfer data
between the host and the X9271; either between the
host and one of the data registers or directly between
the host and the Wiper Counter Register. These
instructions are:
– XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register –
This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
The final command is Increment/Decrement (Figure 5
and 6). It is different from the other commands,
because it’s length is indeterminate. Once the
command is issued, the master can clock the selected
wiper up and/or down in one resistor segment steps;
thereby, providing a fine tuning capability to the host.
For each SCK clock pulse (tHIGH) while SI is HIGH,
the selected wiper will move one resistor segment
towards the RH terminal. Similarly, for each SCK clock
pulse while SI is LOW, the selected wiper will move
one resistor segment towards the RL terminal.
See Instruction format for more details.
Write in Process (WIP bit)
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a Write In Process bit
(WIP). The WIP bit is read with a Read Status
command.
FN8174.1
March 31, 2005
X9271
Figure 2. Two-Byte Instruction Sequence
CS
SCK
SI
1
0
0
ID3 ID2 ID1 ID0
0
0
0
1
0
0
A1
A0
I3
Internal
Address
Device ID
I2
I1 I0
Instruction
Opcode
0
RB RA P1 P0
Register
Address
Pot/Bank
Address
These commands only valid when P1 = P0 = 0
Figure 3. Three-Byte Instruction Sequence (Write)
CS
SCL
SI
0
1
0
1
ID3 ID2 ID1 ID0
0
0
0
0
A1 A0
Internal
Address
Device ID
I3
I1
I2
I0
Instruction
Opcode
D7 D6 D5 D4 D3 D2 D1 D0
RB RA P1 P0
Register
Address
Pot/BankWCR[7:0] valid only when P1 = P0 = 0;
Address
or
Data Register Bit [7:0] for all values of P1 and P0
Figure 4. Three-Byte Instruction Sequence (Read)
CS
SCL
SI
0
1
0
1
ID3 ID2 ID1 ID0
0
0
0
0
X
A1 A0
Internal
Address
Device ID
I3
I2
I1 I0
Instruction
Opcode
RB RA P1 P0
Register
Address
X
X
X
X
X
X
X
Don’t Care
Pot/Bank
Address
S0
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0] valid only when P1 = P0 = 0;
or
Data Register Bit [7:0] for all values of P1 and P0
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FN8174.1
March 31, 2005
X9271
Figure 5. Increment/Decrement Instruction Sequence
CS
SCL
SI
0
1
0
1
ID3 ID2 ID1 ID0
0
0
0
0
0
A1 A0
I3
Internal
Address
Device ID
I1
I2
I0
Instruction
Opcode
0
RA RB P1 P0
Register
Address
Pot/Bank
Address
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
Figure 6. Increment/Decrement Timing Limits
tWRID
SCK
SI
VOLTAGE OUT
VW
INC/DEC CMD ISSUED
Table 6. Instruction Set
Instruction Set
I0 RB RA
1
0
0
Instruction
Read Wiper Counter
Register
Write Wiper Counter
Register
Read Data Register
I3
1
I2
0
I1
0
1
0
1
0
0
1
0
1
1
Write Data Register
1
1
0
XFR Data Register to
Wiper Counter Register
1
1
XFR Wiper Counter
Register to Data Register
1
Increment/Decrement
Wiper Counter Register
Read Status (WIP bit)
Note:
P1
0
P0
Operation
1/0
0
0
1/0
1/0
1/0
1/0
1/0
0
1/0
1/0
1/0
1/0
0
1
1/0
1/0
0
0
1
1
0
1/0
1/0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
1
Read the contents of the Wiper Counter
Register
Write new value to the Wiper Counter
Register
Read the contents of the Data Register
pointed to by P1 - P0 and RB - RA
Write new value to the Data Register
pointed to by P1 - P0 and RB - RA
Transfer the contents of the Data Register
pointed to by RB - RA (Bank 0 only) to the
Wiper Counter Register
Transfer the contents of the Wiper Counter
Register to the Register pointed to by RB-RA
(Bank 0 only)
Enable Increment/decrement of the Wiper
Counter Register
Read the status of the internal write cycle, by
checking the WIP bit.
1/0 = data is one or zero
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March 31, 2005
X9271
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Device Type
Identifier
CS
Falling
Edge 0
1
0
1
Device
Addresses
Instruction
Opcode
0 0 A1 A0 1
0
0
1
DR/Bank
Addresses
0
0
0
Wiper Position
(Sent by X9271 on SO)
W
C
R
6
W
C
0
R
7
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
CS
W Rising
C Edge
R
0
Write Wiper Counter Register (WCR)
Device Type
Identifier
CS
Falling
Edge 0
1
0
1
Device
Addresses
Instruction
Opcode
0 0 A1 A0 1
0
1
0
DR/Bank
Addresses
0
0
0
Data Byte
(Sent by Host on SI)
W
C
0
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
CS
W Rising
C Edge
R
0
Read Data Register (DR)
Device Type
Device
Instruction
DR/Bank
Data Byte
CS
CS
Identifier
Addresses
Opcode
Addresses
(Sent
by
X9271 on SO)
Falling
Rising
Edge 0 1 0 1 0 0 A1 A0 1 0 1 1 RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0 Edge
Device Type
Identifier
CS
Falling
Edge 0
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Data Byte
(Sent by Host on SI)
CS
Rising
1 0 1 0 0 A1 A0 1 1 0 0 RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0 Edge
HIGH-VOLTAGE
WRITE CYCLE
Write Data Register (DR)
Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS
Falling
Edge
Device Type
Identifier
0
1
0
1
Device
Addresses
Instruction
Opcode
0 0 A1 A0 1 1 1 0
11
DR/Bank
Addresses
RB
RA
0
0
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
FN8174.1
March 31, 2005
X9271
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type
Device
CS
Identifier
Addresses
Falling
Edge 0 1 0 1 0 0 A1 A0
Instruction
Opcode
DR/Bank
Addresses
1 1 0 1 RB RA
0
0
CS
Rising
Edge
Increment/Decrement Wiper Counter Register (WCR)
Device Type
CS
Identifier
Falling
Edge 0 1 0 1
Device
Addresses
0 0
A1
A0
Instruction
Opcode
DR/Bank
Addresses
Increment/Decrement
(Sent by Master on SDA)
0 0 1 0 X X 0 0 I/D I/D
.
.
.
.
CS
Rising
I/D I/D Edge
Read Status Register (SR)
Device Type
CS
Identifier
Falling
Edge 0 1 0 1
Notes: (1)
(2)
(2)
(3)
(4)
Device
Addresses
0 0
A1
A0
Instruction
Opcode
DR/Bank
Addresses
Data Byte
(Sent by X9271 on SO)
0 1 0 1 0 0 0 1 0 0 0 0 0 0 0
WIP
CS
Rising
Edge
“A1 ~ A0”: stands for the device addresses sent by the master.
WCRx refers to wiper position data in the Wiper Counter Register
“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
“D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
“X:”: Don’t Care.
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X9271
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias..................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SCK any address input
with respect to VSS ................................. -1V to +7V
∆V = |(VH - VL)|..................................................... 5.5V
Lead temperature (soldering, 10 seconds)........ 300°C
IW (10 seconds)..................................................±6mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
-40°C
Max.
+70°C
+85°C
Supply Voltage (VCC)(4) Limits
5V ± 10%
2.7V to 5.5V
Device
X9271
X9271-2.7
ANALOG CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.)
Limits
Symbol
RTOTAL
RTOTAL
Parameter
Min.
Typ.
End to End Resistance
100
End to End Resistance
50
End to End Resistance
Tolerance
Max.
Units
Test Conditions
kΩ
T version
kΩ
U version
±20
%
Power Rating
50
mW
IW
Wiper Current
±3
mA
RW
Wiper Resistance
300
Ω
IW = ± 3mA @ VCC = 3V
RW
Wiper Resistance
150
Ω
IW = ± 3mA @ VCC = 5V
VTERM
Voltage on any RH or RL Pin
VCC
V
VSS = 0V
Noise
Resolution
VSS
-120
dBV/√Hz
0.4
%
Ref: 1V
Absolute Linearity(1)
±1
MI(3)
Rw(n)(actual) - Rw(n)(expected)(5)
Relative Linearity(2)
±0.2
MI(3)
Rw(n + 1) - [Rw(n) + MI](5)
Temperature Coefficient of
RTOTAL
±300
Ratiometric Temp. Coefficient
CH/CL/CW
25°C, each pot
Potentiometer Capacitancies
ppm/°C
20
10/10/25
ppm/°C
pF
See Macro model
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 255 or (RH - RL) / 255, single pot
(4) During power-up VCC > VH, VL, and VW.
(5) n = 0, 1, 2, …,255; m =0, 1, 2, …., 254.
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X9271
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
400
µA
fSCK = 2.5 MHz, SO = Open, VCC = 6V
Other Inputs = VSS
5
mA
fSCK = 2.5MHz, SO = Open, VCC = 6V
Other Inputs = VSS
ICC1
VCC supply current
(active)
ICC2
VCC supply current
(nonvolatile write)
ISB
VCC current (standby)
3
µA
SCK = SI = VSS, Addr. = VSS,
CS = VCC = 6V
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC + 1
V
-1
VCC x 0.3
V
0.4
V
IOL = 3mA
1
VIL
Input LOW voltage
VOL
Output LOW voltage
VOH
Output HIGH voltage
VCC - 0.8
V
IOH = -1mA, VCC ≥ +3V
VOH
Output HIGH voltage
VCC - 0.4
V
IOH = -0.4mA, VCC ≤ +3V
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
years
CAPACITANCE
Symbol
CIN/OUT
COUT
(6)
(6)
CIN(6)
Test
Max.
Units
Test Conditions
Input / Output capacitance (SI)
8
pF
VOUT = 0V
Output capacitance (SO)
8
pF
VOUT = 0V
Input capacitance (A0, CS, WP, HOLD, and
SCK)
6
pF
VIN = 0V
POWER-UP TIMING
Symbol
tr VCC
(6)
tPUR(7)
tPUW(7)
Parameter
VCC Power-up rate
Min.
Max.
Units
0.2
50
V/ms
Power-up to initiation of read operation
1
ms
Power-up to initiation of write operation
50
ms
A.C. TEST CONDITIONS
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
Notes: (6) This parameter is not 100% tested
(7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued.
These parameters are periodically sampled and not 100% tested.
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X9271
EQUIVALENT A.C. LOAD CIRCUIT
5V
SPICE Macromodel
3V
1462Ω
1382Ω
RTOTAL
RH
SO pin
RL
SO pin
2714Ω
100pF
CW
CL
1217Ω
100pF
CL
10pF
25pF
10pF
RW
AC TIMING
Symbol
Parameter
Min.
Max.
Units
2.5
MHz
fSCK
SSI/SPI clock frequency
tCYC
SSI/SPI clock cycle time
tWH
SSI/SPI clock high time
200
ns
tWL
SSI/SPI clock low time
200
ns
tLEAD
Lead time
250
ns
tLAG
Lag time
250
ns
tSU
SI, SCK, HOLD and CS input setup time
50
ns
tH
SI, SCK, HOLD and CS input hold time
50
ns
tRI
SI, SCK, HOLD and CS input rise time
2
µs
tFI
SI, SCK, HOLD and CS input fall time
2
µs
tDIS
SO output disable time
tV
SO output valid time
tHO
SO output hold time
tRO
SO output rise time
100
ns
tFO
SO output fall time
100
ns
tHOLD
HOLD time
400
ns
tHSU
HOLD setup time
100
ns
tHH
HOLD hold time
100
ns
tHZ
HOLD low to output in high Z
100
ns
tLZ
HOLD high to output in low Z
100
ns
TI
Noise suppression time constant at SI, SCK, HOLD and CS inputs
10
ns
tCS
CS deselect time
2
µs
tWPASU
WP, A0 setup time
0
ns
tWPAH
WP, A0 hold time
0
ns
15
500
0
ns
250
ns
200
ns
0
ns
FN8174.1
March 31, 2005
X9271
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
tWR
Parameter
High-voltage write cycle time (store instructions)
Typ.
Max.
Units
5
10
ms
XDCP TIMING
Symbol
Parameter
Min.
Max.
Units
tWRPO
Wiper response time after the third (last) power supply is stable
5
10
µs
tWRL
Wiper response time after instruction issued (all load instructions)
5
10
µs
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
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X9271
TIMING DIAGRAMS
Input Timing
tCS
CS
tCYC
tLEAD
SCK
tSU
tH
...
tWH
tWL
...
MSB
SI
tLAG
tRI
tFI
LSB
High Impedance
SO
Output Timing
CS
SCK
...
tV
tDIS
...
MSB
SO
SI
tHO
LSB
ADDR
Hold Timing
CS
tHSU
tHH
SCK
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
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X9271
XDCP Timing (for All Load Instructions)
CS
SCK
...
tWRL
SI
...
MSB
LSB
VWx
SO
High Impedance
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
tWPASU
tWPAH
WP
A0
A1
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X9271
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+VR
VR
RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
VS
Voltage Regulator
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Offset Voltage Adjustment
R1
Comparator with Hysterisis
R2
VS
VS
–
+
VO
100kΩ
–
VO
+
}
}
TL072
R1
R2
10kΩ
10kΩ
+12V
10kΩ
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
-12V
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X9271
Application Circuits (continued)
Attenuator
Filter
C
VS
+
R2
R1
VS
VO
–
–
R
VO
+
R3
R4
R2
R1 = R2 = R3 = R4 = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2πRC)
VO = G VS
-1/2 ≤ G ≤ +1/2
R1
R2
}
}
Inverting Amplifier
Equivalent L-R Circuit
VS
R2
C1
–
VS
VO
+
+
–
R1
ZIN
VO = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
Function Generator
C
R2
–
+
R1
–
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
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X9271
PACKAGING INFORMATION
14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8 °
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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X9271
ORDERING INFORMATION
X9271
Y
V
T
V
VCC Limits
Blank = 5V ± 10%
-2.7 = 2.7 to 5.5V
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Package
V = 14-Lead TSSOP
Potentiometer Organization
Pot
U=
50kΩ
T=
100kΩ
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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