X9401
®
Low Noise/Low Power/SPI Bus
Data Sheet
October 12, 2006
DESCRIPTION
Quad, 64 Tap, Digitally Controlled
Potentiometer (XDCP™)
The X9401 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated
microcircuit.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
FN8190.3
Quad–4 separate pots, 64 taps/pot
Nonvolatile storage of wiper position
Four Nonvolatile Data Registers for Each Pot
16-bytes of EEPROM memory
SPI serial interface
RTotal = 10kΩ
Wiper resistance = 150Ω typical
Standby current < 1µA (total package)
Operating current < 400µA max.
VCC = 2.7V to 5V
Package–24 Ld SOIC
100 year data retention
Pb-free plus anneal available (RoHS compliant)
The digitally controlled potentiometer is implemented
using 64 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. Each potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
through the switches. Power-up recalls the contents of
DR0 to the WCR.
The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide
variety of applications including control, parameter
adjustments, and signal processing.
BLOCK DIAGRAM
Pot 0
VCC
VSS
R0 R1
R2 R3
HOLD
CS
SCK
SO
SI
A0
A1
Interface
and
Control
Circuitry
VH0/RH0
Wiper
Counter
Register
(WCR)
VL0/RL0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
VH2/RH2
VL2/RL2
VW0/RW0
VW2/RW2
VW1/RW1
VW3/RW3
8
Data
WP
R0 R1
R2 R3
1
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
VH1/RH1
VL1/RL1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 3
VH3/RH3
VL3/RL3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9401
Ordering Information
PART NUMBER
PART
MARKING
VCC
LIMITS
(V)
POTENTIOMETER
TEMP
ORGANIZATION (kΩ) RANGE (°C)
PACKAGE
PKG. DWG.
#
X9401WS24IZ (Note)
X9401WS ZI
5 ±10%
10
-40 to 85
24 Ld SOIC (300 mil) (Pb-free)
MDP0027
X9401WS24I-2.7*
X9401WS G
2.7 to 5.5
10
-40 to 85
24 Ld SOIC (300 mil)
M24.3
X9401WS24IZ-2.7* (Note)
X9401WS ZG
-40 to 85
24 Ld SOIC (300 mil) (Pb-free)
MDP0027
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN DESCRIPTIONS
Device Address (A0 - A1)
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
The address inputs are used to set the least significant 2
bits of the 8-bit slave address. A match in the slave address
serial data stream must be made with the address
input in order to initiate communication with the
X9401. A maximum of 4 devices may occupy the SPI
serial bus.
Potentiometer Pins
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
VH (VH0 - VH3), VL (VL0 - VL3), RH (RH0 - RH3),
RL (RL0 - RL3)
The VH/RH and VL/RL inputs are equivalent to the
terminal connections on either end of a mechanical potentiometer.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9401.
VW (VW0 - VW3), RW (RW0 - RW3)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Chip Select (CS)
When CS is HIGH, the X9401 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9401, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Wiper Counter Registers.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence
is underway, HOLD may be used to pause the serial
communication with the controller without resetting the
serial sequence. To pause, HOLD must be brought LOW
while SCK is LOW. To resume communication, HOLD is
brought HIGH, again while SCK is LOW. If the pause
feature is not used, HOLD should be held HIGH at all
times.
2
FN8190.3
October 12, 2006
X9401
Array Description
PIN CONFIGURATION
SOIC
VCC
1
24
NC
VL0/RL0
2
23
VL3/RL3
VH0/RH0
3
22
VH3/RH3
VW0/RW0
4
21
VW3/RW3
CS
5
20
A0
WP
6
19
SO
SI
7
18
HOLD
A1
8
17
SCK
VL1/RL1
9
16
VL2/RL2
VH1/RH1
10
15
VH2/RH2
VW1/RW1
11
14
VW2/RW2
12
13
NC
V
SS
X9401
PIN NAMES
Symbol
Description
SCK
Serial Clock
SI, SO
Serial Data
A0 - A1
Device Address
VH0/RH0 - VH3/RH3,
VL0/RL0 - VL3/RL3
Potentiometers (terminal
equivalent)
VW0/RW0 - VW1/RW1
Potentiometers (wiper
equivalent)
WP
Hardware Write Protection
VCC
System Supply Voltage
VSS
System Ground
NC
No Connection
DEVICE DESCRIPTION
The X9401 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9401 supports the SPI interface hardware conventions. The device is accessed via the SI input with
data clocked in on the rising SCK. CS must be LOW
and the HOLD and WP pins must be HIGH during the
entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
3
The X9401 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (VH/RH and VL/RL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(VW/RW) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded
to select, and enable, one of sixty-four switches.
Wiper Counter Register (WCR)
The X9401 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its
outputs decoded to select one of sixty-four switches
along its resistor array. The contents of the WCR can
be altered in four ways: it may be written directly by
the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data
registers via the XFR Data Register or Global XFR
Data Register instructions (parallel load); it can be
modified one step at a time by the Increment/Decrement instruction. Finally, it is loaded with the contents
of its data register zero (R0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9401 is powereddown. Although the register is automatically loaded
with the value in R0 upon power-up, this may be different from the value present at power-down. The wiper
position must be stored in R0 to insure restoring the
wiper position after power-up.
Data Registers
Each potentiometer has four 6-bit nonvolatile data registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four data registers and the associated Wiper Counter
Register. All operations changing data in one of the
data registers is a nonvolatile operation and will take a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the data registers can
be used as memory locations for system parameters
or user preference data.
FN8190.3
October 12, 2006
X9401
Figure 2. Instruction Byte Format
Data Register Detail
(MSB)
(LSB)
D5
D4
D3
D2
D1
D0
NV
NV
NV
NV
NV
NV
Register
Select
I3
I2
I1
I0
R1
R0
P1
P0
Write in Process
The contents of the Data Registers are saved to nonvolatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write operation can be monitored by a Write In Process bit (WIP).
The WIP bit is read with a Read Status command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9401 from the host, following a CS going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave
address are a device type identifier, for the X9401 this
is fixed as 0101[B] (refer to Figure 1).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A0 - A1 input
pins. The X9401 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9401 to successfully
continue the command sequence. The A0 - A1 inputs
can be actively driven by CMOS input signals or tied to
VCC or VSS.
The remaining two bits in the slave byte must be set to 0.
Figure 1. Identification Byte Format
Device Type
Identifier
0
1
0
1
0
0
A1
A0
Device Address
Instruction Byte
The next byte sent to the X9401 contains the instruction and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the four pots and, when applicable,
they point to one of four associated registers. The format is shown below in Figure 2.
4
Instructions
Pot Select
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select
one of the four registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits (P1 and P0) selects which one of the four potentiometers is to be affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
These instructions are:
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register—This
transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
– Global XFR Data Register to Wiper Counter Register
—This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
– Global XFR Wiper Counter Register to Data
Register—This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.
The basic sequence of the two byte instructions is illustrated in Figure 3. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a data register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper
to this action will be delayed by tWRL. A transfer from
the WCR (current wiper position), to a data register is a
write to nonvolatile memory and takes a minimum of
tWR to complete. The transfer can occur between one
of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer
occurs between all potentiometers and one associated
register.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9401; either between the host and
FN8190.3
October 12, 2006
X9401
The sequence of these operations is shown in Figure 4
and Figure 5.
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are:
The final command is Increment/Decrement. It is different from the other commands, because it’s length is
indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning capability to the host. For each SCK clock pulse
(tHIGH) while SI is HIGH, the selected wiper will move
one resistor segment towards the VH/RH terminal.
Similarly, for each SCK clock pulse while SI is LOW,
the selected wiper will move one resistor segment
towards the VL/RL terminal. A detailed illustration of the
sequence and timing for this operation are shown in
Figure 6 and Figure 7.
– Read Wiper Counter Register— read the current
wiper position of the selected pot,
– Write Wiper Counter Register—change current
wiper position of the selected pot,
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
Serial
Bus
Input
From Interface
Circuitry
Register 0
Register 1
8
Register 2
If WCR = 00[H] then VW/RW = VL/RL
If WCR = 3F[H] then VW/RW = VH/RH
6
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
Register 3
UP/DN
Modified SCL
VH/RH
C
o
u
n
t
e
r
D
e
c
o
d
e
INC/DEC
Logic
UP/DN
CLK
VL/RL
VW/RW
5
FN8190.3
October 12, 2006
X9401
Figure 3. Two-Byte Command Sequence
CS
SCK
SI
0
1
0
1
0
0
A1
A0
I3
I2
I1
I0
R1 R0
P1 P0
Figure 4. Three-Byte Command Sequence (Write)
CS
SCL
SI
0
1
0
0
1
0
A1 A0
I3
I2
I1 I0
R1 R0 P1 P0
0
0
D5 D4 D3 D2 D1 D0
Figure 5. Three-Byte Command Sequence (Read)
CS
SCL
SI
Don’t Care
0
1
0
0
1
0
A1 A0
I3
I2
I1 I0
R1 R0 P1 P0
S0
0
0
D5 D4 D3 D2 D1 D0
Figure 6. Increment/Decrement Command Sequence
CS
SCK
SI
0
1
0
1
0
6
0
A1 A0
I3
I2
I1
I0
0
0
P1
P0
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
FN8190.3
October 12, 2006
X9401
Figure 7. Increment/Decrement Timing Limits
tWRID
SCK
SI
Voltage Out
VW/RW
INC/DEC CMD Issued
Table 1. Instruction Set
Read Wiper Counter Register
Instruction
I3
1
I2
0
Write Wiper Counter Register
1
0
Read Data Register
1
0
Write Data Register
1
1
XFR Data Register to Wiper
Counter Register
1
1
XFR Wiper Counter Register
to Data Register
1
1
Global XFR Data Register to
Wiper Counter Register
0
0
Global XFR Wiper Counter
Register to Data Register
1
0
Increment/Decrement Wiper
Counter Register
Read Status (WIP bit)
0
0
0
1
7
Instruction Set
Operation
I1 I0 R1 R0 P1 P0
0 1 0
0 P1 P0 Read the contents of the Wiper Counter Register
pointed to by P1 - P0
1 0 0
0 P1 P0 Write new value to the Wiper Counter Register
pointed to by P1 - P0
1 1 R1 R0 P1 P0 Read the contents of the Data Register pointed to by
P1 - P0 and R1 - R0
0 0 R1 R0 P1 P0 Write new value to the Data Register pointed to by
P1 - P0 and R1 - R0
0 1 R1 R0 P1 P0 Transfer the contents of the Data Register pointed to
by R1 - R0 to the Wiper Counter Register pointed to by
P1 - P0
1 0 R1 R0 P1 P0 Transfer the contents of the Wiper Counter Register
pointed to by P1 - P0 to the Register pointed to by
R1 - R0
0 1 R1 R 0 0
0 Transfer the contents of the Data Registers pointed to
by R1 - R0 of all four pots to their respective Wiper
Counter Register
0 0 R1 R 0 0
0 Transfer the contents of all Wiper Counter Registers
to their respective data Registers pointed to by
R1 - R0 of all four pots
1 0 0
0 P1 P0 Enable Increment/decrement of the Wiper Counter
Register pointed to by P1 - P0
0 1 0
0
0
1 Read the status of the internal write cycle, by
checking the WIP bit.
FN8190.3
October 12, 2006
X9401
Instruction Format
Notes: (1)
(2)
(3)
(4)
“A1 ~ A0”: stands for the device addresses sent by the master.
WPx refers to wiper position data in the Counter Register
“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
“D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
CS
Falling
Edge 0 1 0 1 0 0 A A 1
1 0
0
0
WCR
addresses
1
0
wiper position
(sent by X9401 on SO)
CS
W W W W W W Rising
P P
0
0 0 P P P P P P Edge
1 0
5 4 3 2 1 0
Write Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
CS
Falling
Edge 0 1 0 1 0 0 A A 1
1 0
0
1
WCR
addresses
0
0
Data Byte
(sent by Host on SI)
CS
W W W W W W Rising
P P
0
0 0 P P P P P P Edge
1 0
5 4 3 2 1 0
Read Data Register (DR)
device type
identifier
device
addresses
instruction
opcode
DR and WCR
addresses
CS
Falling
Edge 0 1 0 1 0 0 A A 1 0 1 1 R R P
1 0
1 0 1
Data Byte
(sent by X9401 on SO)
CS
W W W W W W Rising
P
0 0 P P P P P P Edge
0
5 4 3 2 1 0
Write Data Register (DR)
device type
device
identifier
addresses
instruction
opcode
DR and WCR
addresses
CS
Falling
Edge 0 1 0 1 0 0 A A 1 1 0 0 R
1 0
1
R
0
P
1
P
0
Data Byte
(sent by host on SI)
CS
W W W W W W Rising
0 0 P P P P P P Edge
5 4 3 2 1 0
HIGH-VOLTAGE
WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
device
instruction DR and WCR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 1 0 1 R R P P Edge
1 0
1 0 1 0
8
FN8190.3
October 12, 2006
X9401
Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
device
instruction DR and WCR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 1 1 0 R R P P Edge
1 0
1 0 1 0
HIGH-VOLTAGE
WRITE CYCLE
Increment/Decrement Wiper Counter Register (WCR)
device type
device
instruction
WCR
increment/decrement
CS
CS
identifier
addresses
opcode
addresses (sent by master on SDA)
Falling
Rising
Edge 0 1 0 1 0 0 A A 0 0 1 0 X X P P I/ I/ . . . . I/ I/ Edge
1 0
1 0 D D
D D
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
device
instruction
DR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 0 0 0 1 R R 0 0 Edge
1 0
1 0
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
device
instruction
DR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 0 0 0 R R 0 0 Edge
1 0
1 0
HIGH-VOLTAGE
WRITE CYCLE
Read Status
device type
identifier
device
addresses
instruction
opcode
wiper
addresses
Data Byte
(sent by X9401 on SO)
CS
CS
Falling
W Rising
Edge 0 1 0 1 0 0 A A 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 I Edge
1 0
P
9
FN8190.3
October 12, 2006
X9401
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SCK, SCL or any address
input with respect to VSS ......................... -1V to +7V
ΔV = |(VH–VL)|...................................................... 5.5V
Lead temperature (soldering, 10s) .................. +300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
-40°C
Max.
+70°C
+85°C
Device
X9401
X9401-2.7
Supply Voltage (VCC) Limits
5V ± 10%
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
RTOTAL
Parameter
End to end resistance
Min.
Typ.
Max.
Unit
–20
+20
%
50
mW
–6
+6
mA
500
Ω
Wiper Current = ± 3mA
VCC
V
VSS = 0V
-120
dBV
Ref: 1kHz
1.6
%
Power rating
IW
Wiper current
RW
Wiper resistance
VTERM
Voltage on any VH or VL Pin
150
VSS
Noise
Resolution
Absolute linearity (1)
Relative linearity (2)
Temperature coefficient of RTOTAL
-1
-0.2
+1
MI(3)
+0.2
MI(3)
±20
ppm/°C
±300
Ratiometric temp. coefficient
CH/CL/CW
Potentiometer capacitances
10/10/25
IAL
RH, RL, RW leakage current
0.1
Test Condition
+25°C, each pot
Vw(n)(actual) - Vw(n)(expected)
Vw(n + 1) - [Vw(n) + MI]
ppm/°C
10
pF
See Macro model
µA
VIN = VSS to VCC. Device is in
stand-by mode.
POWER-UP AND DOWN REQUIREMENTS
The are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW.
The VCC power-up spec is always in effect.
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (VH - VL)/63, single pot
10
FN8190.3
October 12, 2006
X9401
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
400
µA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ICC1
VCC supply current (active)
ICC2
VCC supply current (nonvolatile write)
1
mA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ISB
VCC current (standby)
1
µA
SCK = SI = VSS, Addr. = VSS,
CS = VCC
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC + 0.5
V
VIL
Input LOW voltage
-0.5
VCC x 0.1
V
VOL
Output LOW voltage
0.4
V
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Unit
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
years
CAPACITANCE
Symbol
COUT
(4)
CIN(4)
Test
Max.
Unit
Test Condition
Output capacitance (SO)
8
pF
VOUT = 0V
Input capacitance (A0, A1, SI, and SCK)
6
pF
VIN = 0V
POWER-UP TIMING
Symbol
tr VCC
(6)
tPUR(5)
tPUW(5)
Parameter
VCC Power-up rate
Min.
Max.
Unit
0.2
50
V/ms
Power-up to initiation of read operation
1
ms
Power-up to initiation of write operation
5
ms
A.C. TEST CONDITIONS
EQUIVALENT A.C. LOAD CIRCUIT
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
Notes: (4) This parameter is periodically sampled and not 100%
tested
(5) tPUR and tPUW are the delays required from the time
the (last) power supply (VCC-) is stable until the specific
instruction can be issued. These parameters are periodically sampled and not 100% tested.
(6) This is not a tested or guaranteed parameter and should
be used only as a guideline.
11
SPICE Macro Model
5V
1533Ω
SDA
Output
RTOTAL
RH
CW
CL
100pF
25pF
RL
CL
10pF
10pF
RW
FN8190.3
October 12, 2006
X9401
AC TIMING
Symbol
Parameter
Min.
Max.
Unit
2.0
MHz
fSCK
SSI/SPI clock frequency
tCYC
SSI/SPI clock cycle rime
500
ns
tWH
SSI/SPI clock high rime
200
ns
tWL
SSI/SPI clock low time
200
ns
tLEAD
Lead time
250
ns
tLAG
Lag time
250
ns
tSU
SI, SCK, HOLD and CS input setup time
50
ns
tH
SI, SCK, HOLD and CS input hold time
50
ns
tRI
SI, SCK, HOLD and CS input rise time
2
µs
tFI
SI, SCK, HOLD and CS input fall time
2
µs
500
ns
100
ns
tDIS
SO output disable time
0
tV
SO output valid time
tHO
SO output hold time
tRO
SO output rise time
50
ns
tFO
SO output fall time
50
ns
tHOLD
0
ns
HOLD time
400
ns
tHSU
HOLD setup time
100
ns
tHH
HOLD hold time
100
ns
tHZ
HOLD low to output in high Z
100
ns
tLZ
HOLD high to output in low Z
100
ns
TI
Noise suppression time constant at SI, SCK, HOLD and CS inputs
20
ns
tCS
CS deselect time
2
µs
tWPASU
WP, A0 and A1 setup time
0
ns
tWPAH
WP, A0 and A1 hold time
0
ns
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
tWR
High-voltage write cycle time (store instructions)
Typ.
Max.
Unit
5
10
ms
XDCP TIMING
Symbol
Max.
Unit
Wiper response time after the third (last) power supply is stable
10
µs
tWRL
Wiper response time after instruction issued (all load instructions)
10
µs
tWRID
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
450
ns
tWRPO
Parameter
12
Min.
FN8190.3
October 12, 2006
X9401
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
TIMING DIAGRAMS
Input Timing
tCS
CS
tCYC
tLEAD
SCK
tSU
tH
...
tWL
tRI
tFI
tWH
...
MSB
SI
tLAG
LSB
High Impedance
SO
Output Timing
CS
SCK
tV
MSB
SO
SI
tHO
...
...
tDIS
LSB
ADDR
13
FN8190.3
October 12, 2006
X9401
Hold Timing
CS
tHSU
tHH
SCK
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
XDCP Timing (for All Load Instructions)
CS
SCK
...
SI
...
MSB
tWRL
LSB
VW/RW
SO
High Impedance
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
...
tWRID
...
VW/RW
ADDR
SI
Inc/Dec
Inc/Dec
...
High Impedance
SO
14
FN8190.3
October 12, 2006
X9401
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
tWPASU
WP
tWPAH
A0
A1
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+VR
VR
VW/RW
I
Three terminal Potentiometer;
Variable voltage divider
15
Two terminal Variable Resistor;
Variable current
FN8190.3
October 12, 2006
X9401
Application Circuits
NONINVERTING AMPLIFIER
VS
VOLTAGE REGULATOR
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
OFFSET VOLTAGE ADJUSTMENT
R1
COMPARATOR WITH HYSTERESIS
R2
VS
VS
–
VO
+
–
100kΩ
VO
+
R1
}
}
TL072
R2
10kΩ
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
10kΩ
10kΩ
+5V
ATTENUATOR
FILTER
C
VS
R2
R1
–
VS
+
+
VO
R
R3
R4
All RS = 10kΩ
V O = G VS
-1/2 ≤ G ≤ +1/2
16
VO
–
R2
R1
GO = 1 + R2/R1
fc = 1/(2πRC)
FN8190.3
October 12, 2006
X9401
Application Circuits (continued)
R2
}
VS
R1
}
INVERTING AMPLIFIER
EQUIVALENT L-R CIRCUIT
R2
C1
–
VS
VO
+
+
–
R1
ZIN
VO = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
FUNCTION GENERATOR
C
R2
–
+
R1
–
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
17
FN8190.3
October 12, 2006
X9401
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
N
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.020
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.5985
0.6141
15.20
15.60
3
E
0.2914
0.2992
7.40
7.60
4
e
α
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
0.05 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
24
0°
24
8°
0°
7
8°
Rev. 1 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
18
FN8190.3
October 12, 2006
X9401
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
SO-8
SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
N
8
14
16
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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19
FN8190.3
October 12, 2006