PCA9620
60 x 8 LCD high-drive segment driver for automotive and
industrial
Rev. 4 — 8 April 2015
Product data sheet
1. General description
The PCA9620 is a peripheral device which interfaces to almost any Liquid Crystal Display
(LCD)1 with low multiplex rates. It generates the drive signals for any static or multiplexed
LCD containing up to eight backplanes, 60 segments, and up to 480 elements. The
PCA9620 is compatible with most microprocessors or microcontrollers and communicates
via a two-line bidirectional I2C-bus. Communication overheads are minimized using a
display RAM with auto-incremented addressing and display memory switching. The
PCA9620 features an internal charge pump with internal capacitors for on-chip generation
of the LCD driving voltages.
For a selection of NXP LCD segment drivers, see Table 44 on page 74.
2. Features and benefits
1.
AEC Q100 grade 2 compliant for automotive applications
Low power consumption
Extended operating temperature range from 40 C to +105 C
60 segments and 8 backplanes allowing to drive:
up to 60 7-segment alphanumeric characters
up to 30 14-segment alphanumeric characters
any graphics of up to 480 elements
480-bit RAM for display data storage
Selectable backplane drive configuration: static, 2, 4, 6, or 8 backplane multiplexing
Programmable internal charge pump for on-chip LCD voltage generation up to
3 VDD2
400 kHz I2C-bus interface
Selectable linear temperature compensation of VLCD
Selectable display bias configuration
Wide range for digital and analog power supply: from 2.5 V to 5.5 V
Wide LCD supply range: from 2.5 V for low threshold LCDs and up to 9.0 V for high
threshold (automobile) twisted nematic LCDs
Display memory bank switching in static, duplex, and quadruplex drive modes
Programmable frame frequency in steps of 10 Hz in the range of 60 Hz to 300 Hz;
factory calibrated with a tolerance of 15 % covering the whole temperature and
voltage range
Selectable inversion scheme for LCD driving waveforms: frame or line inversion
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21 on page 76.
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
Integrated temperature sensor with temperature readout
On chip calibration of internal oscillator frequency and VLCD
3. Applications
Automotive
Instrument cluster
Car radio
Climate control units
Industrial
Machine control systems
Measuring equipment
Signage
Information boards
Panels
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
PCA9620H
LQFP80
plastic low profile quad flat package; 80 leads;
body 12 12 1.4 mm
SOT315-1
PCA9620U
bare die
80 bonding pads
PCA9620U
4.1 Ordering options
Table 2.
Ordering options
Product type number
Sales item (12NC)
Orderable part
number
IC
revision
Delivery form
PCA9620H/Q900/1
935291899518
PCA9620H/Q900/1,51
1
tape and reel, 13 inch, dry pack
PCA9620U/5GA/Q1
935295801015
PCA9620U/5GA/Q1,01 1
wafer, unsawn
5. Marking
Table 3.
PCA9620
Product data sheet
Marking codes
Type number
Marking code
PCA9620H
PCA9620H/Q900
PCA9620U
PC9620-1
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
6. Block diagram
9/&'
%3WR%3
6WR6
9''
%$&.3/$1(
2873876
',63/$<6(*0(172873876
/&'
92/7$*(
6(/(&725
&+$5*(
3803
92/7$*(
08/7,3/,(5
',63/$<5(*,67(5
',63/$<
&21752/
287387%$1.6(/(&7
/&'%,$6
*(1(5$725
966
',63/$<5$0
&/.
7(03(5$785(
6(1625
&/2&.6(/(&7
$1'7,0,1*
26&,//$725
32:(521
5(6(7
6&/
3&$
&200$1'
'(&2'(5
:5,7('$7$
&21752/
'$7$32,17(5
$872,1&5(0(17
,&%86
&21752//(5
6'$
$
$
9''
7 7 7
DDD
(1) The charge pump can generate a maximum output voltage of 3 VDD2.
Fig 1.
Block diagram of PCA9620
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
4 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
7. Pinning information
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7.1 Pinning
6
6'$
6
6&/
6
$
6
$
6
&/.
6
7
6
7
6
7
6
966
6 9''
3&$+
6 9''
6 6 6 6 6 6 6 6 6 6 6 %3
6 %3
6 6 %3
6 6 %3
6 6 %3
6 6 %3
6 6 %3
6 6 %3
6 6 9/&'
6 6 6 DDD
Top view. For mechanical details, see Figure 58 on page 64.
Fig 2.
PCA9620
Product data sheet
Pin configuration for LQFP80 (PCA9620H)
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
5 of 84
PCA9620
NXP Semiconductors
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
60 x 8 LCD high-drive segment driver for automotive and industrial
6
6'$
6
6&/
6
$
6
$
6
&/.
6
7
6
7
6
7
6
966
6
9''
6
9''
6
9/&'
6
%3
6
%3
6
%3
6
%3
6
%3
6
%3
6
%3
6
%3
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3&$8
DDD
Viewed from active side. For mechanical details, see Figure 59 on page 65.
Fig 3.
PCA9620
Product data sheet
Pin configuration for PCA9620U (bare die)
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
7.2 Pin description
Table 4.
Pin description
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.
Symbol
Pin
Type
Description
S0 to S59
61 to 80 and
1 to 40
output
LCD segment
BP0 to BP7
41 to 48
output
LCD backplane
VLCD
49
supply/output[1]
LCD supply voltage
VDD2
50
supply
supply voltage 2 (charge pump)
VDD1
51
supply
supply voltage 1 (analog and digital)
VSS
52
supply
ground supply voltage
T1 to T3
53 to 55
input
test pins; must be tied to VSS in applications
CLK
56
input/output
internal oscillator output, external oscillator input
A0, A1
57, 58
input
I2C-bus slave address selection bit
SCL
59
input
I2C-bus serial clock
SDA
60
input/output
I2C-bus serial data
[1]
PCA9620
Product data sheet
When the internal VLCD generation is used, this pin drives the VLCD voltage. In this case pin VLCD is an
output. When the external supply is requested, then pin VLCD is an input and VLCD can be supplied to it. In
this case, the internal charge pump must be disabled (see Table 9 on page 10).
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
7 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
8. Functional description
The PCA9620 is a versatile peripheral device designed to interface any microprocessor or
microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed
LCD containing up to 480 elements.
8.1 Commands of PCA9620
The PCA9620 is controlled by 22 commands, which are defined in Table 5. Any other
combinations of operation code bits that are not mentioned in this document may lead to
undesired operation modes of PCA9620.
Table 5.
Commands of PCA9620
Command name
initialize
Bits
Reference
7
6
5
4
3
2
1
0
0
0
1
1
1
0
1
0
Section 8.1.1
OTP-refresh
1
1
0
1
0
0
0
0
Section 8.1.2
oscillator-ctrl
1
1
0
0
1
1
COE
OSC
Section 8.1.3
charge-pump-ctrl
1
1
0
0
0
0
CPE
CPC
Section 8.1.4
temp-msr-ctrl
1
1
0
0
1
0
TCE
TME
Section 8.1.5
temp-comp-SLA
0
0
0
1
1
SLA[2:0]
temp-comp-SLB
0
0
1
0
0
SLB[2:0]
temp-comp-SLC
0
0
1
0
1
SLC[2:0]
temp-comp-SLD
0
0
1
1
0
SLD[2:0]
Table 30
set-VPR-MSB
0
1
0
0
VPR[7:4]
set-VPR-LSB
0
1
0
1
VPR[3:0]
Section 8.1.6
display-enable
0
0
1
1
1
0
set-MUX-mode
0
0
0
0
0
M[2:0]
set-bias-mode
1
1
0
0
0
1
load-data-pointer
1
0
P[5:0]
frame-frequency
0
1
1
F[4:0]
input-bank-select
0
0
0
0
1
IB[2:0]
output-bank-select
0
0
0
1
0
OB[2:0]
write-RAM-data
B[7:0]
Section 8.1.13
temp-read
TD[7:0]
Section 8.1.14,
Section 8.4.7
invmode_CPF_ctrl
1
1
0
1
0
1
LF
CPF
Section 8.1.15
temp-filter
1
1
0
1
0
0
1
TFE
Section 8.1.16
0
E
Section 8.1.7
Section 8.1.8
B[1:0]
Section 8.1.9
Section 8.1.10
Section 8.1.11
Section 8.1.12.1
8.1.1 Command: initialize
This command generates a chip-wide reset which resets all command values to their
default values (see Table 26 on page 18). It must be sent to the PCA9620 after power-on.
After this command is sent, it is possible to send additional commands without the need to
re-initialize the interface. Reset takes 100 ns to complete.
For further information, see Section 8.3 on page 17.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
8 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
Table 6.
Initialize - initialize command bit description
Bit
Symbol
Value
Description
7 to 0
-
00111010
fixed value
8.1.2 Command: OTP-refresh
In order to achieve the specified accuracy of VLCD, the frame frequency, and the
temperature measurement, each IC is calibrated during production and testing of the
device. This calibration is performed on EPROM cells called One Time Programmable
(OTP) cells. These cells are read by the device at power-on and every time when the
initialize command or the OTP-refresh command is sent. This command will take
approximately 10 ms to finish.
Table 7.
OTP-refresh - OTP-refresh command bit description
Bit
Symbol
Value
Description
7 to 0
-
11010000
fixed value
8.1.3 Command: oscillator-ctrl
The oscillator-ctrl command switches between internal and external oscillator and enables
or disables pin CLK.
Table 8.
Oscillator-ctrl - oscillator control command bit description
For further information, see Section 8.5 on page 41.
Bit
Symbol
Value
Description
7 to 2
-
110011
fixed value
1
COE
0
[1]
PCA9620
Product data sheet
control pin CLK
0[1]
clock signal not available on pin CLK;
pin CLK is in 3-state and may be left floating
1
clock signal available on pin CLK
OSC
oscillator source
0[1]
internal oscillator running
1
external oscillator used;
pin CLK becomes an input
Default value.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
9 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
8.1.4 Command: charge-pump-ctrl
The charge-pump-ctrl command enables or disables the internal VLCD generation and
controls the charge pump voltage multiplier setting.
Table 9.
Charge-pump-ctrl - charge pump control command bit description
Bit
Symbol
Value
Description
7 to 2
-
110000
fixed value
1
CPE
0
[1]
charge pump switch
0[1]
charge pump disabled;
no internal VLCD generation;
external supply of VLCD
1
charge pump enabled
CPC
charge pump voltage multiplier setting
0[1]
VLCD = 2 VDD2
1
VLCD = 3 VDD2
Default value.
8.1.5 Command: temp-msr-ctrl
The temp-msr-ctrl command enables or disables the temperature measurement block and
the temperature compensation of VLCD.
Table 10. Temp-msr-ctrl - temperature measurement control command bit description
For further information, see Section 8.4.8 on page 39.
Bit
Symbol
Value
Description
7 to 2
-
110010
fixed value
1
TCE
temperature compensation switch
0
no temperature compensation of VLCD
possible
1[1]
0
temperature compensation of VLCD possible
TME
temperature measurement switch
0
temperature measurement disabled;
1[1]
temperature measurement enabled;
no temperature readout possible
temperature readout possible
[1]
Default value.
8.1.6 Command: set-VPR-MSB and set-VPR-LSB
With these two instructions, it is possible to set the target VLCD voltage for the internal
charge pump, see Section 8.4.3 on page 34.
Table 11.
Bit
Symbol
Value
Description
7 to 4
-
0100
fixed value
VPR[7:4]
0000[1]
3 to 0
[1]
PCA9620
Product data sheet
Set-VPR-MSB - set VPR MSB command bit description
to 1111 the four most significant bits of VPR[7:0]
Default value.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
10 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
Table 12.
Set-VPR-LSB - set VPR LSB command bit description
Bit
Symbol
Value
Description
7 to 4
-
0101
fixed value
VPR[3:0]
0000[1]
3 to 0
[1]
to 1111 the four least significant bits of VPR[7:0]
Default value.
8.1.7 Command: display-enable
Table 13.
Display-enable - display enable command bit description
Bit
Symbol
Value
Description
7 to 1
-
0011100
fixed value
0
E
0[1]
display disabled;
backplane and segment outputs are internally
connected to VSS
1
display enabled
[1]
Default value.
8.1.8 Command: set-MUX-mode
Table 14.
Set-MUX-mode - set multiplex drive mode command bit description
Bit
Symbol
Value
Description
7 to 3
-
00000
fixed value
2 to 0
M[2:0]
000[1], 011,
110, 111
1:8 multiplex drive mode: 8 backplanes
001
static drive mode: 1 backplane
010
1:2 multiplex drive mode: 2 backplanes
100
1:4 multiplex drive mode: 4 backplanes
101
1:6 multiplex drive mode: 6 backplanes
[1]
Default value.
8.1.9 Command: set-bias-mode
Table 15.
Set-bias-mode - set bias mode command bit description
Bit
Symbol
Value
Description
7 to 2
-
110001
fixed value
B[1:0]
00[1],
1⁄
4
bias
11
1⁄
3
bias
10
1⁄
2
bias
1 to 0
[1]
01
Default value.
8.1.10 Command: load-data-pointer
The load-data-pointer command defines one of the 60 display RAM addresses where the
following display data will be sent to. For further information, see Section 8.9.1 on
page 44.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
11 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
Table 16.
Load-data-pointer - load data pointer command bit description
Bit
Symbol
Value
Description
7 to 6
-
10
fixed value
5 to 0
P[5:0]
000000 to
111111
6-bit binary value of 0 to 59
8.1.11 Command: frame-frequency
With the frame-frequency command, the frame frequency and the output clock frequency
can be configured.
Table 17.
Bit
Symbol
Value
Description
7 to 5
-
011
fixed value
4 to 0
F[4:0]
see Table 18
nominal frame frequency (Hz)
Table 18.
Product data sheet
Frame frequency values
F[4:0]
Nominal frame
frequency, ffr (Hz)[1]
Resultant oscillator
frequency, fosc (Hz)
Duty cycle (%)[2]
00000
60
2880
20 : 80
00001
70
3360
7 : 93
00010
80
3840
47 : 53
00011
91
4368
40 : 60
00100
100
4800
33 : 67
00101
109
5232
27 : 73
00110
120
5760
20 : 80
00111
129.7
6226
13 : 87
01000
141.2
6778
5 : 95
01001
150
7200
50 : 50
01010
160
7680
47 : 53
01011
171.4
8227
43 : 57
01100
177.8
8534
41 : 59
01101
192
9216
36 : 64
01110[3]
200
9600
33 : 67
01111
208.7
10018
30 : 70
10000
218.2
10474
27 : 73
10001
228.6
10973
23 : 77
10010
240
11520
20 : 80
10011
252.6
12125
16 : 84
10100, 10101
266.7
12802
10 : 90
10110, 10111
282.4
13555
5 : 95
11000 to 11111
300
14400
50 : 50
[1]
PCA9620
Frame frequency - frame frequency and output clock frequency command bit
description
Nominal frame frequency calculated for the default clock frequency of 9600 Hz.
[2]
Duty cycle definition: % HIGH-level time : % LOW-level time.
[3]
Default value.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
12 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
8.1.12 Bank select commands
For multiplex drive modes 1:4, 1:2 and static drive mode, it is possible to write data to one
area of the RAM while displaying from another. These areas are named as RAM banks.
Input and output banks can be set independently from one another with the
input-bank-select and the output-bank-select command. For further information, see
Section 8.9.2 on page 49.
8.1.12.1
Command: input-bank-select
Input-bank-select - input bank select command bit description[1]
Table 19.
8.1.12.2
Bit
Symbol
Value
Description
7 to 3
-
00001
fixed value
2 to 0
IB[2:0]
Product data sheet
static drive mode
1:2 drive mode
1:4 drive mode
000[2]
bank 0: RAM-row 0
001
bank 1: RAM-row 1
bank 0: RAM-rows 0
and 1
bank 0: RAM-rows 0,
1, 2, and 3
010
bank 2: RAM-row 2
011
bank 3: RAM-row 3
100
bank 4: RAM-row 4
101
bank 5: RAM-row 5
110
bank 6: RAM-row 6
111
bank 7: RAM-row 7
[1]
Not applicable for multiplex drive mode 1:6 and 1:8.
[2]
Default value.
bank 2: RAM-rows 2
and 3
bank 4: RAM-rows 4
and 5
bank 4: RAM-rows 4,
5, 6, and 7
bank 6: RAM-rows 6
and 7
Command: output-bank-select
Output-bank-select - output bank select command bit description[1]
Table 20.
PCA9620
selects RAM bank to write to
Bit
Symbol
Value
Description
7 to 3
-
00010
fixed value
2 to 0
OB[2:0]
selects RAM bank to read from to the LCD
static drive mode
1:2 drive mode
1:4 drive mode
000[2]
bank 0: RAM-row 0
001
bank 1: RAM-row 1
bank 0: RAM-rows 0
and 1
bank 0: RAM-rows 0,
1, 2, and 3
010
bank 2: RAM-row 2
011
bank 3: RAM-row 3
100
bank 4: RAM-row 4
101
bank 5: RAM-row 5
110
bank 6: RAM-row 6
111
bank 7: RAM-row 7
[1]
Not applicable for multiplex drive mode 1:6 and 1:8.
[2]
Default value.
bank 2: RAM-rows 2
and 3
bank 4: RAM-rows 4
and 5
bank 6: RAM-rows 6
and 7
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
bank 4: RAM-rows 4,
5, 6, and 7
© NXP Semiconductors N.V. 2015. All rights reserved.
13 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
8.1.13 Command: write-RAM-data
The write-RAM-data command writes data byte-wise to the RAM. After Power-On Reset
(POR) the RAM content is random and should be brought to a defined status by clearing it
(setting it logic 0).
Write-RAM-data - write RAM data command bit description[1]
Table 21.
Bit
Symbol
Value
Description
7 to 0
B[7:0]
00000000 to
11111111
writing data byte-wise to RAM
[1]
For this command bit RS of the control byte has to be set logic 1 (see Table 34 on page 55).
More information about the display RAM can be found in Section 8.9 on page 43.
8.1.14 Command: temp-read
The temp-read command allows reading out the temperature values measured by the
internal temperature sensor.
Table 22. Temp-read - temperature readout command bit description[1]
For further information, see Table 10 on page 10 and Section 8.4.7 on page 38.
Bit
Symbol
Value
Description
7 to 0
TD[7:0]
00000000 to
11111111
readout representing the digital temperature
[1]
For this command bit R/W of the I2C-bus slave address byte has to be set logic 1 (see Table 33 on
page 54).
8.1.15 Command: invmode_CPF_ctrl
The invmode_CPF_ctrl command allows changing the drive scheme inversion mode and
the charge pump frequency.
The waveforms used to drive LCD displays inherently produce a DC voltage across the
display cell. The PCA9620 compensates for the DC voltage by inverting the waveforms on
alternate frames or alternate lines. The choice of compensation method is determined
with the LF bit.
Table 23.
Bit
Symbol
Value
Description
7 to 2
-
110101
fixed value
1
LF
0
[1]
PCA9620
Product data sheet
Invmode_CPF_ctrl - inversion mode and charge pump frequency prescaler
command bit description
set inversion mode
0[1]
line inversion mode
1
frame inversion mode
CPF
set charge pump oscillator frequency
0[1]
fosc(cp) ~ 1 MHz
1
fosc(cp) ~ 500 kHz
Default value.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
14 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
In frame inversion mode, the DC value is compensated across two frames and not within
one frame. Changing the inversion mode to frame inversion reduces the power
consumption, therefore it is useful when power consumption is a key point in the
application.
Frame inversion may not be suitable for all applications. The RMS voltage across a
segment is better defined, however since the switching frequency is reduced there is
possibility for flicker to occur.
The waveforms of Figure 16 on page 26 to Figure 22 on page 32 are showing line
inversion mode. Figure 23 on page 33 shows one example of frame inversion.
8.1.16 Command: temp-filter
Table 24.
Temp-filter - digital temperature filter command bit description
Bit
Symbol
Value
Description
7 to 1
-
1101001
fixed value
0
TFE
[1]
digital temperature filter switch
0[1]
digital temperature filter disabled;
the unfiltered digital value of TD[7:0] is
immediately available for the readout and
VLCD compensation, see Section 8.4.7 on
page 38
1
digital temperature filter enabled
Default value.
8.2 Possible display configurations
The PCA9620 is a versatile peripheral device designed to interface between any
microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 4). It
can directly drive any static or multiplexed LCD containing up to eight backplanes and up
to 60 segments.
The display configurations possible with the PCA9620 depend on the number of active
backplane outputs required. A selection of possible display configurations is given in
Table 25.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
15 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
GRWPDWUL[
VHJPHQWZLWKGRW
VHJPHQWZLWKGRWDQGDFFHQW
DDD
Fig 4.
Example of displays suitable for PCA9620
Table 25.
Selection of possible display configurations
Number of
Backplanes
Icons
8
480
Digits/Characters
7-segment
14-segment
Dot matrix/
Elements
60
30
480 dots (8 60)
6
320
45
22
360 dots (6 60)
4
240
30
15
240 dots (4 60)
2
120
15
7
120 dots (2 60)
1
60
7
3
60 dots (1 60)
All of the display configurations in Table 25 can be implemented in the typical systems
shown in Figure 5 (internal VLCD) and in Figure 6 (external VLCD).
9''
9''
5
WU
&E
9''
+267
352&(6625
0,&52
&21752//(5
9''
9/&'
VHJPHQWGULYHV
6'$
6&/ 3&$
EDFNSODQHV
$
$
&/.
/&'3$1(/
XSWR
HOHPHQWV
966
DDD
QF
966
VDD1 from 2.5 V to 5.5 V and VDD2 from 2.5 V to 5.5 V.
Fig 5.
PCA9620
Product data sheet
Typical system configuration when using the internal VLCD generation
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
16 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
9/&'
9''
W
5 U
&E
9''
9''
9/&'
VHJPHQWGULYHV
6'$
+267
352&(6625
0,&52
&21752//(5
/&'3$1(/
XSWR
HOHPHQWV
6&/ 3&$
EDFNSODQHV
$
$
&/.
966
DDD
QF
966
VDD1 from 2.5 V to 5.5 V, VDD2 from 2.5 V to 5.5 V and VLCD from 2.5 V to 9.0 V.
Fig 6.
Typical system configuration when using an external VLCD
The host microcontroller maintains the two line I2C-bus communication channel with the
PCA9620. The appropriate biasing voltages for the multiplexed LCD waveforms are
generated internally. The only other connections required to complete the system are the
power supplies (VDD1, VDD2, VSS, VLCD), the external capacitors, and the LCD panel
selected for the application.
The minimum recommended values for external capacitors on VDD1, VDD2, and VLCD are
nominal 100 nF. When using bigger capacitors, especially on the VLCD, the generated
ripple will be consequently smaller. However it will take longer for the internal charge
pump to reach the target VLCD voltage first.
If VDD1 and VDD2 are connected externally, the capacitors on VDD1 and VDD2 can be
replaced by a single capacitor with a minimum value of 200 nF.
Remark: In the case of insufficient decoupling, ripple of VDD1 and VDD2 will create
additional VLCD ripple. The ripple on VLCD can be reduced by making the VSS connection
as low-ohmic as possible. Excessive ripple on VLCD may cause flicker on the display.
8.3 Start-up and shut-down
8.3.1 Power-On Reset (POR)
At power-on, the PCA9620 resets to starting conditions as follows:
1. All backplane outputs are set to VSS.
2. All segment outputs are set to VSS.
3. Selected drive mode is: 1:8 with 1⁄4 bias.
4. Input and output bank selectors are reset.
5. The I2C-bus interface is initialized.
6. The data pointer is cleared (set logic 0).
7. The Internal oscillator is running; no clock signal is available on pin CLK; pin CLK is in
3-state.
8. Temperature measurement is enabled.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
17 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
9. Temperature filter is disabled.
10. The internal VLCD voltage generation is disabled. The charge pump is switched off.
11. The VLCD temperature compensation is enabled.
12. The display is disabled.
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
The first command sent to the device after the power-on event must be the initialize
command (see Section 8.1.1 on page 8).
After Power-On Reset (POR) and before enabling the display, the RAM content should be
brought to a defined status
• by clearing it (setting it all logic 0) or
• by writing meaningful content (for example, a graphic)
otherwise unwanted display artifacts may appear on the display.
Table 26. Reset states
Bits labeled - are undefined at power-on.
Command name
PCA9620
Product data sheet
Bits
7
6
5
4
3
2
1
0
initialize
0
0
1
1
1
0
1
0
OTP-refresh
1
1
0
1
0
0
0
0
oscillator-ctrl
1
1
0
0
1
1
0
0
charge-pump-ctrl
1
1
0
0
0
0
0
0
temp-msr-ctrl
1
1
0
0
1
0
1
1
temp-comp-SLA
0
0
0
1
1
0
0
0
temp-comp-SLB
0
0
1
0
0
0
0
0
temp-comp-SLC
0
0
1
0
1
0
0
0
temp-comp-SLD
0
0
1
1
0
0
0
0
set-VPR-MSB
0
1
0
0
0
0
0
0
set-VPR-LSB
0
1
0
1
0
0
0
0
display-enable
0
0
1
1
1
0
0
0
set-MUX-mode
0
0
0
0
0
0
0
0
set-bias-mode
1
1
0
0
0
1
0
0
load-data-pointer
1
0
0
0
0
0
0
0
frame-frequency
0
1
1
0
1
1
1
0
input-bank-select
0
0
0
0
1
0
0
0
output-bank-select
0
0
0
1
0
0
0
0
write-RAM-data
-
-
-
-
-
-
-
-
temp-read
0
1
0
0
0
0
0
0
invmode_CPF_ctrl
1
1
0
1
0
1
0
0
temp-filter
1
1
0
1
0
0
1
0
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
18 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
8.3.2 Recommended start-up sequences
This chapter describes how to proceed with the initialization of the chip in different
application modes.
67$57
3RZHURQ
9''DQG
9''DWWKH
VDPHWLPH
6HW935
UHJLVWHUWR
GHVLUHG9/&'
YDOXH
6HW
PXOWLSOLFDWLRQ
IDFWRUIRU
FKDUJHSXPS
DQGHQDEOHLW
:DLWPV
,QLWLDOL]H
FRPPDQG
,QLWLDWHDQ
273UHIUHVK
:DLWWLOO
9/&'UHDFKHV
SURJUDPPHG
YDOXH
:ULWH5$0
FRQWHQWWREH
GLVSOD\HGDQG
HQDEOHWKH
GLVSOD\
6723
DDD
(1) This time depends on the external capacitor on pin VLCD. For a capacitor of 100 nF a delay of 5 ms
to 15 ms is expected.
When using the internal VLCD generation, the display must not be enabled before the generation of
VLCD with the internal charge pump is completed. Otherwise unwanted display artifacts may
appear on the display.
(2) RAM data may be written before or during the ramp-up of VLCD.
Fig 7.
PCA9620
Product data sheet
Recommended start-up sequence when using the internal charge pump and the
internal clock signal
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
19 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
67$57
,QLWLDWHDQ
273UHIUHVK
3RZHURQ
9''9''
DQG9/&'
DWWKH
VDPHWLPH
:ULWH5$0
FRQWHQWWREH
GLVSOD\HGDQG
HQDEOHWKH
GLVSOD\
:DLWPV
6723
,QLWLDOL]H
FRPPDQG
DDD
Fig 8.
Recommended start-up sequence when using an external supplied VLCD and the
internal clock signal
67$57
3RZHURQ
9''DQG
9''DWWKH
VDPHWLPH
$SSO\H[WHUQDO
FORFNVLJQDO
WRSLQ&/.
VHW26&ELW
ORJLF
:DLWWLOO
9/&'UHDFKHV
SURJUDPPHG
YDOXH
:DLWPV
6HW935
UHJLVWHUWR
GHVLUHG9/&'
YDOXH
,QLWLDOL]H
FRPPDQG
,QLWLDWHDQ
273UHIUHVK
6HW
PXOWLSOLFDWLRQ
IDFWRUIRU
FKDUJHSXPS
DQGHQDEOHLW
:ULWH5$0
FRQWHQWWREH
GLVSOD\HGDQG
HQDEOHWKH
GLVSOD\
6723
DDD
(1) The external clock signal can be applied after the generation of the VLCD voltage as well.
(2) This time depends on the external capacitor on pin VLCD. For a capacitor of 100 nF a delay of 5 ms
to 15 ms is expected.
(3) RAM data may be written before or during the ramp-up of VLCD.
Fig 9.
PCA9620
Product data sheet
Recommended start-up sequence when using the internal charge pump and an
external clock signal
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
20 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
67$57
3RZHURQ
9''9''
DQG9/&'
DWWKH
VDPHWLPH
$SSO\H[WHUQDO
FORFNVLJQDO
WRSLQ&/.
VHW26&ELW
ORJLF
:DLWPV
:ULWH5$0
FRQWHQWWREH
GLVSOD\HGDQG
HQDEOHWKH
GLVSOD\
,QLWLDOL]H
FRPPDQG
6723
,QLWLDWHDQ
273UHIUHVK
DDD
Fig 10. Recommended start-up sequence when using an external supplied VLCD and an
external clock signal
8.3.3 Recommended power-down sequences
With the following sequences, the PCA9620 can be set to a state of minimum power
consumption, called power-down mode.
67$57
'LVDEOHGLV
SOD\E\VHWWLQJ
ELW(ORJLF
6WRSJHQHUD
WLRQRI9/&'
E\VHWWLQJELW
&3(ORJLF
'LVDEOHWHP
SHUDWXUHPHD
VXUHPHQWE\
VHWWLQJELW
70(ORJLF
6723
DDD
Fig 11. Recommended power-down sequence for minimum power-down current when
using the internal charge pump and the internal clock signal
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
21 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
67$57
'LVDEOHGLV
SOD\E\VHWWLQJ
ELW(ORJLF
'LVDEOHWHP
SHUDWXUHPHD
VXUHPHQWE\
VHWWLQJELW
70(ORJLF
6723
DDD
Fig 12. Recommended power-down sequence when using an external supplied VLCD and
the internal clock signal
67$57
'LVDEOHGLV
SOD\E\VHWWLQJ
ELW(ORJLF
6WRSJHQHUD
WLRQRI9/&'
E\VHWWLQJELW
&3(ORJLF
'LVDEOHWHP
SHUDWXUHPHD
VXUHPHQWE\
VHWWLQJELW
70(ORJLF
%ULQJSLQ&/.
WRVWDWHE\
VHWWLQJELW
26&DQGELW
&2(ORJLF
([WHUQDO
FORFNPD\
EHVZLWFKHG
RII
6723
DDD
Fig 13. Recommended power-down sequence when using the internal charge pump and
an external clock signal
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
22 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
67$57
'LVDEOHGLV
SOD\E\VHWWLQJ
ELW(ORJLF
'LVDEOHWHP
SHUDWXUHPHD
VXUHPHQWE\
VHWWLQJELW
70(ORJLF
%ULQJSLQ&/.
WRVWDWHE\
VHWWLQJELW
26&DQGELW
&2(ORJLF
([WHUQDO
FORFNPD\
EHVZLWFKHG
RII
6723
DDD
Fig 14. Recommended power-down sequence when using an external supplied VLCD and
an external clock signal
Remark: It is necessary to run the power-down sequence before removing the supplies.
Depending on the application, care must be taken that no other signals are present at the
chip input or output pins when removing the supplies (refer to Section 10 on page 56).
Otherwise it may cause unwanted display artifacts. The PCA9620 will not be damaged by
uncontrolled removal of supply voltages
Remark: Static voltages across the liquid crystal display can build up when the external
LCD supply voltage (VLCD) is on while the IC supply voltage (VDD1 or VDD2) is off, or vice
versa. It may cause unwanted display artifacts. To avoid such artifacts, external VLCD,
VDD1, and VDD2 must be applied or removed together.
Remark: A clock signal must always be supplied to the device when the device is active;
removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid
crystal. It is recommended to first disable the display and afterwards to remove the clock
signal.
8.4 LCD voltage
8.4.1 LCD voltage selector
The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
set-bias-mode command (see Table 15 on page 11) and the set-MUX-mode command
(see Table 14 on page 11).
Intermediate LCD biasing voltages are obtained from an internal voltage divider. The
biasing configurations that apply to the preferred modes of operation, together with the
biasing characteristics as functions of VLCD and the resulting discrimination ratios (D), are
given in Table 27.
Discrimination is a term which is defined as the ratio of the Von(RMS) and Voff(RMS) across a
segment. It can be thought of as a measurement of contrast.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
23 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
Table 27.
LCD drive modes: summary of characteristics
LCD drive
mode
Number of:
Backplanes Levels
LCD bias
configuration
V off RMS
----------------------V LCD
V on RMS
---------------------V LCD
V on RMS [1] VLCD[2]
D = ---------------------V off RMS
static
1
2
static
0
1
Von(RMS)
1:2 multiplex
2
3
1⁄
2
0.354
0.791
2.236
2.828 Voff(RMS)
4
1⁄
3
0.333
0.745
2.236
3.0 Voff(RMS)
5
1⁄
4
0.395
0.729
1.845
2.529 Voff(RMS)
4
3
1⁄
2
0.433
0.661
1.527
2.309 Voff(RMS)
4
4
1⁄
3
0.333
0.577
1.732
3.0 Voff(RMS)
5
1⁄
4
0.331
0.545
1.646
3.024 Voff(RMS)
3
1⁄
2
0.456
0.612
1.341
2.191 Voff(RMS)
1:2 multiplex
1:2
multiplex[3]
1:4
multiplex[3]
1:4 multiplex
1:4
multiplex[3]
1:6
multiplex[3]
2
2
4
6
1:6 multiplex
6
4
1⁄
3
0.333
0.509
1.527
3.0 Voff(RMS)
1:6 multiplex
6
5
1⁄
4
0.306
0.467
1.527
3.266 Voff(RMS)
3
1⁄
2
0.467
0.586
1.254
2.138 Voff(RMS)
4
1⁄
3
0.333
0.471
1.414
3.0 Voff(RMS)
5
1⁄
4
0.293
0.424
1.447
3.411 Voff(RMS)
1:8
multiplex[3]
1:8
multiplex[3]
1:8 multiplex
8
8
8
[1]
Determined from Equation 3.
[2]
Determined from Equation 2.
[3]
In these examples the discrimination factor and hence the contrast ratios are smaller. The advantage of
these LCD drive modes is a power saving from a reduction of the LCD voltage VLCD.
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode a suitable choice is VLCD > 3Vth(off).
1
Bias is calculated by ------------- , where the values for a are
1+a
a = 1 for 1⁄2 bias
a = 2 for 1⁄3 bias
a = 3 for 1⁄4 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1:
V on RMS =
V LCD
a 2 + 2a + n
-----------------------------2
n 1 + a
(1)
where VLCD is the resultant voltage at the LCD segment and where the values for n are
n = 1 for static mode
n = 2 for 1:2 multiplex
n = 4 for 1:4 multiplex
n = 6 for 1:6 multiplex
n = 8 for 1:8 multiplex
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
24 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
V off RMS =
V LCD
a 2 – 2a + n
-----------------------------2
n 1 + a
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:
V on RMS
--------------------- =
V off RMS
2
a + 1 + n – 1
-------------------------------------------2
a – 1 + n – 1
(3)
It should be noted that VLCD is sometimes referred as the LCD operating voltage.
8.4.1.1
Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of
the pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 15. For a good contrast performance, the following rules should be followed:
V on RMS V th on
(4)
V off RMS V th off
(5)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection
of a, n (see Equation 1 to Equation 3) and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
5HODWLYH7UDQVPLVVLRQ
9WKRII
2))
6(*0(17
9WKRQ
*5(<
6(*0(17
9506>9@
21
6(*0(17
DDD
Fig 15. Electro-optical characteristic: relative transmission curve of the liquid
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
25 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
8.4.2 LCD drive mode waveforms
8.4.2.1
Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD.
7IU
/&'VHJPHQWV
9/&'
%3
966
VWDWH
RQ
9/&'
VWDWH
RII
6Q
966
9/&'
6Q
966
D:DYHIRUPVDWGULYHU
9/&'
VWDWH
9
9/&'
9/&'
VWDWH
9
9/&'
E5HVXOWDQWZDYHIRUPV
DW/&'VHJPHQW
DDD
Vstate1(t) = VSn(t) VBP0(t).
Vstate2(t) = V(Sn + 1)(t) VBP0(t).
Von(RMS)(t) = VLCD. Voff(RMS)(t) = 0 V.
Fig 16. Static drive mode waveforms (line inversion mode)
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
26 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
8.4.2.2
1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCA9620 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 17 and
Figure 18.
7IU
9/&'
%3
/&'VHJPHQWV
9/&'
966
VWDWH
9/&'
%3
VWDWH
9/&'
966
9/&'
6Q
966
9/&'
6Q
966
D:DYHIRUPVDWGULYHU
9/&'
9/&'
VWDWH
9
9/&'
9/&'
9/&'
9/&'
VWDWH
9
9/&'
9/&'
E5HVXOWDQWZDYHIRUPV
DW/&'VHJPHQW
DDD
Vstate1(t) = VSn(t) VBP0(t).
Vstate2(t) = VSn(t) VBP1(t).
Von(RMS)(t) = 0.791VLCD. Voff(RMS)(t) = 0.354VLCD.
Fig 17. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias (line inversion mode)
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
27 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
7IU
9/&'
%3
%3
/&'VHJPHQWV
9/&'
9/&'
966
VWDWH
9/&'
9/&'
VWDWH
9/&'
966
9/&'
6Q
9/&'
9/&'
966
9/&'
6Q
9/&'
9/&'
966
D:DYHIRUPVDWGULYHU
9/&'
9/&'
VWDWH
9/&'
9
9/&'
9/&'
9/&'
9/&'
9/&'
9/&'
VWDWH
9
9/&'
9/&'
9/&'
E5HVXOWDQWZDYHIRUPV
DW/&'VHJPHQW
DDD
Vstate1(t) = VSn(t) VBP0(t).
Vstate2(t) = VSn(t) VBP1(t).
Von(RMS)(t) = 0.745VLCD. Voff(RMS)(t) = 0.333VLCD.
Fig 18. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias (line inversion mode)
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
28 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
8.4.2.3
1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as
shown in Figure 19.
7IU
%3
9/&'
9/&'
9/&'
966
%3
9/&'
9/&'
9/&'
966
%3
9/&'
9/&'
9/&'
966
%3
9/&'
9/&'
9/&'
966
6Q
9/&'
9/&'
9/&'
966
6Q
9/&'
9/&'
9/&'
966
6Q
9/&'
9/&'
9/&'
966
6Q
9/&'
9/&'
9/&'
966
VWDWH
9/&'
9/&'
9/&'
9
9/&'
9/&'
9/&'
VWDWH
9/&'
9/&'
9/&'
9
9/&'
9/&'
9/&'
/&'VHJPHQWV
VWDWH
VWDWH
D:DYHIRUPVDWGULYHU
E5HVXOWDQWZDYHIRUPV
DW/&'VHJPHQW
DDD
Vstate1(t) = VSn(t) VBP0(t).
Vstate2(t) = VSn(t) VBP1(t).
Von(RMS)(t) = 0.577VLCD. Voff(RMS)(t) = 0.333VLCD.
Fig 19. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias (line inversion mode)
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
29 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
8.4.2.4
1:6 Multiplex drive mode
When six backplanes are provided in the LCD, the 1:6 multiplex drive mode applies. The
PCA9620 allows the use of 1⁄3 bias or 1⁄4 bias in this mode as shown in Figure 20 and
Figure 21.
7IU
%3
9/&'
9/&'
9/&'
966
%3
9/&'
9/&'
9/&'
966
%3
9/&'
9/&'
9/&'
966
%3
9/&'
9/&'
9/&'
966
%3
9/&'
9/&'
9/&'
966
%3
9/&'
9/&'
9/&'
966
6Q
9/&'
9/&'
9/&'
966
6Q
9/&'
9/&'
9/&'
966
/&'VHJPHQWV
VWDWH
VWDWH
D:DYHIRUPVDWGULYHU
9/&'
9/&'
VWDWH
9/&'
966
9/&'
9/&'
9/&'
VWDWH
9/&'
9/&'
9/&'
966
9/&'
9/&'
9/&'
E5HVXOWDQWZDYHIRUPVDW/&'VHJPHQW
DDO
Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn + 1(t) VBP0(t).
Von(RMS)(t) = 0.509VLCD. Voff(RMS)(t) = 0.333VLCD.
Fig 20. Waveforms for 1:6 multiplex drive mode with 1⁄3 bias (line inversion mode)
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
30 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
7IU
/&'VHJPHQWV
9/&'
9/&'
VWDWH
%3
VWDWH
9/&'
966
9/&'
9/&'
%3
9/&'
966
9/&'
9/&'
%3
9/&'
966
9/&'
9/&'
%3
9/&'
966
9/&'
9/&'
%3
9/&'
966
9/&'
9/&'
%3
9/&'
966
9/&'
6Q
9/&'
966
9/&'
6Q
9/&'
966
D:DYHIRUPVDWGULYHU
9/&'
9/&'
VWDWH
9/&'
966
9/&'
9/&'
9/&'
9/&'
9/&'
9/&'
9/&'
966
VWDWH
9/&'
9/&'
9/&'
9/&'
E5HVXOWDQWZDYHIRUPVDW/&'VHJPHQW
DDO
Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn + 1(t) VBP0(t).
Von(RMS)(t) = 0.467VLCD. Voff(RMS)(t) = 0.306VLCD.
Fig 21. Waveforms for 1:6 multiplex drive mode with 1⁄4 bias (line inversion mode)
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
31 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
8.4.2.5
9/&'
9/&'
1:8 Multiplex drive mode
7IU
/&'VHJPHQWV
VWDWH
%3
VWDWH
9/&'
966
9/&'
9/&'
%3
9/&'
966
9/&'
9/&'
%3
9/&'
966
9/&'
9/&'
%3
9/&'
966
9/&'
9/&'
%3
/&'
966
9/&'
9/&'
%3
9/&'
966
9/&'
9/&'
%3
9/&'
966
9/&'
9/&'
%3
9/&'
966
9/&'
9/&'
6Q
966
9/&'
6Q
9/&'
966
D:DYHIRUPVDWGULYHU
9/&'
9/&'
VWDWH
9/&'
966
9/&'
9/&'
9/&'
VWDWH
9/&'
9/&'
9/&'
9/&'
966
9/&'
9/&'
9/&'
9/&'
E5HVXOWDQWZDYHIRUPVDW/&'VHJPHQW
DDO
Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn + 1(t) VBP0(t). Von(RMS)(t) = 0.424VLCD. Voff(RMS)(t) = 0.293VLCD.
Fig 22. Waveforms for 1:8 multiplex drive mode with 1⁄4 bias (line inversion mode)
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
32 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
9/&'
9/&'
%3
7IU
IUDPHQ
7IU
IUDPHQ
/&'VHJPHQWV
VWDWH
VWDWH
9/&'
966
9/&'
9/&'
%3
9/&'
966
9/&'
9/&'
%3
9/&'
966
9/&'
9/&'
%3
9/&'
966
9/&'
9/&'
%3
9/&'
966
9/&'
9/&'
%3
9/&'
966
9/&'
9/&'
%3
9/&'
966
9/&'
9/&'
%3
9/&'
966
9/&'
6Q
9/&'
966
9/&'
6Q
9/&'
966
D:DYHIRUPVDWGULYHU
VWDWH
9/&'
9/&'
9/&'
9/&'
966
9/&'
9/&'
9/&'
9/&'
VWDWH
9/&'
9/&'
9/&'
9/&'
966
9/&'
9/&'
9/&'
9/&'
E5HVXOWDQWZDYHIRUPVDW/&'VHJPHQW
DDP
Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn + 1(t) VBP0(t). Von(RMS)(t) = 0.424VLCD. Voff(RMS)(t) = 0.293VLCD.
Fig 23. Waveforms for 1:8 multiplex drive mode with 1⁄4 bias (frame inversion mode)
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
33 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
When eight backplanes are provided in the LCD, the 1:8 multiplex drive mode applies, as
shown in Figure 22 and Figure 23.
8.4.3 VLCD generation
VLCD can be generated and controlled on the chip by using software commands. When
the internal charge pump is used, the programmed VLCD is available on pin VLCD. The
charge pump generates a VLCD of up to 3 VDD2.
The charge pump can be enabled or disabled with the CPE bit (see Table 9 on page 10).
With bit CPC, the charge pump multiplier setting can be configured.
The final value of VLCD is a combination of the programmed VPR[7:0] value and the output
of the temperature compensation block, VT[7:0]. The system is shown in Figure 24.
6/$
6/%
6/&
6/'
2))6(7
7(03(5$785(
5($'287
7'
7(03(5$785(
Q
935>@
P
9/&'
DDD
Fig 24. VLCD generation including temperature compensation
In Equation 6 the main parameters are the programmed digital value term and the
compensated temperature term.
V LCD = VPR 7:0 + VT 7:0 n + m
(6)
1. VPR[7:0] is the binary value of the programmed voltage.
2. VT[7:0] is the binary value of the temperature compensated voltage. Its value comes
from the temperature compensation block and is a two’s complement which has the
value 0h at 20 C.
3. m and n are fixed values (see Table 28).
Table 28.
Symbol
Parameters of VLCD generation
Value
Unit
m
3
V
n
0.03
V
Figure 25 shows how VLCD changes with the programmed value of VPR[7:0].
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
34 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
It has to be taken into account that the charge pump has to be configured (via bit CPC)
properly to obtain the desired voltage range. For example, if VDD2 = 3.0 V and CPC is set
to 2 VDD2 (logic 0) then the maximum theoretical value that the charge pump can reach
is VLCD = 6.0 V. But in reality, lower values will be reached due to internal resistances, see
Section 8.4.5. So, if the requested value for VLCD = 7.0 V then the charge pump has to be
configured with CPC set to 3 VDD2 (logic 1).
9 /&'
9
Q
9''
P
&
&
& &$
)&
)'
)(
))
935>@
DDD
(1) If VDD2 > 3.0 V then VPR[7:0] must be set so that VLCD > VDD2.
(2) Automatic limitation for VLCD > 9.0 V.
Fig 25. VLCD programming of PCA9620 (assuming VT[7:0] = 0h)
Programmable range of VPR[7:0] is from 0h to FFh. This would allow achieving
VLCD > 9.0 V, but the PCA9620 has a built-in automatic limitation of VLCD at 9.0 V.
If VDD2 is higher than 3.0 V, then it is important that VPR[7:0] is set to a value such that the
resultant VLCD (including the temperature correction of VT[7:0]) is higher than VDD2.
8.4.4 External VLCD supply
VLCD can be directly supplied to the VLCD pin. In this case, the internal charge pump must
not be enabled otherwise a high current may occur on pin VDD2 and pin VLCD. When VLCD
is supplied externally, no internal temperature compensation occurs on this voltage even if
bit TCE is set logic 1 (see Section 8.4.8 on page 39). The VLCD voltage which is supplied
externally will be available at the segments and backplanes of the device through the
chosen bias system. Also programming the VPR[7:0] bit field has no effect on the VLCD
which is externally supplied.
8.4.5 Charge pump driving capability
Figure 26 illustrates the main factor determining how much current the charge pump can
deliver.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
35 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
5HJXODWHGGHVLUHG9/&'
7KLVVXSSOLHVWKHVHJPHQWV
DQGEDFNSODQHV
7KHRUHWLFDO9/&'YDOXH
9/&' î9''RU
9/&' î9''
2XWSXW5HVLVWDQFH
5RFS
DDD
Fig 26. Charge pump model (used to characterize the driving strength)
The output resistance of the charge pump is specified in Table 36 on page 58. With these
values, it can be calculated how much current the charge pump can drive under certain
conditions.
Example: Assuming that the normal operation point is at 25 C with VLCD = 7.0 V and
VDD2 = 5.0 V and the charge pump is set to 2 VDD2. Then the theoretical value of VLCD is
10.0 V and the desired one is 7.0 V. The difference between the theoretical maximum
value and desired one is 3.0 V. The charge pump resistance is nominally 0.85 k.
Equation 7 shows the possible current that the charge pump could deliver:
I load = V LCD R o cp
(7)
The result of this example is: I load = 3.0 V 0.85 k = 3.5 mA
In cases where no extreme driving capability is needed, a command is available for
decreasing the charge pump frequency (see Table 23 on page 14) and thus reducing the
total current consumption. If the charge pump frequency is halved, then the driving
capability is halved as well, whereas the output resistance doubles.
8.4.6 Charge pump frequency settings and power efficiency
The PCA9620 offers the possibility to use different frequency settings for the charge
pump. Bit CPF controls the frequency at which the charge pump is running (see Table 23
on page 14). This frequency has a direct influence on the current consumption of the IC
but also on the charge pump driving capability. Using a lower charge pump frequency
decreases the current consumption and the driving capability.
The power efficiency of the charge pump determines in certain applications which
frequency settings to choose for the CPF bit. Concerning the example shown in Figure 27:
The current consumption was measured with
• charge pump set to 2 VDD2
• VDD2 = 3.0 V
• VPR[7:0] set to maximum to obtain the highest possible VLCD with this setup, which is
close to 6.0 V
The current load on pin VLCD determines the output power delivered by the IC:
P o = I load V LCD
(8)
The current consumption on pin VDD2 determines the input power taken by the IC:
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
36 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
P i = I DD2 V DD2
(9)
The ratio between these two numbers determines the charge pump power efficiency:
p = Po Pi
(10)
DDQ
Ș S
9/&'
9
,ORDG$
Charge pump set to 2 VDD2; VDD2 = 3 V.
(1) p, full charge pump frequency.
(2) p, half charge pump frequency.
(3) VLCD, full frequency.
(4) VLCD, half frequency.
Fig 27. Power efficiency of the charge pump
Loading the charge pump with higher currents decreases the output voltage. This
decrease is determined by the charge pump driving capability, respectively by the output
resistance of the charge pump (see Table 36 on page 58).
The power efficiency calculation is only valid when the charge pump is running at its
maximum peak frequency and regulates the generated VLCD voltage with full speed. In
this case, the ripple on the VLCD voltage equals the internal charge pump frequency.
Approximately, this could also be calculated with the parameter of the output resistance of
the charge pump (see Table 36 on page 58), the load current, and the voltage needed to
be provided by using Equation 7 on page 36. This value of Iload is close to the value of the
load current needed for the application.
If the application runs with VDD2 = 3.0 V, the load currents are up to 400 A
(DC measured), and the VLCD generated voltages are up to 5.0 V, then - concerning
power efficiency - it would be the best to have a charge pump frequency set to half
frequency.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
37 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
If it is desired to change the charge pump frequency, it is recommended to make a graph
like Figure 27 and understand what the application requirements are. This would basically
imply to find out what would be the maximum VLCD requirements and what would be the
maximum load currents required. Then it can be decided which is the best setting of bit
CPF.
Tuning the charge pump frequency might be a difficult task to do. It requires good
knowledge of the application in which the IC is being used; therefore, NXP is
recommending to keep the CPF bit set logic 0 to have the maximum charge pump
frequency, thus having the maximum driving strength.
8.4.7 Temperature readout
The PCA9620 has a built-in temperature sensor which provides an 8 bit digital value,
TD[7:0], of the ambient temperature. This value can be read through the I2C interface (see
Figure 50 on page 55). The actual temperature is determined from TD[7:0] using
Equation 11:
T (°C) = 0.9375 TD 7:0 – 40
(11)
The measurement needs about 5 ms to complete. it is repeated periodically as soon as bit
TME is set logic 1 (see Table 10 on page 10). The time between measurements is linked
to the system clock and hence varies with changes in the chosen frame frequency, see
Table 29.
Table 29.
Temperature measurement update rate
Selected frame frequency
Temperature measurement update rate
60 Hz
3.3 s
200 Hz
1s
300 Hz
0.67 s
Due to the nature of a temperature sensor, oscillations on the VLCD may occur. To avoid it,
a filter has been implemented in PCA9620. The system is shown in Figure 28.
7(03(5$785(
0($685(0(17
%/2&.
7'>@
XQILOWHUHG
',*,7$/
7(03(5$785(
),/7(5
7'>@
ILOWHUHG
7RWKHUHDGRXWUHJLVWHU
YLD,&EXVDQGWR
WKH9/&'FRPSHQVDWLRQ
EORFN
HQDEOHGRUGLVDEOHG
E\ELW7)(
DDD
Fig 28. Temperature measurement block with digital temperature filter
Like any other filtering, the digital temperature filter (see Figure 28) introduces a certain
delay in the measurement of temperature. This behavior is illustrated in Figure 29.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
38 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
DDO
7
&
ǻ7
&
WV
(1) Environment temperature, T1 (C).
(2) Measured temperature, T2 (C).
(3) Temperature deviation, T = T2 T1.
Fig 29. Temperature measurement delay
This delay may cause undesired effects at start-up when the environment temperature
may be different than the reset value of the PCA9620 which is 20 °C. In this case, it takes
up to 30 s until the correct measured temperature value will be available. A control bit,
TFE, is implemented to enable or disable the digital temperature filter. This bit is set
logic 0 by default which means that the filter is disabled and the unfiltered environment
temperature value is available to calculate the desired VLCD.
8.4.8 Temperature compensation of VLCD
Due to the temperature dependency of the liquid crystal viscosity, the LCD controlling
voltage VLCD might have to be adjusted at different temperatures to maintain optimal
contrast. The temperature behavior of the liquid comes from the LCD manufacturer. The
slope has to be set to compensate for the liquid behavior. Internal temperature
compensation may be enabled via bit TCE.
The ambient temperature range is split up into four equally sized regions and a different
temperature coefficient can be applied to each (see Figure 30). Each coefficient can be
selected from a choice of eight different slopes. Each one of these coefficients (see
Table 30) may be independently selected via the temp-comp-SLA to temp-comp-SLD
commands (see Table 5 on page 8).
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
39 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
Table 30.
Temperature coefficients
SLA[2:0] to SLD[2:0] value
Corresponding slope factor
(mV/C)
Temperature coefficients
MA, MB, MC, MD[1]
000[2]
0
0.00
001
4
0.125
010
8
0.25
011
16
0.5
100
40
1.25
101
+4
0.125
110
+8
0.25
111
+16
0.5
[1]
The relationship between the temperature coefficients MA to MD and the slope factor is derived from the
0.9375
0.03
slope
1000
following equation: Mx = ---------------- -------------- .
[2]
Default value.
The slope factors imply a linear correction, however the implementation is set in steps of
30 mV (parameter n in Table 28 on page 34).
6/$
6/%
6/&
6/'
7'>@
K
K
K
)K
K
9/&'ZLWKWHPSHUDWXUH
FRPSHQVDWLRQ9
]HURRIIVHW
DW&
0$
0%
0&
0'
7HPSHUDWXUH&
DDD
Fig 30. Example of segmented temperature coefficients
Remark: After reset, VLCD is fixed because the VPR[7:0] bit field is reset logic 0. The
value of VT[7:0] is generated by the reset value of TD[7:0] (40h, representing 20 C).
Temperature compensation is implemented by adding an offset VT[7:0] to the VPR[7:0]
value. VT[7:0] is a two’s complement number that equals 0h at 20 C. The final result for
VLCD calculation is an 8-bit positive number (see Equation 6 on page 34).
Remark: Care must be taken that the ranges of VPR[7:0] and VT[7:0] do not cause
clipping and hence undesired results. The device will not permit overflow or underflow and
will clamp results to either end of the range.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
40 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
The Voffset(LCD) value can be calculated with the equations given in Table 31:
V offset LCD = m V T
Table 31.
(12)
Calculation of the temperature compensated voltage VT
Temperature range
TD[7:0]
Offset equation for VT
T 40 C
0h
V T = – 32 MA – 32 MB
40 C T 10 C
0h to 20h
V T = TD 7:0 – 32 MA – 32 MB
10 C < T 20 C
21h to 40h
V T = TD 7:0 – 64 MB
20 C < T 50 C
41h to 60h
V T = TD 7:0 – 64 MC
50 C < T < 80 C
61h to 7Eh
V T = TD 7:0 – 96 MD + 32 MC
80 C T
7Fh[1]
V T = 31 MD + 32 MC
[1]
No temperature compensation is possible above 80 C. Above this value, the system maintains the
compensation value from 80 C.
Example: Assumed that Tamb = 8 C; TD[7:0] = 22h; MB = 0.5:
V offset LCD = m V T = m TD[7:0] – 64 MB = 30mV 34 – 64 – 0.5 =
30mV – 30 – 0.5 = 450mV
(13)
The VT[7:0] term is calculated using the digital temperature value TD[7:0] which is
provided by the temperature measurement block (Section 8.4.7). Therefore the accuracy
of the temperature measurement block (Tacc, see Table 36 on page 58) will be directly
translated to the LCD voltage deviation VLCD.
Since VT[7:0] = f[T,slope] and Tacc = 6 C then V T = T acc slope , where slope has one
of the possible values specified in Table 30. This term will be added to the total LCD
voltage deviation Voffset(LCD)tot over the temperature range. So the total VLCD offset will
be: V offset LCD tot = V LCD + V T .
8.5 Oscillator
The internal logic and LCD drive signals of the PCA9620 are timed by a frequency fclk
which either is the built-in oscillator frequency fosc or equals an external clock frequency.
8.5.1 Internal oscillator
When the internal oscillator is used, it is possible to make the clock signal available on pin
CLK by using the oscillator-ctrl command (see Table 8 on page 9). If this is not intended,
pin CLK should be left open. At power-on the signal at pin CLK is disabled and pin CLK is
in 3-state.
The duty cycle of the output clock provided on the CLK pin is not always 50 : 50. Table 18
on page 12 shows the expected duty cycle for each of the chosen frame frequencies.
8.5.2 External clock
In applications where an external clock needs to be applied to the PCA9620, bit OSC (see
Table 8 on page 9) must be set logic 1. In this case pin CLK becomes an input.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
41 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
The CLK signal is a signal that is fed into the VDD1 domain so it must have an amplitude
equal to the VDD1 voltage supplied to the chip and be referenced to VSS.
The clock frequency (fclk) determines the LCD frame frequency ffr.
Remark: If an external clock is used then this clock signal must always be supplied to the
device; removing the clock may freeze the LCD in a DC state, which is not suitable for the
liquid crystal. Removal of the clock is possible when following the correct procedures. See
Figure 13 on page 22 and Figure 14 on page 23.
8.5.3 Timing and frame frequency
The timing of the PCA9620 organizes the internal data flow of the device. It includes the
transfer of display data from the display RAM to the display segment outputs. The timing
also generates the LCD frame frequency which it derives as an integer division of the
clock frequency. The frame frequency is a fixed division of the internal clock or of the
frequency applied to pin CLK when an external clock is used:
f clk
f fr = ------48
(14)
When the internal clock is used, the clock and frame frequency can be programmed by
software such that the nominal frame frequency can be chosen in steps of 10 Hz in the
range of 60 Hz to 300 Hz (see Table 18 on page 12). Furthermore the nominal frame
frequency is factory-calibrated with an accuracy of 15 %.
When the internal clock is enabled at pin CLK by using bit COE, the duty ratio of the clock
may change when choosing different values for the frame frequency prescaler. Table 18
on page 12 shows the different output duty ratios for each frame frequency prescaler
setting.
8.6 Backplane outputs
The LCD drive section includes eight backplane outputs: BP0 to BP7. The backplane
output signals are generated based on the selected LCD multiplex drive mode.
Table 32 describes which outputs are active for each of the multiplex drive modes and
what signal is generated.
Table 32.
Multiplex
drive
mode
Output pin
1:8
1:6
Product data sheet
BP0
BP1
BP2
BP3
BP4
BP5
BP6
BP7
BP0
BP1
BP2
BP3
BP4
BP5
BP6
BP7
BP0
BP1
BP2
BP3
BP4
BP5
BP0[1]
BP1[1]
BP1[1]
BP2[1]
BP3[1]
Signal
1:4
BP0
BP1
BP2
BP3
BP0[1]
1:2
BP0
BP1
BP0[1]
BP1[1]
BP0[1]
BP1[1]
BP0[1]
BP1[1]
static
BP0
BP0[1]
BP0[1]
BP0[1]
BP0[1]
BP0[1]
BP0[1]
BP0[1]
[1]
PCA9620
Mapping of output pins and corresponding output signals with respect to the
multiplex driving mode
These pins may optionally be connected to the display to improve drive strength. Connect only with the
corresponding output pin carrying the same signal. If not required, they can be left open-circuit.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
42 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
8.7 Segment outputs
The LCD drive section includes 60 segment outputs (S0 to S59) which must be connected
directly to the LCD. The segment output signals are generated based on the multiplexed
backplane signals and with data resident in the display register. When less than
60 segment outputs are required, the unused segment outputs must be left open-circuit.
8.8 Display register
The display register holds the display data while the corresponding multiplex signals are
generated.
8.9 Display RAM
The display RAM is a static 60 8-bit RAM which stores LCD data. Logic 1 in the RAM bit
map indicates the on-state of the corresponding LCD element; similarly, logic 0 indicates
the off-state.
There is a one-to-one correspondence between
• the bits in the RAM bitmap and the LCD elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
The display RAM bit map, Figure 31, shows row 0 to row 7 which correspond with the
backplane outputs BP0 to BP7, and column 0 to column 59 which correspond with the
segment outputs S0 to S59. In multiplexed LCD applications, the data of each row of the
display RAM is time-multiplexed with the corresponding backplane (row 0 with BP0, row 1
with BP1, and so on).
When display data is transmitted to the PCA9620, the display bytes received are stored in
the display RAM in accordance with the selected LCD multiplex drive mode. The data is
stored as it arrives and does not wait for the acknowledge cycle as with the commands.
Depending on the current multiplex drive mode, data is stored singularly, in pairs,
quadruples, sextuples or bytes.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
43 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
FROXPQV
GLVSOD\5$0FROXPQVVHJPHQWRXWSXWV6
VWDWLFGULYHPRGH
EDQN
EDQN
EDQN
EDQN
EDQN
EDQN
EDQN
EDQN
PXOWLSOH[GULYHPRGH
EDQN
URZV
GLVSOD\5$0URZV
EDFNSODQHRXWSXWV
%3
EDQN
EDQN
EDQN
PXOWLSOH[GULYHPRGH
EDQN
EDQN
DDD
The display RAM bitmap shows the direct relationship between the display RAM column and the
segment outputs, between the bits in a RAM row and the backplane outputs, and between the
RAM rows and banks.
Fig 31. Display RAM bitmap
8.9.1 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. It
allows the loading of an individual display data byte, or a series of display data bytes into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command. Following this command, an arriving data
byte is stored starting at the display RAM address indicated by the data pointer.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
44 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
The data pointer is automatically incremented in accordance with the chosen LCD
multiplex drive mode configuration. That is, after each byte is stored, the contents of the
data pointer are incremented
•
•
•
•
•
by eight (static drive mode)
by four (1:2 multiplex drive mode)
by two (1:4 multiplex drive mode)
by one or two (1:6 multiplex drive mode), see Figure 38 on page 48
by one (1:8 multiplex drive mode)
If the data pointer reaches the end of the RAM row, it is automatically wrapped around to
address 0. This means that it can be continuously written to or read from the display RAM.
The data pointer should always be set to an address where the remaining RAM is divisible
by eight because odd bits will be discarded (see Figure 33). This behavior is only shown
in static drive mode because the 60 RAM cells cannot be divided by eight without
remainder.
If an I2C-bus data access is terminated early, then the state of the data pointer is
unknown. The data pointer must then be re-written before further RAM accesses.
8.9.1.1
RAM filling in static drive mode
In the static drive mode the eight transmitted data bits are placed in eight successive
display RAM columns in row 0 (see Figure 32).
FROXPQV
GLVSOD\5$0FROXPQVVHJPHQWRXWSXWV6
URZV
GLVSOD\5$0URZV
E E E E E E E E
EDFNSODQHRXWSXWV
%3
E E E E E E E E
06%
/6%
WUDQVPLWWHGGDWDE\WH
DDD
Fig 32. Display RAM filling order in static drive mode
In order to fill the whole RAM row, 8 bytes must be sent to the PCA9620, but the last 4 bits
from the last byte are discarded, and the data pointer is wrapped around to column 0 to
start a possible RAM content update (see Figure 33).
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
45 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
GDWDSRLQWHU
D D D D D D D D
I I I I I I I I J J J J J J J J
GLVFDUGHG
GLVSOD\5$0
ZUDSDURXQG
DDD
Fig 33. Discarded bits and data pointer wrap around at the end of data transmission
8.9.1.2
RAM filling in 1:2 multiplex drive mode
In the 1:2 multiplex drive mode the eight transmitted data bits are placed in four
successive display RAM columns of two rows (see Figure 34).
FROXPQV
GLVSOD\5$0FROXPQVVHJPHQWRXWSXWV6
URZV
GLVSOD\5$0URZV E E E E
EDFNSODQHRXWSXWV E E E E
%3
/6%
E E E E E E E E
06%
WUDQVPLWWHGGDWDE\WH
DDD
Fig 34. Display RAM filling order in 1:2 multiplex drive mode
In order to fill the whole two RAM rows 15 bytes need to be sent to the PCA9620. After the
last byte sent, the data pointer is wrapped around to column 0 to start a possible RAM
content update (see Figure 35). Even if a data byte is transmitted during the wrapping of
the data pointer, then all the bits in the byte will be written correctly.
GDWDSRLQWHU
E
GLVSOD\5$0
E
E E E
E E E
ZUDSDURXQG
DDD
Fig 35. Data pointer wrap around in 1:2 multiplex drive mode
8.9.1.3
RAM filling in 1:4 multiplex drive mode
In the 1:4 multiplex drive mode the eight transmitted data bits are placed in two
successive display RAM columns of four rows (see Figure 36).
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
46 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
FROXPQV
GLVSOD\5$0FROXPQVVHJPHQWRXWSXWV6
URZV
E E
E E
E E
GLVSOD\5$0URZV
E E
EDFNSODQHRXWSXWV
%3
E E E E E E E E
06%
/6%
WUDQVPLWWHGGDWDE\WH
DDD
Fig 36. Display RAM filling order in 1:4 multiplex drive mode
In order to fill the whole four RAM rows 30 bytes need to be sent to the PCA9620. After
the last byte sent, the data pointer is wrapped around to column 0 to start a possible RAM
content update (see Figure 37). Even if a data byte is transmitted during the wrapping of
the data pointer, all the bits in the byte will be written correctly.
FROXPQV
GLVSOD\5$0FROXPQVVHJPHQWRXWSXWV6
GDWDSRLQWHU
GLVSOD\5$0
E
E
E
E
E
E
E
E
ZUDSDURXQG
DDD
Fig 37. Data pointer wrap around in 1:4 multiplex drive mode
8.9.1.4
RAM filling in 1:6 multiplex drive mode
In the 1:6 multiplex drive mode the RAM is organized in six rows and 60 columns. The
eight transmitted data bits are placed in such a way, that a column is filled up (see
Figure 38).
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
47 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
FROXPQV
GLVSOD\5$0FROXPQVVHJPHQWRXWSXWV6
GDWDSRLQWHU
LQFUHPHQWDWLRQ
D D E F
D D E F
URZV
D E E F
GLVSOD\5$0URZV
EDFNSODQHRXWSXWV
%3
D E E F
D E F F
D E F F
06%
/6%
D D D D D D D D
E E E E E E E E
F F F F F F F F
WUDQVPLWWHGGDWDE\WHV
DDD
Fig 38. Display RAM filling order in 1:6 multiplex drive mode
The remaining bits are wrapped up into the next column. In order to fill the whole RAM
addresses 45 bytes need to be sent to the PCA9620. After the last byte sent, the data
pointer is wrapped around to column 0 to start a possible RAM content update (see
Figure 39). Even if a data byte is transmitted during the wrapping of the data pointer, all
the bits in the byte will be written correctly.
GDWDSRLQWHU
GLVSOD\5$0
E F
D D
E F
D D
E F
D E
E F
D E
F F
D E
F F
D E
ZUDSDURXQG
DDD
Fig 39. Data pointer wrap around in 1:6 multiplex drive mode
8.9.1.5
RAM filling in 1:8 multiplex drive mode
In the 1:8 multiplex drive mode the eight transmitted data bits are placed into eight rows of
one display RAM column (see Figure 40).
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
48 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
FROXPQV
WUDQVPLWWHGGDWDE\WH
GLVSOD\5$0FROXPQVVHJPHQWRXWSXWV6
06%
/6%
E E E E E E E E
E
E
URZV
E
GLVSOD\5$0URZV
EDFNSODQHRXWSXWV
%3
E
E
E
E
E
DDD
Fig 40. Display RAM filling order in 1:8 multiplex drive mode
In order to fill the whole RAM addresses 60 bytes need to be sent to the PCA9620. After
the last byte sent, the data pointer is wrapped around to column 0 to start a possible RAM
content update (see Figure 41). In this case, there is no situation possible where a
transmitted data byte can be written over the RAM boundary.
GDWDSRLQWHU
GLVSOD\5$0
E
D
E
D
E
D
E
D
E
D
E
D
E
D
E
D
ZUDSDURXQG
DDD
Fig 41. Data pointer wrap around in 1:8 multiplex drive mode
8.9.2 Bank selection
A RAM bank can be thought of as a collection of RAM rows. The PCA9620 includes a
RAM bank switching feature in the static, 1:2, and 1:4 multiplex drive modes.
The RAM bank switching gives the provision for preparing display information in an
alternative bank and to be able to switch to it once it is complete. Input and output banks
can be set independently from one another with the input-bank-select and the
output-bank-select commands; Figure 42 shows the concept.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
49 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
,1387%$1.6(/(&7&200$1'
&21752/67+(,1387'$7$3$7+
287387%$1.6(/(&7&200$1'
&21752/67+(287387'$7$3$7+
%$1.
0,&52&21752//(5
5$0
',63/$<
%$1.
DDD
Fig 42. Example of bank selection in 1:4 multiplex mode
In Figure 42 an example is shown for 1:4 multiplex drive mode. The displayed data is read
from the first four rows of the memory (bank 0), while the transmitted data is stored in the
second four rows of the memory (bank 4) which is currently not accessed for the reading.
Therefore different content can be loaded into the first and second four RAM rows which
will be immediately displayed on the LCD by switching it with the output-bank-select
command (see Figure 43).
FROXPQV
GLVSOD\5$0FROXPQVVHJPHQWRXWSXWV6
URZV
RXWSXW5$0EDQN
WRWKH/&'
GLVSOD\5$0URZV EDFNSODQHRXWSXWV %3
WRWKH5$0
LQSXW5$0EDQN
DDD
Fig 43. Example of the input-bank-select and the output-bank-select command with
multiplex drive mode 1:4
8.9.2.1
Input-bank-select
The input-bank-select command (see Table 19 on page 13) loads display data into the
display RAM in accordance with the selected LCD drive configuration.
• In static drive mode, an individual content can be stored in each RAM bank (bank 0 to
bank 7 which corresponds to row 0 to row 7).
• In 1:2 multiplex drive mode, individual content for RAM bank 0 (row 0 and row 1),
RAM bank 2 (row 2 and row 3), RAM bank 4 (row 4 and 5) and RAM bank 6 (row 6
and row 7) can be stored.
• In 1:4 multiplex drive mode individual content can be stored in RAM bank 0 (row 0 to
row 3) and RAM bank 4 (row 4 to row 7).
The input-bank-select command works independently to the output-bank-select.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
50 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
8.9.2.2
Output-bank-select
The output-bank-select command (see Table 20 on page 13) selects the display RAM
transferring it to the display register in accordance with the selected LCD drive
configuration.
• In the static drive mode, it is possible to request the content of RAM bank 1 (row 1) to
RAM bank 7 (row 7) for display instead of the default RAM bank 0 (row 0).
• In 1:2 multiplex drive mode, the content of RAM bank 2 (row 2 and row 3) or of RAM
bank 4 (row 4 and row 5) or of RAM bank 6 (row 6 and row 7) may be selected
instead of the default RAM bank 0 (row 0 and row 1).
• In 1:4 multiplex drive mode, the content of RAM bank 4 (row 4, 5, 6, and 7) may be
selected instead of RAM bank 0 (row 0, 1, 2, and 3).
The output-bank-select command works independently to the input-bank-select.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
51 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
9. I2C-bus interface characteristics
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 44).
6'$
6&/
GDWDOLQH
VWDEOH
GDWDYDOLG
FKDQJH
RIGDWD
DOORZHG
PED
Fig 44. Bit transfer
9.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW change of the data line, while the clock is HIGH is defined as the START
condition (S).
A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP
condition (P).
The START and STOP conditions are shown in Figure 45.
6'$
6'$
6&/
6&/
6
3
67$57FRQGLWLRQ
6723FRQGLWLRQ
PEF
Fig 45. Definition of START and STOP conditions
9.3 System configuration
A device generating a message is a transmitter; a device receiving a message is the
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves. The system configuration is shown in Figure 46.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
52 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
0$67(5
75$160,77(5
5(&(,9(5
6/$9(
75$160,77(5
5(&(,9(5
6/$9(
5(&(,9(5
0$67(5
75$160,77(5
5(&(,9(5
0$67(5
75$160,77(5
6'$
6&/
PJD
Fig 46. System configuration
9.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 47.
GDWDRXWSXW
E\WUDQVPLWWHU
QRWDFNQRZOHGJH
GDWDRXWSXW
E\UHFHLYHU
DFNQRZOHGJH
6&/IURP
PDVWHU
6
67$57
FRQGLWLRQ
FORFNSXOVHIRU
DFNQRZOHGJHPHQW
PEF
Fig 47. Acknowledgement on the I2C-bus
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
53 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
9.5 I2C-bus controller
The PCA9620 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from PCA9620 are the
acknowledge signals and the temperature readout byte of the selected device.
9.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
9.7 I2C-bus slave address
Device selection depends on the I2C-bus slave address.
Four different I2C-bus slave addresses can be used to address the PCA9620 (see
Table 33).
Table 33.
I2C slave address
Slave address
Bit
7
6
5
4
3
2
1
MSB
slave address
0
0
LSB
1
1
1
0
A1
A0
R/W
The least significant bit of the slave address byte is bit R/W. Bit 1 and bit 2 of the slave
address are defined by connecting the inputs A0 and A1 to either VSS (logic 0) or VDD
(logic 1). Therefore, four instances of PCA9620 can be distinguished on the same
I2C-bus.
9.8 I2C-bus protocol
5: VODYHDGGUHVV
FRQWUROE\WH
$ $
& 5
6 $
2 6
5$0FRPPDQGE\WH
/
6 3
%
0
$ 6
%
(;$03/(6
DWUDQVPLWWZRE\WHVRI5$0GDWD
6 $ $ $ $
5$0'$7$
$
$
&200$1'
$ $
&200$1'
$ 3
$
&200$1'
$ $
5$0'$7$
$
5$0'$7$
$ 3
EWUDQVPLWWZRFRPPDQGE\WHV
6 $ $
$ FWUDQVPLWRQHFRPPDQGE\WHDQGWZR5$0GDWHE\WHV
6 $ $
$ 5$0'$7$
$ 3
DDD
Fig 48. I2C-bus protocol write mode
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
54 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
The I2C-bus protocol is shown in Figure 48. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of the four PCA9620 slave
addresses available. All PCA9620’s with the corresponding A1 and A0 level acknowledge
in parallel to the slave address, but all PCA9620 with the alternative A1 and A0 levels
ignore the whole I2C-bus transfer.
After acknowledgement, a control byte follows which defines if the next byte is RAM or
command information. The control byte also defines if the next byte is a control byte or
further RAM or command data.
Table 34.
Control byte description
Bit
Symbol
7
CO
6
Value
Description
continue bit
0
last control byte
1
control bytes continue
RS
register selection
0
command register
1
5 to 0
-
data register
-
not relevant
06%
&2 56
/6%
QRWUHOHYDQW
PJO
Fig 49. Control byte format
In this way it is possible to configure the device and then fill the display RAM with little
overhead.
The display bytes are stored in the display RAM at the address specified by the data
pointer.
The acknowledgement after each byte is made only by the (A0 and A1) addressed
PCA9620. After the last display byte, the I2C-bus master issues a STOP condition (P).
Alternatively a START may be issued to RESTART an I2C-bus access.
If a temperature readout (byte TD[7:0]) is made the R/W bit must be logic 1 and then the
next data byte following is provided by the PCA9620 as shown in Figure 50.
5: VODYHDGGUHVV
6 WHPSHUDWXUH
UHDGRXWE\WH
0
$ $
$ 6
%
DFNQRZOHGJH
IURP3&$
/
6 $ 3
%
DFNQRZOHGJH
IURPPDVWHU
DDD
Fig 50. I2C-bus protocol read mode
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
55 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
10. Internal circuitry
9''
$$7
7&/.
966
79/&'6'$
6&/9''9''
9/&'
966
%3WR%3
6WR6
966
DDD
Fig 51. Device protection diagram
11. Safety notes
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
CAUTION
Semiconductors are light sensitive. Exposure to light sources can cause the IC to
malfunction. The IC must be protected against light. The protection must be applied to all
sides of the IC.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
56 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
12. Limiting values
Table 35. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDD1
supply voltage 1
analog and digital
0.5
+6.5
V
VDD2
supply voltage 2
charge pump
0.5
+6.5
V
IDD1
supply current 1
analog and digital
50
+50
mA
IDD2
supply current 2
charge pump
50
+50
mA
VLCD
LCD supply voltage
0.5
+10
V
IDD(LCD)
LCD supply current
50
+50
mA
Vi
input voltage
0.5
+6.5
V
II
input current
10
+10
mA
VO
output voltage
0.5
+10
V
0.5
+6.5
V
IO
output current
10
+10
mA
ISS
ground supply current
50
+50
mA
Ptot
total power dissipation
-
400
mW
P/out
power dissipation per
output
-
100
mW
VESD
electrostatic discharge
voltage
on pins CLK,
SDA, SCL, A0,
A1, T1, T2, T3
on pins S0 to S59,
BP0 to BP7
on pins SDA, CLK
PCA9620
Product data sheet
HBM
[1]
-
4000
V
CDM
[2]
-
1500
V
-
100
mA
65
+150
C
40
+105
C
Ilu
latch-up current
[3]
Tstg
storage temperature
[4]
Tamb
ambient temperature
operating device
[1]
Pass level; Human Body Model (HBM), according to Ref. 8 “JESD22-A114”.
[2]
Pass level; Charged-Device Model (CDM), according to Ref. 9 “JESD22-C101”.
[3]
Pass level; latch-up testing according to Ref. 10 “JESD78” at maximum ambient temperature (Tamb(max)).
[4]
According to the store and transport requirements (see Ref. 14 “UM10569”) the devices have to be stored
at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
57 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
13. Static characteristics
Table 36. Static characteristics
VDD1 = 2.5 V to 5.5 V; VDD2 = 2.5 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = 40 C to +105 C; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.5
-
5.5
V
2.5
-
5.5
V
Supplies
VDD1
supply voltage 1
VDD2
supply voltage 2
VDD2 VDD1
LCD supply voltage
VLCD VDD2
VLCD
[1]
2.5
-
9.0
V
[2][3]
0.10
-
+0.10
V
VLCD
LCD voltage variation
IDD(pd)
power-down mode supply on pin VDD1
current
[4][5]
-
1.0
3.0
A
IDD1
supply current 1
[5][6]
-
100
200
A
IDD2
supply current 2
charge pump off; external VLCD
[5][6]
-
0.5
3.0
A
charge pump on; internal VLCD
[5][7]
-
250
550
A
-
125
250
A
-
12
35
A
VDD1 = VDD2 = 5.0 V;
VLCD = 6.99 V
fosc = 9.6 kHz
IDD(LCD)
LCD supply current
external VLCD
[5][8]
ILCD(pd)
power-down LCD current
external VLCD
[4][5]
RO
output resistance
of charge pump (driving capabilities)
Tacc
temperature accuracy
charge pump set to 2 VDD2;
Iload = 3 mA (on pin VLCD)
[9]
0.2
0.85
1.6
k
charge pump set to 3 VDD2;
Iload = 2 mA (on pin VLCD)
[10]
2.0
3.2
4.5
k
Tamb = 40 C to +105 C
6
-
+6
C
Tamb = 27 C
4
-
+4
C
readout temperature error;
VDD1 = 5.0 V
Logic
VI
input voltage
VSS 0.5 -
VDD + 0.5 V
VIL
LOW-level input voltage
on pins CLK, A1, A0
-
-
0.3VDD
V
VIH
HIGH-level input voltage
on pins CLK, A1, A0
0.7VDD
-
-
V
VO
output voltage
0.5
-
VDD + 0.5 V
VOH
HIGH-level output voltage on pin CLK
0.8VDD
-
-
V
VOL
LOW-level output voltage
-
-
0.2VDD
V
IOH
HIGH-level output current output source current;
VOH = 4.6 V; VDD = 5 V; on pin CLK
1
-
-
mA
IOL
LOW-level output current
1
-
-
mA
VPOR
power-on reset voltage
[11]
-
-
1.6
V
leakage current
[12]
-
0
-
A
IL
PCA9620
Product data sheet
on pin CLK
output sink current;
VOL = 0.4 V; VDD = 5 V; on pin CLK
Vi = VDD or VSS; on pins CLK, A1,
A0, T1, T2, T3
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
58 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
Table 36. Static characteristics …continued
VDD1 = 2.5 V to 5.5 V; VDD2 = 2.5 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = 40 C to +105 C; unless otherwise
specified.
Symbol
I2C-bus;
Parameter
pins SDA and
Conditions
Min
Typ
Max
Unit
SCL[13]
VI
input voltage
VSS 0.5 -
5.5
V
VIL
LOW-level input voltage
pins SCL, SDA
-
-
0.3VDD
V
VIH
HIGH-level input voltage
pins SCL, SDA
0.7VDD
-
-
V
VO
output voltage
pins SCL, SDA
0.5
-
5.5
V
IOL
LOW-level output current
VOL = 0.4 V; VDD = 5 V; on pin SDA
3
-
-
mA
IL
leakage current
VI = VDD or VSS
[12]
-
0
-
A
output voltage variation
on pins BP0 to BP7
[14]
15
-
+15
mV
on pins S0 to S59
[15]
15
-
+15
mV
VLCD = 7 V; on pins BP0 to BP7
[16]
0.3
0.8
1.5
k
VLCD = 7 V; on pins S0 to S59
[16]
0.6
1.5
3
k
LCD outputs
VO
output resistance
RO
[1]
When supplying external VLCD it must be VLCD VDD2. Also when using the internal charge pump to generate a certain VLCD, VPR[7:0]
must be set to a value that the voltage is higher than VDD2 (see Section 8.4.3 on page 34).
[2]
Calibrated at testing stage. VLCD temperature compensation is disabled.
[3]
According to Equation 6 on page 34: VLCD = 133 0.03 + 3 = 6.99 V.
[4]
Display is disabled; I2C-bus inactive; temperature measurement disabled.
[5]
The typical value is defined at VDD1 = VDD2 = 5.0 V, VLCD = 7.0 V and 30 C.
[6]
Temperature measurement enabled; 1:8 multiplex drive mode; 1⁄4 bias; display enabled; LCD outputs are open circuit; RAM is all written
with logic 1; inputs at VSS or VDD; internal clock with the default prescale factor; I2C-bus inactive.
[7]
VDD2 = 5.0 V; charge pump set to 2 VDD2; VPR[7:0] set for VLCD = 7.0 V; 1:8 multiplex drive mode; 1⁄4 bias; temperature measurement
enabled; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; external clock with 50 %
duty factor; I2C-bus inactive.
[8]
External supplied VLCD = 7.0 V; 1:8 multiplex drive mode; 1⁄4 bias; temperature measurement enabled; display enabled; LCD outputs
are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.
[9]
VDD2 = 5.0 V; charge pump set to 2 VDD2; VPR[7:0] set for VLCD = 9.0 V; display disabled; CPF (see Table 23 on page 14) set logic 0.
[10] VDD2 = 4.0 V; charge pump set to 3 VDD2; VPR[7:0] set for VLCD = 9.0 V; display disabled; CPF (see Table 23 on page 14) set logic 0.
[11] If VDD1 > VPOR then no reset occurs.
[12] In case of an ESD event, the value may increase slightly.
[13] The I2C-bus interface of PCA9620 is 5 V tolerant.
[14] Variation between any 2 backplanes on a given voltage level; static measured.
[15] Variation between any 2 segments on a given voltage level; static measured.
[16] Outputs measured one at a time.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
59 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
DDQ
9/&'
9
WHPSHUDWXUH&
(1) VPR[7:0] = 85h.
(2) VPR[7:0] = 64h.
(3) VPR[7:0] = A4h.
Temperature compensation disabled.
Fig 52. Typical VLCD with respect to temperature
DDQ
,''
$
WHPSHUDWXUH&
VDD1 = 5.0 V.
Fig 53. Typical IDD1 with respect to temperature
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
60 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
DDQ
,''
$
WHPSHUDWXUH&
Charge pump set to 2 VDD2; VLCD = 7.0 V; VDD1 = VDD2 = 5.0 V.
Fig 54. Typical IDD2 with respect to temperature
DDQ
,/&'
$
WHPSHUDWXUH&
VLCD = 7.0 V, external supplied; VDD1 = VDD2 = 5.0 V; display enabled, but no display attached.
Fig 55. Typical ILCD with respect to temperature
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
61 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
14. Dynamic characteristics
Table 37. Dynamic characteristics
VDD1 = 2.5 V to 5.5 V; VDD2 = 2.5 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = 40 C to +105 C; unless otherwise
specified.
Symbol
Parameter
fosc
oscillator frequency
fclk(ext)
external clock frequency
tclk(H)
HIGH-level clock time
tclk(L)
LOW-level clock time
Conditions
on pin CLK; see Table 18 on
page 12
[1][2]
external clock source used
Min
Typ
Max
Unit
8160
9600
11040
Hz
450
-
14500
Hz
33
-
-
s
33
-
-
s
Timing characteristics: I2C-bus[3]
fSCL
SCL frequency
-
-
400
kHz
tBUF
bus free time between a
STOP and START condition
1.3
-
-
s
tHD;STA
hold time (repeated) START
condition
0.6
-
-
s
tSU;STA
set-up time for a repeated
START condition
0.6
-
-
s
tVD;DAT
data valid time
[4]
-
-
0.9
s
tVD;ACK
data valid acknowledge time
[5]
-
-
0.9
s
tLOW
LOW period of the SCL clock
1.3
-
-
s
tHIGH
HIGH period of the SCL clock
0.6
-
-
s
tf
fall time
of both SDA and SCL signals
-
-
0.3
s
tr
rise time
of both SDA and SCL signals
-
-
0.3
s
Cb
capacitive load for each bus
line
-
-
400
pF
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
tSU;STO
set-up time for STOP
condition
0.6
-
-
s
tw(spike)
spike pulse width
-
-
50
ns
[1]
Internal calibration made with OTP so that the maximum variation is 15 % over whole temperature and voltage range. The typical fosc
generates a typical frame frequency of 200 Hz when the default frequency division factor is used (see Section 8.5.3 on page 42).
[2]
The typical value is defined at VDD1 = VDD2 = 5.0 V and 30 C.
[3]
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
[4]
tVD;DAT = minimum time for valid SDA output following SCL LOW.
[5]
tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
62 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
IFON
WFON/
WFON+
9''
&/.
9''
DDD
Fig 56. Driver timing waveforms
SURWRFRO
67$57
FRQGLWLRQ
6
W6867$
ELW
06%
$
W/2:
ELW
$
W+,*+
I
ELW
5:
DFNQRZOHGJH
$
6723
FRQGLWLRQ
3
6&/
6&/
W%8)
WU
WI
6'$
W68'$7
W+'67$
W+''$7
W9''$7
W9'$&.
W68672
DDD
Fig 57. I2C-bus timing waveforms
15. Test information
15.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated
circuits, and is suitable for use in automotive applications.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
63 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
16. Package outline
/4)3SODVWLFORZSURILOHTXDGIODWSDFNDJHOHDGVERG\[[PP
627
F
\
;
$
=(
H
( +(
$ $
$
$
Z 0
ș
ES
/S
/
SLQLQGH[
GHWDLO;
='
H
Y 0 $
Z 0
ES
'
%
+'
Y 0 %
PP
VFDOH
',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV
$
81,7 PD[
PP
$
$
$
ES
F
'
(
+'
H
+(
/
/S
Y
Z
\
=' =(
ș
R
R
1RWH
3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
5()(5(1&(6
287/,1(
9(56,21
,(&
-('(&
627
(
06
-(,7$
(8523($1
352-(&7,21
,668('$7(
Fig 58. Package outline SOT315-1 (LQFP80)
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
64 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
17. Bare die outline
%DUHGLHERQGLQJSDGV
3&$8
'
SLQLQGH[
H
[
;
\
(
$
3
3
3
3
GHWDLO;
1RWHV
0DUNLQJFRGH3&
2XWOLQH
YHUVLRQ
SFDXBGR
5HIHUHQFHV
,(&
-('(&
-(,7$
(XURSHDQ
SURMHFWLRQ
,VVXHGDWH
3&$8
Fig 59. Bare die outline of PCA9620
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
65 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
Table 38. Dimensions of PCA9620
Original dimensions are in mm.
Unit
(mm)
A
D[1]
E[1]
e[2]
P1[3]
P2[4]
P3[3]
P4[4]
max
-
-
-
0.203
-
-
-
-
nom
0.38
3.166
3.166
-
0.065
0.056
0.065
0.056
min
-
-
-
0.075
-
-
-
-
[1]
Dimension includes saw lane (70 m).
[2]
See Table 39.
[3]
P1 and P3: pad size.
[4]
P2 and P4: passivation opening.
Table 39. Bonding pad description of PCA9620
All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see
Figure 59.
Symbol
S20
Pad
1
Location
Pitch
Description
X(m)
Y(m)
X(m)
Y(m)
1497.3
1208.7
-
-
S21
2
1497.3
1086.3
0
122.4
S22
3
1497.3
963.9
0
122.4
S23
4
1497.3
841.5
0
122.4
S24
5
1497.3
719.1
0
122.4
S25
6
1497.3
568.8
0
150.3
S26
7
1497.3
446.4
0
122.4
S27
8
1497.3
324.0
0
122.4
S28
9
1497.3
201.6
0
122.4
S29
10
1497.3
79.2
0
150.3
S30
11
1497.3
71.1
0
122.4
S31
12
1497.3
193.5
0
122.4
S32
13
1497.3
315.9
0
122.4
S33
14
1497.3
438.3
0
122.4
S34
15
1497.3
560.7
0
122.4
S35
16
1497.3
711.0
0
122.4
S36
17
1497.3
833.4
0
122.4
S37
18
1497.3
955.8
0
122.4
S38
19
1497.3
1078.2
0
122.4
S39
20
1497.3
1200.6
0
122.4
S40
21
1204.2
1497.3
-
-
S41
22
1081.8
1497.3
122.4
0
S42
23
959.4
1497.3
122.4
0
S43
24
837.0
1 497.3
122.4
0
S44
25
714.6
1497.3
122.4
0
S45
26
564.3
1497.3
150.3
0
S46
27
441.9
1497.3
122.4
0
PCA9620
Product data sheet
LCD segment output
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
66 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
Table 39. Bonding pad description of PCA9620 …continued
All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see
Figure 59.
Symbol
Pad
Location
X(m)
Pitch
Y(m)
Description
X(m)
Y(m)
S47
28
319.5
1497.3
122.4
0
S48
29
197.1
1497.3
122.4
0
S49
30
74.7
1497.3
122.4
0
S50
31
75.6
1497.3
150.3
0
S51
32
198.0
1497.3
122.4
0
S52
33
320.4
1497.3
122.4
0
S53
34
442.8
1497.3
122.4
0
S54
35
565.2
1497.3
122.4
0
S55
36
715.5
1497.3
150.3
0
S56
37
837.9
1497.3
122.4
0
S57
38
960.3
1497.3
122.4
0
S58
39
1082.7
1497.3
122.4
0
LCD segment output
S59
40
1205.1
1497.3
122.4
0
BP0
41
1497.3
1201.5
-
-
BP1
42
1497.3
1077.3
0
124.2
BP2
43
1497.3
953.1
0
124.2
BP3
44
1497.3
828.9
0
124.2
BP4
45
1497.3
676.8
0
152.1
BP5
46
1497.3
552.6
0
124.2
BP6
47
1497.3
428.4
0
124.2
BP7
48
1497.3
304.2
0
124.2
VLCD
49
1497.3
171.9
0
132.3
LCD supply voltage
VDD2
50
1497.3
47.7
0
124.2
supply voltage 2 (charge pump)
VDD1
51
1497.3
76.5
0
124.2
supply voltage 1 (analog and digital)
VSS
52
1497.3
166.5
0
90
ground supply voltage
T1
53
1497.3
241.2
0
74.7
test pin
T2
54
1497.3
315.9
0
74.7
T3
55
1497.3
430.2
0
114.3
CLK
56
1497.3
620.1
0
189.9
internal oscillator output, external oscillator input
A0
57
1497.3
729.9
0
109.8
I2C-bus slave address selection bit
A1
58
1497.3
806.4
0
76.5
SCL
59
1497.3
913.5
0
107.1
I2C-bus serial clock
SDA
60
1497.3
1116.9
0
203.4
I2C-bus serial data
S0
61
1205.1
1497.3
-
-
LCD segment output
S1
62
1082.7
1497.3
122.4
0
S2
63
960.3
1497.3
122.4
0
S3
64
837.9
1497.3
122.4
0
S4
65
715.5
1497.3
122.4
0
PCA9620
Product data sheet
LCD backplane output
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
67 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
Table 39. Bonding pad description of PCA9620 …continued
All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see
Figure 59.
Symbol
Pad
Location
X(m)
Pitch
Y(m)
X(m)
Description
Y(m)
S5
66
565.2
1497.3
150.3
0
S6
67
442.8
1497.3
122.4
0
S7
68
320.4
1497.3
122.4
0
S8
69
198.0
1497.3
122.4
0
S9
70
75.6
1497.3
122.4
0
S10
71
74.7
1497.3
150.3
0
S11
72
197.1
1497.3
122.4
0
S12
73
319.5
1497.3
122.4
0
S13
74
441.9
1497.3
122.4
0
S14
75
564.3
1497.3
122.4
0
S15
76
714.6
1497.3
150.3
0
S16
77
837.0
1497.3
122.4
0
S17
78
959.4
1497.3
122.4
0
S18
79
1081.8
1497.3
122.4
0
S19
80
1204.2
1497.3
122.4
0
Table 40.
LCD segment output
Alignment mark dimension and location of all PCA9620 types
Coordinates
X (m)
Y (m)
Location[1]
1495.8
1395.0
Dimension[2]
52.5
63.72
[1]
The x/y coordinates of the alignment mark location represent the position of the REF point (see Figure 60)
with respect to the center (x/y = 0) of the chip; see Figure 59.
[2]
The x/y values of the dimensions represent the extensions of the alignment mark in direction of the
coordinate axis (see Figure 60).
5()
\
[
DDD
Fig 60. Alignment mark
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
68 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
18. Packing information
18.1 Wafer information
P
P
P
6DZODQH
6HDOULQJSOXVJDSWR
DFWLYHFLUFXLWaPP
P
GHWDLO;
3LQ
6WUDLJKWHGJH
RIWKHZDIHU
;
0DUNLQJFRGH
DDD
Wafer thickness, see Table 41.
Fig 61. Wafer layout of PCA9620
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
69 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
Table 41.
PCA9620
Product data sheet
PCA9620 wafer information
Type number
Wafer thickness
Wafer diameter
Marking of bad die
PCA9620/5GA/Q1
0.687 mm
6 inch
wafer mapping
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
70 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
19. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
19.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
19.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
19.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
71 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
19.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 62) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 42 and 43
Table 42.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 43.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 62.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
72 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 62. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
73 of 84
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
PCA9620
Product data sheet
20. Appendix
20.1 LCD segment driver selection
Table 44.
Selection of LCD segment drivers
Type name
Number of elements at MUX
ffr (Hz)
Interface Package
AECQ100
40
80
120 160 -
-
-
1.8 to 5.5 1.8 to 5.5 32 to 256[1]
N
N
40 to 105 I2C / SPI
TSSOP56 Y
PCA8546ATT
-
-
-
176 -
-
-
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 95
I2C
TSSOP56 Y
PCA8546BTT
-
-
-
176 -
-
-
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 95
SPI
TSSOP56 Y
1.8 to 5.5 2.5 to 9
60 to
300[1]
Y
40 to 95
I2C
TQFP64
Y
60 to
300[1]
Y
Y
40 to 95
SPI
TQFP64
Y
N
N
40 to 85
I2C
LQFP80
N
N
40 to 95
I2C
LQFP80
Y
Y
40 to 105
I2C
LQFP80
Y
TSSOP56 N
-
-
-
Rev. 4 — 8 April 2015
All information provided in this document is subject to legal disclaimers.
PCA8547BHT
44
88
176 -
-
-
1.8 to 5.5 2.5 to 9
PCF85134HL
60
120 180 240 -
-
-
1.8 to 5.5 2.5 to 6.5 82
PCA85134H
PCA8543AHL
60
60
-
176 -
120 180 240 120 -
240 -
-
-
1.8 to 5.5 2.5 to 8
2.5 to 5.5 2.5 to 9
82
Y
N
60 to
300[1]
300[1]
Y
PCF8545ATT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 5.5 60 to
N
N
40 to 85
I2C
PCF8545BTT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 5.5 60 to 300[1]
N
N
40 to 85
SPI
TSSOP56 N
PCF8536AT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 85
I2C
TSSOP56 N
1.8 to 5.5 2.5 to 9
60 to
300[1]
N
N
40 to 85
SPI
TSSOP56 N
300[1]
TSSOP56 Y
PCF8536BT
-
-
-
176 252 320 -
PCA8536AT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 9
60 to
N
N
40 to 95
I2C
PCA8536BT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 95
SPI
TSSOP56 Y
PCF8537AH
44
88
-
176 276 352 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
Y
Y
40 to 85
I2C
TQFP64
N
1.8 to 5.5 2.5 to 9
60 to
300[1]
Y
Y
40 to 85
SPI
TQFP64
N
300[1]
PCF8537BH
44
88
-
176 276 352 -
44
88
-
176 276 352 -
1.8 to 5.5 2.5 to 9
60 to
Y
Y
40 to 95
TQFP64
Y
PCA8537BH
44
88
-
176 276 352 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
Y
Y
40 to 95
SPI
TQFP64
Y
PCA9620H
60
120 -
240 320 480 -
2.5 to 5.5 2.5 to 9
60 to 300[1]
Y
Y
40 to 105 I2C
LQFP80
Y
2.5 to 5.5 2.5 to 9
300[1]
Y
40 to 105
I2C
Bare die
Y
PCA9620U
60
120 -
240 320 480 -
60 to
Y
PCF8576DU
40
80
120 160 -
-
-
1.8 to 5.5 2.5 to 6.5 77
N
N
40 to 85
I2C
Bare die
N
PCF8576EUG
40
80
120 160 -
-
-
1.8 to 5.5 2.5 to 6.5 77
N
N
40 to 85
I2C
Bare die
N
N
40 to 105
I2C
Bare die
Y
N
40 to 85
I2C
Bare die
N
N
40 to 95
I2C
Bare die
Y
PCA8576FUG
PCF85133U
PCA85133U
40
80
80
80
120 160 -
160 240 320 160 240 320 -
-
-
1.8 to 5.5 2.5 to 8
200
N
1.8 to 5.5 2.5 to 6.5 82,
110[2]
1.8 to 5.5 2.5 to 8
110[2]
82,
N
N
PCA9620
74 of 84
© NXP Semiconductors N.V. 2015. All rights reserved.
PCA8537AH
I2C
60 x 8 LCD high-drive segment driver for automotive and industrial
PCA8553DTT
88
1:9
VLCD (V) VLCD (V)
Tamb (C)
charge temperature
pump
compensat.
1:2 1:3
44
1:6 1:8
VLCD (V)
1:1
PCA8547AHT
1:4
VDD (V)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Selection of LCD segment drivers …continued
Type name
Number of elements at MUX
ffr (Hz)
VLCD (V) VLCD (V)
Tamb (C)
charge temperature
pump
compensat.
AECQ100
PCA85233UG
80
160 240 320 -
-
-
1.8 to 5.5 2.5 to 8
150, 220[2]
N
N
40 to 105 I2C
Bare die
Y
PCF85132U
160 320 480 640 -
-
-
1.8 to 5.5 1.8 to 8
60 to 90[1]
N
N
40 to 85
I2C
Bare die
N
Y
40 to 105
I2C
Bare die
Y
N
40 to 95
I2C
Bare die
Y
N
N
40 to 95
I2C
Bare die
Y
Y
Y
40 to 85
I2C / SPI
Bare die
N
Y
40 to 105
I2C
Bare die
Y
PCA85132U
408 -
160 320 480 640 -
PCA85232U
160 320 480 640 -
PCF8538UG
102 204 -
PCA8538UG
102 204 -
Software programmable.
[2]
Hardware selectable.
-
-
2.5 to 5.5 4 to 12
1.8 to 5.5 1.8 to 8
1.8 to 5.5 1.8 to 8
45 to
300[1]
60 to
90[1]
117 to
176[1]
408 612 816 918 2.5 to 5.5 4 to 12
45 to 300[1]
408 612 816 918 2.5 to 5.5 4 to 12
300[1]
45 to
Y
N
Y
/ SPI
/ SPI
PCA9620
75 of 84
© NXP Semiconductors N.V. 2015. All rights reserved.
60 x 8 LCD high-drive segment driver for automotive and industrial
Rev. 4 — 8 April 2015
All information provided in this document is subject to legal disclaimers.
[1]
-
1:9
Interface Package
1:2 1:3
102 204 -
1:6 1:8
VLCD (V)
1:1
PCA8530DUG
1:4
VDD (V)
NXP Semiconductors
PCA9620
Product data sheet
Table 44.
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
21. Abbreviations
Table 45.
PCA9620
Product data sheet
Abbreviations
Acronym
Description
AEC
Automotive Electronics Council
CDM
Charged-Device Model
DC
Direct Current
EPROM
Erasable Programmable Read-Only Memory
ESD
ElectroStatic Discharge
HBM
Human Body Model
I2C
Inter-Integrated Circuit bus
IC
Integrated Circuit
LCD
Liquid Crystal Display
LSB
Least Significant Bit
MSB
Most Significant Bit
MSL
Moisture Sensitivity Level
MUX
Multiplexer
OTP
One Time Programmable
PCB
Printed-Circuit Board
POR
Power-On Reset
RC
Resistance-Capacitance
RAM
Random Access Memory
RMS
Root Mean Square
SCL
Serial CLock line
SDA
Serial DAta line
SMD
Surface Mount Device
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
76 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
22. References
[1]
AN10365 — Surface mount reflow soldering description
[2]
AN10706 — Handling bare die
[3]
AN10853 — ESD and EMC sensitivity of IC
[4]
AN11267 — EMC and system level ESD design guidelines for LCD drivers
[5]
IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[6]
IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[7]
IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices
[8]
JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[9]
JESD22-C101 — Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
[10] JESD78 — IC Latch-Up Test
[11] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[12] SNV-FA-01-02 — Marking Formats Integrated Circuits
[13] UM10204 — I2C-bus specification and user manual
[14] UM10569 — Store and transport requirements
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
77 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
23. Revision history
Table 46.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9620 v.4
20150408
Product data sheet
-
PCA9620 v.3
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Fixed typos
PCA9620 v.3
20130703
Product data sheet
-
PCA9620 v.2
PCA9620 v.2
20111108
Product data sheet
-
PCA9620 v.1
PCA9620 v.1
20101209
Product data sheet
-
-
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
78 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
24. Legal information
24.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
24.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
24.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA9620
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
79 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
24.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
25. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
80 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
26. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .3
Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .7
Commands of PCA9620 . . . . . . . . . . . . . . . . . .8
Initialize - initialize command bit description . . .9
OTP-refresh - OTP-refresh command bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Oscillator-ctrl - oscillator control command bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Charge-pump-ctrl - charge pump control
command bit description . . . . . . . . . . . . . . . . .10
Temp-msr-ctrl - temperature measurement control
command bit description . . . . . . . . . . . . . . . . .10
Set-VPR-MSB - set VPR MSB command bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Set-VPR-LSB - set VPR LSB command bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Display-enable - display enable command bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Set-MUX-mode - set multiplex drive mode
command bit description . . . . . . . . . . . . . . . . . 11
Set-bias-mode - set bias mode command bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Load-data-pointer - load data pointer command
bit description . . . . . . . . . . . . . . . . . . . . . . . . .12
Frame frequency - frame frequency and output
clock frequency command bit description . . . .12
Frame frequency values . . . . . . . . . . . . . . . . .12
Input-bank-select - input bank select command
bit description[1] . . . . . . . . . . . . . . . . . . . . . . . .13
Output-bank-select - output bank select
command bit description[1] . . . . . . . . . . . . . . . .13
Write-RAM-data - write RAM data command
bit description[1] . . . . . . . . . . . . . . . . . . . . . . . .14
Temp-read - temperature readout command
bit description[1] . . . . . . . . . . . . . . . . . . . . . . . .14
Invmode_CPF_ctrl - inversion mode and
charge pump frequency prescaler command
bit description . . . . . . . . . . . . . . . . . . . . . . . . .14
Temp-filter - digital temperature filter command
bit description . . . . . . . . . . . . . . . . . . . . . . . . .15
Selection of possible display configurations . . .16
Reset states . . . . . . . . . . . . . . . . . . . . . . . . . . .18
LCD drive modes: summary of characteristics .24
Parameters of VLCD generation . . . . . . . . . . . .34
Temperature measurement update rate . . . . .38
Temperature coefficients. . . . . . . . . . . . . . . . . .40
Calculation of the temperature compensated
voltage VT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Mapping of output pins and corresponding
output signals with respect to the multiplex
driving mode . . . . . . . . . . . . . . . . . . . . . . . . . .42
I2C slave address . . . . . . . . . . . . . . . . . . . . . . .54
Control byte description . . . . . . . . . . . . . . . . . .55
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .57
PCA9620
Product data sheet
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Static characteristics . . . . . . . . . . . . . . . . . . . . 58
Dynamic characteristics . . . . . . . . . . . . . . . . . 62
Dimensions of PCA9620 . . . . . . . . . . . . . . . . . 66
Bonding pad description of PCA9620 . . . . . . . 66
Alignment mark dimension and location of all
PCA9620 types . . . . . . . . . . . . . . . . . . . . . . . . 68
PCA9620 wafer information . . . . . . . . . . . . . . . 70
SnPb eutectic process (from J-STD-020D) . . . 72
Lead-free process (from J-STD-020D) . . . . . . 72
Selection of LCD segment drivers . . . . . . . . . 74
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 76
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 78
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
81 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
27. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Block diagram of PCA9620 . . . . . . . . . . . . . . . . . .4
Pin configuration for LQFP80 (PCA9620H) . . . . . .5
Pin configuration for PCA9620U (bare die) . . . . . .6
Example of displays suitable for PCA9620 . . . . .16
Typical system configuration when using the internal
VLCD generation . . . . . . . . . . . . . . . . . . . . . . . . . .16
Typical system configuration when using an external
VLCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Recommended start-up sequence when
using the internal charge pump and the internal
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Recommended start-up sequence when using
an external supplied VLCD and the internal clock
signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Recommended start-up sequence when using
the internal charge pump and an external clock
signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Recommended start-up sequence when using
an external supplied VLCD and an external clock
signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Recommended power-down sequence for
minimum power-down current when using the
internal charge pump and the internal clock
signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Recommended power-down sequence when
using an external supplied VLCD and the internal
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Recommended power-down sequence when
using the internal charge pump and an external
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Recommended power-down sequence when
using an external supplied VLCD and an external
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Electro-optical characteristic: relative
transmission curve of the liquid . . . . . . . . . . . . . .25
Static drive mode waveforms (line inversion
mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Waveforms for the 1:2 multiplex drive mode
with 1⁄2 bias (line inversion mode) . . . . . . . . . . . .27
Waveforms for the 1:2 multiplex drive mode
with 1⁄3 bias (line inversion mode) . . . . . . . . . . . .28
Waveforms for the 1:4 multiplex drive mode
with 1⁄3 bias (line inversion mode) . . . . . . . . . . . .29
Waveforms for 1:6 multiplex drive mode
with 1⁄3 bias (line inversion mode) . . . . . . . . . . . .30
Waveforms for 1:6 multiplex drive mode
with 1⁄4 bias (line inversion mode) . . . . . . . . . . . .31
Waveforms for 1:8 multiplex drive mode
with 1⁄4 bias (line inversion mode) . . . . . . . . . . . .32
Waveforms for 1:8 multiplex drive mode
with 1⁄4 bias (frame inversion mode) . . . . . . . . . .33
VLCD generation including temperature
compensation . . . . . . . . . . . . . . . . . . . . . . . . . . .34
VLCD programming of PCA9620 (assuming
VT[7:0] = 0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Charge pump model (used to characterize the
PCA9620
Product data sheet
driving strength) . . . . . . . . . . . . . . . . . . . . . . . . . 36
Fig 27. Power efficiency of the charge pump . . . . . . . . . 37
Fig 28. Temperature measurement block with digital
temperature filter . . . . . . . . . . . . . . . . . . . . . . . . . 38
Fig 29. Temperature measurement delay . . . . . . . . . . . . 39
Fig 30. Example of segmented temperature coefficients 40
Fig 31. Display RAM bitmap . . . . . . . . . . . . . . . . . . . . . . 44
Fig 32. Display RAM filling order in static drive mode . . . 45
Fig 33. Discarded bits and data pointer wrap around
at the end of data transmission . . . . . . . . . . . . . . 46
Fig 34. Display RAM filling order in 1:2 multiplex drive
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Fig 35. Data pointer wrap around in 1:2 multiplex drive
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Fig 36. Display RAM filling order in 1:4 multiplex drive
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Fig 37. Data pointer wrap around in 1:4 multiplex drive
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Fig 38. Display RAM filling order in 1:6 multiplex drive
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Fig 39. Data pointer wrap around in 1:6 multiplex drive
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Fig 40. Display RAM filling order in 1:8 multiplex drive
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Fig 41. Data pointer wrap around in 1:8 multiplex drive
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Fig 42. Example of bank selection in 1:4 multiplex
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Fig 43. Example of the input-bank-select and the
output-bank-select command with multiplex
drive mode 1:4 . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Fig 44. Bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Fig 45. Definition of START and STOP conditions . . . . . 52
Fig 46. System configuration. . . . . . . . . . . . . . . . . . . . . . 53
Fig 47. Acknowledgement on the I2C-bus. . . . . . . . . . . . 53
Fig 48. I2C-bus protocol write mode . . . . . . . . . . . . . . . . 54
Fig 49. Control byte format . . . . . . . . . . . . . . . . . . . . . . . 55
Fig 50. I2C-bus protocol read mode . . . . . . . . . . . . . . . . 55
Fig 51. Device protection diagram . . . . . . . . . . . . . . . . . 56
Fig 52. Typical VLCD with respect to temperature . . . . . . 60
Fig 53. Typical IDD1 with respect to temperature . . . . . . . 60
Fig 54. Typical IDD2 with respect to temperature . . . . . . . 61
Fig 55. Typical ILCD with respect to temperature . . . . . . . 61
Fig 56. Driver timing waveforms . . . . . . . . . . . . . . . . . . . 63
Fig 57. I2C-bus timing waveforms . . . . . . . . . . . . . . . . . . 63
Fig 58. Package outline SOT315-1 (LQFP80) . . . . . . . . 64
Fig 59. Bare die outline of PCA9620. . . . . . . . . . . . . . . . 65
Fig 60. Alignment mark . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Fig 61. Wafer layout of PCA9620 . . . . . . . . . . . . . . . . . . 69
Fig 62. Temperature profiles for large and small
components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
82 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
28. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
4.1
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
5
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
7.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
7.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
8
Functional description . . . . . . . . . . . . . . . . . . . 8
8.1
Commands of PCA9620 . . . . . . . . . . . . . . . . . . 8
8.1.1
Command: initialize . . . . . . . . . . . . . . . . . . . . . 8
8.1.2
Command: OTP-refresh . . . . . . . . . . . . . . . . . . 9
8.1.3
Command: oscillator-ctrl . . . . . . . . . . . . . . . . . . 9
8.1.4
Command: charge-pump-ctrl . . . . . . . . . . . . . 10
8.1.5
Command: temp-msr-ctrl . . . . . . . . . . . . . . . . 10
8.1.6
Command: set-VPR-MSB and set-VPR-LSB . 10
8.1.7
Command: display-enable . . . . . . . . . . . . . . . 11
8.1.8
Command: set-MUX-mode . . . . . . . . . . . . . . . 11
8.1.9
Command: set-bias-mode . . . . . . . . . . . . . . . 11
8.1.10
Command: load-data-pointer . . . . . . . . . . . . . 11
8.1.11
Command: frame-frequency . . . . . . . . . . . . . . 12
8.1.12
Bank select commands . . . . . . . . . . . . . . . . . 13
8.1.12.1 Command: input-bank-select . . . . . . . . . . . . . 13
8.1.12.2 Command: output-bank-select . . . . . . . . . . . . 13
8.1.13
Command: write-RAM-data . . . . . . . . . . . . . . 14
8.1.14
Command: temp-read. . . . . . . . . . . . . . . . . . . 14
8.1.15
Command: invmode_CPF_ctrl . . . . . . . . . . . . 14
8.1.16
Command: temp-filter . . . . . . . . . . . . . . . . . . . 15
8.2
Possible display configurations . . . . . . . . . . . 15
8.3
Start-up and shut-down. . . . . . . . . . . . . . . . . . 17
8.3.1
Power-On Reset (POR) . . . . . . . . . . . . . . . . . 17
8.3.2
Recommended start-up sequences . . . . . . . . 19
8.3.3
Recommended power-down sequences . . . . 21
8.4
LCD voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.4.1
LCD voltage selector . . . . . . . . . . . . . . . . . . . 23
8.4.1.1
Electro-optical performance . . . . . . . . . . . . . . 25
8.4.2
LCD drive mode waveforms . . . . . . . . . . . . . . 26
8.4.2.1
Static drive mode . . . . . . . . . . . . . . . . . . . . . . 26
8.4.2.2
1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 27
8.4.2.3
1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 29
8.4.2.4
1:6 Multiplex drive mode. . . . . . . . . . . . . . . . . 30
8.4.2.5
1:8 Multiplex drive mode. . . . . . . . . . . . . . . . . 32
8.4.3
VLCD generation . . . . . . . . . . . . . . . . . . . . . . . 34
8.4.4
External VLCD supply . . . . . . . . . . . . . . . . . . . 35
8.4.5
8.4.6
8.4.7
8.4.8
8.5
8.5.1
8.5.2
8.5.3
8.6
8.7
8.8
8.9
8.9.1
8.9.1.1
8.9.1.2
8.9.1.3
8.9.1.4
8.9.1.5
8.9.2
8.9.2.1
8.9.2.2
9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
10
11
12
13
14
15
15.1
16
17
18
18.1
19
19.1
19.2
19.3
Charge pump driving capability . . . . . . . . . . .
Charge pump frequency settings and power
efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature readout . . . . . . . . . . . . . . . . . . .
Temperature compensation of VLCD . . . . . . . .
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal oscillator . . . . . . . . . . . . . . . . . . . . . .
External clock. . . . . . . . . . . . . . . . . . . . . . . . .
Timing and frame frequency . . . . . . . . . . . . .
Backplane outputs . . . . . . . . . . . . . . . . . . . . .
Segment outputs . . . . . . . . . . . . . . . . . . . . . .
Display register . . . . . . . . . . . . . . . . . . . . . . .
Display RAM . . . . . . . . . . . . . . . . . . . . . . . . .
Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . .
RAM filling in static drive mode . . . . . . . . . . .
RAM filling in 1:2 multiplex drive mode . . . . .
RAM filling in 1:4 multiplex drive mode . . . . .
RAM filling in 1:6 multiplex drive mode . . . . .
RAM filling in 1:8 multiplex drive mode . . . . .
Bank selection . . . . . . . . . . . . . . . . . . . . . . . .
Input-bank-select . . . . . . . . . . . . . . . . . . . . . .
Output-bank-select. . . . . . . . . . . . . . . . . . . . .
I2C-bus interface characteristics . . . . . . . . . .
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . .
START and STOP conditions. . . . . . . . . . . . .
System configuration . . . . . . . . . . . . . . . . . . .
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . .
I2C-bus controller . . . . . . . . . . . . . . . . . . . . . .
Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C-bus slave address . . . . . . . . . . . . . . . . . .
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . .
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . .
Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics. . . . . . . . . . . . . . . . .
Test information . . . . . . . . . . . . . . . . . . . . . . .
Quality information . . . . . . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . .
Packing information . . . . . . . . . . . . . . . . . . . .
Wafer information. . . . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
35
36
38
39
41
41
41
42
42
43
43
43
44
45
46
46
47
48
49
50
51
52
52
52
52
53
54
54
54
54
56
56
57
58
62
63
63
64
65
69
69
71
71
71
71
continued >>
PCA9620
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
83 of 84
PCA9620
NXP Semiconductors
60 x 8 LCD high-drive segment driver for automotive and industrial
19.4
20
20.1
21
22
23
24
24.1
24.2
24.3
24.4
25
26
27
28
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . .
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LCD segment driver selection. . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . . .
Legal information. . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information. . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
74
74
76
77
78
79
79
79
79
80
80
81
82
83
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 8 April 2015
Document identifier: PCA9620