PCA8530
Automotive 102 x 4 Chip-On-Glass LCD segment driver
Rev. 2 — 25 September 2014
Product data sheet
1. General description
The PCA8530 is a fully featured Chip-On-Glass (COG)1 Liquid Crystal Display (LCD)
driver, designed for high-contrast Vertical Alignment (VA) LCD with multiplex rates up to
1:4. It generates the drive signals for a static or multiplexed LCD containing up to
4 backplane, 102 segment outputs, and up to 408 segments/elements. The PCA8530
features an internal charge pump with internal capacitors for on-chip generation of the
LCD driving voltage. To ensure an optimal and stable contrast over the full temperature
range, the PCA8530 offers a programmable temperature compensation of the LCD supply
voltage. The PCA8530 can be easily controlled by a microcontroller through either the
two-line I2C-bus or a four-line bidirectional SPI-bus.
For a selection of NXP LCD segment drivers, see Table 58 on page 93.
2. Features and benefits
1.
AEC Q100 grade 2 compliant for automotive applications
Low power consumption
Extended operating temperature range from 40 C to +105 C
102 segments and 4 backplanes allowing to drive:
up to 51 7-segment numeric characters
up to 25 14-segment alphanumeric characters
any graphics of up to 408 segments/elements
408-bit RAM for display data storage
Two sets of backplane outputs providing higher flexibility for optimal COG layout
configurations
Up to 4 chips can be cascaded to drive larger displays with an internally generated or
externally supplied VLCD
Selectable backplane drive configuration: static, 2, or 4 backplane multiplexing
LCD supply voltage
Programmable internal charge pump for on-chip LCD voltage generation up to
5 VDD2
External LCD voltage supply possible as well
Selectable 400 kHz I2C-bus or 3 MHz SPI-bus interface
Selectable linear temperature compensation of VLCD
Selectable display bias configuration
Wide range for digital and analog power supply: from 2.5 V to 5.5 V
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21 on page 95.
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
Wide LCD voltage range from 4.0 V for low threshold LCDs up to 12.0 V for high
threshold twisted nematic and Vertical Alignment (VA) displays
Display memory bank switching in static and 1:2 multiplex drive modes
Programmable frame frequency in the range of 45 Hz to 300 Hz; factory calibrated
with a tolerance of 3 Hz (at 80 Hz)
Selectable inversion scheme for LCD driving waveforms: frame or n-line inversion
Diagnostic features for status monitoring
Integrated temperature sensor with temperature readout
On chip calibration of internal oscillator frequency and VLCD
Laser marking at the back-side of the die for traceability of the lot number, wafer
number, and die position on the wafer
3. Applications
Automotive
Instrument clusters
Climate control
Car entertainment
Car radio
Industrial
Consumer
Medical and health care
Measuring equipment
Machine control systems
Information boards
White goods
General-purpose display modules
PCA8530
Product data sheet
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PCA8530
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
4. Ordering information
Table 1.
Ordering information
Type number
Package
PCA8530DUG
Name
Description
Version
bare die
247 bumps
PCA8530DUG
4.1 Ordering options
Table 2.
Ordering options
Product type number
Orderable part number Sales item
(12NC)
Delivery form
IC
revision
PCA8530DUG/DA
PCA8530DUG/DAZ
chips with bumps[1] in tray
1
[1]
935304675033
Bump hardness, see Table 56 on page 90.
5. Marking
Table 3.
Marking codes
Product type number
Marking code
PCA8530DUG/DA
on the active side of the die
PC8530-1
on the rear side of the die[1]
LLLLLLL WW XXXXXX
[1]
The rear side marking has the following meaning:
LLLLLLL — wafer lot number
WW — wafer number
XXXXXX — die identification number
PCA8530
Product data sheet
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
6. Block diagram
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Block diagram of PCA8530
PCA8530
Product data sheet
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NXP Semiconductors
PCA8530
6
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Viewed from active side. For mechanical details, see Figure 59 on page 85.
Fig 2.
Pinning diagram of PCA8530DUG
PCA8530
5 of 103
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DDD
Automotive 102 x 4 Chip-On-Glass LCD segment driver
Rev. 2 — 25 September 2014
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3&$'8*
&20
7.1 Pinning
&20
Product data sheet
7. Pinning information
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
7.2 Pin description
Table 4.
Pin description
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.
Symbol
Pin
Type
Description
output
LCD backplane
output
LCD segment
Backplane output pins
COM3
1 to 7, 190 to 195
COM2
8 to 11, 186 to 189
COM1
117 to 120, 182 to 185
COM0
121 to 125, 178 to 181
Segment output pins
S101
126, 127
S100 to S51
128 to 177
S50 to S1
196 to 245
S0
246, 247
VLCD pins
supply
VLCD input
VLCDSENSE 16 to 18
input
VLCD regulation input
VLCDOUT
19 to 22
output
VLCD output
T4
23 to 25
output
not accessible; must be left open
T3
26 to 30
input
not accessible; must be connected to T5
T5
31, 32
output
not accessible; must be connected to T3
T6
33, 34
output
not accessible; must be left open
T1
58, 59
input
not accessible; must be connected to VSS1
T2
60, 61
supply
ground supply
VLCDIN
12 to 15
Test pins
Supply pins
VSS2[1]
35 to 44
VSS3[1]
45 to 48
VSS1[1]
49 to 57
VDD1
74 to 78
supply
supply voltage 1 (analog and digital)
VDD3
79 to 82
supply
supply voltage 3 (analog)
VDD2
83 to 90
supply
supply voltage 2 (charge pump)
Oscillator, synchronization, addressing, and reset pins
CLK[2]
93 to 95
input/output
internal oscillator output, external oscillator input
OSC[2]
68, 69
input
clock (internal/external) selector
SYNC1[3]
96 to 98
input/output
charge pump synchronization for cascaded devices; must not be
connected if VLCD is externally supplied
SYNC0[3]
99 to 101
input/output
display synchronization for cascaded devices
RST
102, 103
input
active LOW reset input
A0
62, 63
input
hardware device address selection for cascading;
A1
64, 65
input
PCA8530
Product data sheet
•
•
connect to VSS1 for logic 0
connect to VDD1 for logic 1
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
Table 4.
Pin description …continued
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.
Symbol
Pin
Type
Description
Bus-related pins
SPI-bus
IFS
66, 67
input
interface selector input
•
SA0
70, 71
input
SA1
72, 73
input
91, 92
CE
input
I2C-bus
connect to VSS1
unused;
•
connect to VSS1
•
connect to VDD1
slave address selector;
•
•
connect to VSS1 for logic 0
connect to VDD1 for logic 1
chip enable input (active LOW)
unused;
•
connect to VDD1
SDI/SDAIN
104 to 106
input
SPI-bus data input
I2C-bus
SDAOUT
107 to 111
output
unused;
serial data output
•
serial data input
must be connected to VSS1
SDO
112, 113
output
SPI serial data output
unused;
SCL
114 to 116
input
serial clock input
serial clock input
•
must be left open
[1]
The substrate (rear side of the die) is connected to VSS1 and should be electrically isolated.
[2]
If pin OSC is tied to VSS1, CLK is the output pin of the internal oscillator. If pin OSC is tied to VDD1, CLK is the input pin for the external
oscillator.
[3]
If cascading is not used, pin must be left floating; for cascading see Section 15.2 on page 80.
PCA8530
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PCA8530
Product data sheet
8. Functional description
8.1 Commands of PCA8530
The PCA8530 is controlled by the commands defined in Table 5.
Remark: Any other combinations of operation code bits that are not mentioned in this document may lead to undesired
operation modes of PCA8530.
Table 5.
Commands of PCA8530
Command name
R/W[1]
Register
selection
RS[1:0][2]
Command bits
Reference
7
6
5
4
3
2
1
0
Initialize
0
0
0
0
0
1
1
1
0
1
0
Section 8.2.1
OTP-refresh
0
0
0
1
1
0
1
1
0
0
0
Section 8.2.2
Device-address
0
0
0
0
0
0
1
1
0
A[1:0]
SYNC1_pin
0
0
0
1
0
1
1
1
0
0
OE
Section 8.2.4
Clock-out-ctrl
0
0
0
1
1
0
1
0
1
0
COE
Section 8.2.5
Read-select
0
0
0
0
0
0
1
1
1
0
SO
Section 8.2.6
Status-readout temperature
1
0
0
TD[7:0]
device status
Clear-reset-flag
0
0
Section 8.2.3
Section 8.2.7
SR7
SR6
SR5
SR4
SR[3:0]
0
0
0
0
1
1
1
CPE
CPC[2:0]
1
1
Section 8.2.8
Charge pump and LCD bias control commands
0
0
0
1
1
0
0
Set-VLCD
MSB
0
0
0
0
1
0
V[8:4]
LSB
0
0
0
0
1
1
0
V[3:0]
0
0
0
1
1
0
1
0
Set-bias-mode
Section 8.3.1
Section 8.3.2
0
B[1:0]
Section 8.3.3
PCA8530
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Charge-pump-ctrl
Automotive 102 x 4 Chip-On-Glass LCD segment driver
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General control commands
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Commands of PCA8530 …continued
Command name
R/W[1]
Register
selection
RS[1:0][2]
Command bits
NXP Semiconductors
PCA8530
Product data sheet
Table 5.
Reference
7
6
5
4
3
2
1
0
TMF
TME
Temperature compensation control commands
1
0
0
0
0
0
0
TCE
TC-slope
A
0
1
0
0
0
0
0
1
TSA[2:0]
B
0
1
0
0
0
0
1
0
TSB[2:0]
C
0
1
0
0
0
0
1
1
TSC[2:0]
D
0
1
0
0
0
1
0
0
TSD[2:0]
E
0
1
0
0
0
1
0
1
TSE[2:0]
F
0
1
0
0
0
1
1
0
TSF[2:0]
1
0
1
0
0
0
1
1
1
T1T[2:0]
2
0
1
0
0
1
0
0
0
T2T[2:0]
3
0
1
0
0
1
0
0
1
T3T[2:0]
4
0
1
0
0
1
0
1
0
T4T[2:0]
Set-MUX-mode
0
0
0
0
0
0
0
0
M[2:0]
Section 8.5.1
Inversion-mode
0
0
0
1
0
1
1
0
INV[2:0]
Section 8.5.2
Display-ctrl
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
FF[4:0]
Write-display-data
0
0
1
DB[7:0]
Input-bank-select
0
0
0
0
0
0
0
1
0
IB[1:0]
Output-bank-select
0
0
0
0
0
0
1
0
0
OB[1:0]
Data-pointer-init
0
0
0
1
0
1
0
0
0
0
MSB
0
0
0
1
0
0
0
0
PX[6:4]
LSB
0
0
0
1
0
0
1
PX[3:0]
TC-set
Section 8.4.1
Section 8.4.3
Section 8.4.2
Display control commands
0
DE
Section 8.5.3
Clock and frame frequency command
Frame-frequency
Section 8.6.4
Display RAM commands
Data-pointer
Section 8.7.1
[1]
For further information about the R/W-bit, see Table 42 on page 56.
[2]
For further information about the register selection bits, see Table 42 on page 56.
Section 8.7.2
0
Section 8.7.3
PCA8530
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
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Temperature-ctrl
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
8.2 General control commands
8.2.1 Initialization
8.2.1.1
Command: Initialize
This command generates a chip-wide reset of the device without changing the content of
the display RAM. For further information about start-up and shut-down, see Section 8.8 on
page 26.
Table 6.
8.2.1.2
Initialize command bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 0
-
00111010
fixed value
RST pin
The RST pin generates a chip-wide reset of the device without changing the content of the
display RAM. For further information about start-up and shut-down, see Section 8.8 on
page 26.
8.2.2 Command: OTP-refresh
Each IC is calibrated during production and testing of the device in order to achieve the
specified accuracy of the VLCD, the frame frequency, and the temperature measurement.
This calibration is performed on EPROM cells called One Time Programmable (OTP)
cells. These cells are read by the device after a reset and every time when the Initialize
command or the OTP-refresh command is sent. The OTP-refresh command takes
approximately 10 ms to finish.
Table 7.
PCA8530
Product data sheet
OTP-refresh - OTP-refresh command bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 0
-
11011000
fixed value
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8.2.3 Command: Device-address
The Device-address command allows setting the address of the device in a cascaded
configuration and corresponds with pins A0 and A1 (see Section 15.2 on page 80).
Table 8.
Device-address - device address command bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 2
-
000110
fixed value
1 to 0
A[1:0]
set address
00
master
01
slave 1
10
slave 2
11
slave 3
8.2.4 Command: SYNC1_pin
With the SYNC1_pin command, the SYNC1 pin can be configured for using the PCA8530
as a single chip or a master in a cascade. If the PCA8530 is a slave in a cascade, the
command has no effect.
Table 9.
SYNC1_pin - SYNC1 pin configuration command bit description
This command has no effect if the PCA8530 is a slave in a cascade.
PCA8530
Product data sheet
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 1
-
1011100
fixed value
0
OE
SYNC1 pin configuration
0
pin SYNC1 is an output;
gated to 0 V;
to be used when PCA8530 is a single chip
1
pin SYNC1 is an output;
providing the synchronization signal;
to be used when PCA8530 is a master in a
cascade
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8.2.5 Command: Clock-out-ctrl
When pin CLK is configured as an output pin, the Clock-out-ctrl command enables or
disables the clock output on pin CLK (Section 8.6.1 on page 22).
Table 10.
Clock-out-ctrl - CLK pin input/output switch command bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 1
-
1101010
fixed value
0
COE
control pin CLK
0
clock signal not available on pin CLK;
pin CLK is in 3-state
1
clock signal available on pin CLK
8.2.6 Command: Read-select
The Read-select command allows choosing to readout the temperature or the device
status.
Table 11.
PCA8530
Product data sheet
Read-select - status read select command bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 1
-
0001110
fixed value
0
SO
readout
0
temperature;
the Status-readout command allows to
readout the temperature TD[7:0], see
Table 12
1
device status:
the Status-readout command allows to
readout some information about the status of
the device, see Table 12
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8.2.7 Command: Status-readout
The Status-readout command offers to readout some status bits of the PCA8530. These
bits indicate the status of the device at the moment of reading.
Table 12. Status-readout - status and temperature read command bit description
For this command, bit R/W has to be set logic 1.
Bit
Symbol
Value
Description
-
R/W
1
fixed value
-
RS[1:0]
00
fixed value
Temperature readout if SO = 0 (see Table 11)
7 to 0
TD[7:0]
00000000 to
11111111
temperature readout (see Section 8.10.4.1 on
page 40)
Device status readout if SO = 1 (see Table 11)
7
SR7
6
display is disabled
1
display is enabled
SR6
5
charge pump switching status
(status of bit CPE, see Table 14 on page 15)
0
charge pump disabled
1
charge pump enabled
SR5
4
charge pump charge status
0
charge pump has not reached programmed
value
1
charge pump has reached programmed value
SR4
3 to 0
[1]
display status (see Table 22 on page 21)
0
reset status flag
0
no reset has occurred since the reset status
flag was cleared last time
1
reset has occurred since the reset status flag
was cleared last time[1]
SR[3:0]
EMC detection
01SA1SA0
pre-defined code for EMC detection when I2C
interface is used
0101
pre-defined code for EMC detection when SPI
interface is used
The flag is set whenever a reset occurs, induced by RST pin, Power-On Reset (POR), or Initialize
command. After power-on, the flag is set and should be cleared for reset monitoring.
Some bits of the Status-readout command have a certain probability of being changed by
an EMC/ESD event. For example, an EMC/ESD event can cause a change of the
hard-wired settings of SA1 or SA0. Therefore SR[3:0] can help to detect if an EMC/ESD
event has occurred which has caused the change of a bit. In environments where
EMC/ESD events may occur, it could be helpful to compare the result of the
Status-readout command with the initial bit settings periodically.
PCA8530
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8.2.8 Command: Clear-reset-flag
The Clear-reset-flag command clears the reset flag SR4, see Table 12.
Table 13.
PCA8530
Product data sheet
Clear-reset-flag - Clear-reset-flag command bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 0
-
00011111
fixed value
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8.3 Charge pump and LCD bias control commands
8.3.1 Command: Charge-pump-ctrl
The Charge-pump-ctrl command enables or disables the internal VLCD generation and
controls the charge pump voltage multiplier settings.
Table 14.
Bit
Charge-pump-ctrl - charge pump control command bit description
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 4
-
1100
fixed value
3
CPE
2 to 0
charge pump status
0
charge pump disabled;
no internal VLCD generation;
external supply of VLCD
1
charge pump enabled;
internal VLCD generation;
no external supply of VLCD
CPC[2:0]
charge pump voltage multiplier setting
000
VLCD = 2 VDD2
001
VLCD = 3 VDD2
010
VLCD = 4 VDD2
011
VLCD = 5 VDD2
100 to 111
VLCD = VDD2 (direct mode)
8.3.2 Command: Set-VLCD
The Set-VLCD command allows setting the LCD voltage.
Table 15.
Bit
Set-VLCD - Set-VLCD command bit description
Symbol
Value
Description
Set-VLCD-MSB
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 5
-
010
fixed value
4 to 0
V[8:4]
set VLCD MSB
00000 to
11111
the 5 most significant bits of V[8:0]
Set-VLCD-LSB
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 4
-
0110
fixed value
3 to 0
V[3:0]
set VLCD LSB
0000 to 1111
the 4 least significant bits of V[8:0]
A value of 0h corresponds to VLCD = 4 V and values equal or higher than 10Ch
correspond to VLCD = 12 V without temperature compensation. Every LSB change
corresponds to a VLCD programming step of 0.03 V. For further information, see
PCA8530
Product data sheet
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Section 8.10.3 on page 34 and Equation 2 on page 35.
8.3.3 Command: Set-bias-mode
Table 16. Set-bias-mode - set bias mode command bit description
This command is not applicable for the static drive mode.
PCA8530
Product data sheet
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 2
-
110100
fixed value
1 to 0
B[1:0]
set bias mode
00, 01
unused
11
1⁄
3
bias
10
1⁄
2
bias
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8.4 Temperature compensation control commands
8.4.1 Command: Temperature-ctrl
The Temperature-ctrl command enables or disables the temperature measurement block
and the temperature compensation of VLCD (see Section 8.10.4 on page 40).
Table 17. Temperature-ctrl - temperature measurement control command bit description
For this command, the register selection bits have to be set RS[1:0] = 10.
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
10
fixed value
7 to 3
-
00000
fixed value
2
TCE
1
0
temperature compensation control
0
temperature compensation of VLCD disabled
1
temperature compensation of VLCD enabled
TMF
temperature measurement filter
0
digital temperature filter disabled[1]
1
digital temperature filter enabled
TME
temperature measurement control
0
temperature measurement disabled;
no temperature readout possible
1
temperature measurement enabled;
temperature readout possible
[1]
PCA8530
Product data sheet
The unfiltered digital value of TD[7:0] is immediately available for the readout and VLCD compensation.
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8.4.2 Command: TC-set
The TC-set command allows defining six temperature intervals in the operating
temperature range from 40 C to +105 C. For each of the temperature intervals, the
TC-slope command (see Section 8.4.3) allows setting the temperature coefficient of VLCD.
Table 18. TC-set - VLCD temperature compensation set command bit description
For this command, the register selection bits have to be set RS[1:0] = 10.
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
10
fixed value
7 to 3
-
00111
fixed value
2 to 0
T1T[2:0]
000 to 111
see Table 32 on page 42
R/W
0
fixed value
TC-set-1
TC-set-2
-
RS[1:0]
10
fixed value
7 to 3
-
01000
fixed value
2 to 0
T2T[2:0]
000 to 111
see Table 32 on page 42
-
R/W
0
fixed value
-
RS[1:0]
10
fixed value
7 to 3
-
01001
fixed value
2 to 0
T3T[2:0]
000 to 111
see Table 32 on page 42
-
R/W
0
fixed value
-
RS[1:0]
10
fixed value
7 to 3
-
01010
fixed value
2 to 0
T4T[2:0]
000 to 111
see Table 32 on page 42
TC-set-3
TC-set-4
PCA8530
Product data sheet
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8.4.3 Command: TC-slope
The TC-slope command allows setting the temperature coefficients of VLCD corresponding
to six temperature intervals defined by the TC-set command.
Table 19. TC-slope - VLCD temperature compensation slope command bit description
For this command, the register selection bits have to be set RS[1:0] = 10.
Bit
Symbol
Value
Description
R/W
0
fixed value
TC-slope-A
-
RS[1:0]
10
fixed value
7 to 3
-
00001
fixed value
2 to 0
TSA[2:0]
000 to 111
see Table 33 on page 43
TC-slope-B
-
R/W
0
fixed value
-
RS[1:0]
10
fixed value
7 to 3
-
00010
fixed value
2 to 0
TSB[2:0]
000 to 111
see Table 33 on page 43
TC-slope-C
-
R/W
0
fixed value
-
RS[1:0]
10
fixed value
7 to 3
-
00011
fixed value
2 to 0
TSC[2:0]
000 to 111
see Table 33 on page 43
TC-slope-D
-
R/W
0
fixed value
-
RS[1:0]
10
fixed value
7 to 3
-
00100
fixed value
2 to 0
TSD[2:0]
000 to 111
see Table 33 on page 43
R/W
0
fixed value
TC-slope-E
-
RS[1:0]
10
fixed value
7 to 3
-
00101
fixed value
2 to 0
TSE[2:0]
000 to 111
see Table 33 on page 43
TC-slope-F
PCA8530
Product data sheet
-
R/W
0
fixed value
-
RS[1:0]
10
fixed value
7 to 3
-
00110
fixed value
2 to 0
TSF[2:0]
000 to 111
see Table 33 on page 43
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8.5 Display control commands
8.5.1 Command: Set-MUX-mode
The Set-MUX-mode command allows setting the multiplex drive mode.
Table 20.
Set-MUX-mode - set multiplex drive mode command bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 3
-
00000
fixed value
2 to 0
M[2:0]
set multiplex drive mode
000 to 100
unused
101
1:4 multiplex drive mode
110
1:2 multiplex drive mode
111
static
8.5.2 Command: Inversion-mode
The Inversion-mode command allows changing the drive scheme inversion mode.
The waveforms used to drive LCD displays (see Figure 25 on page 46 to Figure 28 on
page 49) inherently produce a DC voltage across the display cell. The PCA8530
compensates for the DC voltage by inverting the waveforms on alternate frames or
alternate lines. The choice of the compensation method is determined with INV[2:0] in
Table 21.
Table 21.
8.5.2.1
Inversion-mode - inversion mode command bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 3
-
10110
fixed value
2 to 0
INV[2:0]
set inversion mode
000
frame inversion mode
001
1-line inversion mode
010
2-line inversion mode
011
3-line inversion mode
100 to 111
unused
Line inversion mode (driving scheme A)
In line inversion mode, the DC value is compensated every nth line. Changing the
inversion mode to line inversion mode reduces the possibility for flickering but increases
the power consumption (see example waveforms in Figure 25 on page 46 to Figure 28 on
page 49)
PCA8530
Product data sheet
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8.5.2.2
Frame inversion mode (driving scheme B)
In frame inversion mode, the DC value is compensated across two frames and not within
one frame. Changing the inversion mode to frame inversion reduces the power
consumption, therefore it is useful when power consumption is a key point in the
application.
Frame inversion may not be suitable for all applications. The RMS voltage across a
segment is better defined, however since the switching frequency is reduced there is
possibility for flicker to occur.
8.5.3 Command: Display-ctrl
The Display-ctrl command enables or disables the display.
Table 22.
PCA8530
Product data sheet
Display-ctrl - display on and off switch command bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 1
-
0011100
fixed value
0
DE
display control
0
display disabled
1
display enabled
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8.6 Clock and frame frequency command
8.6.1 Oscillator
The internal logic and LCD drive signals of the PCA8530 are timed by the clock frequency
fclk, which is either internally generated by an on-chip oscillator circuit or externally
supplied.
The clock frequency fclk determines the internal data flow of the device that includes the
transfer of display data from the display RAM to the display segment outputs and the
generation of the LCD frame frequency.
8.6.2 External clock
When an external clock is used, the input pin OSC must be connected to VDD1. The clock
must be supplied to the CLK pin and must have an amplitude equal to the VDD1 voltage
supplied to the chip and be referenced to VSS1.
Remark: If an external clock is used, then this clock signal must always be supplied to the
device. Removing the clock may freeze the LCD in a DC state, which is not suitable for the
liquid crystal. Removal of the clock is possible when following the correct procedures as
described in Section 8.8.3 on page 29.
8.6.3 Internal clock
In applications where the internal clock is used, the input pin OSC must be connected to
VSS1. It is possible to make the clock frequency available on pin CLK by setting bit COE
logic 1 (see Table 10 on page 12). If pin CLK is not used, it should be left open. At
power-on the signal at pin CLK is disabled and pin CLK is in 3-state.
8.6.4 Command: Frame-frequency
With this command, the clock and frame frequency can be programmed when using the
internal clock.
Table 23.
Frame-frequency - frame frequency select command bit description
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 5
-
111
fixed value
4 to 0
FF[4:0]
see Table 24
clock and frame frequency (Hz)
The duty ratio of the clock output may change when choosing different values for the
frame frequency (see Table 24).
The LCD frame frequency is derived from the clock frequency by a fixed division (see
Equation 1).
f clk
f fr = -------144
PCA8530
Product data sheet
(1)
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The Frame-frequency command allows configuring the frame frequency in the range of
45 Hz to 300 Hz with steps of
• 5 Hz from 45 Hz to 100 Hz
• 10 Hz from 100 Hz to 300 Hz
The frame frequency of 80 Hz is factory calibrated with a tolerance of 3 Hz at 25 C.
Table 24. Clock and frame frequency values
Duty cycle definition: % HIGH-level time : % LOW-level time.
PCA8530
Product data sheet
FF[4:0]
Frame frequency (Hz)
Clock frequency (Hz)
Typical duty cycle (%)
00000
45
6472
29 : 71
00001
50
7200
20 : 80
00010
55
7945
12 : 88
00011
60
8662
4 : 96
00100
65
9366
48 : 52
00101
70
10105
44 : 56
00110
75
10766
41 : 59
00111
80
11520
36 : 64
01000
85
12255
32 : 68
01001
90
12944
29 : 71
01010
95
13714
24 : 76
01011
100
14400
20 : 80
01100
110
15781
13 : 87
01101
120
17194
5 : 95
01110
130
18581
49 : 51
01111
140
20211
44 : 56
10000
150
21736
40 : 60
10001
160
23040
36 : 64
10010
170
24511
32 : 68
10011
180
26182
28 : 72
10100
190
27429
24 : 76
10101
200
28800
20 : 80
10110
210
30316
16 : 84
10111
220
32000
12 : 88
11000
230
32914
9 : 91
11001
240
34909
4 : 96
11010
250
36000
50 : 50
11011
260
37161
49 : 51
11100
270
38400
47 : 53
11101
280
39724
45 : 55
11110
290
41143
43 : 57
11111
300
42667
41 : 59
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8.7 Display RAM commands
8.7.1 Command: Write-display-data
The Write-display-data command writes data byte-wise to the RAM. After Power-On
Reset (POR), the RAM content is random and should be brought to a defined status by
clearing it (setting it logic 0).
Table 25. Write-display-data - write display data command bit description
For this command, the register selection bits have to be set RS[1:0] = 01.
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
01
fixed value
7 to 0
DB[7:0]
00000000 to
11111111
writing data byte-wise to RAM
More information about the display RAM can be found in Section 8.14 on page 51.
8.7.2 Bank select commands
For multiplex drive modes 1:2, and static drive mode, it is possible to write data to one
area of the RAM while displaying from another. These areas are named as RAM banks.
Input and output banks can be set independently from one another with the
Input-bank-select and the Output-bank-select command. More information about RAM
bank switching can be found in Section 8.14.3 on page 53.
8.7.2.1
Command: Input-bank-select
Table 26. Input-bank-select - input bank select command bit description
This command is not applicable for multiplex drive mode 1:4.
Bit
PCA8530
Product data sheet
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 2
-
000010
fixed value
1 to 0
IB[1:0]
selects RAM bank to write to
static drive mode
1:2 drive mode
00
bank 0: RAM-row 0
01
bank 1: RAM-row 1
bank 0: RAM-rows 0
and 1
10
bank 2: RAM-row 2
11
bank 3: RAM-row 3
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bank 2: RAM-rows 2
and 3
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8.7.2.2
Command: Output-bank-select
Table 27. Output-bank-select - output bank select command bit description
This command is not applicable for multiplex drive mode 1:4.
Bit
Symbol
Value
Description
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 2
-
000100
fixed value
1 to 0
OB[1:0]
selects RAM bank to read from to the LCD
static drive mode
1:2 drive mode
00
bank 0: RAM-row 0
01
bank 1: RAM-row 1
bank 0: RAM-rows 0
and 1
10
bank 2: RAM-row 2
11
bank 3: RAM-row 3
bank 2: RAM-rows 2
and 3
8.7.3 Command: Data-pointer
The Data-pointer command defines the display RAM address where the following display
data are sent to. For setting the data pointer always the three commands Data-pointer-init,
Data-pointer-MSB and Data-pointer-LSB have to be sent.
Table 28. Data-pointer - set data pointer command bit description
For further information about the RAM, see Section 8.14 on page 51.
Bit
Symbol
Value
Description
Data-pointer-init
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 0
-
10100000
fixed value
Data-pointer-MSB: PX[6:4]
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 3
-
10000
fixed value
2 to 0
PX[6:4]
000 to 111
3-bit binary value
Data-pointer-LSB: PX[3:0]
PCA8530
Product data sheet
-
R/W
0
fixed value
-
RS[1:0]
00
fixed value
7 to 4
-
1001
fixed value
3 to 0
PX[3:0]
0000 to 1111
4-bit binary value
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8.8 Start-up and shut-down
8.8.1 Power-On
At power-on, the PCA8530 resets to the following starting conditions:
1. All backplane and segment outputs are set to VSS1.
2. Input and output bank selectors are reset.
3. The interface is initialized.
4. The data pointer is cleared (set logic 0).
5. The internal oscillator is disabled.
6. Temperature measurement is disabled.
7. Temperature filter is disabled.
8. The internal VLCD voltage generation is disabled. The charge pump is switched off.
9. The VLCD temperature compensation is disabled.
10. The display is disabled.
8.8.2 Recommended start-up sequences
General remarks:
1. Do not transfer data for at least 1 ms after a power-on to allow the reset action to
complete.
2. The first command sent to the device after the power-on event must be the Initialize
command (see Section 8.2.1.1 on page 10).
3. After the initialization, the desired values have to be set by the commands listed in
Table 5 on page 8.
4. Before enabling the display, the RAM content should be brought to a defined status
– by clearing it (setting it all logic 0) or
– by writing meaningful content (for example, a graphic)
otherwise unwanted display artifacts may appear on the display.
The following sequences describe how to proceed with the initialization of the chip in
different application modes.
PCA8530
Product data sheet
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(1) This time depends on the external capacitor on the VLCD pins. For a capacitor of 100 nF a delay
of about 55 ms to 65 ms is expected.
Fig 3.
Recommended start-up sequence when using the internal charge pump and the
internal clock signal
When using the internal VLCD generation, the display must not be enabled before the
generation of VLCD with the internal charge pump is completed. Otherwise unwanted
display artifacts may appear on the display.
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Fig 4.
PCA8530
Product data sheet
Recommended start-up sequence when using an external supplied VLCD and the
internal clock signal
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(1) Alternatively, the external clock signal can be applied after the generation of the VLCD voltage.
(2) This time depends on the external capacitor on the VLCD pins. For a capacitor of 100 nF a delay
of about 55 ms to 65 ms is expected.
Fig 5.
Recommended start-up sequence when using the internal charge pump and an
external clock signal
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Fig 6.
PCA8530
Product data sheet
Recommended start-up sequence when using an external supplied VLCD and an
external clock signal
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8.8.3 Recommended power-down sequences
General remarks:
1. It is necessary to run the power-down sequence before removing the supplies.
Depending on the application, care must be taken that no other signals are present at
the chip input or output pins when removing the supplies (refer to Section 10 on
page 63). Otherwise this may cause unwanted display artifacts. Uncontrolled removal
of supply voltages does not damage the PCA8530.
2. Static voltages across the liquid crystal display can build up when the external LCD
supply voltage (VLCD) is on while the IC supply voltage (VDD1 to VDD3) is off, or the
other way round. This may cause unwanted display artifacts. To avoid such artifacts,
external VLCD, VDD1 to VDD3 must be applied or removed together.
3. A clock signal must always be supplied to the device when the device is active.
Removing the clock may freeze the LCD in a DC state, which is not suitable for the
liquid crystal. It is recommended to disable the display first and to remove the clock
signal afterwards.
With the following sequences, the PCA8530 can be set to a state of minimum power
consumption, called power-down mode.
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(1) If previously enabled.
Remark: When bits DE (Table 22 on page 21), CPE (Table 14 on page 15) and TME (Table 17 on
page 17) are logic 0, the internal clock signal is switched off.
Fig 7.
PCA8530
Product data sheet
Recommended power-down sequence for minimum power-down current when
using the internal charge pump and the internal clock signal
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Remark: When bits DE (Table 22 on page 21), CPE (Table 14 on page 15) and TME (Table 17 on
page 17) are logic 0, the internal clock signal is switched off.
Fig 8.
Recommended power-down sequence when using an external supplied VLCD and
the internal clock signal
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Fig 9.
PCA8530
Product data sheet
Recommended power-down sequence when using the internal charge pump and
an external clock signal
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PCA8530
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
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Fig 10. Recommended power-down sequence when using an external supplied VLCD and
an external clock signal
PCA8530
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8.9 Possible display configurations
The display configurations possible with the PCA8530 depend on the number of active
backplanes outputs required. A selection of possible display configurations is given in
Table 29.
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Fig 11. Example of display types suitable for PCA8530
Table 29.
Selection of possible display configurations
Number of
Backplanes
Icons
Digits/Characters
7-segment[1]
14-segment[2]
Dot matrix:
Segments/
Elements
4
408
51
25
408 dots (4 102)
2
204
25
12
204 dots (2 102)
1
102
12
6
102 dots (1 102)
[1]
7 segment display has 8 segments/elements including the decimal point.
[2]
14 segment display has 16 segments/elements including decimal point and accent dot.
All the display configurations in Table 29 can be implemented in the typical systems
shown in Figure 12 and Figure 13.
PCA8530
Product data sheet
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PCA8530
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
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VDD1 to VDD3 from 2.5 V to 5.5 V.
VDD1 to VDD3 can be connected to the same power supply.
VSS1 to VSS3 can be connected to the same ground supply.
Fig 12. Typical system configuration if using the internal VLCD generation and I2C-bus
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VDD1 to VDD3 from 2.5 V to 5.5 V.
VDD1 to VDD3 can be connected to the same power supply.
VSS1 to VSS3 can be connected to the same ground supply.
Fig 13. Typical system configuration if using the external VLCD and SPI-bus
The host microcontroller maintains the communication channel with the PCA8530. The
only other connections required to complete the system are the power supplies, the VLCD
pins, the external capacitors, and the LCD panel selected for the application. The
appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.
PCA8530
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External capacitors of 100 nF minimum are required on each of the pins VDD1 to VDD3.
VDD1 to VDD3 can be connected to the same power supply. In this case, a capacitor of
300 nF minimum is required.
VSS1 to VSS3 can be connected to the same ground supply.
The VLCD pins (VLCDOUT, VLCDSENSE, VLCDIN) can be connected, whether VLCD is
generated internally or supplied from external. An external capacitor of 300 nF minimum is
recommended for VLCD. For high display loads, 1 F is suggested.
8.10 LCD voltage
8.10.1 VLCD pins
The PCA8530 has 3 VLCD pins:
VLCDIN — VLCD supply input
VLCDOUT — VLCD voltage output
VLCDSENSE — VLCD regulation circuitry input
The VLCD voltage can be generated on-chip or externally supplied.
8.10.2 External VLCD supply
When the external VLCD supply is selected (CPE = 0), the VLCD voltage must be supplied
to the pin VLCDIN. The pins VLCDOUT and VLCDSENSE can be left unconnected or
alternatively connected to VLCDIN.
The internal charge pump must not be enabled, otherwise an extra current may occur on
pin VDD2 and pin VLCD. When VLCD is supplied externally, no internal temperature
compensation occurs on this voltage even if bit TCE is set logic 1 (see Section 8.10.4).
The VLCD voltage which is supplied externally will be available at the segments and
backplanes of the device through the chosen bias system. Also programming the V[8:0]
bit field has no effect on the externally supplied VLCD.
8.10.3 Internal VLCD generation
When the internal VLCD generation is selected (CPE = 1), the VLCD voltage is available on
pin VLCDOUT. The pins VLCDIN and VLCDSENSE must be connected to the pin
VLCDOUT.
VLCD can be generated by an on-chip charge pump and controlled by command (Table 15
on page 15). The VLCD voltage is available on pin VLCDOUT.
The charge pump is controlled by the Charge-pump-ctrl command (see Table 14 on
page 15). It can be enabled with the CPE bit. The multiplier setting can be configured with
the CPC[2:0] bits. The charge pump can generate a VLCD up to 5 VDD2.
8.10.3.1
VLCD programming
VLCD can be programmed by using the V[8:0] (see Table 15 on page 15).
The final value of VLCD is a combination of the programmed V[8:0] value and the output of
the temperature compensation block, VT[8:0] (see Equation 2). The system is exemplified
in Figure 14.
PCA8530
Product data sheet
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PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
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Fig 14. VLCD generation including temperature compensation
In Equation 2 the main parameters are the programmed digital value term and the
compensated temperature term.
V LCD = V 8:0 + VT 8:0 n + m
(2)
1. V[8:0] is the binary value of the programmed voltage.
2. VT[8:0] is the binary value of the temperature compensated voltage. Its value comes
from the temperature compensation block and is a two’s complement which has the
value 0h at 20 C.
3. m and n are fixed values (see Table 30 and Figure 15).
Table 30.
Parameters of VLCD generation
Symbol
Value
Unit
m
3.99
V
n
0.03
V
Figure 15 shows how VLCD changes with the programmed value of V[8:0].
PCA8530
Product data sheet
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PCA8530
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
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(1) V[8:0] must be set so that VLCD > VDD2.
(2) Automatic limitation for VLCD > 12 V.
Fig 15. VLCD programming of PCA8530 (assuming VT[8:0] = 0h)
Remarks:
1. It is important that V[8:0] is set to such a value that the resultant VLCD, including the
temperature compensation VT[8:0], is higher than VDD2.
2. Programmable range of V[8:0] is from 0h to 1FFh. This would allow achieving a VLCD
above 12 V but 12 V is the built-in automatic limit.
8.10.3.2
VLCD driving capability
Figure 16 illustrates the main factor determining how much current the charge pump can
deliver.
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Fig 16. Charge pump model (used to characterize the driving strength)
The output resistance of the charge pump is specified in Table 31.
PCA8530
Product data sheet
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Table 31. Output resistance of the charge pump
RITO(VSS2), RITO(VDD2), RITO(VLCDOUT) = 50 .
Charge pump configuration
Ro(VLCDOUT) (typical)
Unit
VLCD = 2 VDD2
2.5
k
VLCD = 3 VDD2
6
k
VLCD = 4 VDD2
10.5
k
VLCD = 5 VDD2
18
k
Remark: The PCA8530 has a built-in automatic limitation of VLCD, set to 12 V. The
maximum VLCD that can be programmed is expressed by the following equation:
V LCD max = min 12 V, n V DD2 – R o VLCDOUT I load , where n is the multiplication factor of
the charge pump. Iload is the overall current sink by the segments and backplanes outputs
depending on the display, plus the on-chip VLCD current consumption.
With these values, it can be calculated how much current the charge pump can drive
under certain conditions, as shown in Figure 17 and Figure 18.
DDD
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Conditions: VDD2 = 3.0 V, RITO(VSS2), RITO(VDD2), RITO(VLCDOUT) = 50 , Tamb = 27 C.
Charge pump configuration:
(1) VLCD = 2 VDD2.
(2) VLCD = 3 VDD2.
(3) VLCD = 4 VDD2.
(4) VLCD = 5 VDD2.
Iload is the overall current sink by the segments and backplanes outputs depending on the display,
plus the on-chip VLCD current consumption.
Reading example: VLCD can be programmed to 10 V by using the charge pump configuration (3)
or (4). With configuration (3), VLCD can be programmed to 10 V for a current load up to about
120 A. With configuration (4), VLCD can be programmed to 10 V for a current load up to about
260 A.
Remark: Only the charge pump configuration (4) allows programming VLCD = 12 V when
VDD2 = 3.0 V.
Fig 17. Charge pump driving capability with VDD2 = 3.0 V
PCA8530
Product data sheet
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PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
DDD
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Conditions: VDD2 = 5.0 V, RITO(VSS2), RITO(VDD2), RITO(VLCDOUT) = 50 , Tamb = 27 C.
Charge pump configuration:
(1) VLCD = 2 VDD2.
(2) VLCD = 3 VDD2.
(3) VLCD = 4 VDD2.
(4) VLCD = 5 VDD2.
Iload is the overall current sink by the segment and backplane outputs depending on the display,
plus the on-chip VLCD current consumption.
Reading example: VLCD can be programmed to 10 V by using the charge pump configuration (2)
or (3). With configuration (2), VLCD can be programmed to 10 V for a current load up to about
780 A. With configuration (3), VLCD can be programmed to 10 V for a current load up to about
940 A.
Remark: The charge pump configuration (4) has no benefit compared to configuration (3) and is
therefore not recommended when VDD2 = 5.0 V.
Fig 18. Charge pump driving capability with VDD2 = 5.0 V
It has to be considered that the driving capability of the charge pump is depending on the
resistance of the Indium Tin Oxide (ITO) tracks, see Figure 20 and Figure 19.
PCA8530
Product data sheet
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PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
DDD
9/&'
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Conditions: VDD2 = 3 V; charge pump configuration: VLCD = 4 VDD2; VLCD = 8 V; Tamb = 27 C.
(1) RITO(VSS2), RITO(VDD2), RITO(VLCDOUT) = 50 .
(2) RITO(VSS2), RITO(VDD2), RITO(VLCDOUT) = 100 .
Iload is the overall current sink of the segment and backplane outputs depending on the display,
plus the on-chip VLCD current consumption.
Fig 19. VLCD with respect to Iload at VDD2 = 3 V
DDD
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9
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Conditions: VDD2 = 5 V; charge pump configuration: VLCD = 2 VDD2; VLCD = 8 V; Tamb = 27 C.
(1) RITO(VSS2), RITO(VDD2), RITO(VLCDOUT) = 50 .
(2) RITO(VSS2), RITO(VDD2), RITO(VLCDOUT) = 100 .
Iload is the overall current sink of the segment and backplane outputs depending on the display,
plus the on-chip VLCD current consumption.
Fig 20. VLCD with respect to Iload at VDD2 = 5 V
PCA8530
Product data sheet
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Rev. 2 — 25 September 2014
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PCA8530
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
8.10.4 Temperature measurement and temperature compensation of VLCD
8.10.4.1
Temperature readout
The PCA8530 has a built-in temperature sensor which provides an 8-bit digital value
(TD[7:0]) of the ambient temperature. This value can be read by command (see
Section 8.2.6 on page 12 and Section 8.2.7 on page 13). The actual temperature is
determined from TD[7:0] using Equation 3.
T C = 0.6275 TD 7:0 – 40
(3)
TD[7:0] = FFh means that no temperature readout is available or was performed. The
measurement needs about 8 ms to complete. It is repeated periodically every second as
long as bit TME is set logic 1 (see Table 17 on page 17).
Due to the nature of a temperature sensor, oscillations may occur. To avoid this, a filter
has been implemented in PCA8530. A control bit, TMF, is implemented to enable or
disable the digital temperature filter (see Table 17 on page 17). The system is exemplified
in Figure 21.
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Fig 21. Temperature measurement block with digital temperature filter
The digital temperature filter introduces a certain delay in the measurement of the
temperature. This behavior is illustrated in Figure 22.
PCA8530
Product data sheet
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PCA8530
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
DDD
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(1) Environment temperature, T1 (C).
(2) Measured temperature, T2 (C).
(3) Temperature deviation, T = T2 T1.
Fig 22. Temperature measurement delay
8.10.4.2
Temperature adjustment of the VLCD
Due to the temperature dependency of the liquid crystal viscosity, the LCD supply voltage
may have to be adjusted at different temperatures to maintain optimal contrast. The
temperature characteristics of the liquid is provided by the LCD manufacturer. The slope
has to be set to compensate for the liquid behavior. Internal temperature compensation
can be enabled via bit TCE (see Table 17 on page 17).
The ambient temperature range is split up to six programmable regions and to each a
different temperature coefficient can be applied (see Figure 23).
PCA8530
Product data sheet
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PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
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Fig 23. Example of segmented temperature coefficients
The temperature regions are determined by programming the temperature limits T1 to T4
via the TC-set-1 to TC-set-4 commands (see Section 8.4.2 on page 18). The temperature
coefficients can be selected from a choice of eight different slopes. Each one of theses
coefficients is independently selected via the TC-slope command (see Section 8.4.3 on
page 19).
Table 32.
Temperature regions
T1T[2:0] to
T4T[2:0]
Temperature region 1 and 2
Temperature region 3 and 4
T1, T2 (C)
Corresponding
TD value[1]
T3, T4 (C)
Corresponding
TD value[1]
000
34
10
+29
110
001
27
20
+38
124
010
21
30
+47
138
011
15
40
+55
152
100
9
50
+64
166
101
2
60
+73
180
110
+4
70
+82
194
111
+10
80
+91
208
[1]
The relation between the actual temperature and TD[7:0] is derived from Equation 3 on page 40.
Remark: The programming has to be made such that T1 < T2 and T3 < T4 otherwise the
VLCD temperature compensation will not be executed.
PCA8530
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Table 33.
Temperature coefficients
TSA[2:0] to TSF[2:0] value
Slope factor (mV/C)
Temperature coefficients
SA to SF[1]
000
0
0.000
001
6
0.125
010
12
0.250
011
24
0.500
100
60
1.250
101
+6
+0.125
110
+12
+0.250
111
+24
+0.500
[1]
The relationship between the temperature coefficients SA to SF and the slope factor is derived from the
0.6275 C
LSB of V[8:0] mV
following equation: Sn = ----------------------------------------------- slope factor (mV/C , where LSB of V[8:0] 30 mV.
The binary value of the temperature compensated voltage VT[8:0] is calculated according
to Table 34.
Table 34.
PCA8530
Product data sheet
Calculation of the temperature compensated value VT
Temperature
(C)
Digital temperature:
TD[7:0]
Binary value of the temperature compensated
voltage: VT[8:0]
T –40 C
TD 7:0 = 0
– 96 – T2 SC – T2 – T1 SB – T1 SA
– 40 C T T1
0 TD 7:0 T1
– 96 – T2 SC – T2 – T1 SB – T1 – TD 7:0 SA
T1 T T2
T1 TD 7:0 T2
– 96 – T2 SC – T2 – TD 7:0 SB
T2 T 20 C
T2 TD 7:0 96
– 96 – TD 7:0 SC
20 C T T3
96 TD 7:0 T3
TD 7:0 – 96 SD
T3 T T4
T3 TD 7:0 T4
T3 – 96 SD + TD 7:0 – T3 SE
T4 T 105 C
T4 TD 7:0 231
T3 – 96 SD + T4 – T3 SE + TD 7:0 – T4 SF
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8.10.5 LCD voltage selector
The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
Set-bias-mode command (see Table 16 on page 16) and the Set-MUX-mode command
(see Table 20 on page 20).
Table 35.
LCD drive modes: summary of characteristics
LCD bias
configuration
V off RMS
----------------------V LCD
V on RMS
---------------------V LCD
V on RMS [1] VLCD[2]
D = ---------------------V off RMS
2
static
0
1
Von(RMS)
3
1⁄
2
0.354
0.791
2.236
2.828 Voff(RMS)
4
1⁄
3
0.333
0.745
2.236
3.0 Voff(RMS)
4
3
1⁄
2
0.433
0.661
1.527
2.309 Voff(RMS)
4
4
1⁄
3
0.333
0.577
1.732
3.0 Voff(RMS)
LCD drive
mode
Number of:
static
1
1:2 multiplex
1:2 multiplex
1:4
multiplex[3]
1:4 multiplex
Backplanes Levels
2
2
[1]
Determined from Equation 6.
[2]
Determined from Equation 5.
[3]
In this example, the discrimination factor and hence the contrast ratio is smaller. The advantage of this LCD drive mode is a power
saving from a reduction of VLCD.
Intermediate LCD biasing voltages are obtained from an internal voltage divider. The
biasing configurations that apply to the preferred modes of operation, together with the
biasing characteristics as functions of VLCD and the resulting discrimination ratios (D), are
given in Table 35. Discrimination is a term which is defined as the ratio of the on and off
RMS voltage across a segment. It can be thought of as a measurement of contrast.
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode, a suitable choice is VLCD > 3Vth(off).
1
Bias is calculated by ------------- , where the values for a are
1+a
a = 1 for 1⁄2 bias
a = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 4:
V on RMS =
V LCD
a 2 + 2a + n
-----------------------------2
n 1 + a
(4)
where VLCD is the resultant voltage at the LCD segment and where the values for n are
n = 1 for static mode
n = 2 for 1:2 multiplex
n = 4 for 1:4 multiplex
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 5:
V off RMS =
PCA8530
Product data sheet
V LCD
a 2 – 2a + n
-----------------------------2
n 1 + a
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Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 6:
V on RMS
D = ---------------------- =
V off RMS
2
a + 2a + n
--------------------------2
a – 2a + n
(6)
VLCD is sometimes referred as the LCD operating voltage.
8.10.5.1
Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel is switched on or off, determine the transmissibility of the
pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 24.
For a good contrast performance, the following rules should be followed:
V on RMS V th on
(7)
V off RMS V th off
(8)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection
of a, n (see Equation 4 to Equation 6) and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer. Vth(off) is sometimes named Vth. Vth(on) is sometimes named saturation
voltage Vsat.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
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Fig 24. Electro-optical characteristic: relative transmission curve of the liquid
PCA8530
Product data sheet
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8.10.6 LCD drive mode waveforms
8.10.6.1
Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD.
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Vstate1(t) = VSn(t) VBP0(t).
Vstate2(t) = V(Sn + 1)(t) VBP0(t).
Von(RMS)(t) = VLCD.
Voff(RMS)(t) = 0 V.
Fig 25. Static drive mode waveforms, line inversion mode (n = 1)
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8.10.6.2
1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCA8530 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 26 and
Figure 27.
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Vstate1(t) = VSn(t) VBP0(t).
Vstate2(t) = VSn(t) VBP1(t).
Von(RMS)(t) = 0.791VLCD.
Voff(RMS)(t) = 0.354VLCD.
Fig 26. Waveforms for the 1:2 multiplex drive mode, 1⁄2 bias, line inversion mode (n = 1)
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PCA8530
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
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Vstate1(t) = VSn(t) VBP0(t).
Vstate2(t) = VSn(t) VBP1(t).
Von(RMS)(t) = 0.745VLCD.
Voff(RMS)(t) = 0.333VLCD.
Fig 27. Waveforms for the 1:2 multiplex drive mode, 1⁄3 bias, line inversion mode (n = 1)
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8.10.6.3
1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as
shown in Figure 28.
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Vstate1(t) = VSn(t) VBP0(t).
Vstate2(t) = VSn(t) VBP1(t).
Von(RMS)(t) = 0.577VLCD.
Voff(RMS)(t) = 0.333VLCD.
Fig 28. Waveforms for the 1:4 multiplex drive mode, 1⁄3 bias, line inversion mode (n = 1)
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8.11 Backplane outputs
The LCD drive section includes 4 backplane outputs: COM0 to COM3. The backplanes
are double implemented to offer a higher flexibility for the glass layout.
The backplane output signals are generated based on the selected LCD multiplex drive
mode. Table 36 describes which outputs are active for each of the multiplex drive modes
and what signal is generated.
Table 36.
Mapping of output pins and corresponding output signals with respect to the
multiplex driving mode
Multiplex
drive mode
Output pin
COM0
COM1
COM2
COM3
Signal
static
BP0
BP0
BP0
BP0
1:2
BP0
BP1
BP0
BP1
1:4
BP0
BP1
BP2
BP3
Table 37 describes the corresponding layout topology.
Table 37.
Layout topology of output pins and corresponding output signals with respect to
the multiplex driving mode
Multiplex drive mode
Static
1:2
1:4
Signal
On pin
Signal
On pin
Signal
On pin
BP0
COM0
BP0
COM0
BP0
COM0
COM2
BP1
COM1
BP1
COM1
BP2
COM2
COM3
BP3
COM3
COM1
COM2
COM3
8.11.1 Driving strength on the backplanes
Corresponding output pins (COMx), which are carrying the same signal (BPx), may
optionally be connected to the display. This allows gaining a higher driving strength. If not
required, the unused pins can be left open-circuit.
8.12 Segment outputs
The LCD drive section includes 102 segment outputs (S0 to S101) which must be
connected directly to the LCD. The segment output signals are generated based on the
multiplexed backplane signals and with data resident in the display register. When less
than 102 segment outputs are required, the unused segment outputs must be left
open-circuit.
8.13 Display register
The display register holds the display data while the corresponding multiplex signals are
generated.
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8.14 Display RAM
The display RAM is a static 102 4-bit RAM which stores LCD data. Logic 1 in the RAM
bit map indicates the on-state, logic 0 the off-state of the corresponding LCD element.
There is a one-to-one correspondence between
• the bits in the RAM bitmap and the LCD segments/elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
The display RAM bit map, Figure 29 on page 53, shows row 0 to row 3 which correspond
with the backplane outputs COM0 to COM3, and column 0 to column 101 which
correspond with the segment outputs S0 to S101. In multiplexed LCD applications, the
data of each row of the display RAM is time-multiplexed with the corresponding backplane
(row 0 with COM0, row 1 with COM1, and so on).
When display data is transmitted to the PCA8530, the display bytes received are stored in
the display RAM in accordance with the selected LCD multiplex drive mode. The data is
stored as it arrives and does not wait for the acknowledge cycle as with the commands.
Depending on the current multiplex drive mode, data is stored singularly, in pairs, or
quadruples.
8.14.1 Data pointer
The addressing mechanism for the display RAM is realized using a data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the Data-pointer-init command followed by setting the data pointer with the
Data-pointer-MSB and Data-pointer-LSB commands. Then the display RAM content can
be written. An arriving data byte is stored starting at the display RAM address indicated by
the data pointer.
The data pointer is automatically incremented in accordance with the chosen LCD
multiplex drive mode configuration. After each byte is stored, the content of the data
pointer is incremented
• by eight (static drive mode)
• by four (1:2 multiplex drive mode)
• by two (1:4 multiplex drive mode)
When the address counter reaches the end of the RAM, it stops incrementing after the last
byte is transmitted. Redundant bits of the last byte and subsequent bytes transmitted are
discarded. To send new RAM data, the data pointer must be reset.
If a data access with the I2C- or SPI-bus is terminated early, then the state of the data
pointer is unknown. The data pointer must then be rewritten before further RAM accesses.
8.14.1.1
Data pointer in cascade configuration
In cascaded applications each PCA8530 in the cascade must be addressed separately.
Initially, the first PCA8530 is selected by sending the Device-address command matching
the first hardware address. Then the data pointer is set to the preferred display RAM
address with the Data-pointer commands.
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Storage is allowed only when the content of the device address register matches with the
hardware device address applied to A0 and A1 (see Section 8.2.3). If the content of the
device address register and the hardware device address do not match, then data storage
is inhibited but the data pointer is incremented as if data storage had taken place.
8.14.2 RAM filling
For the following examples showing the RAM filling patterns, it is assumed that the bits
shown in Table 38 are transferred to the RAM.
Table 38.
8.14.2.1
Bit scheme used to illustrate the RAM filling patterns
Bit 7
MSB
Byte
6
5
4
3
2
1
0
LSB
1
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aa6
aa5
aa4
aa3
aa2
aa1
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2
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ab6
ab5
ab4
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ab2
ab1
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:
:
:
:
:
:
:
:
:
51
by7
by6
by5
by4
by3
by2
by1
by0
RAM filling in static drive mode
In the static drive mode, the eight transmitted data bits are placed in eight successive
display RAM columns in row 0 (see Table 39).
Table 39.
RAM filling in static drive mode
RAM row/
backplane
output
(COM)
RAM column/Segment output (S)
0
aa7 aa6 aa5 aa4 aa3 aa2 aa1 aa0 ab7 ab6 ab5 ab4 ab3 ab2 ab1 ab0 :
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1
2
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4
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10
11
12
13
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-
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In order to fill the whole RAM row, 13 bytes must be sent to the PCA8530. Any data bits
that spill over the RAM and additional data bytes sent are discarded.
8.14.2.2
RAM filling in 1:2 multiplex drive mode
In the 1:2 multiplex drive mode the eight transmitted data bits are placed in four
successive display RAM columns of two rows (see Table 40).
Table 40.
RAM filling in 1:2 multiplex drive mode
RAM row/
backplane
output
(COM)
RAM column/Segment output (S)
0
1
2
3
4
5
6
7
:
99
100
101
0
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aa1
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3
-
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:
-
-
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In order to fill the whole two RAM rows 26 bytes need to be sent to the PCA8530. Any
data bits that spill over the RAM and additional data bytes sent are discarded.
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8.14.2.3
RAM filling in 1:4 multiplex drive mode
In the 1:4 multiplex drive mode the eight transmitted data bits are placed in two
successive display RAM columns of four rows (see Table 41).
Table 41.
RAM filling in 1:4 multiplex drive mode
RAM row/
backplane
output
(COM)
RAM column/Segment output (S)
0
1
2
3
:
99
100
101
0
aa7
aa3
ab7
ab3
:
bx3
by7
by3
1
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aa2
ab6
ab2
:
bx2
by6
by2
2
aa5
aa1
ab5
ab1
:
bx1
by5
by1
3
aa4
aa0
ab4
ab0
bx0
by4
by0
In order to fill the whole four RAM rows 51 bytes need to be sent to the PCA8530.
Depending on the start address of the data pointer, there is the possibility for a boundary
condition. This occurs when more data bits are sent than fit into the remaining RAM. The
additional data bits are discarded.
8.14.3 Bank selection
The PCA8530 includes a RAM bank switching feature in the static and 1:2 multiplex drive
modes. A bank can be thought of as a RAM row or a collection of RAM rows. The RAM
bank switching gives the provision for preparing display information in an alternative bank
and to be able to switch to it once it is complete. Figure 29 shows the location of the banks
relative to the RAM map.
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The display RAM bitmap shows the direct relationship between the display RAM column and the
segment outputs, between the bits in a RAM row and the backplane outputs, and between the
RAM rows and banks.
Fig 29. Display RAM bitmap and bank definition
Input and output banks can be set independently from one another with the bank-select
commands (see Section 8.7.2 on page 24). Figure 31 shows the concept.
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Fig 30. Bank selection in multiplex drive mode 1:2
In the 1:2 multiplex mode, the bank-select command may request the contents of bank 2
to be selected for display instead of the contents of bank 0. This gives the provision for
preparing display information in an alternative bank and to be able to switch to it once it is
assembled.
In Figure 31 an example is shown for 1:2 multiplex drive mode where the displayed data is
read from the first two rows of the memory (bank 0), while the transmitted data is stored in
the second two rows of the memory (bank 1).
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Fig 31. Example of the Bank-select command with multiplex drive mode 1:2
8.14.3.1
Input-bank-select
The Input-bank-select command (see Table 26 on page 24) loads display data into the
display RAM in accordance with the selected LCD drive configuration (see Figure 29 on
page 53).
• In static drive mode, an individual content can be stored in each RAM bank (bank 0 to
bank 3 which corresponds to row 0 and row 3).
• In 1:2 multiplex drive mode, individual content for RAM bank 0 (row 0 and row 1),
RAM bank 2 (row 2 and row 3) can be stored.
The Input-bank-select command works independently to the Output-bank-select
command.
8.14.3.2
Output-bank-select
The Output-bank-select command (see Table 27 on page 25) selects the display RAM
transferring it to the display register in accordance with the selected LCD drive
configuration (see Figure 29 on page 53).
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• In the static drive mode, it is possible to request the content of RAM bank 1 for display
instead of the default RAM bank 0.
• In 1:2 multiplex drive mode, the content of RAM bank 2 may be selected instead of
the default RAM bank 0.
The Output-bank-select command works independently to the Input-bank-select
command.
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9. Bus interfaces
9.1 Control byte and register selection
After initiating the communication over the bus and sending the slave address (I2C-bus,
see Section 9.2) or subaddress (SPI-bus, see Section 9.3 on page 61), a control byte
follows. The purpose of this byte is to indicate both, the content for the following data
bytes (RAM or command) and to indicate that more control bytes will follow.
Typical sequences could be:
• Slave address/subaddress - control byte - command byte - command byte - command
byte - end
• Slave address/subaddress - control byte - RAM byte - RAM byte - RAM byte - end
• Slave address/subaddress - control byte - command byte - control byte - RAM byte end
This allows sending a mixture of RAM and command data in one access or alternatively,
to send just one type of data in one access. In this way, it is possible to configure the
device and then fill the display RAM with little overhead. The display bytes are stored in
the display RAM at the address specified by the data pointer.
Table 42.
Control byte description
Bit
Symbol
7
CO
6 to 5
4 to 0
Value
Description
continue bit
0
last control byte
1
control bytes continue
RS[1:0]
register selection
-
00, 10
command register
01
RAM data
11
unused
-
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Fig 32. Control byte format
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9.2 I2C interface
The I2C-bus is selected by connecting pin IFS to VDD1.
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
In Chip-On-Glass (COG) applications, where the track resistance between the SDA
output pin to the system SDA input line can be significant, the bus pull-up resistor and the
Indium Tin Oxide (ITO) track resistance may generate a voltage divider. As a
consequence it may be possible that the acknowledge cycle, generated by the LCD driver,
cannot be interpreted as logic 0 by the master. Therefore it is an advantage for COG
applications to have the acknowledge output separated from the data line. For that
reason, the SDA line of the PCA8530 is split into SDI/SDAIN and SDAOUT.
In COG applications where the acknowledge cycle is required, it is necessary to minimize
the track resistance from the SDAOUT pin to the system SDI/SDAIN line to guarantee a
valid LOW level.
By splitting the SDA line into SDI/SDAIN and SDAOUT (having the SDAOUT open
circuit), the device could be used in a mode that ignores the acknowledge cycle.
Separating the acknowledge output from the serial data line can avoid design efforts to
generate a valid acknowledge level. However, in that case the I2C-bus master has to be
set up in such a way that it ignores the acknowledge cycle.2
By connecting pin SDAOUT to pin SDI/SDAIN, the SDI/SDAIN line becomes fully I2C-bus
compatible. The following definition assumes SDI/SDAIN and SDAOUT are connected
and refers to the pair as SDA.
9.2.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as a control signal (see Figure 33).
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Fig 33. I2C-bus - bit transfer
9.2.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW change of the data line, while the clock is HIGH is defined as the START
condition (S).
2.
For further information, consider the NXP application note: Ref. 1 “AN10170”.
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A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP
condition (P).
The START and STOP conditions are shown in Figure 34.
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Fig 34. I2C-bus - definition of START and STOP conditions
9.2.3 System configuration
A device generating a message is a transmitter; a device receiving a message is the
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves. The system configuration is shown in Figure 35.
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Fig 35. I2C-bus - system configuration
9.2.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge
cycle.
• A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 36.
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
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Fig 36. Acknowledgement on the I2C-bus
9.2.5 I2C-bus controller
The PCA8530 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers. The
only data output from PCA8530 is the acknowledge signals and the temperature readout
byte of the selected device.
9.2.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
9.2.7 I2C-bus slave address
Device selection depends on the I2C-bus slave address.
Table 43.
I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
MSB
slave address
0
0
LSB
1
1
1
0
SA1
SA0
R/W
The least significant bit of the slave address byte is bit R/W (see Table 44).
Table 44.
R/W-bit description
R/W
Description
0
write data
1
read data
Bit 1 and bit 2 of the slave address are defined by connecting the inputs SA0 and SA1 to
either VSS1 (logic 0) or VDD1 (logic 1). Therefore, four instances of PCA8530 can be
distinguished on the same I2C-bus.
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9.2.8 I2C-bus protocol
The I2C-bus protocol is shown in Figure 37. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of the four PCA8530 slave
addresses available. All PCA8530 with the corresponding SA1 and SA0 level
acknowledge in parallel to the slave address, but all PCA8530 with the alternative SA1
and SA0 levels ignore the whole I2C-bus transfer.
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Fig 37. I2C-bus protocol - write mode
After acknowledgement, a control byte follows which defines if the next byte is RAM or
command information. The control byte (see Table 42 on page 56) also defines whether
the next byte is a control byte or further RAM or command data.
For a temperature readout (see Section 8.10.4.1 on page 40), the R/W bit must be logic 1.
The next data byte following is provided by the PCA8530 as shown in Figure 38.
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Fig 38. I2C-bus protocol - read mode
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9.3 SPI interface
The SPI interface is selected by connecting pin IFS to VSS1.
Data transfer to the device is made via a four-line SPI-bus (see Table 45). The SPI-bus is
initialized whenever the chip enable line pin CE is LOW.
Table 45.
Serial interface
Symbol
Function
Description
CE
chip enable input;
active LOW[1]
when HIGH, the interface is reset
SCL
serial clock input
input may be higher than VDD1
SDI/SDAIN serial data input
input may be higher than VDD1;
input data is sampled on the rising edge of SCL
SDO
[1]
serial data output
-
The chip enable must not be wired permanently LOW.
9.3.1 Data transmission
The chip enable signal (CE) is used to initialize data transmission. Each data transfer is a
byte, with the MSB sent first. The first byte transmitted is the subaddress byte.
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Fig 39. SPI-bus protocol - data transfer overview
The subaddress byte opens the communication with a read/write bit and a subaddress.
The subaddress is used to identify multiple devices on one SPI bus.
Table 46.
Subaddress byte definition
Bit
Symbol
7
R/W
6 to 5
SA
4 to 0
-
Value
Description
data read or write selection
0
write data
1
read data
01
subaddress; other codes cause the device to
ignore data transfer
unused
Figure 40 shows an example of an SPI data transfer.
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5:
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In this example, the bias system is set to 1⁄3. The transfer is terminated by CE returning to logic 1. After the last bit is
transmitted, the state of the SDI/SDAIN line is not important.
Fig 40. SPI-bus example
For a temperature readout (see Section 8.10.4.1 on page 40), the R/W bit must be logic 1.
The next data byte following is provided by the PCA8530 as shown in Figure 41.
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Fig 41. SPI-bus protocol - read example
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DDD
Data transfers are terminated by de-asserting CE (set CE to logic 1).
Fig 42. SPI-bus protocol - write example
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10. Internal circuitry
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Fig 43. Device protection diagram
PCA8530
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11. Safety notes
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
CAUTION
Semiconductors are light sensitive. Exposure to light sources can cause the IC to
malfunction. The IC must be protected against light. The protection must be applied to all
sides of the IC.
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12. Limiting values
Table 47. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDD1
supply voltage 1
analog and digital
0.5
+6.5
V
VDD2
supply voltage 2
charge pump
0.5
+6.5
V
VDD3
supply voltage 3
analog
0.5
+6.5
V
IDD1
supply current 1
analog and digital
50
+50
mA
IDD2
supply current 2
charge pump
50
+50
mA
IDD3
supply current 3
analog
50
+50
mA
VLCD
LCD supply voltage
external supply, input on pin
VLCDIN
0.5
+20
V
IDD(LCD)
LCD supply current
50
+50
mA
Vi
input voltage
on pins CLK, OSC, A0, A1,
RST, IFS, SCL, SDI/SDAIN,
SA0, CE, SA1, SYNC0,
SYNC1
0.5
+6.5
V
on pin VLCDSENSE
0.5
+20
V
II
input current
10
+10
mA
VO
output voltage
on pins S0 to S101,
COM0 to COM3, VLCDOUT
0.5
+20
V
on pins SDO, SA0,
SDAOUT, CLK, SYNC0,
SYNC1
0.5
+6.5
V
10
+10
mA
IO
output current
ISS
ground supply current
50
+50
mA
Ptot
total power dissipation
-
400
mW
P/out
power dissipation per
output
-
100
mW
VESD
electrostatic discharge
voltage
[1]
-
2000
V
Ilu
latch-up current
[2]
-
150
mA
Tstg
storage temperature
[3]
65
+150
C
Tamb
ambient temperature
40
+105
C
HBM
operating device
[1]
Pass level; Human Body Model (HBM), according to Ref. 8 “JESD22-A114”.
[2]
Pass level; latch-up testing according to Ref. 9 “JESD78” at maximum ambient temperature (Tamb(max)).
[3]
According to the store and transport requirements (see Ref. 14 “UM10569”) the devices have to be stored at a temperature of +8 C to
+45 C and a humidity of 25 % to 75 %.
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13. Static characteristics
Table 48. Static characteristics
VDD1, VDD2, VDD3 = 2.5 V to 5.5 V; VSS1 = 0 V; VLCD = 4.0 V to 12.0 V; Tamb = 40 C to +105 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD1
supply voltage 1
2.5
-
5.5
V
VDD2
supply voltage 2
2.5
-
5.5
V
VDD3
supply voltage 3
2.5
-
5.5
V
VLCD
LCD supply voltage
external supply, input on
pin VLCDIN
4.0
-
12.0
V
internal supply, output on
pin VLCDOUT
4.0
-
12.0
V
default condition after
power-on and Initialize
command, see Figure 44
-
40[1]
58[2]
A
display enabled;
internal clock
-
45[1]
-
A
default condition after
power-on and Initialize
command
-
0
-
A
VDD2 = 5 V;
charge pump at
VLCD = 2 VDD2;
VLCD = 8 V;
CVLCD = 100 nF;
display disabled;
see Figure 45
-
25
-
A
default condition after
power-on and Initialize
command, see Figure 46
-
40[3]
58[4]
A
display enabled;
internal clock
-
90[3]
-
A
display disabled, see
Figure 47
-
6.5
10
A
MUX 1:4;
bias;
ffr = 80 Hz;
RAM entirely filled with 1;
frame inversion mode;
display enabled;
no display attached
-
85
-
A
IDD1
IDD2
IDD3
IDD(LCD)
supply current 1
supply current 2
supply current 3
LCD supply current
VLCD VDD2
on pin VDD1
on pin VDD2
on pin VDD3
on pin VLCDIN;
external VLCD = 8 V
1⁄
3
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Table 48. Static characteristics …continued
VDD1, VDD2, VDD3 = 2.5 V to 5.5 V; VSS1 = 0 V; VLCD = 4.0 V to 12.0 V; Tamb = 40 C to +105 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VLCD
LCD voltage variation
on pin VLCDOUT;
internal VLCD;
V[8:0] = 86h;
Tamb = 25 C;
see Figure 48
7950
8010
8070
mV
ffr
frame frequency variation
internal clock;
FF[4:0] = 00111;
Tamb = 25 C;
see Figure 49
77
80
83
Hz
Tmeas
measurement temperature
variation
see Figure 50
-
0
-
C
external VLCD = 8 V
-
1
-
k
output resistance on pin S0 external VLCD = 8 V
to S101
-
2.5
-
k
Accuracy
Output resistance
Ro(COM[0:8]) output resistance on pin
COM0 to COM3
Ro(S[0:101])
Logic
On pins CLK, OSC, A0, A1, SYNC0, SYNC1, RST, IFS
VI
input voltage
VSS1 0.5 -
VDD1 + 0.5 V
VIL
LOW-level input voltage
-
-
0.3VDD1
V
VIH
HIGH-level input voltage
0.7VDD1
-
-
V
ILI
input leakage current
-
0
-
A
VI = VDD1 or VSS1
On pins CLK, SYNC0, SYNC1
VO
output voltage
0.5
-
VDD1 + 0.5 V
VOH
HIGH-level output voltage
0.8VDD1
-
-
V
VOL
LOW-level output voltage
-
-
0.2VDD1
V
IOH
HIGH-level output current
output source current;
VOH = 4.6 V;
VDD1 = 5 V
1
-
-
mA
IOL
LOW-level output current
output sink current;
VOL = 0.4 V;
VDD1 = 5 V
1
-
-
mA
ILO
output leakage current
VO = VDD1 or VSS1
-
0
-
A
I2C-bus
On pins SCL, SDI/SDAIN
VI
input voltage
VSS1 0.5 -
5.5
V
VIL
LOW-level input voltage
-
0.3VDD1
V
VIH
HIGH-level input voltage
ILI
input leakage current
VI = VDD1 or VSS1
-
0.7VDD1
-
-
V
-
0
-
A
0.5
-
+5.5
V
6
-
-
mA
On pin SDAOUT
VO
output voltage
IOL
LOW-level output current
PCA8530
Product data sheet
output sink current;
VOL = 0.4 V
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Table 48. Static characteristics …continued
VDD1, VDD2, VDD3 = 2.5 V to 5.5 V; VSS1 = 0 V; VLCD = 4.0 V to 12.0 V; Tamb = 40 C to +105 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ILI
input leakage current
VI = VDD1 or VSS1
-
0
-
A
ILO
output leakage current
VO = VSS1
-
0
-
A
on pins SCL, SDI/SDAIN
VSS1 0.5 -
5.5
V
on pin CE
VSS1 0.5 -
VDD1 + 0.5 V
SPI-bus
On pins SCL, SDI/SDAIN, CE
VI
input voltage
VIL
LOW-level input voltage
-
-
0.3VDD1
V
VIH
HIGH-level input voltage
0.7VDD1
-
-
V
ILI
input leakage current
-
0
-
A
VI = VDD1 or VSS1
On pin SDO
VO
output voltage
0.5
-
VDD1 + 0.5 V
VOH
HIGH-level output voltage
0.8VDD1
-
-
V
VOL
LOW-level output voltage
-
-
0.2VDD1
V
IOH
HIGH-level output current
output source current;
VOH = 4.6 V;
VDD1 = 5 V
1
-
-
mA
IOL
LOW-level output current
output sink current;
VOL = 0.4 V;
VDD1 = 5 V
1
-
-
mA
ILO
output leakage current
VO = VDD1 or VSS1
-
0
-
A
[1]
VDD1 = 5 V; Tamb = 25 C.
[2]
VDD1 = 5.5 V; Tamb = 105 C.
[3]
VDD3 = 5 V; Tamb = 25 C.
[4]
VDD3 = 5.5 V; Tamb = 105 C.
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
DDD
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Default conditions after power-on and initialization.
(1) VDD1 = 5.5 V.
(2) VDD1 = 5 V.
(3) VDD1 = 3 V.
(4) VDD1 = 2.5 V.
Fig 44. Typical IDD1 with respect to temperature
DDD
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7DPE&
(1) VDD2 = 3 V; charge pump at VLCD = 3 VDD2; VLCD = 8 V; CVLCD = 100 nF; display disabled.
(2) VDD2 = 5 V; charge pump at VLCD = 2 VDD2; VLCD = 8 V; CVLCD = 100 nF; display disabled.
Fig 45. Typical IDD2 with respect to temperature
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
DDD
,''
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7DPE&
Default conditions after power-on.
(1) VDD1 = 5.5 V.
(2) VDD1 = 5 V.
(3) VDD1 = 3 V.
(4) VDD1 = 2.5 V.
Fig 46. Typical IDD3 with respect to temperature
DDD
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9/&' 9
9/&' 9
9/&' 9
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Conditions: External VLCD; display disabled.
Fig 47. Typical IDD(LCD) with respect to temperature
PCA8530
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
DDD
9/&'
9
7DPE&
Conditions: VDD2 = 5 V; charge pump at VLCD = 2 VDD2; VLCD = 8 V; V[8:0] = 134h; temperature
compensation disabled.
Fig 48. Typical VLCD variation with respect to temperature
DDD
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7DPE&
Conditions: frame frequency prescaler = 00111; 80 Hz typical.
Fig 49. Typical frame frequency variation with respect to temperature
PCA8530
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
DDD
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The values of Tmeas(max) and Tmeas(min) are obtained from the chip evaluation process and are not
production tested.
Fig 50. Measurement temperature variation with respect to temperature
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14. Dynamic characteristics
14.1 General dynamic characteristics
Table 49. General dynamic characteristics
VDD1, VDD2, VDD3 = 2.5 V to 5.5 V; VSS1 = 0 V; VLCD = 4.0 V to 12.0 V; Tamb = 40 C to +105 C; unless otherwise specified.
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and
VIH with an input voltage swing of VSS1 to VDD1.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fclk(int)
internal clock frequency
on pin CLK;
FF[4:0] = 00111;
Tamb = 25 C
11088
11520
11952
Hz
fclk(ext)
external clock frequency
on pin CLK
6400
-
42700
Hz
tclk(H)
HIGH-level clock time
external clock source used
5
-
-
s
tclk(L)
LOW-level clock time
5
-
-
s
twL(RST_N)
RST_N LOW pulse width
Cb
capacitive load for each
bus line
I2C-bus
3
-
-
s
-
-
400
pF
IFON
WFON+
WFON/
9''
&/.
9''
DDD
Fig 51. Driver timing waveforms
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14.2 I2C-bus timing characteristics
Table 50. I2C-bus timing characteristic
VDD1, VDD2, VDD3 = 2.5 V to 5.5 V; VSS1 = 0 V; VLCD = 4.0 V to 12.0 V; Tamb = 40 C to +105 C; unless otherwise specified.
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and
VIH with an input voltage swing of VSS1 to VDD1.
Symbol
Parameter
Min
Typ
Max
Unit
fSCL
SCL frequency
Conditions
-
-
400
kHz
tBUF
bus free time between a
STOP and START
condition
1.3
-
-
s
tHD;STA
hold time (repeated)
START condition
0.6
-
-
s
tSU;STA
set-up time for a repeated
START condition
0.6
-
-
s
tVD;DAT
data valid time
[1]
-
-
0.9
s
tVD;ACK
data valid acknowledge
time
[2]
-
-
0.9
s
tLOW
LOW period of the SCL
clock
1.3
-
-
s
tHIGH
HIGH period of the SCL
clock
0.6
-
-
s
tf
fall time
of both SDA and SCL
signals
-
-
0.3
s
tr
rise time
of both SDA and SCL
signals
-
-
0.3
s
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
tSU;STO
set-up time for STOP
condition
0.6
-
-
s
tw(spike)
spike pulse width
-
-
50
ns
[1]
tVD;DAT = minimum time for valid SDA output following SCL LOW.
[2]
tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW.
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© NXP Semiconductors N.V. 2014. All rights reserved.
74 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
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Fig 52. I2C-bus timing
14.3 SPI-bus timing characteristics
Table 51. SPI-bus timing characteristics
VDD1, VDD2, VDD3 = 2.5 V to 5.5 V; VSS1 = 0 V; VLCD = 4.0 V to 12.0 V; Tamb = 40 C to +105 C; unless otherwise specified.
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and
VIH with an input voltage swing of VSS1 to VDD1.
Symbol
Parameter
Conditions
Min
Max
Unit
Pin SCL
fclk(SCL)
SCL clock frequency
-
3.0
MHz
tSCL
SCL time
333
-
ns
tclk(H)
clock HIGH time
100
-
ns
tclk(L)
clock LOW time
150
-
ns
tr
rise time
for SCL signal
-
100
ns
tf
fall time
for SCL signal
-
100
ns
Pin CE
tsu(CE_N)
CE_N set-up time
30
-
ns
th(CE_N)
CE_N hold time
30
-
ns
trec(CE_N)
CE_N recovery time
30
-
ns
Pin SDI/SDAIN
tsu
set-up time
set-up time for SDI data
30
-
ns
th
hold time
hold time for SDI data
30
-
ns
SDO read delay time
CL = 100 pF
-
150
ns
-
50
ns
0
-
ns
Pin SDO
td(R)SDO
tdis(SDO)
SDO disable time
tt(SDI-SDO)
transition time from SDI to
SDO
[1]
[1]
to avoid bus conflict
No load value; bus will be held up by bus capacitance; use RC time constant with application values.
PCA8530
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 25 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
75 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
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Fig 53. SPI-bus timing
PCA8530
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 25 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
76 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
15. Application information
15.1 ITO layout recommendations for ESD/EMC robustness in COG
applications
The crucial factor for gaining an EMC and ESD robust application is the quality of the
VSS1 line.
• To get an EMC/ESD robust ITO/glass layout, the RITO(VSS1) has to be kept as low as
possible.
• In the most common applications VSS1 is connected to the pins T1, T2, A0, A1, OSC,
SA0, SA1 and IFS (in the case of using the SPI interface) by using a very wide ITO
connection
• If possible, the ITO connection of VSS1 should be made wide, for example by fanning
out the other connections
• When the display is enabled, the charge and discharge caused by display activity
affects the VSS1 line. This causes a dynamic current in the VSS1 line which means
that dynamic voltage peaks in the VSS1 line may interfere with the low voltage part of
the PCA8530. Therefore a low RITO(VSS1) is also important for an improved noise
immunity of the PCA8530 especially at high VLCD values (VLCD > 10 V).
• A low RITO(VSS1) also improves the communication stability with the microcontroller by
reducing the effects of local ground (VSS1) bounce caused by high SDAACK
currents.
• It should be considered that VSS1 is internally connected to the IC substrate,
therefore noise on the VSS1 line causes noise inside the IC.
Figure 54 and Figure 55 are showing the recommended ITO connections for a COG
layout according to the interface type use.
PCA8530
Product data sheet
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Rev. 2 — 25 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
77 of 103
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(2) RITO 50 .
(3) RITO 200 .
Fig 54. Recommended ITO connections for the I2C interface
PCA8530
78 of 103
© NXP Semiconductors N.V. 2014. All rights reserved.
(1) RITO 100 .
DDD
Automotive 102 x 4 Chip-On-Glass LCD segment driver
Rev. 2 — 25 September 2014
All information provided in this document is subject to legal disclaimers.
3&$'8*
NXP Semiconductors
PCA8530
Product data sheet
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NXP Semiconductors
PCA8530
Product data sheet
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Fig 55. Recommended ITO connections for the SPI interface
PCA8530
79 of 103
© NXP Semiconductors N.V. 2014. All rights reserved.
(1) RITO 100 .
DDD
Automotive 102 x 4 Chip-On-Glass LCD segment driver
Rev. 2 — 25 September 2014
All information provided in this document is subject to legal disclaimers.
6<1&
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PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
15.2 Cascaded operation
In large display configurations, up to four PCA8530 can be distinguished on the same bus
by using the 2-bit hardware device addresses (A0 and A1).
Table 52.
Addressing cascaded PCA8530
Pin A1
Pin A0
Device
0
0
0 (master)
0
1
1 (slave)
1
0
2 (slave)
1
1
3 (slave)
15.2.1 Wiring backplane and segment outputs
When the cascaded PCA8530 are synchronized, they can share the backplane signals
from one of the devices in the cascade. Such an arrangement is cost-effective in large
LCD applications since the backplane outputs of only one device need to be
through-plated to the backplane electrodes of the display. The other PCA8530 of the
cascade contribute additional segment outputs. The backplanes can either be connected
together to enhance the drive capability or some can be left open-circuit (such as the ones
from the slave in Figure 56 and Figure 57) or just some of the master and some of the
slave will be taken to facilitate the layout of the display.
PCA8530
Product data sheet
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Rev. 2 — 25 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
80 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
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(1) Is master (OSC and A0 connected to VSS1).
(2) Is slave (OSC and A0 connected to VDD1).
Fig 56. Cascaded configuration with two PCA8530 with external VLCD and internal clock
PCA8530
Product data sheet
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Rev. 2 — 25 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
81 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
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(1) Is master (A0 connected to VSS1).
(2) Is slave (A0 connected to VDD1).
Fig 57. Cascaded configuration with two PCA8530 with internal VLCD and external clock
15.2.2 Device synchronization
The SYNC0 and SYNC1 lines are provided to maintain the correct synchronization
between all cascaded PCA8530. (SYNC1 must not be connected when using an
externally supplied VLCD.) This synchronization is guaranteed after the Power-On Reset
(POR). SYNC0 and SYNC1 are organized as input/output pins.
Both, the internally generated clock frequency or, alternatively, an externally supplied
clock signal can be used in cascaded applications.
In cascaded applications that use the internal clock, the master PCA8530 with device
address A[1:0] = 00 must have the OSC pin connected to VSS1 and the COE bit is set
logic 1, so that this device uses its internal clock to generate a clock signal at the CLK pin.
PCA8530
Product data sheet
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Rev. 2 — 25 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
82 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
The other PCA8530 devices are having the OSC pin connected to VDD1, meaning that
these devices are ready to receive an external clock signal which is provided by the
master device with subaddress A[1:0] = 00.
If the master is providing the clock signal to the slave devices, care must be taken that the
sending of display enable or disable will be received by both, the master and the slaves at
the same time. When the display is disabled, the output from pin CLK is disabled too. The
disconnection of the clock may result in a DC component for the display.
In cascaded applications that use an external clock, all devices have the OSC pin
connected to VDD1 and thus an external CLK being provided for the system (all devices
connected to the same external CLK).
15.2.3 Display data
The storage of display data is determined by the contents of the device address register
(see Section 8.2.3 on page 11). Storage is allowed only when the content of the device
address register matches with the hardware device address applied to the pins A0 and
A1. If the content of the device address register and the hardware device address do not
match, data storage is inhibited but the data pointer is incremented as if data storage had
taken place. The hardware device address must not be changed while the device is being
accessed on the interface.
15.2.4 Data read
Only when the content of the device address register (see Section 8.2.3 on page 11)
matches with the hardware device address applied to the pins A0 and A1, the temperature
or device status readout (see Section 8.2.7 on page 13) is activated. If the content of the
device address register and the hardware device address do not match, the data output
pin (SDA or SDO) of the device is in 3-state. With this, bus conflicts and incorrect reading
is prevented.
PCA8530
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 25 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
83 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
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(1) Master.
(2) Slave.
a. I2C interface
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(1) Master.
(2) Slave.
b. SPI interface
Fig 58. Cascade configuration for data reading
16. Test information
16.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated
circuits, and is suitable for use in automotive applications.
PCA8530
Product data sheet
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Rev. 2 — 25 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
84 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
17. Bare die outline
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PCA8530
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 25 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
85 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
Table 53. Bump locations of PCA8530DUG
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 59.
Symbol
Pin Coordinates
X (m)
COM3
COM2
VLCDIN
VLCDSENSE
VLCDOUT
T4
T3
T5
T6
PCA8530
Product data sheet
Pitch
Symbol
Y (m) X (m)
1
2847.5 495
-
2
2802.5 495
45
3
2757.5 495
45
4
2712.5 495
45
5
2667.5 495
6
2622.5 495
Pin Coordinates
X (m)
S101
Pitch
Y (m) X (m)
126 2846.7
495
-
127 2801.7
495
45
S100
128 2756.7
495
45
S99
129 2711.7
495
45
45
S98
130 2666.7
495
45
45
S97
131 2621.7
495
45
7
2577.5 495
45
S96
132 2576.7
495
45
8
2532.5 495
45
S95
133 2531.7
495
45
9
2487.5 495
45
S94
134 2486.7
495
45
10
2442.5 495
45
S93
135 2441.7
495
45
11
2397.5 495
45
S92
136 2396.7
495
45
12
2352.5 495
45
S91
137 2351.7
495
45
13
2307.5 495
45
S90
138 2306.7
495
45
14
2262.5 495
45
S89
139 2261.7
495
45
15
2217.5 495
45
S88
140 2216.7
495
45
16
2172.5 495
45
S87
141 2171.7
495
45
17
2127.5 495
45
S86
142 2126.7
495
45
18
2082.5 495
45
S85
143 2081.7
495
45
19
2037.5 495
45
S84
144 1975.7
495
106
20
1992.5 495
45
S83
145 1930.7
495
45
21
1947.5 495
45
S82
146 1885.7
495
45
22
1902.5 495
45
S81
147 1840.7
495
45
23
1857.5 495
45
S80
148 1795.7
495
45
24
1812.5 495
45
S79
149 1750.7
495
45
25
1767.5 495
45
S78
150 1705.7
495
45
26
1722.5 495
45
S77
151 1660.7
495
45
27
1677.5 495
45
S76
152 1615.7
495
45
28
1632.5 495
45
S75
153 1570.7
495
45
29
1587.5 495
45
S74
154 1525.7
495
45
30
1542.5 495
45
S73
155 1480.7
495
45
31
1497.5 495
45
S72
156 1435.7
495
45
32
1452.5 495
45
S71
157 1390.7
495
45
33
1407.5 495
45
S70
158 1345.7
495
45
34
1362.5 495
45
S69
159 1300.7
495
45
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 25 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
86 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
Table 53. Bump locations of PCA8530DUG …continued
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 59.
Symbol
Pin Coordinates
X (m)
VSS2
VSS3
VSS1
Y (m) X (m)
Pin Coordinates
X (m)
Pitch
Y (m) X (m)
35
1317.5 495
45
S68
160 1255.7
495
45
36
1272.5 495
45
S67
161 1210.7
495
45
37
1227.5 495
45
S66
162 1165.7
495
45
38
1182.5 495
45
S65
163 1120.7
495
45
39
1137.5 495
45
S64
164 1075.7
495
45
40
1092.5 495
45
S63
165 1030.7
495
45
41
1047.5 495
45
S62
166 985.7
495
45
42
1002.5 495
45
S61
167 940.7
495
45
43
957.5
495
45
S60
168 895.7
495
45
44
912.5
495
45
S59
169 850.7
495
45
45
867.5
495
45
S58
170 805.7
495
45
46
822.5
495
45
S57
171 760.7
495
45
47
777.5
495
45
S56
172 715.7
495
45
48
732.5
495
45
S55
173 670.7
495
45
49
687.5
495
45
S54
174 625.7
495
45
50
642.5
495
45
S53
175 580.7
495
45
51
597.5
495
45
S52
176 535.7
495
45
52
552.5
495
45
S51
177 490.7
495
45
53
507.5
495
45
COM0
178 382.1
495
108.6
54
462.5
495
45
179 337.1
495
45
55
417.5
495
45
180 292.1
495
45
372.5
495
45
181 247.1
495
45
57
327.5
495
45
182 202.1
495
45
58
282.5
495
45
183 157.1
495
45
59
237.5
495
45
184 112.1
495
45
60
192.5
495
45
185 67.1
495
45
61
147.5
495
45
186 22.1
495
45
A0
62
102.5
495
45
187 22.9
495
45
63
57.5
495
45
188 67.9
495
45
A1
64
12.5
495
45
189 112.9
495
45
65
32.5
495
45
190 157.9
495
45
66
77.5
495
45
191 202.9
495
45
67
122.5
495
45
192 247.9
495
45
68
167.5
495
45
193 292.9
495
45
69
212.5
495
45
194 337.9
495
45
70
257.5
495
45
195 382.9
495
45
71
302.5
495
45
196 491.5
495
108.6
T2
IFS
OSC
SA0
Product data sheet
Symbol
56
T1
PCA8530
Pitch
COM1
COM2
COM3
S50
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 25 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
Table 53. Bump locations of PCA8530DUG …continued
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 59.
Symbol
Pin Coordinates
X (m)
SA1
VDD1
VDD3
VDD2
CE
CLK
SYNC1
SYNC0
RST
SDI/SDAIN
PCA8530
Product data sheet
Pitch
Symbol
Y (m) X (m)
Pin Coordinates
X (m)
Pitch
Y (m) X (m)
72
347.5
495
45
S49
197 536.5
495
45
73
392.5
495
45
S48
198 581.5
495
45
74
437.5
495
45
S47
199 626.5
495
45
75
482.5
495
45
S46
200 671.5
495
45
76
527.5
495
45
S45
201 716.5
495
45
77
572.5
495
45
S44
202 761.5
495
45
78
617.5
495
45
S43
203 806.5
495
45
79
662.5
495
45
S42
204 851.5
495
45
80
707.5
495
45
S41
205 896.5
495
45
81
752.5
495
45
S40
206 941.5
495
45
82
797.5
495
45
S39
207 986.5
495
45
83
842.5
495
45
S38
208 1031.5 495
45
84
887.5
495
45
S37
209 1076.5 495
45
85
932.5
495
45
S36
210 1121.5 495
45
86
977.5
495
45
S35
211 1166.5 495
45
87
1022.5
495
45
S34
212 1211.5 495
45
88
1067.5
495
45
S33
213 1256.5 495
45
89
1112.5
495
45
S32
214 1301.5 495
45
90
1157.5
495
45
S31
215 1346.5 495
45
91
1202.5
495
45
S30
216 1391.5 495
45
92
1247.5
495
45
S29
217 1436.5 495
45
93
1292.5
495
45
S28
218 1481.5 495
45
94
1337.5
495
45
S27
219 1526.5 495
45
95
1382.5
495
45
S26
220 1571.5 495
45
96
1427.5
495
45
S25
221 1616.5 495
45
97
1472.5
495
45
S24
222 1661.5 495
45
98
1517.5
495
45
S23
223 1706.5 495
45
99
1562.5
495
45
S22
224 1751.5 495
45
100 1607.5
495
45
S21
225 1796.5 495
45
101 1652.5
495
45
S20
226 1841.5 495
45
102 1697.5
495
45
S19
227 1886.5 495
45
103 1742.5
495
45
S18
228 1931.5 495
45
104 1787.5
495
45
S17
229 1976.5 495
45
105 1832.5
495
45
S16
230 2082.5 495
106
106 1877.5
495
45
S15
231 2127.5 495
45
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PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
Table 53. Bump locations of PCA8530DUG …continued
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 59.
Symbol
Pin Coordinates
X (m)
SDAOUT
SDO
SCL
COM1
COM0
Pitch
Symbol
Pin Coordinates
Y (m) X (m)
X (m)
Pitch
Y (m) X (m)
107 1922.5
495
45
S14
232 2172.5 495
45
108 1967.5
495
45
S13
233 2217.5 495
45
109 2012.5
495
45
S12
234 2262.5 495
45
110 2057.5
495
45
S11
235 2307.5 495
45
111 2102.5
495
45
S10
236 2352.5 495
45
112 2147.5
495
45
S9
237 2397.5 495
45
113 2192.5
495
45
S8
238 2442.5 495
45
114 2237.5
495
45
S7
239 2487.5 495
45
115 2282.5
495
45
S6
240 2532.5 495
45
116 2327.5
495
45
S5
241 2577.5 495
45
117 2485.2
495
157.7
S4
242 2622.5 495
45
118 2530.2
495
45
S3
243 2667.5 495
45
119 2575.2
495
45
S2
244 2712.5 495
45
120 2620.2
495
45
S1
245 2757.5 495
45
121 2665.2
495
45
S0
246 2802.5 495
45
122 2710.2
495
45
247 2847.5 495
45
123 2755.2
495
45
-
-
-
-
124 2800.2
495
45
-
-
-
-
125 2845.2
495
45
-
-
-
-
e
e1
Table 54. Dimensions of PCA8530DUG
Original dimensions are in mm.
Unit (mm)
A
A1
A2
b
D
E
L
max
-
0.018
-
-
-
-
-
-
-
nom
0.40
0.015
0.38
0.03
5.88
1.20
0.045
0.158
0.09
min
-
0.012
-
-
-
-
-
-
-
The alignment marks are shown in Table 55.
5()
6
5()
&
DDD
Fig 60. Alignment marks
PCA8530
Product data sheet
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
Table 55. Alignment marking
All x/y coordinates represent the position of the REF point (see Figure 60) with respect to the center
(x/y = 0) of the chip; see Figure 59.
Symbol
Size (m)
X (m)
Y (m)
S1
90 90
2375
15
C1
90 90
2312
15
Table 56.
Gold bump hardness
Type number
Min
Max
Unit[1]
PCA8530DUG/DA
60
120
HV
[1]
Pressure of diamond head: 10 g to 50 g.
18. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
PCA8530
Product data sheet
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
19. Packing information
19.1 Tray information
-
$
+
%
$
$
[
;
.
)
GLH
(
GHWDLO;
'
\
\
[
*
)
(
&
2
1
/
0
6(&7,21$$
<
'LPHQVLRQVLQPP
GHWDLO<
DDD
Schematic drawing, not drawn to scale. Top side view. For dimensions, see Table 57. Tray has pockets on both, top side and
bottom side. The IC is stored with the active side up. To get the active side down, turn the tray.
Fig 61. Tray details of PCA8530DUG
PCA8530
Product data sheet
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91 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
Table 57. Description of tray details
Tray details are shown in Figure 61.
Tray details
Dimensions
A
B
C
D
E
F
G
H
J
K
L
M
N
O
Unit
8
2.5
5.978
1.298
76
68
56
6.75
10
62.5
4.2
2.6
3.2
0.6
mm
Number of pockets
x direction
y direction
8
26
SLQ
DDD
The orientation of the IC in a pocket with active side up is indicated by the position of pin 1 with
respect to the chamfer on the upper left corner of the tray.
Fig 62. Die alignment in the tray
PCA8530
Product data sheet
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92 of 103
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
PCA8530
Product data sheet
20. Appendix
20.1 LCD segment driver selection
Table 58.
Selection of LCD segment drivers
Type name
Number of elements at MUX
ffr (Hz)
Interface Package
AECQ100
40
80
120 160 -
-
-
1.8 to 5.5 1.8 to 5.5 32 to 256[1]
N
N
40 to 105 I2C / SPI
TSSOP56 Y
PCA8546ATT
-
-
-
176 -
-
-
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 95
I2C
TSSOP56 Y
PCA8546BTT
-
-
-
176 -
-
-
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 95
SPI
TSSOP56 Y
1.8 to 5.5 2.5 to 9
60 to
300[1]
Y
40 to 95
I2C
TQFP64
Y
60 to
300[1]
Y
Y
40 to 95
SPI
TQFP64
Y
N
N
40 to 85
I2C
LQFP80
N
N
40 to 95
I2C
LQFP80
Y
Y
40 to 105
I2C
LQFP80
Y
TSSOP56 N
-
-
-
Rev. 2 — 25 September 2014
All information provided in this document is subject to legal disclaimers.
PCA8547BHT
44
88
176 -
-
-
1.8 to 5.5 2.5 to 9
PCF85134HL
60
120 180 240 -
-
-
1.8 to 5.5 2.5 to 6.5 82
PCA85134H
PCA8543AHL
60
60
-
176 -
120 180 240 120 -
240 -
-
-
1.8 to 5.5 2.5 to 8
2.5 to 5.5 2.5 to 9
82
Y
N
60 to
300[1]
300[1]
Y
PCF8545ATT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 5.5 60 to
N
N
40 to 85
I2C
PCF8545BTT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 5.5 60 to 300[1]
N
N
40 to 85
SPI
TSSOP56 N
PCF8536AT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 85
I2C
TSSOP56 N
1.8 to 5.5 2.5 to 9
60 to
300[1]
N
N
40 to 85
SPI
TSSOP56 N
300[1]
TSSOP56 Y
PCF8536BT
-
-
-
176 252 320 -
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 9
60 to
N
N
40 to 95
PCA8536BT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 95
SPI
TSSOP56 Y
PCF8537AH
44
88
-
176 276 352 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
Y
Y
40 to 85
I2C
TQFP64
N
1.8 to 5.5 2.5 to 9
60 to
300[1]
Y
Y
40 to 85
SPI
TQFP64
N
300[1]
Y
Y
40 to 95
I2C
TQFP64
Y
Y
Y
40 to 95
SPI
TQFP64
Y
Y
40 to 105
I2C
LQFP80
Y
Y
40 to 105
I2C
Bare die
Y
PCF8537BH
44
88
-
176 276 352 -
93 of 103
© NXP Semiconductors N.V. 2014. All rights reserved.
PCA8537AH
44
88
-
176 276 352 -
1.8 to 5.5 2.5 to 9
60 to
PCA8537BH
44
88
-
176 276 352 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
2.5 to 5.5 2.5 to 9
60 to
300[1]
60 to
300[1]
PCA9620H
PCA9620U
60
60
120 120 -
240 320 480 240 320 480 -
2.5 to 5.5 2.5 to 9
Y
Y
PCF8576DU
40
80
120 160 -
-
-
1.8 to 5.5 2.5 to 6.5 77
N
N
40 to 85
I2C
Bare die
N
PCF8576EUG
40
80
120 160 -
-
-
1.8 to 5.5 2.5 to 6.5 77
N
N
40 to 85
I2C
Bare die
N
N
40 to 105
I2C
Bare die
Y
N
40 to 85
I2C
Bare die
N
N
40 to 95
I2C
Bare die
Y
PCA8576FUG
PCF85133U
PCA85133U
40
80
80
80
120 160 -
160 240 320 160 240 320 -
-
-
1.8 to 5.5 2.5 to 8
200
1.8 to 5.5 2.5 to 6.5 82,
110[2]
1.8 to 5.5 2.5 to 8
110[2]
82,
N
N
N
PCA8530
PCA8536AT
I2C
Automotive 102 x 4 Chip-On-Glass LCD segment driver
PCA8553DTT
88
1:9
VLCD (V) VLCD (V)
Tamb (C)
charge temperature
pump
compensat.
1:2 1:3
44
1:6 1:8
VLCD (V)
1:1
PCA8547AHT
1:4
VDD (V)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Selection of LCD segment drivers …continued
Type name
Number of elements at MUX
ffr (Hz)
VLCD (V) VLCD (V)
Tamb (C)
charge temperature
pump
compensat.
AECQ100
PCA85233UG
80
160 240 320 -
-
-
1.8 to 5.5 2.5 to 8
150, 220[2]
N
N
40 to 105 I2C
Bare die
Y
PCF85132U
160 320 480 640 -
-
-
1.8 to 5.5 1.8 to 8
60 to 90[1]
N
N
40 to 85
I2C
Bare die
N
Y
40 to 105
I2C
Bare die
Y
N
40 to 95
I2C
Bare die
Y
N
N
40 to 95
I2C
Bare die
Y
Y
Y
40 to 85
I2C / SPI
Bare die
N
Y
40 to 105
I2C
Bare die
Y
PCA85132U
408 -
160 320 480 640 -
PCA85232U
160 320 480 640 -
PCF8538UG
102 204 -
PCA8538UG
102 204 -
Software programmable.
[2]
Hardware selectable.
-
-
2.5 to 5.5 4 to 12
1.8 to 5.5 1.8 to 8
1.8 to 5.5 1.8 to 8
45 to
300[1]
60 to
90[1]
117 to
176[1]
408 612 816 918 2.5 to 5.5 4 to 12
45 to 300[1]
408 612 816 918 2.5 to 5.5 4 to 12
300[1]
45 to
Y
N
Y
/ SPI
/ SPI
PCA8530
94 of 103
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[1]
-
1:9
Interface Package
1:2 1:3
102 204 -
1:6 1:8
VLCD (V)
1:1
PCA8530DUG
1:4
VDD (V)
NXP Semiconductors
PCA8530
Product data sheet
Table 58.
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
21. Abbreviations
Table 59.
Acronym
PCA8530
Product data sheet
Abbreviations
Description
AEC
Automotive Electronics Council
COG
Chip-On-Glass
DC
Direct Current
EPROM
Erasable Programmable Read-Only Memory
ESD
ElectroStatic Discharge
HBM
Human Body Model
I2C
Inter-Integrated Circuit bus
IC
Integrated Circuit
ITO
Indium Tin Oxide
LCD
Liquid Crystal Display
LSB
Least Significant Bit
MCU
Microcontroller Unit
MM
Machine Model
MSB
Most Significant Bit
MSL
Moisture Sensitivity Level
MUX
Multiplexer
OTP
One Time Programmable
POR
Power-On Reset
RC
Resistance-Capacitance
RAM
Random Access Memory
RMS
Root Mean Square
SCL
Serial CLock line
SDA
Serial DAta line
SMD
Surface Mount Device
SPI
Serial Peripheral Interface
VA
Vertical Alignment
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22. References
[1]
AN10170 — Design guidelines for COG modules with NXP monochrome LCD
drivers
[2]
AN10439 — Wafer Level Chip Size Package
[3]
AN10853 — ESD and EMC sensitivity of IC
[4]
AN10706 — Handling bare die
[5]
AN11267 — EMC and system level ESD design guidelines for LCD drivers
[6]
IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[7]
IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[8]
JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[9]
JESD78 — IC Latch-Up Test
[10] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[11] R_10015 — Chip-On-Glass (COG) – a cost-effective and reliable technology for
LCD displays, White Paper
[12] SNV-FA-01-02 — Marking Formats Integrated Circuits
[13] UM10204 — I2C-bus specification and user manual
[14] UM10569 — Store and transport requirements
PCA8530
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
23. Revision history
Table 60.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA8530 v.2
20140925
Product data sheet
-
PCA8530 v.1
Modifications:
PCA8530 v.1
PCA8530
Product data sheet
•
Adjusted Figure 13, Figure 56, Section 8.9 and Section 8.10
20140815
Product data sheet
-
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-
© NXP Semiconductors N.V. 2014. All rights reserved.
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
24. Legal information
24.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
24.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
24.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA8530
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 25 September 2014
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98 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
24.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
25. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCA8530
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 25 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
99 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
26. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .3
Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6
Commands of PCA8530 . . . . . . . . . . . . . . . . . .8
Initialize command bit description . . . . . . . . . .10
OTP-refresh - OTP-refresh command bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Device-address - device address command
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 11
SYNC1_pin - SYNC1 pin configuration
command bit description. . . . . . . . . . . . . . . . . . 11
Clock-out-ctrl - CLK pin input/output switch
command bit description . . . . . . . . . . . . . . . . .12
Read-select - status read select command
bit description . . . . . . . . . . . . . . . . . . . . . . . . .12
Status-readout - status and temperature read
command bit description . . . . . . . . . . . . . . . . .13
Clear-reset-flag - Clear-reset-flag command
bit description . . . . . . . . . . . . . . . . . . . . . . . . .14
Charge-pump-ctrl - charge pump control
command bit description . . . . . . . . . . . . . . . . .15
Set-VLCD - Set-VLCD command bit description .15
Set-bias-mode - set bias mode command
bit description . . . . . . . . . . . . . . . . . . . . . . . . .16
Temperature-ctrl - temperature measurement
control command bit description . . . . . . . . . . .17
TC-set - VLCD temperature compensation
set command bit description . . . . . . . . . . . . . .18
TC-slope - VLCD temperature compensation
slope command bit description . . . . . . . . . . . .19
Set-MUX-mode - set multiplex drive mode
command bit description . . . . . . . . . . . . . . . . .20
Inversion-mode - inversion mode command
bit description . . . . . . . . . . . . . . . . . . . . . . . . .20
Display-ctrl - display on and off switch c
ommand bit description . . . . . . . . . . . . . . . . . .21
Frame-frequency - frame frequency select
command bit description . . . . . . . . . . . . . . . . .22
Clock and frame frequency values . . . . . . . . .23
Write-display-data - write display data
command bit description . . . . . . . . . . . . . . . . .24
Input-bank-select - input bank select
command bit description . . . . . . . . . . . . . . . . .24
Output-bank-select - output bank select
command bit description . . . . . . . . . . . . . . . . .25
Data-pointer - set data pointer command
bit description . . . . . . . . . . . . . . . . . . . . . . . . .25
Selection of possible display configurations . . .32
Parameters of VLCD generation . . . . . . . . . . . .35
Output resistance of the charge pump . . . . . . .37
Temperature regions . . . . . . . . . . . . . . . . . . . .42
Temperature coefficients. . . . . . . . . . . . . . . . . .43
Calculation of the temperature compensated
value VT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
LCD drive modes: summary of characteristics 44
PCA8530
Product data sheet
Table 36. Mapping of output pins and corresponding
output signals with respect to the multiplex
driving mode . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 37. Layout topology of output pins and
corresponding output signals with respect to
the multiplex driving mode . . . . . . . . . . . . . . . 50
Table 38. Bit scheme used to illustrate the RAM filling
patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 39. RAM filling in static drive mode . . . . . . . . . . . . 52
Table 40. RAM filling in 1:2 multiplex drive mode . . . . . . 52
Table 41. RAM filling in 1:4 multiplex drive mode . . . . . . 53
Table 42. Control byte description . . . . . . . . . . . . . . . . . 56
Table 43. I2C slave address byte . . . . . . . . . . . . . . . . . . . 59
Table 44. R/W-bit description. . . . . . . . . . . . . . . . . . . . . . 59
Table 45. Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 46. Subaddress byte definition. . . . . . . . . . . . . . . . 61
Table 47. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 48. Static characteristics . . . . . . . . . . . . . . . . . . . . 66
Table 49. General dynamic characteristics . . . . . . . . . . . 73
Table 50. I2C-bus timing characteristic . . . . . . . . . . . . . . 74
Table 51. SPI-bus timing characteristics . . . . . . . . . . . . . 75
Table 52. Addressing cascaded PCA8530 . . . . . . . . . . . 80
Table 53. Bump locations of PCA8530DUG . . . . . . . . . . 86
Table 54. Dimensions of PCA8530DUG . . . . . . . . . . . . 89
Table 55. Alignment marking . . . . . . . . . . . . . . . . . . . . . . 90
Table 56. Gold bump hardness . . . . . . . . . . . . . . . . . . . . 90
Table 57. Description of tray details. . . . . . . . . . . . . . . . . 92
Table 58. Selection of LCD segment drivers . . . . . . . . . 93
Table 59. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 60. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 97
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 25 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
100 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
27. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Fig 27.
Fig 28.
Block diagram of PCA8530 . . . . . . . . . . . . . . . . . .4
Pinning diagram of PCA8530DUG. . . . . . . . . . . . .5
Recommended start-up sequence when using the
internal charge pump and the internal
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Recommended start-up sequence when using an
external supplied VLCD and the internal
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Recommended start-up sequence when using the
internal charge pump and an external
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Recommended start-up sequence when using an
external supplied VLCD and an external
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Recommended power-down sequence for minimum
power-down current when using the internal
charge pump and the internal clock signal. . . . . .29
Recommended power-down sequence when using
an external supplied VLCD and the internal
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Recommended power-down sequence when using
the internal charge pump and an external
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Recommended power-down sequence when using
an external supplied VLCD and an external
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Example of display types suitable for PCA8530 .32
Typical system configuration if using the internal
VLCD generation and I2C-bus . . . . . . . . . . . . . . . .33
Typical system configuration if using the
external VLCD and SPI-bus . . . . . . . . . . . . . . . . .33
VLCD generation including temperature
compensation . . . . . . . . . . . . . . . . . . . . . . . . . . .35
VLCD programming of PCA8530 (assuming
VT[8:0] = 0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Charge pump model (used to characterize
the driving strength) . . . . . . . . . . . . . . . . . . . . . . .36
Charge pump driving capability with
VDD2 = 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Charge pump driving capability with
VDD2 = 5.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
VLCD with respect to Iload at VDD2 = 3 V . . . . . . . .39
VLCD with respect to Iload at VDD2 = 5 V . . . . . . . .39
Temperature measurement block with digital
temperature filter . . . . . . . . . . . . . . . . . . . . . . . . .40
Temperature measurement delay . . . . . . . . . . . .41
Example of segmented temperature coefficients.42
Electro-optical characteristic: relative transmission
curve of the liquid. . . . . . . . . . . . . . . . . . . . . . . . .45
Static drive mode waveforms, line inversion mode
(n = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Waveforms for the 1:2 multiplex drive mode,
1⁄ bias, line inversion mode (n = 1) . . . . . . . . . . .47
2
Waveforms for the 1:2 multiplex drive mode,
1⁄ bias, line inversion mode (n = 1) . . . . . . . . . . .48
3
Waveforms for the 1:4 multiplex drive mode,
PCA8530
Product data sheet
1⁄
3
bias, line inversion mode (n = 1). . . . . . . . . . . 49
Fig 29. Display RAM bitmap and bank definition . . . . . . 53
Fig 30. Bank selection in multiplex drive mode 1:2 . . . . . 54
Fig 31. Example of the Bank-select command with
multiplex drive mode 1:2 . . . . . . . . . . . . . . . . . . . 54
Fig 32. Control byte format . . . . . . . . . . . . . . . . . . . . . . . 56
Fig 33. I2C-bus - bit transfer . . . . . . . . . . . . . . . . . . . . . . 57
Fig 34. I2C-bus - definition of START and STOP
conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Fig 35. I2C-bus - system configuration . . . . . . . . . . . . . . 58
Fig 36. Acknowledgement on the I2C-bus. . . . . . . . . . . . 59
Fig 37. I2C-bus protocol - write mode . . . . . . . . . . . . . . . 60
Fig 38. I2C-bus protocol - read mode . . . . . . . . . . . . . . . 60
Fig 39. SPI-bus protocol - data transfer overview . . . . . . 61
Fig 40. SPI-bus example. . . . . . . . . . . . . . . . . . . . . . . . . 62
Fig 41. SPI-bus protocol - read example. . . . . . . . . . . . . 62
Fig 42. SPI-bus protocol - write example . . . . . . . . . . . . 62
Fig 43. Device protection diagram . . . . . . . . . . . . . . . . . 63
Fig 44. Typical IDD1 with respect to temperature . . . . . . . 69
Fig 45. Typical IDD2 with respect to temperature . . . . . . . 69
Fig 46. Typical IDD3 with respect to temperature . . . . . . . 70
Fig 47. Typical IDD(LCD) with respect to temperature . . . . 70
Fig 48. Typical VLCD variation with respect to
temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Fig 49. Typical frame frequency variation with respect to
temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Fig 50. Measurement temperature variation with
respect to temperature . . . . . . . . . . . . . . . . . . . . 72
Fig 51. Driver timing waveforms . . . . . . . . . . . . . . . . . . . 73
Fig 52. I2C-bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Fig 53. SPI-bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Fig 54. Recommended ITO connections for the I2C
interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Fig 55. Recommended ITO connections for the SPI
interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Fig 56. Cascaded configuration with two PCA8530
with external VLCD and internal clock . . . . . . . . . 81
Fig 57. Cascaded configuration with two PCA8530
with internal VLCD and external clock . . . . . . . . . 82
Fig 58. Cascade configuration for data reading . . . . . . . 84
Fig 59. Bare die outline of PCA8530DUG. . . . . . . . . . . . 85
Fig 60. Alignment marks . . . . . . . . . . . . . . . . . . . . . . . . . 89
Fig 61. Tray details of PCA8530DUG . . . . . . . . . . . . . . . 91
Fig 62. Die alignment in the tray . . . . . . . . . . . . . . . . . . . 92
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 25 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
101 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
28. Contents
1
2
3
4
4.1
5
6
7
7.1
7.2
8
8.1
8.2
8.2.1
8.2.1.1
8.2.1.2
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.3
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 8
Commands of PCA8530 . . . . . . . . . . . . . . . . . . 8
General control commands . . . . . . . . . . . . . . 10
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Command: Initialize . . . . . . . . . . . . . . . . . . . . 10
RST pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Command: OTP-refresh . . . . . . . . . . . . . . . . . 10
Command: Device-address . . . . . . . . . . . . . . 11
Command: SYNC1_pin . . . . . . . . . . . . . . . . . 11
Command: Clock-out-ctrl . . . . . . . . . . . . . . . . 12
Command: Read-select . . . . . . . . . . . . . . . . . 12
Command: Status-readout . . . . . . . . . . . . . . . 13
Command: Clear-reset-flag . . . . . . . . . . . . . . 14
Charge pump and LCD bias control
commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.3.1
Command: Charge-pump-ctrl . . . . . . . . . . . . . 15
8.3.2
Command: Set-VLCD . . . . . . . . . . . . . . . . . . . . 15
8.3.3
Command: Set-bias-mode . . . . . . . . . . . . . . . 16
8.4
Temperature compensation control
commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.4.1
Command: Temperature-ctrl . . . . . . . . . . . . . . 17
8.4.2
Command: TC-set . . . . . . . . . . . . . . . . . . . . . 18
8.4.3
Command: TC-slope . . . . . . . . . . . . . . . . . . . 19
8.5
Display control commands . . . . . . . . . . . . . . . 20
8.5.1
Command: Set-MUX-mode . . . . . . . . . . . . . . 20
8.5.2
Command: Inversion-mode . . . . . . . . . . . . . . 20
8.5.2.1
Line inversion mode (driving scheme A). . . . . 20
8.5.2.2
Frame inversion mode (driving scheme B) . . . 21
8.5.3
Command: Display-ctrl . . . . . . . . . . . . . . . . . . 21
8.6
Clock and frame frequency command . . . . . . 22
8.6.1
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.6.2
External clock . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.6.3
Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.6.4
Command: Frame-frequency . . . . . . . . . . . . . 22
8.7
Display RAM commands . . . . . . . . . . . . . . . . 24
8.7.1
Command: Write-display-data . . . . . . . . . . . . 24
8.7.2
8.7.2.1
8.7.2.2
8.7.3
8.8
8.8.1
8.8.2
8.8.3
8.9
8.10
8.10.1
8.10.2
8.10.3
8.10.3.1
8.10.3.2
8.10.4
Bank select commands . . . . . . . . . . . . . . . . .
Command: Input-bank-select. . . . . . . . . . . . .
Command: Output-bank-select . . . . . . . . . . .
Command: Data-pointer. . . . . . . . . . . . . . . . .
Start-up and shut-down . . . . . . . . . . . . . . . . .
Power-On. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended start-up sequences . . . . . . . .
Recommended power-down sequences . . . .
Possible display configurations . . . . . . . . . . .
LCD voltage . . . . . . . . . . . . . . . . . . . . . . . . . .
VLCD pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External VLCD supply . . . . . . . . . . . . . . . . . . .
Internal VLCD generation . . . . . . . . . . . . . . . .
VLCD programming . . . . . . . . . . . . . . . . . . . . .
VLCD driving capability . . . . . . . . . . . . . . . . . .
Temperature measurement and
temperature compensation of VLCD . . . . . . .
8.10.4.1 Temperature readout . . . . . . . . . . . . . . . . . . .
8.10.4.2 Temperature adjustment of the VLCD . . . . . . .
8.10.5
LCD voltage selector . . . . . . . . . . . . . . . . . . .
8.10.5.1 Electro-optical performance . . . . . . . . . . . . . .
8.10.6
LCD drive mode waveforms. . . . . . . . . . . . . .
8.10.6.1 Static drive mode . . . . . . . . . . . . . . . . . . . . . .
8.10.6.2 1:2 Multiplex drive mode . . . . . . . . . . . . . . . .
8.10.6.3 1:4 Multiplex drive mode . . . . . . . . . . . . . . . .
8.11
Backplane outputs . . . . . . . . . . . . . . . . . . . . .
8.11.1
Driving strength on the backplanes . . . . . . . .
8.12
Segment outputs . . . . . . . . . . . . . . . . . . . . . .
8.13
Display register . . . . . . . . . . . . . . . . . . . . . . .
8.14
Display RAM . . . . . . . . . . . . . . . . . . . . . . . . .
8.14.1
Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . .
8.14.1.1 Data pointer in cascade configuration . . . . . .
8.14.2
RAM filling . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.14.2.1 RAM filling in static drive mode . . . . . . . . . . .
8.14.2.2 RAM filling in 1:2 multiplex drive mode . . . . .
8.14.2.3 RAM filling in 1:4 multiplex drive mode . . . . .
8.14.3
Bank selection . . . . . . . . . . . . . . . . . . . . . . . .
8.14.3.1 Input-bank-select . . . . . . . . . . . . . . . . . . . . . .
8.14.3.2 Output-bank-select. . . . . . . . . . . . . . . . . . . . .
9
Bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . .
9.1
Control byte and register selection . . . . . . . .
9.2
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.1
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.2
START and STOP conditions. . . . . . . . . . . . .
9.2.3
System configuration . . . . . . . . . . . . . . . . . . .
9.2.4
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.5
I2C-bus controller . . . . . . . . . . . . . . . . . . . . . .
9.2.6
Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
24
25
25
26
26
26
29
32
34
34
34
34
34
36
40
40
41
44
45
46
46
47
49
50
50
50
50
51
51
51
52
52
52
53
53
54
54
56
56
57
57
57
58
58
59
59
continued >>
PCA8530
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 25 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
102 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
I2C-bus slave address . . . . . . . . . . . . . . . . . . 59
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 60
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Data transmission . . . . . . . . . . . . . . . . . . . . . . 61
Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 63
Safety notes . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 65
Static characteristics. . . . . . . . . . . . . . . . . . . . 66
Dynamic characteristics . . . . . . . . . . . . . . . . . 73
General dynamic characteristics. . . . . . . . . . . 73
I2C-bus timing characteristics . . . . . . . . . . . . . 74
SPI-bus timing characteristics . . . . . . . . . . . . 75
Application information. . . . . . . . . . . . . . . . . . 77
ITO layout recommendations for ESD/EMC
robustness in COG applications . . . . . . . . . . . 77
15.2
Cascaded operation . . . . . . . . . . . . . . . . . . . . 80
15.2.1
Wiring backplane and segment outputs . . . . . 80
15.2.2
Device synchronization. . . . . . . . . . . . . . . . . . 82
15.2.3
Display data . . . . . . . . . . . . . . . . . . . . . . . . . . 83
15.2.4
Data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
16
Test information . . . . . . . . . . . . . . . . . . . . . . . . 84
16.1
Quality information . . . . . . . . . . . . . . . . . . . . . 84
17
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 85
18
Handling information. . . . . . . . . . . . . . . . . . . . 90
19
Packing information . . . . . . . . . . . . . . . . . . . . 91
19.1
Tray information . . . . . . . . . . . . . . . . . . . . . . . 91
20
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
20.1
LCD segment driver selection. . . . . . . . . . . . . 93
21
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 95
22
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 97
24
Legal information. . . . . . . . . . . . . . . . . . . . . . . 98
24.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 98
24.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
24.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
24.4
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 99
25
Contact information. . . . . . . . . . . . . . . . . . . . . 99
26
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
27
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
28
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
9.2.7
9.2.8
9.3
9.3.1
10
11
12
13
14
14.1
14.2
14.3
15
15.1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 25 September 2014
Document identifier: PCA8530