PCA9620 Universal LCD driver for low multiplex rates Rev. 1 — 9 December 2010 Product data sheet 1. General description The PCA9620 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to eight backplanes, 60 segments, and up to 480 elements. The PCA9620 is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized using a display RAM with auto-incremented addressing and display memory switching. The PCA9620 features an internal charge pump with internal capacitors for on-chip generation of the LCD driving voltages. AEC Q100 grade 2 compliant for automotive applications. 2. Features and benefits Low power consumption Extended operating temperature range from −40 °C to +105 °C 60 segments and 8 backplanes allowing to drive: up to 60 7-segment alphanumeric characters up to 30 14-segment alphanumeric characters any graphics of up to 480 elements 480 bit RAM for display data storage Selectable backplane drive configuration: static, 2, 4, 6, or 8 backplane multiplexing Programmable internal charge pump for on-chip LCD voltage generation up to 3 × VDD2 400 kHz I2C-bus interface Selectable linear temperature compensation of VLCD Selectable display bias configuration Wide range for digital and analog power supply: from 2.5 V to 5.5 V Wide LCD supply range: from 2.5 V for low threshold LCDs and up to 9.0 V for high threshold (automobile) twisted nematic LCDs Display memory bank switching in static, duplex, and quadruplex drive modes Programmable frame frequency in steps of 10 Hz in the range of 60 Hz to 300 Hz; factory calibrated with a tolerance of ±15 % covering the whole temperature and voltage range Selectable inversion scheme for LCD driving waveforms: frame or line inversion Integrated temperature sensor with temperature readout On chip calibration of internal oscillator frequency and VLCD 1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 15 on page 65. PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 3. Ordering information Table 1. Ordering information Type number Package PCA9620H Name Description Version LQFP80 plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm SOT315-1 4. Marking Table 2. Marking codes Type number Marking code PCA9620H PCA9620H/Q900 5. Block diagram VLCD S0 to S59 BP0 to BP7 60 VDD2 BACKPLANE OUTPUTS DISPLAY SEGMENT OUTPUTS LCD VOLTAGE SELECTOR CHARGE PUMP(1) (VOLTAGE MULTIPLIER) DISPLAY REGISTER DISPLAY CONTROL OUTPUT BANK SELECT LCD BIAS GENERATOR VSS DISPLAY RAM CLK SCL SDA TEMPERATURE SENSOR CLOCK SELECT AND TIMING OSCILLATOR POWER-ON RESET INPUT FILTERS PCA9620 COMMAND DECODER WRITE DATA CONTROL DATA POINTER, AUTO INCREMENT I2C-BUS CONTROLLER 013aaa246 A0 A1 VDD1 T1 T2 T3 (1) The charge pump can generate a maximum output voltage of 3 × VDD2. Fig 1. Block diagram of PCA9620 PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 2 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 6. Pinning information 61 S0 62 S1 63 S2 64 S3 65 S4 66 S5 67 S6 68 S7 69 S8 70 S9 71 S10 72 S11 73 S12 74 S13 75 S14 76 S15 77 S16 78 S17 79 S18 80 S19 6.1 Pinning S20 1 60 SDA S21 2 59 SCL S22 3 58 A1 S23 4 57 A0 S24 5 56 CLK S25 6 55 T3 S26 7 54 T2 S27 8 53 T1 S28 9 52 VSS S29 10 51 VDD1 PCA9620 S30 11 50 VDD2 S59 40 S58 39 S57 38 S56 37 S55 36 S54 35 S53 34 S52 33 S51 32 S50 31 S49 30 41 BP0 S48 29 42 BP1 S39 20 S47 28 43 BP2 S38 19 S46 27 44 BP3 S37 18 S45 26 45 BP4 S36 17 S44 25 46 BP5 S35 16 S43 24 47 BP6 S34 15 S42 23 48 BP7 S33 14 S41 22 49 VLCD S32 13 S40 21 S31 12 013aaa244 Top view. For mechanical details, see Figure 57 on page 61. Fig 2. Pin configuration for LQFP80 (PCA9620H) PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 3 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 6.2 Pin description Table 3. Pin Type Description S0 to S59 61 to 80 and 1 to 40 output LCD segment BP0 to BP7 41 to 48 output LCD backplane VLCD 49 supply/output[1] LCD supply voltage VDD2 50 supply supply voltage 2 (charge pump) VDD1 51 supply supply voltage 1 (analog and digital) VSS 52 supply ground supply voltage T1 to T3 53 to 55 input test pins; must be tied to VSS in applications CLK 56 input/output internal oscillator output, external oscillator input A0, A1 57, 58 input I2C-bus slave address selection bit SCL 59 input I2C-bus serial clock SDA 60 input/output I2C-bus serial data [1] PCA9620 Product data sheet Pin description Symbol When the internal VLCD generation is used, this pin drives the VLCD voltage. In this case pin VLCD is an output. When the external supply is requested then pin VLCD is an input and VLCD can be supplied to it. In this case the internal charge pump must be disabled (see Table 8 on page 7). All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 4 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 7. Functional description The PCA9620 is a versatile peripheral device designed to interface any microprocessor or microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to 480 elements. 7.1 Commands of PCA9620 The PCA9620 is controlled by 22 commands, which are defined in Table 4. Any other combinations of operation code bits that are not mentioned in this document may lead to undesired operation modes of PCA9620. Table 4. Commands of PCA9620 Command name initialize Bits Reference 7 6 5 4 3 2 1 0 0 0 1 1 1 0 1 0 Section 7.1.1 OTP-refresh 1 1 0 1 0 0 0 0 Section 7.1.2 oscillator-ctrl 1 1 0 0 1 1 COE OSC Section 7.1.3 charge-pump-ctrl 1 1 0 0 0 0 CPE CPC Section 7.1.4 temp-msr-ctrl 1 1 0 0 1 0 TCE TME Section 7.1.5 temp-comp-SLA 0 0 0 1 1 SLA[2:0] temp-comp-SLB 0 0 1 0 0 SLB[2:0] temp-comp-SLC 0 0 1 0 1 SLC[2:0] temp-comp-SLD 0 0 1 1 0 SLD[2:0] Table 29 set-VPR-MSB 0 1 0 0 VPR[7:4] set-VPR-LSB 0 1 0 1 VPR[3:0] Section 7.1.6 display-enable 0 0 1 1 1 0 set-MUX-mode 0 0 0 0 0 M[2:0] set-bias-mode 1 1 0 0 0 1 load-data-pointer 1 0 P[5:0] frame-frequency 0 1 1 F[4:0] input-bank-select 0 0 0 0 1 IB[2:0] output-bank-select 0 0 0 1 0 OB[2:0] write-RAM-data B[7:0] Section 7.1.13 temp-read TD[7:0] Section 7.1.14, Section 7.4.7 invmode_CPF_ctrl 1 1 0 1 0 1 LF CPF Section 7.1.15 temp-filter 1 1 0 1 0 0 1 TFE Section 7.1.16 0 E Section 7.1.7 Section 7.1.8 B[1:0] Section 7.1.9 Section 7.1.10 Section 7.1.11 Section 7.1.12.1 7.1.1 Command: initialize This command generates a chip wide reset which resets all command values to their default values (see Table 25 on page 15). It must be sent to the PCA9620 after power-on. After this command is sent, it is possible to send additional commands without the need to re-initialize the interface. Reset takes 100 ns to complete. For further information see Section 7.3 on page 14. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 5 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates Table 5. Initialize - initialize command bit description Bit Symbol Value Description 7 to 0 - 00111010 fixed value 7.1.2 Command: OTP-refresh During production and testing of the device, each IC is calibrated in order to achieve the specified accuracy of VLCD, the frame frequency, and the temperature measurement. This calibration is performed on EPROM cells called One Time Programmable (OTP) cells. These cells are being read by the device at power-on, after a reset, and every time when the initialize command or the OTP-refresh command is sent. This command will take approximately 10 ms to finish. Table 6. OTP-refresh - OTP-refresh command bit description Bit Symbol Value Description 7 to 0 - 11010000 fixed value 7.1.3 Command: oscillator-ctrl The oscillator-ctrl command switches between internal and external oscillator and enables or disables pin CLK. Table 7. Oscillator-ctrl - oscillator control command bit description For further information, see Section 7.5 on page 38. Bit Symbol Value Description 7 to 2 - 110011 fixed value 1 COE 0 [1] PCA9620 Product data sheet control pin CLK 0[1] clock signal not available on pin CLK; pin CLK is in 3-state and may be left floating 1 clock signal available on pin CLK OSC oscillator source 0[1] internal oscillator running 1 external oscillator used; pin CLK becomes an input Default value. All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 6 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 7.1.4 Command: charge-pump-ctrl The charge-pump-ctrl command enables or disables the internal VLCD generation and controls the charge pump voltage multiplier setting. Table 8. Charge-pump-ctrl - charge pump control command bit description Bit Symbol Value Description 7 to 2 - 110000 fixed value 1 CPE 0 [1] charge pump switch 0[1] charge pump disabled; no internal VLCD generation; external supply of VLCD 1 charge pump enabled CPC charge pump voltage multiplier setting 0[1] VLCD = 2 × VDD2 1 VLCD = 3 × VDD2 Default value. 7.1.5 Command: temp-msr-ctrl The temp-msr-ctrl command enables or disables the temperature measurement block and the temperature compensation of VLCD. Table 9. Temp-msr-ctrl - temperature measurement control command bit description For further information, see Section 7.4.8 on page 36. Bit Symbol Value Description 7 to 2 - 110010 fixed value 1 TCE temperature compensation switch 0 no temperature compensation of VLCD possible 1[1] 0 temperature compensation of VLCD possible TME temperature measurement switch 0 temperature measurement disabled; 1[1] temperature measurement enabled; no temperature readout possible temperature readout possible [1] Default value. 7.1.6 Command: set-VPR-MSB and set-VPR-LSB With these two instructions it is possible to set the target VLCD voltage for the internal charge pump, see Section 7.4.3 on page 31. Table 10. Bit Symbol Value Description 7 to 4 - 0100 fixed value VPR[7:4] 0000[1] 3 to 0 [1] PCA9620 Product data sheet Set-VPR-MSB - set VPR MSB command bit description to 1111 the four most significant bits of VPR[7:0] Default value. All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 7 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates Table 11. Set-VPR-LSB - set VPR LSB command bit description Bit Symbol Value Description 7 to 4 - 0101 fixed value VPR[3:0] 0000[1] 3 to 0 [1] to 1111 the four least significant bits of VPR[7:0] Default value. 7.1.7 Command: display-enable Table 12. Display-enable - display enable command bit description Bit Symbol Value Description 7 to 1 - 0011100 fixed value 0 E 0[1] display disabled; backplane and segment outputs are internally connected to VSS 1 display enabled [1] Default value. 7.1.8 Command: set-MUX-mode Table 13. Set-MUX-mode - set multiplex drive mode command bit description Bit Symbol Value Description 7 to 3 - 00000 fixed value 2 to 0 M[2:0] 000[1], 011, 110, 111 1:8 multiplex drive mode: 8 backplanes 001 static drive mode: 1 backplane 010 1:2 multiplex drive mode: 2 backplanes 100 1:4 multiplex drive mode: 4 backplanes 101 1:6 multiplex drive mode: 6 backplanes [1] Default value. 7.1.9 Command: set-bias-mode Table 14. Set-bias-mode - set bias mode command bit description Bit Symbol Value Description 7 to 2 - 110001 fixed value B[1:0] 00[1], 1⁄ 4 bias 11 1⁄ 3 bias 10 1⁄ 2 bias 1 to 0 [1] 01 Default value. 7.1.10 Command: load-data-pointer The load-data-pointer command defines one of the 60 display RAM addresses where the following display data will be sent to. For further information, see Section 7.9.1 on page 41. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 8 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates Table 15. Load-data-pointer - load data pointer command bit description Bit Symbol Value Description 7 to 6 - 10 fixed value 5 to 0 P[5:0] 000000 to 111111 6-bit binary value of 0 to 59 7.1.11 Command: frame-frequency With the frame-frequency command the frame frequency and the output clock frequency can be configured. Table 16. Bit Symbol Value Description 7 to 5 - 011 fixed value 4 to 0 F[4:0] see Table 17 nominal frame frequency (Hz) Table 17. Product data sheet Frame frequency values F[4:0] Nominal frame frequency, ffr (Hz)[1] Resultant oscillator frequency, fosc (Hz) Duty cycle (%)[2] 00000 60 2880 20 : 80 00001 70 3360 7 : 93 00010 80 3840 47 : 53 00011 91 4368 40 : 60 00100 100 4800 33 : 67 00101 109 5232 27 : 73 00110 120 5760 20 : 80 00111 129.7 6226 13 : 87 01000 141.2 6778 5 : 95 01001 150 7200 50 : 50 01010 160 7680 47 : 53 01011 171.4 8227 43 : 57 01100 177.8 8534 41 : 59 01101 192 9216 36 : 64 01110[3] 200 9600 33 : 67 01111 208.7 10018 30 : 70 10000 218.2 10474 27 : 73 10001 228.6 10973 23 : 77 10010 240 11520 20 : 80 10011 252.6 12125 16 : 84 10100, 10101 266.7 12802 10 : 90 10110, 10111 282.4 13555 5 : 95 11000 to 11111 300 14400 50 : 50 [1] PCA9620 Frame frequency - frame frequency and output clock frequency command bit description Nominal frame frequency calculated for the default clock frequency of 9600 Hz. [2] Duty cycle definition: % HIGH-level time : % LOW-level time. [3] Default value. All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 9 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 7.1.12 Bank select commands For multiplex drive modes 1:4, 1:2 and static drive mode, it is possible to write data to one area of the RAM whilst displaying from another. These areas are named as RAM banks. Input and output banks can be set independently from one another with the input-bank-select and the output-bank-select command. For further information see Section 7.9.2 on page 46. 7.1.12.1 Command: input-bank-select Input-bank-select - input bank select command bit description[1] Table 18. 7.1.12.2 Bit Symbol Value Description 7 to 3 - 00001 fixed value 2 to 0 IB[2:0] Product data sheet static drive mode 1:2 drive mode 1:4 drive mode 000[2] bank 0: RAM-row 0 001 bank 1: RAM-row 1 bank 0: RAM-rows 0 and 1 bank 0: RAM-rows 0, 1, 2, and 3 010 bank 2: RAM-row 2 011 bank 3: RAM-row 3 100 bank 4: RAM-row 4 101 bank 5: RAM-row 5 110 bank 6: RAM-row 6 111 bank 7: RAM-row 7 [1] Not applicable for multiplex drive mode 1:6 and 1:8. [2] Default value. bank 2: RAM-rows 2 and 3 bank 4: RAM-rows 4 and 5 bank 4: RAM-rows 4, 5, 6, and 7 bank 6: RAM-rows 6 and 7 Command: output-bank-select Output-bank-select - output bank select command bit description[1] Table 19. PCA9620 selects RAM bank to write to Bit Symbol Value Description 7 to 3 - 00010 fixed value 2 to 0 OB[2:0] selects RAM bank to read from to the LCD static drive mode 1:2 drive mode 1:4 drive mode 000[2] bank 0: RAM-row 0 001 bank 1: RAM-row 1 bank 0: RAM-rows 0 and 1 bank 0: RAM-rows 0, 1, 2, and 3 010 bank 2: RAM-row 2 011 bank 3: RAM-row 3 100 bank 4: RAM-row 4 101 bank 5: RAM-row 5 110 bank 6: RAM-row 6 111 bank 7: RAM-row 7 [1] Not applicable for multiplex drive mode 1:6 and 1:8. [2] Default value. bank 2: RAM-rows 2 and 3 bank 4: RAM-rows 4 and 5 bank 6: RAM-rows 6 and 7 All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 bank 4: RAM-rows 4, 5, 6, and 7 © NXP B.V. 2010. All rights reserved. 10 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 7.1.13 Command: write-RAM-data The write-RAM-data command writes data byte-wise to the RAM. After Power-On Reset (POR) the RAM content is random and should be brought to a defined status by clearing it (setting it logic 0). Write-RAM-data - write RAM data command bit description[1] Table 20. Bit Symbol Value Description 7 to 0 B[7:0] 00000000 to 11111111 writing data byte-wise to RAM [1] For this command bit RS of the control byte has to be set logic 1 (see Table 33 on page 52). More information about the display RAM can be found in Section 7.9 on page 40. 7.1.14 Command: temp-read The temp-read command allows reading out the temperature values measured by the internal temperature sensor. Table 21. Temp-read - temperature readout command bit description[1] For further information, see Table 9 on page 7 and Section 7.4.7 on page 35. Bit Symbol Value Description 7 to 0 TD[7:0] 00000000 to 11111111 readout representing the digital temperature [1] For this command bit R/W of the I2C-bus slave address byte has to be set logic 1 (see Table 32 on page 51). 7.1.15 Command: invmode_CPF_ctrl The invmode_CPF_ctrl command allows changing the drive scheme inversion mode and the charge pump frequency. The waveforms used to drive LCD displays inherently produce a DC voltage across the display cell. The PCA9620 will compensate for the DC voltage by inverting the waveforms on alternate frames or alternate lines. The choice of compensation method is determined with the LF bit. Table 22. Bit Symbol Value Description 7 to 2 - 110101 fixed value 1 LF 0 [1] PCA9620 Product data sheet Invmode_CPF_ctrl - inversion mode and charge pump frequency prescaler command bit description set inversion mode 0[1] line inversion mode 1 frame inversion mode CPF set charge pump oscillator frequency 0[1] fosc(cp) ~ 1 MHz 1 fosc(cp) ~ 500 kHz Default value. All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 11 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates In frame inversion mode the DC value is compensated across two frames and not within one frame. Changing the inversion mode to frame inversion reduces the power consumption, therefore it is useful when power consumption is a key point in the application. Frame inversion may not be suitable for all applications. The RMS voltage across a segment is better defined, however since the switching frequency is reduced there is possibility for flicker to occur. The waveforms of Figure 15 on page 23 to Figure 21 on page 29 are showing line inversion mode. Figure 22 on page 30 shows one example of frame inversion. 7.1.16 Command: temp-filter Table 23. Temp-filter - digital temperature filter command bit description Bit Symbol Value Description 7 to 1 - 1101001 fixed value 0 TFE [1] digital temperature filter switch 0[1] digital temperature filter disabled; the unfiltered digital value of TD[7:0] is immediately available for the readout and VLCD compensation, see Section 7.4.7 on page 35 1 digital temperature filter enabled Default value. 7.2 Possible display configurations The PCA9620 is a versatile peripheral device designed to interface between any microprocessor or microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 3). It can directly drive any static or multiplexed LCD containing up to eight backplanes and up to 60 segments. The display configurations possible with the PCA9620 depend on the number of active backplane outputs required; a selection of possible display configurations is given in Table 24. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 12 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates dot matrix 7-segment with dot 14-segment with dot and accent 013aaa312 Fig 3. Example of displays suitable for PCA9620 Table 24. Selection of possible display configurations Number of Backplanes Icons Digits/Characters 7-segment 14-segment Dot matrix/ Elements 8 480 60 30 480 dots (8 × 60) 6 320 45 22 360 dots (6 × 60) 4 240 30 15 240 dots (4 × 60) 2 120 15 7 120 dots (2 × 60) 1 60 7 3 60 dots (1 × 60) All of the display configurations in Table 24 can be implemented in the typical systems shown in Figure 4 (internal VLCD) and in Figure 5 (external VLCD). VDD2 VDD1 R≤ tr 2Cb VDD1 HOST PROCESSOR/ MICROCONTROLLER VDD2 VLCD 60 segment drives SDA LCD PANEL (up to 480 elements) SCL PCA9620 8 backplanes A0 A1 CLK VSS 013aaa247 n.c. VSS VDD1 from 2.5 V to 5.5 V and VDD2 from 2.5 V to 5.5 V. Fig 4. PCA9620 Product data sheet Typical system configuration when using the internal VLCD generation All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 13 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates VLCD VDD1 R≤ tr 2Cb VDD1 VDD2 VLCD 60 segment drives SDA HOST PROCESSOR/ MICROCONTROLLER LCD PANEL (up to 480 elements) SCL PCA9620 8 backplanes A0 A1 CLK VSS 013aaa248 n.c. VSS VDD1 from 2.5 V to 5.5 V, VDD2 from 2.5 V to 5.5 V and VLCD from 2.5 V to 9.0 V. Fig 5. Typical system configuration when using an external VLCD The host microprocessor or microcontroller maintains the 2 line I2C-bus communication channel with the PCA9620. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are the power supplies (VDD1, VDD2, VSS, VLCD), the external capacitors, and the LCD panel selected for the application. The minimum recommended values for external capacitors on VDD1, VDD2, and VLCD are nominal 100 nF. When using bigger capacitors, especially on the VLCD, the generated ripple will be consequently smaller, however it will take longer for the internal charge pump to first reach the target VLCD voltage. In the case that VDD1 and VDD2 are connected externally, the capacitors on VDD1 and VDD2 can be replaced by a single capacitor with a minimum value of 200 nF. Remark: In the case of insufficient decoupling, ripple of VDD1 and VDD2 will create additional VLCD ripple. The ripple on VLCD can be reduced by making the VSS connection as low-ohmic as possible. Excessive ripple on VLCD may give rise to flicker on the display. 7.3 Start-up and shut-down 7.3.1 Power-On Reset (POR) At power-on the PCA9620 resets to starting conditions as follows: 1. All backplane outputs are set to VSS. 2. All segment outputs are set to VSS. 3. Selected drive mode is: 1:8 with 1⁄4 bias. 4. Input and output bank selectors are reset. 5. The I2C-bus interface is initialized. 6. The data pointer is cleared (set logic 0). 7. The Internal oscillator is running; no clock signal is available on pin CLK; pin CLK is in 3-state. 8. Temperature measurement is enabled. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 14 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 9. Temperature filter is disabled. 10. The internal VLCD voltage generation is disabled. The charge pump is switched off. 11. The VLCD temperature compensation is enabled. 12. The display is disabled. Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow the reset action to complete. The first command sent to the device after the power-on event must be the initialize command (see Section 7.1.1 on page 5). After Power-On Reset (POR) and before enabling the display, the RAM content should be brought to a defined status • by clearing it (setting it all logic 0) or • by writing meaningful content (e.g. a graphic) otherwise unwanted display artifacts may appear on the display. Table 25. Reset states Bits labeled - are undefined at power-on. Command name PCA9620 Product data sheet Bits 7 6 5 4 3 2 1 0 initialize 0 0 1 1 1 0 1 0 OTP-refresh 1 1 0 1 0 0 0 0 oscillator-ctrl 1 1 0 0 1 1 0 0 charge-pump-ctrl 1 1 0 0 0 0 0 0 temp-msr-ctrl 1 1 0 0 1 0 1 1 temp-comp-SLA 0 0 0 1 1 0 0 0 temp-comp-SLB 0 0 1 0 0 0 0 0 temp-comp-SLC 0 0 1 0 1 0 0 0 temp-comp-SLD 0 0 1 1 0 0 0 0 set-VPR-MSB 0 1 0 0 0 0 0 0 set-VPR-LSB 0 1 0 1 0 0 0 0 display-enable 0 0 1 1 1 0 0 0 set-MUX-mode 0 0 0 0 0 0 0 0 set-bias-mode 1 1 0 0 0 1 0 0 load-data-pointer 1 0 0 0 0 0 0 0 frame-frequency 0 1 1 0 1 1 1 0 input-bank-select 0 0 0 0 1 0 0 0 output-bank-select 0 0 0 1 0 0 0 0 write-RAM-data - - - - - - - - temp-read 0 1 0 0 0 0 0 0 invmode_CPF_ctrl 1 1 0 1 0 1 0 0 temp-filter 1 1 0 1 0 0 1 0 All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 15 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 7.3.2 Recommended start-up sequences This chapter describes how to proceed with the initialization of the chip in different application modes. START Power-on VDD1 and VDD2 at the same time Set VPR register to desired VLCD value Set multiplication factor for charge pump and enable it Wait 1 ms Initialize command Initiate an OTP-refresh Wait till VLCD reaches programmed value(1) Write RAM content to be displayed and enable the display(2) STOP 013aaa249 (1) This time depends on the external capacitor on pin VLCD. For a capacitor of 100 nF a delay of 5 ms to 15 ms is expected. When using the internal VLCD generation, the display must not be enabled before the generation of VLCD with the internal charge pump is completed, otherwise unwanted display artifacts may appear on the display. (2) RAM data may be written before or during the ramp-up of VLCD. Fig 6. PCA9620 Product data sheet Recommended start-up sequence when using the internal charge pump and the internal clock signal All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 16 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates START Initiate an OTP-refresh Power-on VDD1, VDD2, and VLCD at the same time Write RAM content to be displayed and enable the display Wait 1 ms STOP Initialize command 013aaa250 Fig 7. Recommended start-up sequence when using an external supplied VLCD and the internal clock signal START Power-on VDD1 and VDD2 at the same time Apply external clock signal to pin CLK; set OSC bit logic 1(1) Wait till VLCD reaches programmed value(2) (1) Wait 1 ms Set VPR register to desired VLCD value Initialize command Initiate an OTP-refresh Set multiplication factor for charge pump and enable it Write RAM content to be displayed and enable the display(3) STOP 013aaa251 (1) The external clock signal can be applied after the generation of the VLCD voltage as well. (2) This time depends on the external capacitor on pin VLCD. For a capacitor of 100 nF a delay of 5 ms to 15 ms is expected. (3) RAM data may be written before or during the ramp-up of VLCD. Fig 8. PCA9620 Product data sheet Recommended start-up sequence when using the internal charge pump and an external clock signal All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 17 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates START Power-on VDD1, VDD2, and VLCD at the same time Apply external clock signal to pin CLK; set OSC bit logic 1 Wait 1 ms Write RAM content to be displayed and enable the display Initialize command STOP Initiate an OTP-refresh Fig 9. 013aaa252 Recommended start-up sequence when using an external supplied VLCD and an external clock signal 7.3.3 Recommended power-down sequences With the following sequences the PCA9620 can be set to a state of minimum power consumption, called power-down mode. START Disable display by setting bit E logic 0 Stop generation of VLCD by setting bit CPE logic 0 Disable temperature measurement by setting bit TME logic 0 STOP 013aaa253 Fig 10. Recommended power-down sequence for minimum power-down current when using the internal charge pump and the internal clock signal PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 18 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates START Disable display by setting bit E logic 0 Disable temperature measurement by setting bit TME logic 0 STOP 013aaa254 Fig 11. Recommended power-down sequence when using an external supplied VLCD and the internal clock signal START Disable display by setting bit E logic 0 Stop generation of VLCD by setting bit CPE logic 0 Disable temperature measurement by setting bit TME logic 0 Bring pin CLK to 3-state by setting bit OSC and bit COE logic 0 External clock may be switched off STOP 013aaa255 Fig 12. Recommended power-down sequence when using the internal charge pump and an external clock signal PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 19 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates START Disable display by setting bit E logic 0 Disable temperature measurement by setting bit TME logic 0 Bring pin CLK to 3-state by setting bit OSC and bit COE logic 0 External clock may be switched off STOP 013aaa256 Fig 13. Recommended power-down sequence when using an external supplied VLCD and an external clock signal Remark: It is necessary to run the power-down sequence before removing the supplies. Depending on the application, care must be taken that no other signals are present at the chip input or output pins when removing the supplies (please refer to Section 9 on page 53). Otherwise this may cause unwanted display artifacts. In case of uncontrolled removal of supply voltages the PCA9620 will not be damaged. Remark: Static voltages across the liquid crystal display can build up when the external LCD supply voltage (VLCD) is on while the IC supply voltage (VDD1 or VDD2) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, external VLCD, VDD1, and VDD2 must be applied or removed together. Remark: A clock signal must always be supplied to the device when the device is active; removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal. It is recommended to first disable the display and afterwards to remove the clock signal. 7.4 LCD voltage 7.4.1 LCD voltage selector The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the set-bias-mode command (see Table 14 on page 8) and the set-MUX-mode command (see Table 13 on page 8). Intermediate LCD biasing voltages are obtained from an internal voltage divider. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D), are given in Table 26. Discrimination is a term which is defined as the ratio of the on and off RMS voltage across a segment. It can be thought of as a measurement of contrast. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 20 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates Table 26. LCD drive modes: summary of characteristics LCD drive mode Number of: Backplanes Levels LCD bias configuration V off ( RMS ) ----------------------V LCD V on ( RMS ) ---------------------V LCD VLCD[2] V on ( RMS ) D = ----------------------- [1] V off ( RMS ) static 1 2 static 0 1 ∞ Von(RMS) 1:2 multiplex 2 3 1⁄ 2 0.354 0.791 2.236 2.828 × Voff(RMS) 1:2 multiplex 2 4 1⁄ 3 0.333 0.745 2.236 3.0 × Voff(RMS) 5 1⁄ 4 0.395 0.729 1.845 2.529 × Voff(RMS) 4 3 1⁄ 2 0.433 0.661 1.527 2.309 × Voff(RMS) 4 4 1⁄ 3 0.333 0.577 1.732 3.0 × Voff(RMS) 5 1⁄ 4 0.331 0.545 1.646 3.024 × Voff(RMS) 3 1⁄ 2 0.456 0.612 1.341 2.191 × Voff(RMS) 1:2 multiplex[3] 1:4 multiplex[3] 1:4 multiplex 1:4 multiplex[3] 1:6 multiplex[3] 2 4 6 1:6 multiplex 6 4 1⁄ 3 0.333 0.509 1.527 3.0 × Voff(RMS) 1:6 multiplex 6 5 1⁄ 4 0.306 0.467 1.527 3.266 × Voff(RMS) 3 1⁄ 2 0.467 0.586 1.254 2.138 × Voff(RMS) 4 1⁄ 3 0.333 0.471 1.414 3.0 × Voff(RMS) 5 1⁄ 4 0.293 0.424 1.447 3.411 × Voff(RMS) 1:8 multiplex[3] 1:8 multiplex[3] 1:8 multiplex 8 8 8 [1] Determined from Equation 3. [2] Determined from Equation 2. [3] In this examples the discrimination factor and hence the contrast ratios are smaller. The advantage of these LCD drive modes is a power saving from a reduction of the LCD voltage VLCD. A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is VLCD > 3Vth. 1 Bias is calculated by ------------- , where the values for a are 1+a a = 1 for 1⁄2 bias a = 2 for 1⁄3 bias a = 3 for 1⁄4 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1: V on ( RMS ) = V LCD a 2 + 2a + n -----------------------------2 n × (1 + a) (1) where VLCD is the resultant voltage at the LCD segment and where the values for n are n = 1 for static mode n = 2 for 1:2 multiplex n = 4 for 1:4 multiplex n = 6 for 1:6 multiplex n = 8 for 1:8 multiplex The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2: PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 21 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates V off ( RMS ) = V LCD a 2 – 2a + n -----------------------------2 n × (1 + a) (2) Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3: V on ( RMS ) --------------------- = V off ( RMS ) 2 (a + 1) + (n – 1) -------------------------------------------2 (a – 1) + (n – 1) (3) It should be noted that VLCD is sometimes referred as the LCD operating voltage. 7.4.1.1 Electro-optical performance Suitable values for Von(RMS) and Voff(RMS) are dependant on the LCD liquid used. The RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of the pixel. For any given liquid, there are two threshold values defined. One point is at 10 % relative transmission (at Vlow) and the other at 90 % relative transmission (at Vhigh), see Figure 14. For a good contrast performance, the following rules should be followed: V on ( RMS ) ≥ V high (4) V off ( RMS ) ≤ V low (5) Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection of a, n (see Equation 1 to Equation 3) and the VLCD voltage. Vlow and Vhigh are properties of the LCD liquid and can be provided by the module manufacturer. It is important to match the module properties to those of the driver in order to achieve optimum performance. 100 % Relative Transmission 90 % 10 % Vlow OFF SEGMENT Vhigh GREY SEGMENT VRMS [V] ON SEGMENT 001aam358 Fig 14. Electro-optical characteristic: relative transmission curve of the liquid PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 22 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.2 LCD drive mode waveforms 7.4.2.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. Tfr LCD segments VLCD BP0 VSS state 1 (on) VLCD state 2 (off) Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD state 1 0V −VLCD VLCD state 2 0V −VLCD (b) Resultant waveforms at LCD segment. 013aaa207 Vstate1(t) = VSn(t) − VBP0(t). Vstate2(t) = V(Sn + 1)(t) − VBP0(t). Von(RMS)(t) = VLCD. Voff(RMS)(t) = 0 V. Fig 15. Static drive mode waveforms (line inversion mode) PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 23 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.2.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCA9620 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 16 and Figure 17. Tfr VLCD BP0 LCD segments VLCD/2 VSS state 1 VLCD BP1 state 2 VLCD/2 VSS VLCD Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD VLCD/2 state 1 0V −VLCD/2 −VLCD VLCD VLCD/2 state 2 0V −VLCD/2 −VLCD (b) Resultant waveforms at LCD segment. 013aaa208 Vstate1(t) = VSn(t) − VBP0(t). Vstate2(t) = VSn(t) − VBP1(t). Von(RMS)(t) = 0.791VLCD. Voff(RMS)(t) = 0.354VLCD. Fig 16. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias (line inversion mode) PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 24 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates Tfr BP0 BP1 Sn Sn+1 VLCD 2VLCD/3 LCD segments VLCD/3 VSS state 1 VLCD 2VLCD/3 state 2 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 state 1 0V −VLCD/3 −2VLCD/3 −VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V −VLCD/3 −2VLCD/3 −VLCD (b) Resultant waveforms at LCD segment. 013aaa209 Vstate1(t) = VSn(t) − VBP0(t). Vstate2(t) = VSn(t) − VBP1(t). Von(RMS)(t) = 0.745VLCD. Voff(RMS)(t) = 0.333VLCD. Fig 17. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias (line inversion mode) PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 25 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.2.3 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in Figure 18. Tfr BP0 VLCD 2VLCD/3 VLCD/3 VSS BP1 VLCD 2VLCD/3 VLCD/3 VSS BP2 VLCD 2VLCD/3 VLCD/3 VSS BP3 VLCD 2VLCD/3 VLCD/3 VSS Sn VLCD 2VLCD/3 VLCD/3 VSS Sn+1 VLCD 2VLCD/3 VLCD/3 VSS Sn+2 VLCD 2VLCD/3 VLCD/3 VSS Sn+3 VLCD 2VLCD/3 VLCD/3 VSS state 1 VLCD 2VLCD/3 VLCD/3 0V −VLCD/3 −2VLCD/3 −VLCD state 2 VLCD 2VLCD/3 VLCD/3 0V −VLCD/3 −2VLCD/3 −VLCD LCD segments state 1 state 2 (a) Waveforms at driver. (b) Resultant waveforms at LCD segment. 013aaa211 Vstate1(t) = VSn(t) − VBP0(t). Vstate2(t) = VSn(t) − VBP1(t). Von(RMS)(t) = 0.577VLCD. Voff(RMS)(t) = 0.333VLCD. Fig 18. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias (line inversion mode) PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 26 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.2.4 1:6 Multiplex drive mode When six backplanes are provided in the LCD, the 1:6 multiplex drive mode applies. The PCA9620 allows the use of 1⁄3 bias or 1⁄4 bias in this mode as shown in Figure 19 and Figure 20. Tfr BP0 VLCD 2VLCD / 3 VLCD / 3 VSS BP1 VLCD 2VLCD / 3 VLCD / 3 VSS BP2 VLCD 2VLCD / 3 VLCD / 3 VSS BP3 VLCD 2VLCD / 3 VLCD / 3 VSS BP4 VLCD 2VLCD / 3 VLCD / 3 VSS BP5 VLCD 2VLCD / 3 VLCD / 3 VSS Sn VLCD 2VLCD / 3 VLCD / 3 VSS Sn + 1 VLCD 2VLCD / 3 VLCD / 3 VSS LCD segments state 1 state 2 VLCD 2VLCD / 3 state 1 VLCD / 3 VSS −VLCD / 3 −2VLCD / 3 −VLCD state 2 VLCD 2VLCD / 3 VLCD / 3 VSS −VLCD / 3 −2VLCD / 3 −VLCD 001aal399 Vstate1(t) = VSn(t) − VBP0(t). Vstate2(t) = VSn(t) − VBP1(t). Von(RMS)(t) = 0.509VLCD. Voff(RMS)(t) = 0.333VLCD. Fig 19. Waveforms for 1:6 multiplex drive mode with 1⁄3 bias (line inversion mode) PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 27 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates Tfr LCD segments VLCD 3VLCD / 4 state 1 state 2 BP0 VLCD / 4 VSS VLCD 3VLCD / 4 BP1 VLCD / 4 VSS VLCD 3VLCD / 4 BP2 VLCD / 4 VSS VLCD 3VLCD / 4 BP3 VLCD / 4 VSS VLCD 3VLCD / 4 BP4 VLCD / 4 VSS VLCD 3VLCD / 4 BP5 VLCD / 4 VSS VLCD Sn VLCD / 2 VSS VLCD Sn + 1 VLCD / 2 VSS VLCD 3VLCD / 4 state 1 VLCD / 4 VSS −VLCD / 4 −3VLCD / 4 −VLCD VLCD 3VLCD / 4 VLCD / 2 VLCD / 4 VSS state 2 −VLCD / 4 −VLCD / 2 −3VLCD / 4 −VLCD 001aal400 Vstate1(t) = VSn(t) − VBP0(t). Vstate2(t) = VSn(t) − VBP1(t). Von(RMS)(t) = 0.467VLCD. Voff(RMS)(t) = 0.306VLCD. Fig 20. Waveforms for 1:6 multiplex drive mode with 1⁄4 bias (line inversion mode) PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 28 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.2.5 1:8 Multiplex drive mode Tfr VLCD 3VLCD / 4 LCD segments state 1 state 2 BP0 VLCD / 4 VSS VLCD 3VLCD / 4 BP1 VLCD / 4 VSS VLCD 3VLCD / 4 BP2 VLCD / 4 VSS VLCD 3VLCD / 4 BP3 VLCD / 4 VSS VLCD 3VLCD / 4 BP4 3LCD / 4 VSS VLCD 3VLCD / 4 BP5 VLCD / 4 VSS VLCD 3VLCD / 4 BP6 VLCD / 4 VSS VLCD 3VLCD / 4 BP7 VLCD / 4 VSS VLCD Sn VLCD / 2 VSS VLCD Sn + 1 VLCD / 2 VSS VLCD 3VLCD / 4 state 1 VLCD / 4 VSS −VLCD / 4 −3VLCD / 4 −VLCD state 2 VLCD 3VLCD / 4 VLCD / 2 VLCD / 4 VSS −VLCD / 4 −VLCD / 2 −3VLCD / 4 −VLCD 001aal398 Vstate1(t) = VSn(t) − VBP0(t). Vstate2(t) = VSn(t) − VBP1(t). Von(RMS)(t) = 0.424VLCD. Voff(RMS)(t) = 0.293VLCD. Fig 21. Waveforms for 1:8 multiplex drive mode with 1⁄4 bias (line inversion mode) PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 29 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates VLCD 3/4 VLCD Tfr frame n Tfr frame n+1 LCD segments state 1 BP0 state 2 1/4 VLCD VSS VLCD 3/4 VLCD BP1 1/4 VLCD VSS VLCD 3/4 VLCD BP2 1/4 VLCD VSS VLCD 3/4 VLCD BP3 1/4 VLCD VSS VLCD 3/4 VLCD BP4 1/4 VLCD VSS VLCD 3/4 VLCD BP5 1/4 VLCD VSS VLCD 3/4 VLCD BP6 1/4 VLCD VSS VLCD 3/4 VLCD BP7 1/4 VLCD VSS VLCD Sn 1/2 VLCD VSS VLCD Sn + 1 1/2 VLCD VSS state 1 VLCD 3/4 VLCD 1/2 VLCD 1/4 VLCD VSS 1/4 VLCD 1/2 VLCD 3/4 VLCD VLCD state 2 VLCD 3/4 VLCD 1/2 VLCD 1/4 VLCD VSS 1/4 VLCD 1/2 VLCD 3/4 VLCD VLCD 001aam359 Vstate1(t) = VSn(t) − VBP0(t). Vstate2(t) = VSn(t) − VBP1(t). Von(RMS)(t) = 0.424VLCD. Voff(RMS)(t) = 0.293VLCD. Fig 22. Waveforms for 1:8 multiplex drive mode with 1⁄4 bias (frame inversion mode) PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 30 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates When eight backplanes are provided in the LCD, the 1:8 multiplex drive mode applies, as shown in Figure 21 and Figure 22. 7.4.3 VLCD generation VLCD can be generated and controlled on the chip by using software commands. When the internal charge pump is used, the programmed VLCD is available on pin VLCD. The charge pump generates a VLCD of up to 3 × VDD2. The charge pump can be enabled or disabled with the CPE bit (see Table 8 on page 7). With bit CPC the charge pump multiplier setting can be configured. The final value of VLCD is a combination of the programmed VPR[7:0] value and the output of the temperature compensation block, VT[7:0]. The system is shown in Figure 23. SLA SLB SLC SLD 0 OFFSET TEMPERATURE READOUT 8 8 TD −40 0 +20 +50 +80 TEMPERATURE n VPR[7:0] m 8 VLCD 013aaa257 Fig 23. VLCD generation including temperature compensation In Equation 6 the main parameters are the programmed digital value term and the compensated temperature term. V LCD = [ VPR [ 7:0 ] + VT [ 7:0 ] ] × n + m (6) 1. VPR[7:0] is the binary value of the programmed voltage. 2. VT[7:0] is the binary value of the temperature compensated voltage. Its value comes from the temperature compensation block and is a two’s complement which has the value 0h at 20 °C. 3. m and n are fixed values (see Table 27). Table 27. Symbol Parameters of VLCD generation Value Unit m 3 V n 0.03 V Figure 24 shows how VLCD changes with the programmed value of VPR[7:0]. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 31 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates It has to be taken into account that the charge pump has to be configured (via bit CPC) properly to obtain the desired voltage range. For example, if VDD2 = 3.0 V and CPC is set to 2 × VDD2 (logic 0) then the maximum theoretical value that the charge pump can reach is VLCD = 6.0 V. But in reality, lower values will be reached due to internal resistances, see Section 7.4.5. So, if the requested value for VLCD = 7.0 V then the charge pump has to be configured with CPC set to 3 × VDD2 (logic 1). V LCD (2) 9V n (1) VDD2 m 00 01 02 03 04 05 06 ........................ C7 C8 C9 CA ... FC FD FE FF VPR[7:0] 013aaa258 (1) If VDD2 > 3.0 V then VPR[7:0] must be set so that VLCD > VDD2. (2) Automatic limitation for VLCD > 9.0 V. Fig 24. VLCD programming of PCA9620 (assuming VT[7:0] = 0h) Programmable range of VPR[7:0] is from 0h to FFh. This would allow to achieve VLCD > 9.0 V, but the PCA9620 has a built-in automatic limitation of VLCD at 9.0 V. In case that VDD2 is higher than 3.0 V, then it is important that VPR[7:0] is set to a value such that the resultant VLCD (including the temperature correction of VT[7:0]) is higher than VDD2. 7.4.4 External VLCD supply VLCD can be directly supplied to the VLCD pin. In this case the internal charge pump must not be enabled otherwise a high current may occur on pin VDD2 and pin VLCD. When VLCD is supplied externally, no internal temperature compensation occurs on this voltage even if bit TCE is set logic 1 (see Section 7.4.8 on page 36). The VLCD voltage which is supplied externally will be available at the segments and backplanes of the device through the chosen bias system. Also programming the VPR[7:0] bit field has no effect on the VLCD which is externally supplied. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 32 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.5 Charge pump driving capability Figure 25 illustrates the main factor determining how much current the charge pump can deliver. Regulated desired VLCD This supplies the segments and backplanes Theoretical VLCD value VLCD = 2 × VDD2 or VLCD = 3 × VDD2 Output Resistance Ro(cp) 013aaa259 Fig 25. Charge pump model (used to characterize the driving strength) The output resistance of the charge pump is specified in Table 35 on page 55. With these values it can be calculated how much current the charge pump can drive under certain conditions. Example: Assuming the user would like to have the normal operation point at 25 °C with VLCD = 7.0 V and VDD2 = 5.0 V and the charge pump is set to 2 × VDD2. Then the theoretical value of VLCD is 10.0 V and the desired one is 7.0 V. The difference between the theoretical maximum value and desired one is 3.0 V. The charge pump resistance is nominally 0.85 kΩ. Equation 7 shows the possible current that the charge pump could deliver: I load = ΔV LCD ⁄ R o ( cp ) (7) For this example we get: I load = 3.0 V ⁄ 0.85 kΩ = 3.5 mA In cases where no extreme driving capability is needed, a command is available for decreasing the charge pump frequency (see Table 22 on page 11) and thus reducing the total current consumption. If the charge pump frequency is halved, then the driving capability is halved as well, whereas the output resistance doubles. 7.4.6 Charge pump frequency settings and power efficiency The PCA9620 offers the possibility to use different frequency settings for the charge pump. Bit CPF controls the frequency at which the charge pump is running (see Table 22 on page 11). This frequency has a direct influence on the current consumption of the IC but also on the charge pump driving capability. Using a lower charge pump frequency decreases the current consumption and the driving capability. The power efficiency of the charge pump determines in certain applications which frequency settings to choose for the CPF bit. In the example shown in Figure 26, the current consumption was measured with the charge pump set to 2 × VDD2 and with VDD2 = 3.0 V and VPR[7:0] set to maximum to obtain the maximum possible VLCD with this setup, which is close to 6.0 V. The current load on pin VLCD determines the output power delivered by the IC: P o = I load × V LCD (8) The current consumption on pin VDD2 determines the input power taken by the IC: PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 33 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates P i = I DD2 × V DD2 (9) The ratio between these two numbers determines the charge pump power efficiency: ηp = Po ⁄ Pi (10) 001aan027 90 ηp (%) 7 VLCD (V) 70 5 (3) (4) (1) (2) 50 3 30 0 200 400 600 1 1000 800 Iload (μA) Charge pump set to 2 × VDD2; VDD2 = 3 V. (1) ηp, full charge pump frequency. (2) ηp, half charge pump frequency. (3) VLCD, full frequency. (4) VLCD, half frequency. Fig 26. Power efficiency of the charge pump Loading the charge pump with higher currents decreases the output voltage. This decrease is determined by the charge pump driving capability, respectively by the output resistance of the charge pump (see Table 35 on page 55). The power efficiency calculation is only valid when the charge pump is running at its maximum peak frequency and regulates the generated VLCD voltage with full speed. In this case, the ripple on the VLCD voltage equals the internal charge pump frequency. Approximately, this could also be calculated with the parameter of the output resistance of the charge pump (see Table 35 on page 55), the load current, and the voltage needed to be provided by using Equation 7 on page 33. This value of Iload is close to the value of the load current needed for the application. If the application runs with VDD2 = 3.0 V, the load currents are up to 400 μA (DC measured), and the VLCD generated voltages are up to 5.0 V, then - concerning power efficiency - it would be the best to have a charge pump frequency set to half frequency. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 34 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates In case it is desired to change the charge pump frequency, it is recommended to make a graph like Figure 26 and understand what the application requirements are. This would basically imply to find out what would be the maximum VLCD requirements and what would be the maximum load currents required. Then it can be decided which is the best setting of bit CPF. Tuning the charge pump frequency might be a difficult task to do and requires good knowledge of the application in which the IC is being used; therefore, NXP recommends to keep the CPF bit set logic 0 to have the maximum charge pump frequency, thus having the maximum driving strength. 7.4.7 Temperature readout The PCA9620 has a built-in temperature sensor which provides a 8 bit digital value, TD[7:0], of the ambient temperature. This value can be read through the I2C interface (see Figure 49 on page 52). The actual temperature is determined from TD[7:0] using Equation 11: T (°C) = 0.9375 × TD [ 7:0 ] – 40 (11) The measurement needs about 5 ms to complete and is repeated periodically as soon as bit TME is set logic 1 (see Table 9 on page 7). The time between measurements is linked to the system clock and hence varies with changes in the chosen frame frequency, see Table 28. Table 28. Temperature measurement update rate Selected frame frequency Temperature measurement update rate 60 Hz 3.3 s 200 Hz 1s 300 Hz 0.67 s Due to the nature of a temperature sensor, oscillations on the VLCD may occur. To avoid this, a filter has been implemented in PCA9620. The system is shown in Figure 27. TEMPERATURE MEASUREMENT BLOCK TD[7:0] unfiltered DIGITAL TEMPERATURE FILTER TD[7:0] filtered To the readout register via I2C-bus and to the VLCD compensation block enabled or disabled by bit TFE 013aaa260 Fig 27. Temperature measurement block with digital temperature filter Like any other filtering, the digital temperature filter (see Figure 27) introduces a certain delay in the measurement of temperature. This behavior is illustrated in Figure 28. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 35 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 001aal393 50 16 ΔT (°C)(3) T (°C) 40 12 30 8 (1) (2) 20 4 (3) 10 0 −4 160 0 0 40 80 120 t (s) (1) Environment temperature, T1 (°C). (2) Measured temperature, T2 (°C). (3) Temperature deviation, ΔT = T2 − T1. Fig 28. Temperature measurement delay This delay may cause undesired effects at start-up when the environment temperature may be different than the reset value of the PCA9620 which is 20 °C. In this case it takes up to 30 s till the correct measured temperature value will be available. A control bit, TFE, is implemented to enable or disable the digital temperature filter. This bit is set logic 0 by default which means that the filter is disabled and the unfiltered environment temperature value is available to calculate the desired VLCD. 7.4.8 Temperature compensation of VLCD Due to the temperature dependency of the liquid crystal viscosity the LCD controlling voltage VLCD might have to be adjusted at different temperatures to maintain optimal contrast. The temperature behavior of the liquid comes from the LCD manufacturer. The slope has to be set to compensate for the liquid behavior. Internal temperature compensation may be enabled via bit TCE. The ambient temperature range is split up into four equally sized regions and a different temperature coefficient can be applied to each (see Figure 29). Each coefficient can be selected from a choice of eight different slopes. Each one of these coefficients (see Table 29) may be independently selected via the temp-comp-SLA to temp-comp-SLD commands (see Table 4 on page 5). PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 36 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates Table 29. Temperature coefficients SLA[2:0] to SLD[2:0] value Corresponding slope factor (mV/°C) Temperature coefficients MA, MB, MC, MD[1] 000[2] 0 0.00 001 −4 −0.125 010 −8 −0.25 011 −16 −0.5 100 −40 −1.25 101 +4 0.125 110 +8 0.25 111 +16 0.5 [1] The relationship between the temperature coefficients MA to MD and the slope factor is derived from the 0.9375 0.03 slope 1000 following equation: Mx = ---------------- × -------------- . [2] Default value. The slope factors imply a linear correction, however the implementation is set in steps of 30 mV (parameter n in Table 27 on page 31). SLA SLB SLC SLD TD[7:0] 0h 40h 20h 7Fh 60h VLCD with temperature compensation (V) zero offset at 20 °C MA −40 MB −10 MC 20 MD 50 79 Temperature (°C) 013aaa261 Fig 29. Example of segmented temperature coefficients Remark: After reset, VLCD is fixed because the VPR[7:0] bit field is reset logic 0. The value of VT[7:0] is generated by the reset value of TD[7:0] (40h, representing 20 °C). Temperature compensation is implemented by adding an offset VT[7:0] to the VPR[7:0] value. VT[7:0] is a two’s complement number that equals 0h at 20 °C. The final result for VLCD calculation is an 8-bit positive number (see Equation 6 on page 31). Remark: Care must be taken that the ranges of VPR[7:0] and VT[7:0] don’t cause clipping and hence undesired results. The device will not permit overflow or underflow and will clamp results to either end of the range. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 37 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates The Voffset(LCD) value can be calculated with the equations given in Table 30: V offset ( LCD ) = m × V T Table 30. (12) Calculation of the temperature compensated voltage VT Temperature range TD[7:0] Offset equation for VT T ≤ −40 °C 0h V T = – 32 × MA – 32 × MB −40 °C ≤ T ≤ −10 °C 0h to 20h V T = ( TD [ 7:0 ] – 32 ) × MA – 32 × MB −10 °C < T ≤ 20 °C 21h to 40h V T = ( TD [ 7:0 ] ( – 64 ) ) × MB 20 °C < T ≤ 50 °C 41h to 60h V T = ( TD [ 7:0 ] – 64 ) × MC 50 °C < T < 80 °C 61h to 7Eh V T = ( TD [ 7:0 ] – 96 ) × MD + 32 × MC 80 °C ≤ T 7Fh[1] V T = 31 × MD + 32 × MC [1] No temperature compensation is possible above 80 °C. Above this value, the system maintains the compensation value from 80 °C. Example: Assumed that Tamb = −8 °C; TD[7:0] = 22h; MB = −0.5: V offset ( LCD ) = m × V T = m × ( TD[7:0] – 64 ) × MB = 30mV × ( ( 34 – 64 ) × – 0.5 ) = 30mV × – 30 × – 0.5 = 450mV The VT[7:0] term is calculated using the digital temperature value TD[7:0] which is provided by the temperature measurement block (Section 7.4.7). Therefore the accuracy of the temperature measurement block (Tacc, see Table 35 on page 55) will be directly translated to the LCD voltage deviation ΔVLCD. Since VT[7:0] = f[T,slope] and Tacc = ±6 °C then ΔV T = T acc × slope , where slope has one of the possible values specified in Table 29. This term will be added to the total LCD voltage deviation ΔVoffset(LCD)tot over the temperature range. So the total VLCD offset will be: ΔV offset ( LCD )tot = ΔV LCD + ΔV T . 7.5 Oscillator The internal logic and LCD drive signals of the PCA9620 are timed by a frequency fclk which either is the built-in oscillator frequency fosc or equals an external clock frequency. 7.5.1 Internal oscillator When the internal oscillator is used, it is possible to make the clock signal available on pin CLK by using the oscillator-ctrl command (see Table 7 on page 6). If this is not intended, pin CLK should be left open. At power-on the signal at pin CLK is disabled and pin CLK is in 3-state. The duty cycle of the output clock provided on the CLK pin is not always 50 : 50. Table 17 on page 9 shows the expected duty cycle for each of the chosen frame frequencies. 7.5.2 External clock In applications where an external clock needs to be applied to the PCA9620, bit OSC (see Table 7 on page 6) must be set logic 1. In this case pin CLK becomes an input. The CLK signal is a signal that is fed into the VDD1 domain so it must have an amplitude equal to the VDD1 voltage supplied to the chip and be referenced to VSS. The clock frequency (fclk) determines the LCD frame frequency ffr. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 38 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates Remark: In case that a external clock is used then this clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal. Removal of the clock is possible when following the correct procedures. See Figure 12 on page 19 and Figure 13 on page 20. 7.5.3 Timing and frame frequency The timing of the PCA9620 organizes the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. The timing also generates the LCD frame frequency which it derives as an integer division of the clock frequency. The frame frequency is a fixed division of the internal clock or of the frequency applied to pin CLK when an external clock is used: f clk f fr = ------48 (13) When the internal clock is used, the clock and frame frequency can be programmed by software such that the nominal frame frequency can be chosen in steps of 10 Hz in the range of 60 Hz to 300 Hz (see Table 17 on page 9). Furthermore the nominal frame frequency is factory-calibrated with an accuracy of ±15 %. When the internal clock is enabled at pin CLK by using bit COE, the duty ratio of the clock may change when choosing different values for the frame frequency prescaler. Table 17 on page 9 shows the different output duty ratios for each frame frequency prescaler setting. 7.6 Backplane outputs The LCD drive section includes eight backplane outputs: BP0 to BP7. The backplane output signals are generated based on the selected LCD multiplex drive mode. Table 31 describes which outputs are active for each of the multiplex drive modes and what signal is generated. Table 31. Multiplex drive mode Output pin 1:8 BP0 Product data sheet BP0 BP1 BP2 BP3 BP4 BP5 BP6 BP7 BP1 BP2 BP3 BP4 BP5 BP6 BP7 BP1[1] Signal 1:6 BP0 BP1 BP2 BP3 BP4 BP5 BP0[1] 1:4 BP0 BP1 BP2 BP3 BP0[1] BP1[1] BP2[1] BP3[1] BP1[1] BP0[1] BP1[1] BP0[1] BP1[1] BP0[1] BP0[1] BP0[1] BP0[1] BP0[1] 1:2 BP0 BP1 BP0[1] static BP0 BP0[1] BP0[1] [1] PCA9620 Mapping of output pins and corresponding output signals with respect to the multiplex driving mode These pins may optionally be connected to the display to improve drive strength. Connect only with the corresponding output pin carrying the same signal. If not required they can be left open-circuit. All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 39 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 7.7 Segment outputs The LCD drive section includes 60 segment outputs (S0 to S59) which must be connected directly to the LCD. The segment output signals are generated based on the multiplexed backplane signals and with data resident in the display register. When less than 60 segment outputs are required, the unused segment outputs must be left open-circuit. 7.8 Display register The display register holds the display data while the corresponding multiplex signals are generated. 7.9 Display RAM The display RAM is a static 60 × 8-bit RAM which stores LCD data. Logic 1 in the RAM bit map indicates the on-state of the corresponding LCD element; similarly, logic 0 indicates the off-state. There is a one-to-one correspondence between • the bits in the RAM bitmap and the LCD elements • the RAM columns and the segment outputs • the RAM rows and the backplane outputs. The display RAM bit map, Figure 30, shows row 0 to row 7 which correspond with the backplane outputs BP0 to BP7, and column 0 to column 59 which correspond with the segment outputs S0 to S59. In multiplexed LCD applications the data of each row of the display RAM is time-multiplexed with the corresponding backplane (row 0 with BP0, row 1 with BP1 and so on). When display data is transmitted to the PCA9620 the display bytes received are stored in the display RAM in accordance with the selected LCD multiplex drive mode. The data is stored as it arrives and does not wait for the acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, quadruples, sextuples or bytes. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 40 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates columns display RAM columns/segment outputs (S) static drive mode 0 1 2 3 4 55 56 57 58 59 0 bank 0 1 bank 1 2 bank 2 3 bank 3 4 bank 4 5 bank 5 6 bank 6 7 bank 7 multiplex 1:2 drive mode 0 1 2 3 4 55 56 57 58 59 0 bank 0 1 2 rows bank 2 display RAM rows/ backplane outputs (BP) 3 4 bank 4 5 6 bank 6 7 0 multiplex 1:4 drive mode 1 2 3 4 55 56 57 58 59 0 1 bank 0 2 3 4 5 bank 4 6 7 013aaa262 The display RAM bitmap shows the direct relationship between the display RAM column and the segment outputs, between the bits in a RAM row and the backplane outputs, and between the RAM rows and banks. Fig 30. Display RAM bitmap 7.9.1 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command. Following this command, an arriving data byte is stored starting at the display RAM address indicated by the data pointer. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 41 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates The data pointer is automatically incremented in accordance with the chosen LCD multiplex drive mode configuration. That is, after each byte is stored, the contents of the data pointer are incremented • • • • • by eight (static drive mode) by four (1:2 multiplex drive mode) by two (1:4 multiplex drive mode) by one or two (1:6 multiplex drive mode), see Figure 37 on page 45 by one (1:8 multiplex drive mode) If the data pointer reaches the end of the RAM row it is automatically wrapped around to address 0. This means that it can be continuously written to or read from the display RAM. The data pointer should always be set to an address where the remaining RAM is divisible by eight because odd bits will be discarded (see Figure 32). This behavior is actually only shown in static drive mode because of the fact that the 60 RAM cells can’t be divided by eight without remainder. If an I2C-bus data access is terminated early then the state of the data pointer is unknown. The data pointer must then be re-written prior to further RAM accesses. 7.9.1.1 RAM filling in static drive mode In the static drive mode the eight transmitted data bits are placed in eight successive display RAM columns in row 0 (see Figure 31). columns display RAM columns/segment outputs (S) rows 0 1 2 3 4 5 6 7 55 56 57 58 59 display RAM rows/ 0 b7 b6 b5 b4 b3 b2 b1 b0 backplane outputs (BP) b7 b6 b5 b4 b3 b2 b1 b0 MSB LSB transmitted data byte 013aaa263 Fig 31. Display RAM filling order in static drive mode In order to fill the whole RAM row, 8 bytes must be sent to the PCA9620, but the last 4 bits from the last byte are discarded, and the data pointer is wrapped around to column 0 to start a possible RAM content update (see Figure 32). PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 42 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates data pointer 0 1 2 3 4 5 6 48 49 50 51 52 53 54 55 56 57 58 59 7 0 a7 a6 a5 a4 a3 a2 a1 a0 f7 f6 f5 f4 f3 f2 f1 f0 g7 g6 g5 g4 g3 g2 g1 g0 discarded display RAM wrap around 013aaa287 Fig 32. Discarded bits and data pointer wrap around at the end of data transmission 7.9.1.2 RAM filling in 1:2 multiplex drive mode In the 1:2 multiplex drive mode the eight transmitted data bits are placed in four successive display RAM columns of two rows (see Figure 33). columns display RAM columns/segment outputs (S) rows 0 1 2 3 4 5 6 7 55 56 57 58 59 display RAM rows/ 0 b7 b5 b3 b1 backplane outputs 1 b6 b4 b2 b0 (BP) LSB b7 b6 b5 b4 b3 b2 b1 b0 MSB transmitted data byte 013aaa264 Fig 33. Display RAM filling order in 1:2 multiplex drive mode In order to fill the whole two RAM rows 15 bytes need to be sent to the PCA9620. After the last byte sent the data pointer is wrapped around to column 0 to start a possible RAM content update (see Figure 34). Even if a data byte is transmitted during the wrapping of the data pointer, then all the bits in the byte will be written correctly. data pointer 0 1 2 3 4 5 6 7 55 56 57 58 59 0 b1 display RAM 1 b0 b7 b5 b3 b6 b4 b2 wrap around 013aaa288 Fig 34. Data pointer wrap around in 1:2 multiplex drive mode 7.9.1.3 RAM filling in 1:4 multiplex drive mode In the 1:4 multiplex drive mode the eight transmitted data bits are placed in two successive display RAM columns of four rows (see Figure 35). PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 43 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates columns display RAM columns/segment outputs (S) 0 1 2 0 b7 b3 1 b6 b2 rows 3 4 5 6 7 55 56 57 58 59 2 b5 b1 display RAM rows/ backplane outputs (BP) 3 b4 b0 b7 b6 b5 b4 b3 b2 b1 b0 MSB LSB transmitted data byte 013aaa265 Fig 35. Display RAM filling order in 1:4 multiplex drive mode In order to fill the whole four RAM rows 30 bytes need to be sent to the PCA9620. After the last byte sent, the data pointer is wrapped around to column 0 to start a possible RAM content update (see Figure 36). Even if a data byte is transmitted during the wrapping of the data pointer, all the bits in the byte will be written correctly. columns display RAM columns/segment outputs (S) data pointer display RAM 0 1 0 b3 1 b2 2 3 4 5 6 7 55 56 57 58 59 b7 b6 2 b1 b5 3 b0 b4 wrap around 013aaa289 Fig 36. Data pointer wrap around in 1:4 multiplex drive mode 7.9.1.4 RAM filling in 1:6 multiplex drive mode In the 1:6 multiplex drive mode the RAM is organized in six rows and 60 columns. The eight transmitted data bits are placed in such a way, that a column is filled up (see Figure 37). PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 44 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates columns display RAM columns/segment outputs (S) data pointer incrementation 0 1 2 3 4 5 6 7 55 56 57 58 59 0 a7 a1 b3 c5 rows 1 a6 a0 b2 c4 2 a5 b7 b1 c3 display RAM rows/ backplane outputs (BP) 3 a4 b6 b0 c2 4 a3 b5 c7 c1 5 a2 b4 c6 c0 LSB MSB a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0 transmitted data bytes 013aaa266 Fig 37. Display RAM filling order in 1:6 multiplex drive mode The remaining bits are wrapped up into the next column. In order to fill the whole RAM addresses 45 bytes need to be sent to the PCA9620. After the last byte sent the data pointer is wrapped around to column 0 to start a possible RAM content update (see Figure 38). Even if a data byte is transmitted during the wrapping of the data pointer, all the bits in the byte will be written correctly. data pointer display RAM 0 1 2 3 4 5 6 7 55 56 57 58 59 0 b3 c5 a7 a1 1 b2 c4 a6 a0 2 b1 c3 a5 b7 3 b0 c2 a4 b6 4 c7 c1 a3 b5 5 c6 c0 a2 b4 wrap around 013aaa290 Fig 38. Data pointer wrap around in 1:6 multiplex drive mode 7.9.1.5 RAM filling in 1:8 multiplex drive mode In the 1:8 multiplex drive mode the eight transmitted data bits are placed into eight rows of one display RAM column (see Figure 39). PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 45 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates columns transmitted data byte display RAM columns/segment outputs (S) MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 0 1 2 3 4 5 6 7 55 56 57 58 59 0 b7 1 b6 rows 2 b5 3 b4 display RAM rows/ backplane outputs (BP) 4 b3 5 b2 6 b1 7 b0 013aaa267 Fig 39. Display RAM filling order in 1:8 multiplex drive mode In order to fill the whole RAM addresses 60 bytes need to be sent to the PCA9620. After the last byte sent the data pointer is wrapped around to column 0 to start a possible RAM content update (see Figure 40). In this case there is no situation possible where a transmitted data byte can be written over the RAM boundary. data pointer display RAM 0 1 2 3 4 5 6 7 55 56 57 58 59 0 b7 a7 1 b6 a6 2 b5 a5 3 b4 a4 4 b3 a3 5 b2 a2 6 b1 a1 7 b0 a0 wrap around 013aaa291 Fig 40. Data pointer wrap around in 1:8 multiplex drive mode 7.9.2 Bank selection A RAM bank can be thought of as a collection of RAM rows. The PCA9620 includes a RAM bank switching feature in the static, 1:2, and 1:4 multiplex drive modes. The RAM bank switching gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is complete. Input and output banks can be set independently from one another with the input-bank-select and the output-bank-select commands; Figure 41 shows the concept. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 46 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates INPUT-BANK-SELECT COMMAND CONTROLS THE INPUT DATA PATH OUTPUT-BANK-SELECT COMMAND CONTROLS THE OUTPUT DATA PATH BANK 0 MICROCONTROLLER RAM DISPLAY BANK 4 013aaa422 Fig 41. Example of bank selection in 1:4 multiplex mode In Figure 41 an example is shown for 1:4 multiplex drive mode where the displayed data is read from the first four rows of the memory (bank 0), while the transmitted data is stored in the second four rows of the memory (bank 4) which is currently not accessed for the reading. Therefore different content can be loaded into the first and second four RAM rows which will be immediately displayed on the LCD by switching it with the output-bank-select command (see Figure 42). columns display RAM columns/segment outputs (S) 0 1 2 3 4 5 6 7 55 56 57 58 59 0 1 rows to the LCD 2 display RAM rows/ backplane outputs (BP) output RAM bank 3 4 5 to the RAM 6 7 input RAM bank 013aaa424 Fig 42. Example of the input-bank-select and the output-bank-select command with multiplex drive mode 1:4 7.9.2.1 Input-bank-select The input-bank-select command (see Table 18 on page 10) loads display data into the display RAM in accordance with the selected LCD drive configuration. • In static drive mode, an individual content can be stored in each RAM bank (bank 0 to bank 7 which corresponds to row 0 to row 7). • In 1:2 multiplex drive mode, individual content for RAM bank 0 (row 0 and row 1), RAM bank 2 (row 2 and row 3), RAM bank 4 (row 4 and 5) and RAM bank 6 (row 6 and row 7) can be stored. • In 1:4 multiplex drive mode individual content can be stored in RAM bank 0 (row 0 to row 3) and RAM bank 4 (row 4 to row 7). The input-bank-select command works independently to the output-bank-select. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 47 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 7.9.2.2 Output-bank-select The output-bank-select command (see Table 19 on page 10) selects the display RAM transferring it to the display register in accordance with the selected LCD drive configuration. • In the static drive mode it is possible to request the content of RAM bank 1 (row 1) to RAM bank 7 (row 7) for display instead of the default RAM bank 0 (row 0). • In 1:2 multiplex drive mode, the content of RAM bank 2 (row 2 and row 3) or of RAM bank 4 (row 4 and row 5) or of RAM bank 6 (row 6 and row 7) may be selected instead of the default RAM bank 0 (row 0 and row 1). • In 1:4 multiplex drive mode, the content of RAM bank 4 (row 4, 5, 6, and 7) may be selected instead of RAM bank 0 (row 0, 1, 2, and 3). The output-bank-select command works independently to the input-bank-select. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 48 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 8. I2C-bus interface characteristics The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 43). SDA SCL data line stable; data valid change of data allowed mba607 Fig 43. Bit transfer 8.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are shown in Figure 44. SDA SDA SCL SCL S P START condition STOP condition mbc622 Fig 44. Definition of START and STOP conditions 8.3 System configuration A device generating a message is a transmitter; a device receiving a message is the receiver. The device that controls the message is the master; and the devices which are controlled by the master are the slaves. The system configuration is shown in Figure 45. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 49 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates MASTER TRANSMITTER/ RECEIVER SLAVE TRANSMITTER/ RECEIVER SLAVE RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER SDA SCL mga807 Fig 45. System configuration 8.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A slave receiver which is addressed must generate an acknowledge after the reception of each byte. • Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. • The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). • A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is shown in Figure 46. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 8 9 S START condition clock pulse for acknowledgement mbc602 Fig 46. Acknowledgement on the I2C-bus PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 50 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 8.5 I2C-bus controller The PCA9620 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from PCA9620 are the acknowledge signals and the temperature readout byte of the selected device. 8.6 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 8.7 I2C-bus slave address Device selection depends on the I2C-bus slave address. Four different I2C-bus slave addresses can be used to address the PCA9620 (see Table 32). Table 32. I2C slave address Slave address Bit 7 6 5 4 3 2 1 MSB slave address 0 0 LSB 1 1 1 0 A1 A0 R/W The least significant bit of the slave address byte is bit R/W. Bit 1 and bit 2 of the slave address are defined by connecting the inputs A0 and A1 to either VSS (logic 0) or VDD (logic 1). Therefore, four instances of PCA9620 can be distinguished on the same I2C-bus. 8.8 I2C-bus protocol R/W = 0 slave address control byte A A C R S 0 1 1 1 0 0 A 1 0 O S RAM/command byte M A S B L S P B EXAMPLES a) transmit two bytes of RAM data S 0 1 1 1 0 A A 0 A 0 1 1 0 A RAM DATA A A COMMAND A 0 0 A COMMAND A P A COMMAND A 0 1 A RAM DATA A RAM DATA A P b) transmit two command bytes S 0 1 1 1 0 A A 0 A 1 0 1 0 c) transmit one command byte and two RAM date bytes S 0 1 1 1 0 A A 0 A 1 0 1 0 RAM DATA A P 013aaa293 Fig 47. I2C-bus protocol write mode PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 51 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates The I2C-bus protocol is shown in Figure 47. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the four PCA9620 slave addresses available. All PCA9620’s with the corresponding A1 and A0 level acknowledge in parallel to the slave address, but all PCA9620 with the alternative A1 and A0 levels ignore the whole I2C-bus transfer. After acknowledgement, a control byte follows which defines if the next byte is RAM or command information. The control byte also defines if the next byte is a control byte or further RAM or command data. Table 33. Control byte description Bit Symbol 7 CO 6 Value Description continue bit 0 last control byte 1 control bytes continue RS register selection 0 command register 1 5 to 0 - data register - not relevant MSB 7 6 5 4 CO RS 3 2 1 LSB 0 not relevant mgl753 Fig 48. Control byte format In this way it is possible to configure the device and then fill the display RAM with little overhead. The display bytes are stored in the display RAM at the address specified by the data pointer. The acknowledgement after each byte is made only by the (A0 and A1) addressed PCA9620. After the last display byte, the I2C-bus master issues a STOP condition (P). Alternatively a START may be issued to RESTART an I2C-bus access. In case that a temperature readout (byte TD[7:0]) is made the R/W bit must be logic 1 and then the next data byte following is provided by the PCA9620 as shown in Figure 49. R/W = 1 slave address S 0 1 1 1 0 temperature readout byte M A A 1 A S 1 0 B acknowledge from PCA9620 L S A P B acknowledge from master 013aaa294 Fig 49. I2C-bus protocol read mode PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 52 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 9. Internal circuitry VDD1 A0, A1, T1, T2, CLK T3, VLCD, SDA, SCL, VDD1, VDD2 VSS VLCD VSS BP0 to BP7, S0 to S59 VSS 013aaa295 Fig 50. Device protection diagram PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 53 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 10. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. Table 34. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDD1 supply voltage 1 analog and digital −0.5 +6.5 V VDD2 supply voltage 2 charge pump −0.5 +6.5 V IDD1 supply current 1 analog and digital −50 +50 mA IDD2 supply current 2 charge pump −50 +50 mA VLCD LCD supply voltage −0.5 +10 V IDD(LCD) LCD supply current −50 +50 mA Vi input voltage −0.5 +6.5 V II input current −10 +10 mA VO output voltage on pins S0 to S59, BP0 to BP7 −0.5 +10 V on pins SDA, CLK −0.5 +6.5 V IO output current −10 +10 mA ISS ground supply current −50 +50 mA Ptot total power dissipation - 400 mW P/out power dissipation per output - 100 mW VESD electrostatic discharge voltage HBM [1] - ±4000 V CDM [2] - ±1500 V latch-up current [3] - 100 mA Tstg storage temperature [4] −65 +150 °C Tamb ambient temperature −40 +105 °C Ilu [1] PCA9620 Product data sheet on pins CLK, SDA, SCL, A0, A1, T1, T2, T3 operating device Pass level; Human Body Model (HBM), according to Ref. 6 “JESD22-A114”. [2] Pass level; Charged-Device Model (CDM), according to Ref. 7 “JESD22-C101”. [3] Pass level; latch-up testing according to Ref. 8 “JESD78” at maximum ambient temperature (Tamb(max)). [4] According to the NXP store and transport requirements (see Ref. 10 “NX3-00092”) the devices have to be stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products divergent conditions are described in that document. All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 54 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 11. Static characteristics Table 35. Static characteristics VDD1 = 2.5 V to 5.5 V; VDD2 = 2.5 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = −40 °C to +105 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 2.5 - 5.5 V 2.5 - 5.5 V 2.5 - 9.0 V Tamb = −40 °C to −10 °C −100 - +100 mV Tamb = −10 °C to +70 °C −70 - +70 mV Supplies VDD1 supply voltage 1 VDD2 supply voltage 2 VDD2 ≥ VDD1 LCD supply voltage VLCD ≥ VDD2 [1] VLCD = 5.0 V to 9.0 V [2] VLCD ΔVLCD LCD voltage variation Tamb = +70 °C to +105 °C −100 - +100 mV - 1.0 3.0 μA 200 μA IDD(pd) power-down mode supply on pin VDD1 current [3][4] IDD1 supply current 1 [4][5] - 100 IDD2 supply current 2 charge pump off; external VLCD [4][5] - 0.5 3.0 μA charge pump on; internal VLCD [4][6] - 250 550 μA external VLCD [4][7] - 125 250 μA [3][4] - 12 35 μA IDD(LCD) LCD supply current fosc = 9.6 kHz ILCD(pd) power-down LCD current external VLCD RO output resistance of charge pump (driving capabilities) Tacc temperature accuracy charge pump set to 2 × VDD2; Iload = 3 mA (on pin VLCD) [8] 0.2 0.85 1.6 kΩ charge pump set to 3 × VDD2; Iload = 2 mA (on pin VLCD) [9] 2.0 3.2 4.5 kΩ Tamb = −40 °C to +105 °C −6 - +6 °C Tamb = 27 °C −4 - +4 °C readout temperature error; VDD1 = 5.0 V Logic VSS − 0.5 - VDD + 0.5 V on pins CLK, A1, A0 - 0.3VDD V on pins CLK, A1, A0 0.7VDD - - V −0.5 - VDD + 0.5 V HIGH-level output voltage on pin CLK 0.8VDD - - V VOL LOW-level output voltage - - 0.2VDD V IOH HIGH-level output current output source current; VOH = 4.6 V; VDD = 5 V; on pin CLK 1 - - mA IOL LOW-level output current 1 - - mA VPOR power-on reset voltage [10] - - 1.6 V IL leakage current [11] - 0 - μA VI input voltage VIL LOW-level input voltage VIH HIGH-level input voltage VO output voltage VOH PCA9620 Product data sheet on pin CLK output sink current; VOL = 0.4 V; VDD = 5 V; on pin CLK Vi = VDD or VSS; on pins CLK, A1, A0, T1, T2, T3 All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 - © NXP B.V. 2010. All rights reserved. 55 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates Table 35. Static characteristics …continued VDD1 = 2.5 V to 5.5 V; VDD2 = 2.5 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = −40 °C to +105 °C; unless otherwise specified. Symbol I2C-bus; Parameter Conditions Min Typ Max Unit pins SDA and SCL VI input voltage VSS − 0.5 - 5.5 V VIL LOW-level input voltage pins SCL, SDA - - 0.3VDD V VIH HIGH-level input voltage pins SCL, SDA 0.7VDD - - V VO output voltage pins SCL, SDA −0.5 - 5.5 V IOL LOW-level output current VOL = 0.4 V; VDD = 5 V; on pin SDA 3 - - mA IL leakage current VI = VDD or VSS [11] - 0 - μA output voltage variation on pins BP0 to BP7 [12] −15 - +15 mV on pins S0 to S59 [13] −15 - +15 mV VLCD = 7 V; on pins BP0 to BP7 [14] 0.3 0.8 1.5 kΩ VLCD = 7 V; on pins S0 to S59 [14] 0.6 1.5 3 kΩ LCD outputs ΔVO output resistance RO [1] When supplying external VLCD it must be VLCD ≥ VDD2. Also when using the internal charge pump to generate a certain VLCD, VPR[7:0] must be set to a value that the voltage is higher than VDD2 (see Section 7.4.3 on page 31). [2] Calibrated at testing stage with VDD1 = VDD2 = 5.0 V. VLCD temperature compensation is disabled. [3] Display is disabled; I2C-bus inactive; temperature measurement disabled. [4] The typical value is defined at VDD1 = VDD2 = 5.0 V, VLCD = 7.0 V and 30 °C. [5] Temperature measurement enabled; 1:8 multiplex drive mode; 1⁄4 bias; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; internal clock with the default prescale factor; I2C-bus inactive. [6] VDD2 = 5.0 V; charge pump set to 2 × VDD2; VPR[7:0] set for VLCD = 7.0 V; 1:8 multiplex drive mode; 1⁄4 bias; temperature measurement enabled; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. [7] External supplied VLCD = 7.0 V; 1:8 multiplex drive mode; 1⁄4 bias; temperature measurement enabled; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. [8] VDD2 = 5.0 V; charge pump set to 2 × VDD2; VPR[7:0] set for VLCD = 9.0 V; display disabled; CPF (see Table 22 on page 11) set logic 0. [9] VDD2 = 4.0 V; charge pump set to 3 × VDD2; VPR[7:0] set for VLCD = 9.0 V; display disabled; CPF (see Table 22 on page 11) set logic 0. [10] If VDD1 > VPOR then no reset occurs. [11] In case of an ESD event, the value may increase slightly. [12] Variation between any 2 backplanes on a given voltage level; static measured. [13] Variation between any 2 segments on a given voltage level; static measured. [14] Outputs measured one at a time. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 56 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 001aan026 8.3 VLCD (V) (3) 7.8 7.3 (1) 6.8 6.3 (2) 5.8 −50 0 50 100 150 temperature (°C) (1) VPR[7:0] = 85h. (2) VPR[7:0] = 64h. (3) VPR[7:0] = A4h. Temperature compensation disabled. Fig 51. Typical VLCD with respect to temperature 001aan023 120 IDD1 (μA) 100 80 60 −40 0 40 80 120 temperature (°C) VDD1 = 5.0 V. Fig 52. Typical IDD1 with respect to temperature PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 57 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 001aan024 300 IDD2 (μA) 260 220 180 140 100 −40 0 40 80 120 temperature (°C) Charge pump set to 2 × VDD2; VLCD = 7.0 V; VDD1 = VDD2 = 5.0 V. Fig 53. Typical IDD2 with respect to temperature 001aan025 140 ILCD (μA) 120 100 80 −40 0 40 80 120 temperature (°C) VLCD = 7.0 V, external supplied; VDD1 = VDD2 = 5.0 V; display enabled, but no display attached. Fig 54. Typical ILCD with respect to temperature PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 58 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 12. Dynamic characteristics Table 36. Dynamic characteristics VDD1 = 2.5 V to 5.5 V; VDD2 = 2.5 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = −40 °C to +105 °C; unless otherwise specified. Symbol Parameter fosc oscillator frequency fclk(ext) external clock frequency tclk(H) HIGH-level clock time tclk(L) LOW-level clock time Conditions on pin CLK; see Table 17 on page 9 [1][2] external clock source used Min Typ Max Unit 8160 9600 11040 Hz 450 - 14500 Hz 33 - - μs 33 - - μs Timing characteristics: I2C-bus[3] fSCL SCL frequency - - 400 kHz tBUF bus free time between a STOP and START condition 1.3 - - μs tHD;STA hold time (repeated) START condition 0.6 - - μs tSU;STA set-up time for a repeated START condition 0.6 - - μs tVD;DAT data valid time [4] - - 0.9 μs tVD;ACK data valid acknowledge time [5] - - 0.9 μs tLOW LOW period of the SCL clock 1.3 - - μs tHIGH HIGH period of the SCL clock 0.6 - - μs tf fall time of both SDA and SCL signals - - 0.3 μs tr rise time of both SDA and SCL signals - - 0.3 μs Cb capacitive load for each bus line - - 400 pF tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - - ns tSU;STO set-up time for STOP condition 0.6 - - μs tw(spike) spike pulse width - - 50 ns [1] Internal calibration made with OTP so that the maximum variation is ±15 % over whole temperature and voltage range. The typical fosc generates a typical frame frequency of 200 Hz when the default frequency division factor is used (see Section 7.5.3 on page 39). [2] The typical value is defined at VDD1 = VDD2 = 5.0 V and 30 °C. [3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. [4] tVD;DAT = minimum time for valid SDA output following SCL LOW. [5] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 59 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 1/fclk tclk(H) tclk(L) 0.7 VDD CLK 0.3 VDD 013aaa296 Fig 55. Driver timing waveforms protocol START condition (S) tSU;STA bit 7 MSB (A7) tLOW bit 6 (A6) tHIGH bit 0 (R/W) acknowledge (A) STOP condition (P) 1/f SCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO 013aaa417 Fig 56. I2C-bus timing waveforms PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 60 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 13. Package outline LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1 c y X A 60 41 40 Z E 61 e E HE A A2 (A 3) A1 w M θ bp Lp L pin 1 index 80 21 detail X 20 1 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.9 12.1 11.9 0.5 HD HE 14.15 14.15 13.85 13.85 L Lp v w y 1 0.75 0.30 0.2 0.15 0.1 Z D (1) Z E (1) θ 1.45 1.05 7 o 0 1.45 1.05 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT315-1 136E15 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 57. Package outline SOT315-1 (LQFP80) PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 61 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 62 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 58) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 37 and 38 Table 37. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 38. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 58. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 63 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 58. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 64 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 15. Abbreviations Table 39. PCA9620 Product data sheet Abbreviations Acronym Description AEC Automotive Electronics Council CDM Charged-Device Model DC Direct Current EPROM Erasable Programmable Read-Only Memory ESD ElectroStatic Discharge HBM Human Body Model I2C Inter-Integrated Circuit bus IC Integrated Circuit LCD Liquid Crystal Display LSB Least Significant Bit MSB Most Significant Bit MSL Moisture Sensitivity Level MUX Multiplexer OTP One Time Programmable PCB Printed-Circuit Board POR Power-On Reset RC Resistance-Capacitance RAM Random Access Memory RMS Root Mean Square SCL Serial CLock line SDA Serial DAta line SMD Surface Mount Device All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 65 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 16. References [1] AN10365 — Surface mount reflow soldering description [2] AN10853 — ESD and EMC sensitivity of IC [3] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [4] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [5] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [6] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [7] JESD22-C101 — Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components [8] JESD78 — IC Latch-Up Test [9] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [10] NX3-00092 — NXP store and transport requirements [11] SNV-FA-01-02 — Marking Formats Integrated Circuits [12] UM10204 — I2C-bus specification and user manual PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 66 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 17. Revision history Table 40. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9620 v.1 20101209 Product data sheet - - PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 67 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be PCA9620 Product data sheet suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 68 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 69 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 7.1 Commands of PCA9620 . . . . . . . . . . . . . . . . . . 5 7.1.1 Command: initialize . . . . . . . . . . . . . . . . . . . . . 5 7.1.2 Command: OTP-refresh . . . . . . . . . . . . . . . . . . 6 7.1.3 Command: oscillator-ctrl . . . . . . . . . . . . . . . . . . 6 7.1.4 Command: charge-pump-ctrl . . . . . . . . . . . . . . 7 7.1.5 Command: temp-msr-ctrl . . . . . . . . . . . . . . . . . 7 7.1.6 Command: set-VPR-MSB and set-VPR-LSB . . 7 7.1.7 Command: display-enable . . . . . . . . . . . . . . . . 8 7.1.8 Command: set-MUX-mode . . . . . . . . . . . . . . . . 8 7.1.9 Command: set-bias-mode . . . . . . . . . . . . . . . . 8 7.1.10 Command: load-data-pointer . . . . . . . . . . . . . . 8 7.1.11 Command: frame-frequency . . . . . . . . . . . . . . . 9 7.1.12 Bank select commands . . . . . . . . . . . . . . . . . 10 7.1.12.1 Command: input-bank-select . . . . . . . . . . . . . 10 7.1.12.2 Command: output-bank-select . . . . . . . . . . . . 10 7.1.13 Command: write-RAM-data . . . . . . . . . . . . . . 11 7.1.14 Command: temp-read. . . . . . . . . . . . . . . . . . . 11 7.1.15 Command: invmode_CPF_ctrl . . . . . . . . . . . . 11 7.1.16 Command: temp-filter . . . . . . . . . . . . . . . . . . . 12 7.2 Possible display configurations . . . . . . . . . . . 12 7.3 Start-up and shut-down. . . . . . . . . . . . . . . . . . 14 7.3.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . 14 7.3.2 Recommended start-up sequences . . . . . . . . 16 7.3.3 Recommended power-down sequences . . . . 18 7.4 LCD voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.4.1 LCD voltage selector . . . . . . . . . . . . . . . . . . . 20 7.4.1.1 Electro-optical performance . . . . . . . . . . . . . . 22 7.4.2 LCD drive mode waveforms . . . . . . . . . . . . . . 23 7.4.2.1 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 23 7.4.2.2 1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 24 7.4.2.3 1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 26 7.4.2.4 1:6 Multiplex drive mode. . . . . . . . . . . . . . . . . 27 7.4.2.5 1:8 Multiplex drive mode. . . . . . . . . . . . . . . . . 29 7.4.3 VLCD generation . . . . . . . . . . . . . . . . . . . . . . . 31 7.4.4 External VLCD supply . . . . . . . . . . . . . . . . . . . 32 7.4.5 Charge pump driving capability . . . . . . . . . . . 33 7.4.6 Charge pump frequency settings and power efficiency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.4.7 7.4.8 7.5 7.5.1 7.5.2 7.5.3 7.6 7.7 7.8 7.9 7.9.1 7.9.1.1 7.9.1.2 7.9.1.3 7.9.1.4 7.9.1.5 7.9.2 7.9.2.1 7.9.2.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 18 18.1 18.2 18.3 18.4 Temperature readout . . . . . . . . . . . . . . . . . . . Temperature compensation of VLCD . . . . . . . . Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal oscillator . . . . . . . . . . . . . . . . . . . . . . External clock. . . . . . . . . . . . . . . . . . . . . . . . . Timing and frame frequency . . . . . . . . . . . . . Backplane outputs . . . . . . . . . . . . . . . . . . . . . Segment outputs . . . . . . . . . . . . . . . . . . . . . . Display register . . . . . . . . . . . . . . . . . . . . . . . Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . RAM filling in static drive mode . . . . . . . . . . . RAM filling in 1:2 multiplex drive mode . . . . . RAM filling in 1:4 multiplex drive mode . . . . . RAM filling in 1:6 multiplex drive mode . . . . . RAM filling in 1:8 multiplex drive mode . . . . . Bank selection . . . . . . . . . . . . . . . . . . . . . . . . Input-bank-select . . . . . . . . . . . . . . . . . . . . . . Output-bank-select. . . . . . . . . . . . . . . . . . . . . I2C-bus interface characteristics . . . . . . . . . . Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . START and STOP conditions. . . . . . . . . . . . . System configuration . . . . . . . . . . . . . . . . . . . Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C-bus slave address . . . . . . . . . . . . . . . . . . I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics. . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 35 36 38 38 38 39 39 40 40 40 41 42 43 43 44 45 46 47 48 49 49 49 49 50 51 51 51 51 53 54 55 59 61 62 62 62 62 63 65 66 67 68 68 68 68 69 continued >> PCA9620 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 December 2010 © NXP B.V. 2010. All rights reserved. 70 of 71 PCA9620 NXP Semiconductors Universal LCD driver for low multiplex rates 19 20 Contact information. . . . . . . . . . . . . . . . . . . . . 69 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 9 December 2010 Document identifier: PCA9620