EVB-LAN9252-DIGIO
EtherCAT® Evaluation Board
User’s Guide
2014-2015 Microchip Technology Inc.
DS50002332B
Note the following details of the code protection feature on Microchip devices:
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Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck,
MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and
UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK,
MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial
Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2014-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
EtherCAT® is registered trademark and patented technology, licensed by Beckhoff Automation GmbH, Germany.
ISBN: 97816312773739
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS50002332B-page 2
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2014-2015 Microchip Technology Inc.
Object of Declaration: EVB-LAN9252-DIGIO
2014-2015 Microchip Technology Inc.
Preliminary
DS50002332B-page 3
EVB-LAN9252-DIGIO User’s Guide
NOTES:
DS50002332B-page 4
Preliminary
2014-2015 Microchip Technology Inc.
EVB-LAN9252-DIGIO
USER’S GUIDE
Table of Contents
Preface ........................................................................................................................... 6
Introduction............................................................................................................ 6
Document Layout .................................................................................................. 6
Conventions Used in this Guide ............................................................................ 7
The Microchip Web Site ........................................................................................ 8
Development Systems Customer Change Notification Service ............................ 8
Customer Support ................................................................................................. 8
Document Revision History ................................................................................... 9
Chapter 1. Overview
1.1 Introduction ................................................................................................... 10
1.2 References ................................................................................................... 11
1.3 Terms and Abbreviations ............................................................................. 11
Chapter 2. Board Details & Configuration
2.1 Power ........................................................................................................... 12
2.1.1 +5V Power ................................................................................................. 12
2.2 Resets .......................................................................................................... 12
2.2.1 Power-on Reset ......................................................................................... 12
2.3 Clock ............................................................................................................ 12
2.4 Configuration ................................................................................................ 13
2.4.1 Strap Options ............................................................................................ 14
2.4.2 LED Indicators ........................................................................................... 16
2.4.3 EEPROM Switch ....................................................................................... 17
2.4.4 DIG INPUT Mode ...................................................................................... 17
2.4.5 DIG OUTPUT Mode .................................................................................. 17
2.4.6 DIG Bidirectional Mode ............................................................................. 18
2.4.7 Control Signals .......................................................................................... 18
2.5 Mechanicals ................................................................................................. 19
Chapter 3. LAN9252 EEPROM Programming
3.1 Programming the LAN9252 EEPROM ......................................................... 20
Appendix A. EVB-LAN9252-DIGIO Evaluation Board
A.1 Introduction .................................................................................................. 23
Appendix B. EVB-LAN9252-DIGIO Evaluation Board Schematics
B.1 Introduction .................................................................................................. 24
Appendix C. Bill of Materials (BOM)
C.1 Introduction .................................................................................................. 32
Worldwide Sales and Service .................................................................................... 36
2014-2015 Microchip Technology Inc.
DS50002332B-page 5
EVB-LAN9252-DIGIO
USER’S GUIDE
Preface
NOTICE TO CUSTOMERS
All documentation becomes dated, and this manual is no exception. Microchip tools and
documentation are constantly evolving to meet customer needs, so some actual dialogs
and/or tool descriptions may differ from those in this document. Please refer to our web site
(www.microchip.com) to obtain the latest documentation available.
Documents are identified with a “DS” number. This number is located on the bottom of each
page, in front of the page number. The numbering convention for the DS number is
“DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the
document.
For the most up-to-date information on development tools, see the MPLAB® IDE online help.
Select the Help menu, and then Topics to open a list of available online help files.
INTRODUCTION
This chapter contains general information that will be useful to know before using the
EVB-LAN9252-DIGIO. Items discussed in this chapter include:
•
•
•
•
•
•
Document Layout
Conventions Used in this Guide
The Microchip Web Site
Development Systems Customer Change Notification Service
Customer Support
Document Revision History
DOCUMENT LAYOUT
This document describes how to use the EVB-LAN9252-DIGIO as a development tool for the
Microchip LAN9252 EtherCAT® slave controller. The manual layout is as follows:
• Chapter 1. “Overview” – Shows a brief description of the EVB-LAN9252-DIGIO.
• Chapter 2. “Board Details & Configuration” – Includes details and instructions for using
the EVB-LAN9252-DIGIO.
• Chapter 3. “LAN9252 EEPROM Programming” – Includes details and instructions for
programming the LAN9252 EEPROM.
• Appendix A. “EVB-LAN9252-DIGIO Evaluation Board” – This appendix shows the
EVB-LAN9252-DIGIO.
• Appendix B. “EVB-LAN9252-DIGIO Evaluation Board Schematics” – This appendix
shows the EVB-LAN9252-DIGIO schematics.
• Appendix C. “Bill of Materials (BOM)” – This appendix includes the
EVB-LAN9252-DIGIO Bill of Materials (BOM).
2014-2015 Microchip Technology Inc.
DS50002332B-page 6
Preface
CONVENTIONS USED IN THIS GUIDE
This manual uses the following documentation conventions:
DOCUMENTATION CONVENTIONS
Description
Arial font:
Italic characters
Represents
Examples
Referenced books
Emphasized text
A window
A dialog
A menu selection
A field name in a window or
dialog
A menu path
MPLAB® IDE User’s Guide
...is the only compiler...
the Output window
the Settings dialog
select Enable Programmer
“Save project before build”
A dialog button
A tab
A number in verilog format,
where N is the total number of
digits, R is the radix and n is a
digit.
A key on the keyboard
Click OK
Click the Power tab
4‘b0010, 2‘hF1
Italic Courier New
Sample source code
Filenames
File paths
Keywords
Command-line options
Bit values
Constants
A variable argument
Square brackets [ ]
Optional arguments
Curly brackets and pipe
character: { | }
Ellipses...
Choice of mutually exclusive
arguments; an OR selection
Replaces repeated text
#define START
autoexec.bat
c:\mcc18\h
_asm, _endasm, static
-Opa+, -Opa0, 1
0xFF, ‘A’
file.o, where file can be
any valid filename
mcc18 [options] file
[options]
errorlevel {0|1}
Initial caps
Quotes
Underlined, italic text with
right angle bracket
Bold characters
N‘Rnnnn
Text in angle brackets < >
Courier New font:
Plain Courier New
Represents code supplied by
user
2014-2015 Microchip Technology Inc.
File>Save
Press <Enter>, <F1>
var_name [,
var_name...]
void main (void)
{ ...
}
DS50002332B-page 7
EVB-LAN9252-DIGIO USER’S GUIDE
THE MICROCHIP WEB SITE
Microchip provides online support via our web site at www.microchip.com. This web site is used
as a means to make files and information easily available to customers. Accessible by using your
favorite Internet browser, the web site contains the following information:
• Product Support – Data sheets and errata, application notes and sample programs,
design resources, user’s guides and hardware support documents, latest software releases
and archived software
• General Technical Support – Frequently Asked Questions (FAQs), technical support
requests, online discussion groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press
releases, listing of seminars and events, listings of Microchip sales offices, distributors and
factory representatives
DEVELOPMENT SYSTEMS CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products.
Subscribers will receive e-mail notification whenever there are changes, updates, revisions or
errata related to a specified product family or development tool of interest.
To register, access the Microchip web site at www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
The Development Systems product group categories are:
• Compilers – The latest information on Microchip C compilers, assemblers, linkers and
other language tools. These include all MPLAB C compilers; all MPLAB assemblers
(including MPASM assembler); all MPLAB linkers (including MPLINK object linker); and all
MPLAB librarians (including MPLIB object librarian).
• Emulators – The latest information on Microchip in-circuit emulators.This includes the
MPLAB REAL ICE and MPLAB ICE 2000 in-circuit emulators.
• In-Circuit Debuggers – The latest information on the Microchip in-circuit debuggers. This
includes MPLAB ICD 3 in-circuit debuggers and PICkit 3 debug express.
• MPLAB IDE – The latest information on Microchip MPLAB IDE, the Windows Integrated
Development Environment for development systems tools. This list is focused on the
MPLAB IDE, MPLAB IDE Project Manager, MPLAB Editor and MPLAB SIM simulator, as
well as general editing and debugging features.
• Programmers – The latest information on Microchip programmers. These include production programmers such as MPLAB REAL ICE in-circuit emulator, MPLAB ICD 3 in-circuit
debugger and MPLAB PM3 device programmers. Also included are nonproduction development programmers such as PICSTART Plus and PIC-kit 2 and 3.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for
support. Local sales offices are also available to help customers. A listing of sales offices and
locations is included in the back of this document.
Technical support is available through the web site at: http://www.microchip.com/support
DS50002332B-page 8
2014-2015 Microchip Technology Inc.
Preface
DOCUMENT REVISION HISTORY
Revision
DS50002332B (05-12-15)
DS50002332A
Section/Figure/Entry
Correction
All
Updated board name to “EVB-LAN9252-DIGIO”
throughout document, corrected misc. typos and
grammatical errors.
Section 1.2 “References”
Updated list of application notes
Initial Release of document
2014-2015 Microchip Technology Inc.
DS50002332B-page 9
EVB-LAN9252-DIGIO
USER’S GUIDE
Chapter 1. Overview
1.1
INTRODUCTION
The LAN9252 is a 2-port EtherCAT® slave controller with dual integrated Ethernet
PHYs which each contain a full-duplex 100BASE-TX transceiver and support 100Mbps
(100BASE-TX) operation. 100BASE-FX is supported via an external fiber transceiver.
Each port receives an EtherCAT® frame, performs frame checking and forwards it to
the next port. Time stamps of received frames are generated when they are received.
The Loop-back function of each port forwards the frames to the next logical port if there
is either no link at a port, if the port is not available, or if the loop is closed for that port.
The Loop-back function of port 0 forwards the frames to the EtherCAT® Processing
Unit. The loop settings can be controlled by the EtherCAT® master.
Packets are forwarded in the following order:
Port 0 -> EtherCAT® Processing Unit -> Port 1 -> Port 2.
The EtherCAT® Processing Unit (EPU) receives, analyzes and processes the EtherCAT® data stream. The main purpose of the EtherCAT® Processing unit is to enable
and coordinate access to the internal registers and the memory space of the ESC,
which can be addressed both from the EtherCAT® master and from the local application. Data exchange between master and slave applications is comparable to a
dual-ported memory (process memory), enhanced by special functions for consistency
checking (SyncManager) and data mapping (FMMU). Each FMMU performs bitwise
mapping of logical EtherCAT® system addresses to physical device addresses.
The scope of this document is to describe the EVB-LAN9252-DIGIO setup, which supports a Digital I/O PDI Interface and corresponding jumper configurations. The
LAN9252 is connected to an RJ45 Ethernet jack with integrated magnetics for
100BASE-TX connectivity. A simplified block diagram of the EVB-LAN9252-DIGIO is
shown in Figure 1-1.
2014-2015 Microchip Technology Inc.
DS50002332B-page 10
Overview
FIGURE 1-1:
EVB-LAN9252-DIGIO BLOCK DIAGRAM
EVB-LAN9252-DIGIO
Digital I/O Circuit
15
Switches
8 7
Switches
0
Jumper Selection
15
LEDs
8 7
LEDs
0
Control
Signals
EEPROM
Power
Supply
Module
Microchip
LAN9252
Straps
Oscillator
Port 0
FiberSFP
Port 0
100BASE-TX
Ethernet
Magnetics &
RJ45
Ethernet
1.2
5V
Port 1
100BASE-TX
Ethernet
Magnetics &
RJ45
FiberSFP
Port 1
Ethernet
REFERENCES
Concepts and material available in the following documents may be helpful when reading this document. Visit www.microchip.com for the latest documentation.
•
•
•
•
•
1.3
LAN9252 Data Sheet
AN 8.13 Suggested Magnetics
EVB-LAN9252-DIGIO Schematics
AN1920 Microchip LAN9252 EEPROM Configuration and Programming
AN1907 Microchip LAN9252 Migration from Beckhoff ET1100
TERMS AND ABBREVIATIONS
IDE - Integrated Development Environment
ESC - EtherCAT® Slave Controller
EVB - Engineering Validation Board
HAL - Hardware Abstraction Layer
HBI - Host Bus Interface
SPI - Serial Protocol Interface
SSC - Slave Stack Code
2014-2015 Microchip Technology Inc.
DS50002332B-page 11
EVB-LAN9252-DIGIO
USER’S GUIDE
Chapter 2. Board Details & Configuration
This section includes sub-sections on the following EVB-LAN9252-DIGIO details:
•
•
•
•
•
2.1
Power
Resets
Clock
Configuration
Mechanicals
POWER
2.1.1
+5V Power
Power is supplied to the LAN9252 by a +3.3V on-board regulator, which is powered by
a +5V external wall adapter (Manufacturer: TRIAD MAGNETICS and P/N:
WSU050-3000). The LAN9252 includes an internal +1.2V regulator which supplies
power to the internal core logic. Assertion of the D1 Green LED indicates successful
generation of +3.3V output. The SW1 switch must be in the ON position for the +5V to
power the +3.3V regulator.
2.2
RESETS
2.2.1
Power-on Reset
A power-on reset occurs whenever power is initially applied to the LAN9252 or if the
power is removed and reapplied to the LAN9252. This event resets all circuitry within
the LAN9252. After initial power-on, the LAN9252 can be reset by pressing the reset
switch SW2. The reset LED D2 will assert (Red) if when the LAN9252 is in reset condition. For stability, a delay of approximately 180ms is added from the +3.3V output to
reset release.
2.3
CLOCK
The EVB-LAN9252-DIGIO utilizes an external 25Mhz 25ppm crystal from Cardinal
Components Inc. (P/N: CSM1Z-A5B2C5-40-25.0D18-F).
2014-2015 Microchip Technology Inc.
DS50002332B-page 12
Board Details & Configuration
2.4
CONFIGURATION
The following sub-sections describe the various board features and configuration settings. A top view of the EVB-LAN9252-DIGIO is shown in Figure 2-1.
FIGURE 2-1:
EVB-LAN9252-DIGIO TOP VIEW WITH CALLOUTS
Digital Output
LEDs
Reset
Microchip
LAN9252
Power
Straps
EEPROM
Digital I/O
Control Signals
Input Switches
Port 0
2014-2015 Microchip Technology Inc.
RJ45
Port 1
(with Magnetics)
DS50002332B-page 13
EVB-LAN9252-DIGIO User’s Guide
2.4.1
Strap Options
2.4.1.1
CHIP MODE SELECTION
Table 2-1 details the LAN9252 chip mode configuration straps.
TABLE 2-1:
CHIP MODE CONFIGURATION STRAP
Header
Description
Pins
Settings
J4,J5,J7,J8
Chip mode configuration strap
inputs. This strap determines
the number of active ports and
port types.
1-2
Short 1-2 for high (pull-up)
(Not supported in this EVB)
Short 2-3 for low (pull-down) (default)
Note:
2.4.1.2
2-3
This EVB supports Chip mode 00 which is 2-port mode, where Port 0 = PHY
A and Port 1 = PHY B. This requires J4, J5, J7, and J8 to be pulled-down
(2-3) shorted. All other configurations are not supported by this EVB.
EEPROM SIZE CONFIGURATION
The EEPROM size configuration strap (J6 & J9) determines the supported EEPROM
size range. A low selects 1Kbits (128 x 8) through 16Kbits (2K x 8)_24C16. A high
selects 32Kbits (4K x 8) through 512Kbits (64K x 8) or 4Mbits (512K x 8)_24C512.
TABLE 2-2:
EEPROM SIZE CONFIGURATION STRAP
Header
Description
Pins
J6, J9
EEPROM size configuration
strap inputs. This strap determines the supported
EEPROM size range.
1-2
2-3
2.4.1.3
Settings
Short 1-2 for high (pull-up) (default)
Short 2-3 for low (pull-down)
COPPER AND FIBER STRAPS
The LAN9252 supports 100BASE-TX (Copper) and 100BASE-FX (Fiber) modes. In
100BASE-FX operation, the presence of the receive signal is indicated by the external
transceiver as either an open-drain, CMOS level, Loss of Signal (SFP) or a LVPECL
Signal Detect (SFF).
This EVB supports 100BASE-TX (Copper) and SFP 100BASE-FX (Fiber) modes. By
default Copper Mode is active. Fiber Mode is supported as an assembly option. To
select the Copper or Fiber Mode, the respective strap and signal routing resister
assembly options must to be configured.
Note:
DS50002332B-page 14
Vendor part number for SFP: Finisar/FTLF1217P2
2014-2015 Microchip Technology Inc.
Board Details & Configuration
2.4.1.3.1
Copper Mode
The EVB-LAN9252-DIGIO is set to Copper Mode by default. Table 2-3 details the
required strap resistor settings for Copper Mode operation.
TABLE 2-3:
COPPER MODE STRAP RESISTORS
Resistors
Description
R79 (10K)
Configures Port 0 & 1 to Copper Mode
R76, R80 (10K)
Configures Port 0 and Port 1 to Copper Mode, respectively
Note:
R75, R77, and R78 must not be populated (DNP).
Additionally, the signal routing resistors detailed in Table 2-4 must be assembled for
Copper Mode operation.
TABLE 2-4:
COPPER MODE SIGNAL ROUTING RESISTORS
Resistors
Description
R17, R19, R21, R23
Port 0 Copper Mode enabled
R31, R33, R35, R37
Port 1 Copper mode enabled
Note:
R16, R18, R20, R22, R30, R32, R34, and R36 (0402 package) must not be
populated (DNP).
2.4.1.3.2
Fiber Mode
The EVB-LAN9252-DIGIO supports SFP type 100BASE-FX. To enable Fiber Mode,
the respective strap and signal routing resistors must be configured.
Note:
Copper Mode related resistors must be DNP while Fiber Mode is active
(See Section 2.4.1.3.1 “Copper Mode”).
Table 2-5 details the required strap resistor settings for Fiber Mode operation.
TABLE 2-5:
FIBER MODE STRAP RESISTORS
Resistors
Description
R77 (10K)
Configures Port 0 & 1 to FX-LOS Mode
R75, R78 (10K)
Configures Port 0 and Port 1 to Fiber Mode, respectively
Note:
R76, R79, and R80 must not be populated (DNP).
Additionally, the signal routing resistors detailed in Table 2-6 must be assembled for
Fiber Mode operation.
TABLE 2-6:
FIBER MODE SIGNAL ROUTING RESISTORS
Resistors
Description
R16, R18, R20, R22
Port 0 Fiber Mode enabled
R30, R32, R34, R36
Port 1 Fiber mode enabled
Note:
R17, R19, R21, R23, R31, R33, R35, and R37 (0402 package) must not be
populated (DNP).
2014-2015 Microchip Technology Inc.
DS50002332B-page 15
EVB-LAN9252-DIGIO User’s Guide
2.4.1.3.3
FX-LOS Fiber Mode Strap
FX-LOS strap details are shown in Table 2-7. These strap settings determine if the
ports are to operate in FX-LOS Fiber Mode or FX-SD/Copper Mode.
TABLE 2-7:
FX-LOS MODE STRAP SETTINGS
R77 (10K)
R79 (10K)
Reference
Voltage (V)
Populate
DNP
3.3
A level above 2V selects FX-LOS for Port 0 and
Port 1
Populate
Populate
1.5
A level greater than 1.5V and below 2V selects
FX-LOS for Port 0 and FX-SD / copper twisted
pair for Port 1, further determined by FXSDB
DNP
Populate
0 (Default)
Note:
2.4.2
Function
A level of 0V selects FX-SD / copper twisted pair
for Ports 0 and 1, further determined by FXSDA
and FXSDB
The above strap details describe the LAN9252 function. This EVB does not
support SFF Fiber Mode. Therefore, FX-SD related straps are not applicable.
LED Indicators
The D3 and D4 LEDs are used to indicate the Link/Activity status on the corresponding
EVB ports, as detailed in Table 2-8. The Link/Act LED should be ON at each port when
the cable is present. If the Link/Act LED is not ON, it indicates there is an issue with the
connection or cable.
TABLE 2-8:
D3 AND D4 LINK/ACTIVITY LED STATUS INDICATORS
State
Off
Description
Link is down
Flashing Green
Link is up with activity
Steady Green
Link is up with no activity
Additionally, the D5 LED is used as a RUN indicator (green) to show the AL status of
the EtherCAT® State Machine (ESM), as detailed in Table 2-9.
TABLE 2-9:
D5 RUN LED STATUS INDICATOR
State
Off
DS50002332B-page 16
Description
The device is in the INITIALIZATION state
Blinking (on 200ms, off 200ms)
The device is in the PRE-OPERATIONAL state
Single Flash (on 200ms, off 1000ms)
The device is in the SAFE-OPERATIONAL state
On
The device is in the OPERATIONAL state
Flickering (on 50ms, off 50ms)
The device is booting and has not yet entered
the INITIALIZATION state, or the device is in the
BOOTSTRAP state and firmware download is in
progress. (Optional. Off when not implemented.)
2014-2015 Microchip Technology Inc.
Board Details & Configuration
2.4.3
EEPROM Switch
The EVB-LAN9252-DIGIO utilizes 0x50 (7-bit) I2C slave addressing. The SW3 switch
can be used to select the A0, A1, and A2 address bits, as shown in Figure 2-2 and
Table 2-10. The eighth bit of the slave address determines if the master device wants
to read or write to the EEPROM (24C512).
FIGURE 2-2:
SLAVE ADDRESS ALLOCATION
Start
1
Read/Write
0
1
0
A2
A1
A0 R/W
A
Slave Address
TABLE 2-10:
Switch
Description
SW3
2.4.4
EEPROM SWITCH
Settings
I2C EEPROM address selection switch ON for logic 0 (default)
(A0, A1, A2). See Figure 2-2.
OFF for logic 1
DIG INPUT Mode
The DIG INPUT Mode can be selected through the headers J10 and J11:
• Logic 1 : (Default) SW4 & SW5 Off position. DIG I/P 0 to 15 tied to pull-up (R98 to
R113)
• Logic 0 : The respective knob of 2-way, 8-position dip switch (SW4 & SW5) need
to be moved to ON position. Signals can be selected individually.
TABLE 2-11:
DIGITAL I/O INPUT MODE SELECTION
Header
Description
Short Pins
J10
Digital Input 0 to 7
1&2, 4&5, 7&8, 10&11, 13&14, 16&17, 19&20, 22&23
J11
Digital Input 8 to 15
1&2, 4&5, 7&8, 10&11, 13&14, 16&17, 19&20, 22&23
2.4.5
DIG OUTPUT Mode
The DIG OUTPUT Mode can be selected through the headers J10 and J11. The
updated Digital I/O values can be seen on the LEDs (D6 to D21):
• Logic 1 : LED illuminated
• Logic 0 : LED not illuminated.
Note:
LED (D6 to D21) anode connected to ASIC.
TABLE 2-12:
Header
DIGITAL I/O OUTPUT MODE SELECTION (DEFAULT MODE)
Description
Short Pins
J10
Digital I/O 0 to 7
2&3, 5&6, 8&9, 11&12, 14&15, 17&18, 20&21, 23&24
J11
Digital I/O 8 to 15
2&3, 5&6, 8&9, 11&12, 14&15, 17&18, 20&21, 23&24
Note:
The control signal OE_EXT should be connected high by shorting J12 pins
15 and 16.
2014-2015 Microchip Technology Inc.
DS50002332B-page 17
EVB-LAN9252-DIGIO User’s Guide
2.4.6
DIG Bidirectional Mode
The DIG Bidirectional Mode can be selected by shorting the respective test point pins
with the headers J10 and J11, as detailed in Table 2-13. The input and output signal
states in this mode are the same as detailed in Section 2.4.4 “DIG INPUT Mode” and
Section 2.4.5 “DIG OUTPUT Mode”.
TABLE 2-13:
DIGITAL I/O BIDIRECTIONAL MODE DESCRIPTION
Description
Short Pins
Digital I/O 0 to 7
TP5 & J10.1, TP6 & J10.4, TP7 & J10.7, TP8 & J10.10 TP9 & J10.13,
TP10 & J10.16, TP11 & J10.19, TP12 & J10.22, TP13&J10.3,
TP14&J10.6, TP15&J10.9, TP16& J10.12, TP17&J10.15,
TP18&J10.18, TP19& J10.21, TP20&J10.24
Digital I/O 8 to 15
TP21 & J11.1, TP22 & J11.4, TP23 & J11.7, TP24 & J11.10, TP25 &
J11.13, TP26 & J11.16, TP27 & J11.19, TP28 & J11.22, TP29&J11.3,
TP30&J11.6, TP31&J11.9, TP32& J11.12, TP33&J11.15,
TP34&J11.18,TP35& J11.21, TP36&J11.24
2.4.7
Control Signals
All control signals can be probed and controlled via the J12 header, as shown in
Table 2-14.
TABLE 2-14:
J12 HEADER CONTROL SIGNAL MAPPING
J12 Pin Number
Note:
2.4.7.1
J12 Signal
J12 Pin Number
J12 Signal
1
3V3
2
3V3
3
WD_STATE
4
GND
5
EOF
6
GND
7
SOF
8
GND
9
LATCH0
10
GND
11
LATCH1
12
GND
13
WD_TRIG
14
GND
15
OE_EXIT
16
3V3
17
OUTVALID
18
GND
19
LATCH_IN
20
GND
J12 pins 15 & 16 must be shorted in output mode.
WD_STATE
This pin is the SyncManager Watchdog State output. A “0” indicates the watchdog has
expired. The state of this signal can be seen in the LED D22.
Note:
2.4.7.2
This signal is not driven (high impedance) until the EEPROM is loaded.
LATCH_IN
This pin is the external data latch signal. The input data is sampled each time a rising
edge of LATCH_IN is recognized. By default, this signals is pulled high through
R131and can be made low using switch SW6.
DS50002332B-page 18
2014-2015 Microchip Technology Inc.
Board Details & Configuration
2.5
MECHANICALS
FIGURE 2-3:
2014-2015 Microchip Technology Inc.
EVB-LAN9252-DIGIO MECHANICAL DIMENSIONS
DS50002332B-page 19
EVB-LAN9252-DIGIO
USER’S GUIDE
Chapter 3. LAN9252 EEPROM Programming
3.1
PROGRAMMING THE LAN9252 EEPROM
The LAN9252 configures itself to the desired mode (SPI, 6 HBI modes) by reading the
strap settings located in EEPROM. The LAN9252 EEPROM is programmed and validated via the TwinCAT master tool. The programming procedure is as follows:
Note 1:
This example utilizes the TwinCAT tool. Procedures may differ when using
other EtherCAT® master tools.
2:
Ensure the system network properties are configured properly for the EtherCAT® frames, Ethernet cable linking your system, and EtherCAT® slave
board.
1. Load the corresponding ESI file in the directory path “C:\TwinCAT\Io\EtherCAT”.
For this demo, the ESI file for the 16-Bit Multiplexed Single-Phase Mode is used.
2. If TwinCAT installed successfully, a TwinCAT icon will be shown in the bottom-right corner of the desktop. After clicking the icon, a pop-up list will display.
Select “System Manager”, as shown in Figure 3-1.
FIGURE 3-1:
2014-2015 Microchip Technology Inc.
TWINCAT SYSTEM MANAGER
DS50002332B-page 20
LAN9252 EEPROM Programming
3. If any devices are present, delete them accordingly by clicking the device and
selecting “Delete Device”, as shown in Figure 3-2.
FIGURE 3-2:
TWINCAT DELETE DEVICE
4. Scan for EtherCAT® slave devices by clicking “I/O devices” and selecting “Scan
Devices”, as shown in Figure 3-3.
FIGURE 3-3:
2014-2015 Microchip Technology Inc.
TWINCAT SCAN DEVICES
DS50002332B-page 21
EVB-LAN9252-DIGIO User’s Guide
5. After scanning is complete, the right panel of the TwinCAT window will appear as
shown in Figure 3-4.
FIGURE 3-4:
TWINCAT DEVICE LIST
6. After a successful scan, click the “Device 2 (EtherCAT)” drop down bar on the left
panel of the TwinCAT tool (as highlighted in Figure 3-4). Then click the “Online”
tab on the right-side panel of the TwinCAT tool, as shown in Figure 3-5. Right
click the LAN9252 listing and select “EEPROM Update” from the contextual
menu.
FIGURE 3-5:
TWINCAT EEPROM UPDATE
7. Upon selecting “EEPROM Update”, the Write EEPROM window will open. Click
the “OK” button to initiate EEPROM programming.
FIGURE 3-6:
DS50002332B-page 22
TWINCAT WRITE EEPROM
2014-2015 Microchip Technology Inc.
EVB-LAN9252-DIGIO
USER’S GUIDE
Appendix A. EVB-LAN9252-DIGIO Evaluation Board
A.1
INTRODUCTION
This appendix shows the EVB-LAN9252-DIGIO Evaluation Board.
FIGURE A-1:
EVB-LAN9252-DIGIO EVALUATION BOARD
2014-2015 Microchip Technology Inc.
DS50002332B-page 23
EVB-LAN9252-DIGIO
USER’S GUIDE
Appendix B. EVB-LAN9252-DIGIO Evaluation Board
Schematics
B.1
INTRODUCTION
This appendix shows the EVB-LAN9252-DIGIO Evaluation Board Schematics.
2014-2015 Microchip Technology Inc.
DS50002332B-page 24
EVB-LAN9252-DIGIO SCHEMATIC POWER SUPPLY & RESET
5
4
3
2
1
D
D
POWER SUPPLY
FB1
2
5V_SW
3
EN12_1
2A/0.05DCR
2
R1
Switch, SPDT, Slide
P/N:1101M2S3CQE2
J1
2
1
0E
C2
10uF
25V
VIN
ENABLE
VOUT
TRIM
3_Amp
GND
C3
4
5
3
OKR-T/3-W12-C
0.1uF
R2
VOUT_3V3
1K
DNP
C1
R3
3.30K
1%
R4
470E
1%
(Ra)
(Rb)
R4A
33E
1%
C4
C5
10uF
0.1uF
4.7uF
1
1
A
5V_EXT
3
D1
GRN
C
1
3V3
3V3
U1
"3V3 Present"
SW1
TP2
ORANGE
3 V REGULATOR, 3A
( 3V3 fixed when Rb=470E)
2
TP1
RED
5V
C
C
RESET Options
Preliminary
3V3
3V3
3V3
Reset Generator
2
B
RESET
NDS355AN_NMOS
1
D
RST#
Q1
3
R8
1K
1
G
5
RESET#
2
3V3
MR#
3
4
5
U2
2
1/10W
1%
VDD
1
R7
100
GND
SW2
sw_pb_2P
R5
4.75K
1%
0.1uF
2
1
C6
R6
10.0K
1/10W
1%
Note:
1.POR -> Reset to ASIC & SOC (Default)
2.RESET O/P from ASIC -> Reset to EX-PHY (PORT2) & SOC :Only Ethercat sku
3.RESET from SOC (GPIO/RST-O/P) -> Reset to ASIC
4.RESET from Push Botton -> Reset to ASIC & SOC
RED
U3
S
2
4
1
R9
TPS3125
2.2K
74LVC1G14
C
B
2
D2
"Reset"
1
3
SOT23_5
Threshold = 2.64V
Delay = 180ms
A
2014-2015 Microchip Technology Inc.
A
A
TP3
BLACK
TP4
BLACK
Chennai
India
Part Number:
EVB-LAN9252-DIGIO
Size:
Project
Name:LAN9252
Date:
5
4
3
2
B
Page:
Board
Name:
Power Supply & RST
Rev
EVB-LAN9252-DIGIO
Sheet
Friday, April 24, 2015
1
3
of
B
9
EVB-LAN9252-DIGIO User’s Guide
DS50002332B-page 25
FIGURE B-1:
EVB-LAN9252-DIGIO SCHEMATIC LAN9252 PT1
5
4
3
2
1
Power Supply Filtering
3V3
VDD33TXRX1
3V3
FB2
D
C25
0.1uF
C20
C21
C22
470pF
0.1uF
0.1uF
C19
1uF
C16
C14
C15
C17
0.1uF
0.1uF
0.1uF
C12
DNP
C11
C10
FB5
2A/0.05DCR
BLM18EG221SN1D
56
59
6
24
38
14
20
32
37
47
58
5
U4A
51
64
VDD12TX1
VDD12TX2
0.1uF
1.0uF
Low ESR
2A/0.05DCR
BLM18EG221SN1D
C24
C18
DNP
C23
0.1uF
TP72
SMT
VDDCR
0.1uF
2A/0.05DCR
3V3
0.1uF
3V3
FB4
1.0uF
VDD33TXRX2
FB3
0.1uF
3V3
0.1uF
0.1uF
C13
C8
DNP
C9
1.0uF
VDDCR
VDD12TX1
VDD12TX2
1.0uF
D
DNP
C7
VDD33TXRX1
VDD33TXRX2
2A/0.05DCR
18pF
REG_EN
R10
12.1K
1%
RBIAS
RST#
TP71
WHITE
DNP
IRQ
ATEST/FXLOSEN
7
57
11
44
8
41
B
I2C2_SCL
I2C2_SDA
43
42
GPIO0
GPIO1
GPIO2
48
46
45
VDD12TX1
VDD12TX2
VDDCR1
VDDCR2
VDDCR3
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
FXSDENA/FXSDA/FXLOSA
INT PORT0
C27
OSCVDD12
OSCI
OSCO
OSCVSS
REG_EN
RBIAS
RST#
TXNA
TXPA
RXNA
RXPA
9
FXSDA/FXLOSA
52
53
54
55
TXNA
TXPA
RXNA
RXPA
63
62
61
60
TXNB
TXPB
RXNB
RXPB
10
FXSDB/FXLOSB
IRQ
ATEST/FXLOSEN
TESTMODE
I2CSCL/EESCL/TCK
I2CSDA/EESDA/TMS
INT PORT1
(Only for
Lan9252)
1
3
1
2
4
I2C
OSCI
OSCO
3V3
OTHER
SIGNALS
Preliminary
25.000MHz
25ppm
Y1
OSC
POWER
18pF
2
C26
VDD33BIAS
VDD33
C
Note:
OSCVSS need to connect to Chip gnd.
VDD33TXRX1
VDD33TXRX2
C
TXNB
TXPB
RXNB
RXPB
FXSDENB/FXSDB/FXLOSB
B
LINKACTLED0/TDO/LEDPOL0/CHIP_MODE0
LINKACTLED1/TDI/LEDPOL1/CHIP_MODE1
RUNLED/LEDPOL2/E2PSIZE
GND
GPIO
65
LAN9252
A
A
DS50002332B-page 26
Chennai
India
Part Number:
EVB-LAN9252-DIGIO
Size:
Project
Name:LAN9252
Date:
5
4
3
2
B
Page:
Board
Name:
LAN9252 (Part1)
Rev
EVB-LAN9252-DIGIO
Sheet
Friday, April 24, 2015
1
4
of
B
9
EVB-LAN9252-DIGIO Evaluation Board Schematics
2014-2015 Microchip Technology Inc.
FIGURE B-2:
EVB-LAN9252-DIGIO SCHEMATIC COPPER MODE INTERFACE
5
4
3
2
1
VDD33TXRX1
0E
0E
FX_SFP-RXPA
RXNA
DNP
R22
R23
3
FX_SFP-RXNA
A
75
4&5
TD-
2
RCV
5
0E
0E
10
C
COP-RXPA
75
TXCT
6
COP-RXNA
DNP
C29
10pF
50V
5%
DNP
C30
10pF
50V
5%
DNP
C31
10pF
50V
5%
C32
0.022uF
50V
10%
7
8
75
3
75
7&8
RXCT
6
RD-
1000 pF
NC
CHS GND
13
C
14
GND
DNP
C28
10pF
50V
5%
RD+
Preliminary
Note:
Capacitors C28 through C31 are optional for EMI purposes
and are not populated on the LAN9252 evaluation board.
These capacitors are required for operation in an EMI
constrained environment.
2 kV
YEL
R24
C
A1
DNP
R20
R21
2
12
RXPA
4
COP-TXNA
D
1
C1
FX_SFP-TXNA
RJ45
XMIT
TD+
11
0E
0
GRN
1
COP-TXPA
MTG1
DNP
R18
R19
TXNA
R15
0E
MTG
FX_SFP-TXPA
R14
49.9
1/10W
1%
16
0E
0E
R13
49.9
1/10W
1%
15
DNP
R16
R17
TXPA
R12
49.9
1/10W
1%
GND1
D
T1
Pulse J0011D01BNL
R11
49.9
1/10W
1%
9
PORT0
0E
RES1210
VDD33TXRX2
PORT1
2
COP-RXPB
3
9
B
1
TXCT
4&5
TD-
2
DNP
C35
10pF
50V
5%
DNP
C36
10pF
50V
5%
C37
0.022uF
50V
10%
7
8
75
6
RD-
1000 pF
NC
CHS GND
A
3
7&8
2 kV
YEL
A
A1
DNP
C34
10pF
50V
5%
GND
DNP
C33
10pF
50V
5%
75
RXCT
12
6
COP-RXNB
RD+
C1
FX_SFP-RXNB
RJ45
RCV
5
0E
0E
75
11
FX_SFP-RXPB
COP-TXNB
75
MTG1
0E
0
FX_SFP-TXNB
A
C
4
0E
0
TD+
MTG
RXNB
DNP
R36
R37
1
COP-TXPB
16
DNP
R34
R35
GRN
XMIT
13
2014-2015 Microchip Technology Inc.
RXPB
FX_SFP-TXPB
R29
0E
15
DNP
R32
R33
TXNB
0E
0E
R28
49.9
1/10W
1%
GND1
TXPB
R27
49.9
1/10W
1%
14
DNP
R30
R31
B
R26
49.9
1/10W
1%
10
T2
Pulse J0011D01BNL
R25
49.9
1/10W
1%
Chennai
India
Note:
Capacitors C33 through C36 are optional for EMI purposes
and are not populated on the LAN9252 evaluation board.
These capacitors are required for operation in an EMI
constrained environment.
R38
0E
RES1210
Part Number:
EVB-LAN9252-DIGIO
Size:
Project
Name:LAN9252
Date:
5
4
3
2
B
Page:
Board
Name:
Copper Mode Interface
Rev
EVB-LAN9252-DIGIO
Sheet
Friday, April 24, 2015
1
5
of
B
9
EVB-LAN9252-DIGIO User’s Guide
DS50002332B-page 27
FIGURE B-3:
EVB-LAN9252-DIGIO SCHEMATIC SFP INTERFACE
5
4
3V3
R39
82
D
R40
82
R41
49.9
R42
49.9
3
Note:Place
capacitors,
and resistors
close to FOT
3V3
Fiber Port 0 :SFP Interface
R43
82
FX_SFP-RXNA
C38
0.1uF
FX_SFP-RXPA
C40
0.1uF
FX_SFP-TXPA
C42
0.1uF
R44
82
R45
49.9
2
1
Note:Place
capacitors,
and resistors
close to FOT
Fiber Port 1 :SFP Interface
R46
49.9
FX_SFP-RXNB
C39
0.1uF
FX_SFP-RXPB
C41
0.1uF
FX_SFP-TXPB
C43
0.1uF
D
R47
100
3V3
R48
3V3
SFP_VCCT
SFP_VCCT2
100
0.1uF
SFP_VCCR
C45
+
C47
C48
10uF
16V
0.1uF
+
0.1uF
1uH
C49
0.1uF
R51
130
SFP_VCCR2
SFP_TD2SFP_TD2+
R50
130
SFP_RD+
SFP_RD-
R49
130
SFP_TDSFP_TD+
FX_SFP-TXNB
C46
10uF
16V
DNP
L1
1uH
R52
130
C50
10uF
16V
DNP
SFP_RD2+
SFP_RD2-
C44
FX_SFP-TXNA
L2
+
C51
C52
10uF
16V
0.1uF
L3
L4
B
R53
4.7K
R54
4.7K
C55
VeeT1
TDTD+
VeeT2
VccT
VccR
VeeR2
RD+
RDVeeR3
+
Note:Place
resistors
close to
0.1uF
ASIC
J3
FTLF1217P2
R55
4.7K
VeeT
TXFault
TX Disable
MOD-DEF(2)
MOD-DEF (1)
MOD-DEF (0)
Rate Select
LOS
VeeR
VeeR1
C54
10uF
16V
31
30
29
28
27
26
25
24
23
22
21
31
30
29
28
27
26
25
24
23
22
21
C56
10uF
16V
+
C57
0.1uF
SFP_VCCT2
1
2
3
4
5
6
7
8
9
10
SFP_VCCT
31
30
29
28
27
26
25
24
23
22
21
1uH
1
2
3
4
5
6
7
8
9
10
VeeT1
TDTD+
VeeT2
VccT
VccR
VeeR2
RD+
RDVeeR3
J2
FTLF1217P2
VeeT
TXFault
TX Disable
MOD-DEF(2)
MOD-DEF (1)
MOD-DEF (0)
Rate Select
LOS
VeeR
VeeR1
ASIC
31
30
29
28
27
26
25
24
23
22
21
0.1uF
C
20
19
18
17
16
15
14
13
12
11
Preliminary
Note:Place
resistors
close to
C53
1uH
20
19
18
17
16
15
14
13
12
11
C
+
R57
4.7K
R56
4.7K
FXSDA/FXLOSA
R58
4.7K
R59
4.7K
B
R60
4.7K
FXSDB/FXLOSB
A
A
DS50002332B-page 28
Chennai
India
Part Number:
EVB-LAN9252-DIGIO
Size:
Project
Name:LAN9252
Date:
5
4
3
2
B
Page:
Board
Name:
SFP Interface
Rev
EVB-LAN9252-DIGIO
Sheet
Friday, April 24, 2015
1
6
of
B
9
EVB-LAN9252-DIGIO Evaluation Board Schematics
2014-2015 Microchip Technology Inc.
FIGURE B-4:
EVB-LAN9252-DIGIO SCHEMATIC STRAP, GPIO, I2C & FXLOS
5
4
3
2
1
GPIO [0:2] & LED_POL_Strap
3V3
R68
8
VCC
SDA
SCL
WP
SW DIP-4/SM
24FC512
5
I2C2_SDA
6
I2C2_SCL
TH IC.
Different sizes can be mounted
GPIO2
I2C EEPROM Lower size
Below 16K(2K X 8) (24FC04)
3
1
J8
3
1
R67
R66
7
A0
A1
A2
GND
1
2
3
I2C2_1
I2C2_2
I2C2_3
I2C2_7
2
2
2
GPIO0
2K
R65
4.7K
1
2
3
4
4
8
7
6
5
R74
1K
J9
3
1
C
2K
R64
4.7K
U5
SW3
2
2
2
LED1_CATHODE
R73
1K
0.1uF
D
2
R71
10.0K
'HIDXOW$OOVLJQDOV21
J7
C58
LED1_ANODE
1
1
R70
10.0K
LED0_CATHODE
LED2_CATHODE
R72
1K
3V3
GPIO2
J5
2
2
1
LED0_ANODE
LED2_ANODE
R69
10.0K
GPIO1
3
1
J6
3V3
GPIO0
R63
J4
I2C EEPROM
3V3
GPIO1
3
1
3
1
D
GPIO2
4.7K
3V3
GPIO0
4.7K
3V3
6LJQDOV)XQFWLRQV
GPIO1
C
*3,2 /,1.$&7/('7'2/('32/&+,3B02'(
I2C EEPROM Higher size
Above 16K(2K X 8) (24FC512 )
*3,2 /,1.$&7/('7',/('32/&+,3B02'(
*3,2 581/('/('32/(36,=(
Preliminary
LINK/ACT for PORT0
LED0_ANODE
LED0_CATHODE
D3 1
GRN A
2
&+,3B02'(>@6WUDS'HWDLOV
C
LINK/ACT for PORT1
LED1_ANODE
LED1_CATHODE
D4 1
GRN A
2
C
&+,3B02'(>@
3RUW'HVFULSWLRQ
>'HIDXOW@
3RUW 3+<$
3RUW 3+<%
RUNLED
LED2_ANODE
LED2_CATHODE
D5 1
GRN A
2
C
B
5(6(59('
3RUW
3RUW
3RUW
3RUW
3RUW
3RUW
3257
'2:1675($002'(
3+<$
3+<%
0,,
0,,
3+<%
3+<$
3V3
325702'(
5(6(59('
FX_Mode_Strap_1 & 2
FX_Los_Strap_1 & 2
02'(
DNP
R77
10K
FXSDA/FXLOSA
3257
83675($002'(
R79
10K
FXSDB/FXLOSB
&+,3B02'(
2014-2015 Microchip Technology Inc.
&+,3B02'(
(36,=(
A
R76
10K
DNP
R78
10K
R80
10K
3V3
B
/('3RODULW\6WUDS
&RQQHFWRU
--
'HIDXOW
--
7KH/('LVVHWDVDFWLYHORZ
5
5
--
'HIDXOW
7KH/('LVVHWDVDFWLYHKLJK
3RXSXODWH
'13
9
$ERYH9VHOHFWV);/26IRUSRUWVDQG
--
7KH/('LVVHWDVDFWLYHORZ
3RXSXODWH
9
--
--
'HIDXOW
3RXSXODWH
'HIDXOW
/HYHORI9VHOHFWV);/26IRUSRUWDQG
);6'FRSSHUWZLVWHGSDLUIRUSRUW
IXUWKHUGHWHUPLQHGE\);6'%
/HYHORI96HOHFWV);6'FRSSHUWZLVWHGSDLU
IRUSRUWV$DQG%
IXUWKHUGHWHUPLQHGE\);6'$DQG);6'%
/RJLF
10K
ATEST/FXLOSEN
Strap Details
6LJQDO1DPH
3V3
DNP
R75
7KH/('LVVHWDVDFWLYHKLJK
3RXSXODWH
7KH/('LVVHWDVDFWLYHKLJK
((35206L]H .ELWV[WKURXJK.ELWV.[
7KH/('LVVHWDVDFWLYHORZ
((35206L]H .ELWV.[WKURXJK.ELWV.[RU0ELWV.[/$1RQO\
>'HIDXOW@
'13
'HIDXOW
5HI9ROWDJH
'HIDXOW
)XQFWLRQ
3257
02'(
3257
&RSSHU
'HIDXOW
)LEHU
3257
&RSSHU
'HIDXOW
)LEHU
3RXSXODWH
'13
5
5
5
5
5
5
5
5
Note:
--To use GPIOs as LED
* Short 2-3 of both jumpers (ex. for GPIO0 short 2-3 of J4 & J7)
A
Chennai
India
Part Number:
EVB-LAN9252-DIGIO
Size:
Project
Name:LAN9252
Date:
5
4
3
2
B
Page:
Board
Name:
STRAP,GPIO,I2C & FXLOS
Rev
EVB-LAN9252-DIGIO
Sheet
Friday, April 24, 2015
1
7
of
B
9
EVB-LAN9252-DIGIO User’s Guide
DS50002332B-page 29
FIGURE B-5:
EVB-LAN9252-DIGIO SCHEMATIC LAN9252 PT2
5
4
3
2
1
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
DIG-IO
D
D
19
OUTVALID
C
1
20
A0
A1
A2
A3
A4
A5
A6
A7
DIR
VCC
U6
2
3
4
5
6
7
8
9
DIGIO0
DIGIO1
DIGIO2
DIGIO3
DIGIO4
DIGIO5
DIGIO6
DIGIO7
OE
3V3
18
17
16
15
14
13
12
11
OUT_BUF_DIGIO0
OUT_BUF_DIGIO1
OUT_BUF_DIGIO2
OUT_BUF_DIGIO3
OUT_BUF_DIGIO4
OUT_BUF_DIGIO5
OUT_BUF_DIGIO6
OUT_BUF_DIGIO7
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
U4B
A4/DIGIO12/GPI12/GPO12/MII_RXD0
A3/DIGIO11/GPI11/GPO11/MII_RXDV
A2/ALEHI/DIGIO10/GPI10/GPO10/LINKACTLED2/MII_LINKPOL/LEDPOL6
A1/ALELO/OE_EXT/MII_CLK25
10
74LC245A/SO
B0
B1
B2
B3
B4
B5
B6
B7
GND
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
R81
R82
R83
R84
R85
R86
R87
R88
3V3
DIGIO15
DIGIO14
DIGIO13
31
30
28
Preliminary
OUTVALID
19
1
20
A0
A1
A2
A3
A4
A5
A6
A7
DIR
VCC
U7
2
3
4
5
6
7
8
9
DIGIO8
DIGIO9
DIGIO10
DIGIO11
DIGIO12
DIGIO13
DIGIO14
DIGIO15
OE
74LC245A/SO
B0
B1
B2
B3
B4
B5
B6
B7
18
17
16
15
14
13
12
11
OUT_BUF_DIGIO8
OUT_BUF_DIGIO9
OUT_BUF_DIGIO10
OUT_BUF_DIGIO11
OUT_BUF_DIGIO12
OUT_BUF_DIGIO13
OUT_BUF_DIGIO14
OUT_BUF_DIGIO15
18
LATCH0
34
SYNC/LATCH1
SYNC/LATCH0
A0/D15/AD15/DIGIO9/GPI9/GPO9/MII_RXER
D14/AD14/DIGIO8/GPI8/GPO8/MII_TXD3/TX_SHIFT1
D13/AD13/DIGIO7/GPI7/GPO7/MII_TXD2/TX_SHIFT0
D12/AD12/DIGIO6/GPI6/GPO6/MII_TXD1
D11/AD11/DIGIO5/GPI5/GPO5/MII_TXD0
D10/AD10/DIGIO4/GPI4/GPO4/MII_TXEN
D9/AD9/LATCH_IN/SCK
D8/AD8/DIGIO2/GPI2/GPO2/MII_MDIO
D7/AD7/DIGIO1/GPI1/GPO1/MII_MDC
D6/AD6/DIGIO0/GPI0/GPO0/MII_RXCLK
D5/AD5/OUTVALID/SCS#
D4/AD4/DIGIO3/GPI3/GPO3/MII_LINK
D3/AD3/WD_TRIG/SIO3
D2/AD2/SOF/SIO2
D1/AD1/EOF/SO/SIO1
D0/AD0/WD_STATE/SI/SIO0
DIGIO9
DIGIO8
DIGIO7
DIGIO6
DIGIO5
DIGIO4
LATCH_IN
DIGIO2
DIGIO1
DIGIO0
OUTVALID
DIGIO3
WD_TRIG
SOF
EOF
WD_STATE
LAN9252
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
B
GND
B
LATCH1
33
15
16
21
22
23
19
40
39
36
50
49
35
12
13
17
C
10
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
R90
R91
R92
R93
R94
R95
R96
R97
3V3
DIGIO12
DIGIO11
DIGIO10
OE_EXT
RD/RD_WR/DIGIO15/GPI15/GPO15/MII_RXD3
WR/ENB/DIGIO14/GPI14/GPO14/MII_RXD2
CS/DIGIO13/GPI13/GPO13/MII_RXD1
TP21
TP22
TP23
TP24
TP25
TP26
TP27
TP28
R89
10K
27
26
29
25
Note: Placement Instruction
Place the TPs in 100 mil distance from the respective IN_DIGIOx or OUT_DIGIOx PINS of J10 & J11
Placement should be such a way that, jumpers should be able to
added between the test points and J10 or J11 connectors
A
A
DS50002332B-page 30
Chennai
India
Part Number:
Size:
Date:
5
4
3
2
B
EVB-LAN9252-DIGIO
Project
Name:LAN9252
Page:
Board
Name:
LAN9252-Part2
Rev
EVB-LAN9252-DIGIO
Sheet
Friday, April 24, 2015
1
8
of
B
9
EVB-LAN9252-DIGIO Evaluation Board Schematics
2014-2015 Microchip Technology Inc.
FIGURE B-6:
EVB-LAN9252-DIGIO SCHEMATIC DIGITAL I/O
5
4
3
3
OUT_DIGIO0
IN_DIGIO1
DIGIO1
4
5
6
OUT_DIGIO1
IN_DIGIO2
DIGIO2
7
8
9
OUT_DIGIO2
IN_DIGIO3
DIGIO3
10
11
12
OUT_DIGIO3
Digital OUTPUTS
OUT_DIGIO0
OUT_DIGIO4
R98
R99
R100
R101
R102
R103
R104
R105
15
OUT_DIGIO1
OUT_DIGIO5
OUT_DIGIO2
IN_DIGIO5
DIGIO5
16
17
18
IN_DIGIO6
DIGIO6
19
20
21
IN_DIGIO7
DIGIO7
22
23
24
SW4
OUT_DIGIO6
OUT_DIGIO7
J11
3
OUT_DIGIO7
6
OUT_DIGIO9
7
8
9
OUT_DIGIO10
OUT_DIGIO11
IN_DIGIO11
DIGIO11
10
11
12
OUT_DIGIO11
IN_DIGIO12
DIGIO12
13
14
15
OUT_DIGIO12
IN_DIGIO13
DIGIO13
16
17
18
OUT_DIGIO13
IN_DIGIO14
DIGIO14
19
20
21
OUT_DIGIO14
IN_DIGIO15
DIGIO15
22
23
24
OUT_DIGIO15
R106
R107
R108
R109
R110
R111
R112
R113
OUT_DIGIO12
OUT_DIGIO14
OUT_DIGIO15
1
2
3
4
5
6
7
8
IN_DIGIO8
IN_DIGIO9
IN_DIGIO10
IN_DIGIO11
IN_DIGIO12
IN_DIGIO13
IN_DIGIO14
IN_DIGIO15
R117
R118
R119
1K
R120
1K
R121
1K
R122
1K
R123
R124
1K
R125
1K
R126
1K
OUT_DIGIO13
SW5
R116
1K
OUT_DIGIO10
10K
10K
10K
10K
10K
10K
10K
10K
Preliminary
4
5
IN_DIGIO10
DIGIO10
OUT_DIGIO9
Default: All 8 Signals OFF
3V3
IN_DIGIO9
DIGIO9
B
OUT_DIGIO6
SW DIP-8
OUT_DIGIO8
R115
1K
1K
OUT_DIGIO5
OUT_DIGIO8
1
2
IN_DIGIO8
DIGIO8
16
15
14
13
12
11
10
9
R114
1K
1K
OUT_DIGIO4
1
2
3
4
5
6
7
8
IN_DIGIO0
IN_DIGIO1
IN_DIGIO2
IN_DIGIO3
IN_DIGIO4
IN_DIGIO5
IN_DIGIO6
IN_DIGIO7
1K
1K
OUT_DIGIO3
HDR_3x8
C
D
3V3
13
14
IN_DIGIO4
DIGIO4
)RU3XOO'RZQPRYH6:6:WR21SRVLWLRQ
10K
10K
10K
10K
10K
10K
10K
10K
D
1
2
1
'HIDXOW
6:6:DUHLQ2))SRVLWLRQ3XOOXSDFWLYH
J10
IN_DIGIO0
DIGIO0
2
Digital INPUTS
1-2 side short of J10 = Input Mode (Default)
2-3 side short of J10 = Output Mode
I/P O/P
R127
1K
R128
1K
R129
D6 1
GRN
D7 1
GRN
D8 1
GRN
D9 1
GRN
D10 1
GRN
D11 1
GRN
D12 1
GRN
D13 1
GRN
D14 1
GRN
D15 1
GRN
D16 1
GRN
D17 1
GRN
D18 1
GRN
D19 1
GRN
D20 1
GRN
D21 1
GRN
2
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
2
2
2
2
2
2
2
2
2
C
2
2
2
2
2
2
16
15
14
13
12
11
10
9
SW DIP-8
HDR_3x8
B
Default: All 8 Signals OFF
1-2 side short of J11 = Input Mode (Default)
2-3 side short of J11 = Output Mode
3V3
WD_STATE
R130
DIG-IO JUMPER OPTIONS
1K
D22 1
GRN A
DIGIO0
DIGIO1
DIGIO2
DIGIO3
DIGIO4
DIGIO5
DIGIO6
DIGIO7
DIGIO8
DIGIO9
DIGIO10
DIGIO11
DIGIO12
DIGIO13
DIGIO14
DIGIO15
2
C
LED for WD_STATE
J12
4
J10 & J11
1
2
3
TP13 to 20
TP29 to 36
5
Short 1-2 = Input Mode
1
2
Short 2-3 = Output Mode
2
3
Short 1-4 & 3-5 = Bidirectional Mode
4
1
2
3
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
3V3
R131
5
100K
SW6
LATCH_IN
sw_pb_2P
Default Short:
Pins 15-16 - OE_EXT
A
10K
10K
10K
10K
10K
2014-2015 Microchip Technology Inc.
WD_STATE
EOF
SOF
LATCH0
LATCH1
WD_TRIG
OE_EXT
OUTVALID
LATCH_IN
R132
R133
R134
R135
R136
TP5 to 12
TP21 to 28
A
C59
0.1uF
Chennai
India
Part Number:
EVB-LAN9252-DIGIO
Size:
Project
Name:LAN9252
Date:
5
4
3
2
B
Page:
Board
Name:
DIG-I/O
Rev
EVB-LAN9252-DIGIO
Sheet
Friday, April 24, 2015
1
9
of
B
9
EVB-LAN9252-DIGIO User’s Guide
DS50002332B-page 31
FIGURE B-7:
EVB-LAN9252-DIGIO
USER’S GUIDE
Appendix C. Bill of Materials (BOM)
C.1
INTRODUCTION
This appendix includes the EVB-LAN9252-DIGIO Evaluation Board Bill of Materials (BOM).
2014-2015 Microchip Technology Inc.
DS50002332B-page 32
Reference
Part
Preliminary
1
2
10uF
2
18
3
1
C19
4
1
5
2
6
2
7
21
0.022uF
C32,C37
D1,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D1
GRN
5,D16,D17,D18,D19,D20,D21,D22
8
1
D2
9
5
FB1,FB2,FB3,FB4,FB5
10
1
11
6
12
2
13
1
14
1
15
3
16
22
0E
R1,R15,R29
R2,R8,R72,R73,R74,R114,R115,R116,R117,R118,R119
1K
,R120,R121,R122,R123,R124,R125,R126,
PCB Footprint
DNP
Vender
Vender Part NO
CAP0805
No
Murata
GRM21BR61E106KA73L
CAP0603
No
Murata
GRM188R71E104KA01D
1uF
CAP0603
No
Murata
GRM188R61C105KA93D
C20
470pF
CAP0603
No
Kemet
C0603C471K3RACTU
C26,C27
18pF
CAP0603
No
Murata
GRM1885C1H180JA01D
CAP0603
No
Kemet
C0603C223K5RACTU
LED0603
No
Wurth electronics
150 060 GS7 500 0
RED
LED0603
No
Wurth electronics
150 060 RS7 500 0
2A/0.05DCR
RES0603
No
Murata
BLM18EG221SN1D
SKT_PWR_2R0mm_4A_THRU_RA th_conn_pwrjack_dc-210_rt
No
Cui Stack
PJ-002AH
J4,J5,J6,J7,J8,J9
HDR_1x3
No
FCI
68000-103HLF
J10,J11
HDR_3x8
TH_CONN_3x8P
No
FCI
68000-108HLF
J12
2x10
TH_CONN_2x10P
No
FCI
67997-220HLF
Q1
NDS355AN_NMOS
sot23-NDS
No
Fairchild
NDS355AN
RES0603
No
Panasonic
ERJ-3GEY0R00V
RES0603
No
Panasonic
ERJ-3GEYJ102V
C2,C4
C3,C5,C6,C8,C10,C11,C13,C14,C15,C16,C17,C18,C21,
0.1uF
C22,C24,C25,C58,C59
J1
TH_CONN_1X3P
R127,R128,R129,R130
2014-2015 Microchip Technology Inc.
17
1
R3
3.30K
RES0603
No
Yageo America
9C06031A3301FKHFT
18
1
R4
470E
RES0603
No
BOURNS
CR0603-FX-4700ELF
19
1
R4A
33E
RES0603
No
BOURNS
CR0603-FX-33R0ELF
20
1
R5
4.75K
RES0603
No
Panasonic
ERJ-3EKF4751V
21
4
R6,R69,R70,R71
10.0K
RES0603
No
Panasonic
ERJ-3EKF1002V
22
1
R7
100
RES0603
No
Panasonic
ERJ-3EKF1000V
23
1
R9
2.2K
RES0603
No
Panasonic
ERJ-3GEYJ222V
24
1
R10
12.1K
RES0603
No
Rohm
MCR01MZPF1202
25
8
R11,R12,R13,R14,R25,R26,R27,R28
49.9
RES0603
No
Yageo America
9C06031A49R9FKHFT
26
8
R17,R19,R21,R23,R31,R33,R35,R37
0E
RES0402
No
Panasonic
ERJ-2GE0R00X
EVB-LAN9252-DIGIO User’s Guide
DS50002332B-page 33
Item Quantity
2014-2015 Microchip Technology Inc.
27
2
R24,R38
0E
28
2
29
25
2K
R67,R68
R76,R79,R80,R89,R98,R99,R100,R101,R102,R103,R10
4,R105,R106,R107,R108,R109,R110,R111,R112,R113, 10K
RES1210
No
Vishay
CRCW12100000Z0EA
RES0603
No
Panasonic
ERJ-3GEYJ202V
RES0603
No
Panasonic
ERJ-3GEYJ103V
R132,R133,R134,R135,R136
30
1
Preliminary
100K
RES0603
No
Panasonic
ERJ-3EKF1003V
31
20
4.7K
RES0603
No
Panasonic
ERJ-3EKF4701V
32
1
SW1
SW-SPDT-SLIDE
sw_ck_1101m2s3cqe2
No
C&K
1101M2S3CQE2
33
2
SW2,SW6
sw_pb_2P
sw_pb_2P
No
Panasonic
EVQ-PJU04K
34
1
SW3
SW DIP-4/SM
TH_SW_DIP4
No
Wurth electronics
418117270904
35
2
SW DIP-8
SW_DIP_SMT_8P-ade08s04
No
TE
1-1825058-9/ade08s04
36
1
TP1
RED
TH_TP_60D40
No
Keystone
5000
37
1
TP2
ORANGE
TH_TP_60D40
No
Keystone
5003
38
2
BLACK
TH_TP_60D40
No
Keystone
5001
39
32
TH_TP
No
FCI
68000-101HLF
40
2
T1,T2
Pulse - J0011D01BNL
th_conn_pulse_rj45_j0026
No
Pulse Electronics
J0011D01BNL
41
1
U1
3_Amp
TH_DC-DC_VERT_5PIN_P67
No
Murata
OKR-T/3-W12-C
42
1
U2
TPS3125
SOT23_5
No
TI
TPS3125L30DBVR
43
1
U3
74LVC1G14
SOT23_5
No
TI
SN74L VCIG14DBVR
44
1
U4
LAN9252
IC_QFN64
No
Microchip
LAN9252
45
1
U5
24FC512
IC_DIP8_300
No
Microchip
24FC512-I/P
46
2
U6,U7
74LC245A/SO
IC_SO20-MO-153
No
TI
SN74LVC245APWR
47
1
25.000MHz
XTAL_HCM49
No
Cardinal Components Inc.
CSM1Z-A5B2C5-40-25.0D18-F
SW4,SW5
TP3,TP4
TP5,TP6,TP7,TP8,TP9,TP10,TP11,TP12,TP13,TP14,TP1
5,TP16,TP17,TP18,TP19,TP20,TP21,TP22,
WHITE
TP23,TP24,TP25,TP26,TP27,TP28,TP29,TP30,
Y1
DS50002332B-page 34
Bill of Materials (BOM)
R131
R81,R82,R83,R84,R85,R86,R87,R88,R90,R91,
R92,R93,R94,R95,R96,R97,R63,R64,R65,R66
Item Quantity
Reference
Part
PCB Footprint
DNP
Vender
Vender Part NO
Preliminary
1
1
C1
4.7uF
CAP0603
DNP Murata
GRM188R60J475KE19D
2
4
C7,C9,C12,C23
1.0uF
CAP0603
DNP Murata
GRM188R61C105KA93D
3
8
C28,C29,C30,C31,C33,C34,C35,C36
10pF
CAP0402
DNP Murata
GRM1885C1H100JA01D
4
14
C38,C39,C40,C41,C42,C43,C44,C45,C47,C49,
C51,C53,C55,C57
0.1uF
CAP0603
DNP Murata
GRM188R71E104KA01D
5
6
C46,C48,C50,C52,C54,C56
10uF
CAP_B_3528
DNP Kemet
B45190E3106K209
6
2
J2,J3
FTLF1217P2
CONN_FX_SFP_FTLF1217P2
DNP Finisar
775-1011-ND
7
4
L1,L2,L3,L4
1uH
L0805
DNP
8
8
R16,R18,R20,R22,R30,R32,R34,R36
0
RES0402
DNP
9
4
R39,R40,R43,R44
82
RES0603
DNP Panasonic
ERJ-3EKF1300V
10
4
R41,R42,R45,R46
49.9
RES0603
DNP Yageo America
9C06031A49R9FKHFT
11
2
R47,R48
100
RES0603
DNP Panasonic
ERJ-3EKF1000V
12
4
R49,R50,R51,R52
130
RES0603
DNP Panasonic
ERJ-3EKF1300V
13
8
R53,R54,R55,R56,R57,R58,R59,R60
4.7K
RES0603
DNP Panasonic
ERJ-3EKF4701V
14
3
R75,R77,R78
10K
RES0603
DNP Panasonic
ERJ-3GEYJ103V
15
1
TP71
WHITE
TH_TP_60D40
DNP Keystone
5002
16
1
TP72
SMT
tp-smd40
DNP NA
NA
EVB-LAN9252-DIGIO User’s Guide
DS50002332B-page 35
Do NOT Populate components:
2014-2015 Microchip Technology Inc.
Worldwide Sales and Service
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01/27/15
DS00000A-page 36
2015 Microchip Technology Inc.