EVB USB2642 Evaluation Board Schematics, PDF

5
4
3
USB2642QFN48 Evaluation Board
2
Revision History
Evaluation Board for USB2642, 48 pin QFN
Rev.
Date
Revision Summary
Author
00A
20110621
Initial schematic based off of Tyche_A
J. Hancock
01A
20110701
Made all resistors 1%, replaced 3.3V regulator with
J. Hancock
MIC37100, removed VBUS_UP and REGEN DNP resistors,
removed I2C reference as configuration option, and added
SMBus addresses to slave devices.
D
USB2642
(48-PIN)
C
Ext. 5V supply
USB Port 1
Functional Block Diagram
USB
Upstream Port 0
1
SD/MMC4.0
Port Power
02A
20110708
Changed PRTPWR3 LED circuit.
J. Hancock
A
20110718
Renumbered and released.
J. Hancock
A1
20111116
Shorted pins 25 and 26 together (VDD33).
J. Hancock
0B
20111221
Depopulated pull-up resistor on ALERTn, populated 0Ohm J. Hancock
on ALERTn to USB chip, added RC circuit to PPWR3_H
between USB and UCS chip, added EEPROM, and wired
ESD diodes to 5V instead of VBUS on downstream ports.
B
20120105
Released.
B1
20120307
Updated SMBus address for UCS chip. Updated UCS p/n. J. Hancock
B2
20120605
Changed UCS part number to UCS81001 and changed
cap on UCS PWR_EN to 1uF. Updated Block Diagram.
D
J. Hancock
C
J. Hancock
Downstream Port 2
UCS81001 Port Power
B
SPI External
Firmware
EEPROM
SMBus / I2C I/F
(SMBus write: xAE, read xAF)
B
Downstream Port 3
SMBus I/F
Certification IC
(SMBus write: x20, read: x21)
A
A
11000 N. Mopac Expressway
Stonelake Building 6, Suite 500
Austin, TX 78759-5428
512.502.0070
Title: Evaluation Platform for USB2642,
Document Number: EVB-USB2642
Project
Size:
B
Name:
Date:
Tuesday, September 17, 2013
QFN48 pkg
EVB-USB2642
5
4
3
2
Sheet
1
1
Rev
B2
of 3
3
2
1
"PPWR2"
330.0 PWR2_LED
D1
GRN
J4
USB_A
1
PPWR2
3 VCC Jack
USBDN_DP2
D+
RA-TH
2
USBDN_DM2
D6
SL1 8
4
GND
SL2 5
SR1 7
C24
SR2
+
R2
U6
1
4
PPWR2_H
R20
10.0K
1%
ENA
ENB
MIC2026-1BM
8
OUTA 5
OUTB
5V
C43 +
C44
0.1uF
D
5V
2
3
FLAGA
FLAGB
7
6
PPWR2
1
*Cut shorting traces to use the devices indicated by an *.
BR1
C12
IN
GND
4
0.1uF
2
100uF
1%
100uF
3
L1
ESD*
DLP11SN900SL2
2
1
3
4
0.1uF
R5
2A/0.05DCR
EMI*
100.0K
1%
C7
R6
100.0K
1%
1.0uF
FB2
R1
2A/0.05DCR
EMI*
1%
C4
39
VBUS_DET
Upstream
42
43
USBUP_DM
0.1uF
USB
PRTCTL2
USBDN_DP2
USBUP_DP
330.0
VBUS_DET
USBUP_DP
USBUP_DM
USBDN_DM2
PRTCTL3
USBDN_DP3
USBDN_DM3
3V3
6
USBDN_DP2
1
USBDN_DM2
7
PPWR3_H p3
R14
ZERO
3
R4
100.0K
1%
nRESET
SPI_CE_N
SPI_CLK/GPIO4
SPI_DO&SPD_SEL/GPIO5
SPI_DI
C10
38
0.1uF
C18
18pF
45
XTAL1
RESET
L2
ESD*
DLP11SN900SL2
2
1
3
4
B
12.0K
1%
R9
GPIO1
47
RBIAS
XTAL2
SCL
GPIO1
36
46
WHITE
R19
10.0K
1%
SCL
R25
10.0K
1%
U5
SDA
SCL
Test ONLY
Do not populate
TP13
BLACK
C26
1.0uF
0.1uF
VDD18
C41
5V
DNP
1.0uF
SCL
(ss2/scl)
SDA
(ss3/sda)
nRESET (miso)
(sclk)
(ss1)
SDA
MODE0 8
MODE1 1
1
3
5
7
9
1
J7
SMBus
J8
2
4
6
8
10
(gnd)
(nc/5V)
(nc/5V)
(mosi)
(gnd)
S0
7
6
R26
10.0K
1%
GPIO1
3
SDA/MISO
SCL/MOSI
15
C42
0.1uF
D2 VBUS_UP
4
3
7
C45
RESET
3V3
DNP
SCK
SI
SO
CS
8
VCC
C39
0.1uF
WP
HOLD
4
GND
B
SPI_FLASH-25X20_SO8
nc
GND
2
5
0.1uF
Option 1: External Firmware
SPI_ROM
DNP
(SMBus write address: x20,
read address: x21)
U10
R57
DNP
10.0K
1%
(SCL)
(SDA)
5
41
48
VDDA33
C31
FB4
C27
C28
2A/0.05DCR
ISO*
C19
VDD33
(r)VDD33
VDD33
(f)VDD33
(o)VDD33
TP8
BLACK
1
2
3
6
5
DNP
A0
A1
A2
VCC
SCL
SDA
GND
flag
WP
3V3
8
7
C49
4
9
0.1uF
24C0X-DFN8
0.1uF 0.1uF 0.1uF 4.7uF
12
16
25
34
Option 3:
Configuration EEPROM, I2C
3V3
A
26 VDD33o
C33
ORANGE
TP7
C36
C40
C37
C30
0.1uF
0.1uF 0.1uF 0.1uF 4.7uF
11000 N. Mopac Expressway
Stonelake Building 6, Suite 500
Austin, TX 78759-5428
512.502.0070
C20
0.1uF
Title: Evaluation Platform for USB2642,
Document Number: EVB-USB2642
Project
Size:
B
Name:
Date:
Tuesday, September 17, 2013
B240A-13
5
4
Power
VDDA33
VDDA33
(r)VDDA33
VDD18
VCC
MODE0/SPI_CLK
MODE1/SPI_nSS
3V3
C25
C32
SPI Flash
6
5
2
1
3V3
OmegaID_SO8
VDDPLL18
TP12
YELLOW
A
29
C
R12
3V3
REGEN
VSS(FLAG)
VDD18PLL
SDA
(*Put at least 16
GND vias in the
GND FLAG.)
TP6
BLACK
22
TEST0
TEST1
TEST2
6
8
5
7
60MHz SPI I/F or
EEPROM
U4
Option 2: Certification IC
RBIAS
49
TP5
YELLOW
3V3
10.0K
3V3
SCL p3
SDA p3
40
27
28
1%
DNP
50ppm
44
0.1uF
3V3
37
1%
330.0
R13
TP14
XTAL2
100uF
XTAL1/CLKIN
24.000MHz
18pF
BGX50A
ESD
SPI_CLK/GPIO4
SPI_DO/GPIO5
SPI_DI
2
C16
4
J6
USB_A
VCC Jack
D+ RA-TH
DSL1
GND
SL2
SR1
SR2
D5
SPI_CE_EN
Misc.
Y1
R8
1Meg
8
9
10
11
330.0 PWR3_LED
GRN
C29
+
p3 USBDN_DP3_OUT
p3 USBDN_DM3_OUT
SPI I/F
3V3
"PPWR3"
4
USBDN_DM3_IN p3
TP4
DNP
BR2
2
0.1uF
R11
1%
1
PPWR3
USBDN_DP3_OUT3
USBDN_DM3_OUT2
C38
ALERTn p3
USBDN_DP3_IN p3
4
4
5V
C
*Note:
System should supply
nRESET in an embedded
hub implementation.
2
p3 PPWR3
2
C23
U2
74LVC1G14_DCK
3
4
5
6
FB3
USB2642_QFN48
1
GND
SH1
SH2
VBUS_UP
USBUP_DP
USBUP_DM
R10
D
3V3
3
VCC
D+
D-
1
3
2
U3A
Downstream
USB_B-REC
RA-THRU
UP STREAM
J3
330.0
BGX50A
ESD
5
PPWR2_H
1%
DOWN STREAM 2
4
DOWN STREAM 3
5
3
2
QFN48 pkg
EVB-USB2642
Sheet
1
2
Rev
B2
of 3
5
4
3
2
1
*Cut shorting traces to use the devices indicated by an *.
Note:
Jumper Selections marked with an asterisk (*) are default settings.
5V
J2
FB1
+
C6
J1
3
2
1
100uF
5V_EXT
DNP
2
1
5V_REG
2A/0.05DCR
3V3
MIC37100-3.3WS
U1
1
3
VIN
OUT
4.7uF
+ C11
10uF
16V
1A
C1
GND
12
3V3
C14
C17
4.7uF
1.0nF
R7
2.20K
1%
C46
0.1uF
C47
0.1uF
C48
10uF
9
10
11
UCS81001_QFN28
D
VDD
VS1
VS2
VS3
VBUS3
VBUS2
VBUS1
2
R21
R22
R23
10.0K
10.0K
10.0K
1%
1%
1%
2
5V
EM_EN
M1
M2
J10
1
1
J9
J11
C
M1
M2
24
23
USBDN_DP3_OUT p2
USBDN_DM3_OUT p2
A_DET#
ALERT#
PWR_EN
EM_EN
M1
M2
SMDATA/LATCH
SMCLK/S0
SEL
COMM_SEL/ILIM
25
18
R18
10.0K
1%
A_DETn
R27
10.0K
1%
DNP
ALERTn p2
16
17
8
7
R16
R17
1%
SDA p2
SCL p2
5V
100.0K
33.0K
3V3
0.5%
(SMBus Address: x57
[AFh (r) / AEh (w)])
2
U8
74LVC1G14_DCK
"Device Detect"
R15
4
1.00K
1%
D6
C
Bright_GRN
3
EM_EN
26
2
3
2
C50
1.0uF
13
PPWR3_UCS
3V3
DPIN
DMIN
nc1
nc2
nc3
nc4
nc5
nc6
100.0K
1
R58
2
p2 PPWR3_H
PPWR3 p2
1
14
15
21
22
28
p2 USBDN_DP3_IN
p2 USBDN_DM3_IN
GND
VSS(FLAG)
19
20
DPOUT
DMOUT
27
29
D4
ORANGE
"3.3V Power"
6
5
4
5
D
U7
3V3 Regulator
5V
USB2642_QFN48
SD_WP/GPIO6
SD_CD#/GPIO15
3V3
35
CARD_PWR/GPIO10
FB5
500mA/0.10DCR
EMI*
5
13
14
SD_WP/GPIO6
SD_nCD/GPIO15
CRD_PWR
Media I/F: SD/MMC
SD_CMD
SD_D0
SD_D1
SD_D2
SD_D3
SD_CLK
B
SD_D4
SD_D5
SD_D6
SD_D7
24
SD_CMD
2
18
17
33
32
SD_D0
SD_D1
SD_D2
SD_D3
7
8
9
1
21
SD_CLK
5
30
23
20
19
SD_D4
SD_D5
SD_D6
SD_D7
10
11
12
13
TP9
31
GPIO12
GPIO12
WHITE
20
21
J5
Normal Mount
SD/MMC4.0
(Proconn)
CMD
VCC
0.1uF
C21
C34
EMI
0.001uF
5
RED
4.7uF
CLK
D4
D5
D6
D7
14
15
DET
SD_WP
SwGND1
SwGND2
SwGND3
SwGND4
nc1
nc2
SD_CD#/GPIO15
SD_WP/GPIO6
R3
2.20K
1%
16
17
18
19
TP2
TP1
DNP
DNP
B
TP10 TP11 TP3
DNP
DNP
DNP
5V
3V3
C22
EMI
33pF
D7
D3
Bright_GRN
"Card Power"
C8
EMI
0.001uF
C13
EMI
0.001uF
C9
EMI
33pF
C5
EMI
33pF
C3
EMI
0.001uF
A
11000 N. Mopac Expressway
Stonelake Building 6, Suite 500
Austin, TX 78759-5428
512.502.0070
C2
EMI
0.1uF
SHUNT1
+ C15
DNP
100uF
1.00K
1%
CRD_PWR
3
6
GND1
GND2
3V3
CRD_PWR
CRD_PWR
4
"Alert"
R24
4
C35
D0
D1
D2
D3
Optional Devices
A
2
U9
74LVC1G14_DCK
3
U3B
4
3
2
Title: Evaluation Platform for USB2642,
Document Number: EVB-USB2642
Project
Size:
B
Name:
Date:
Thursday, September 19, 2013
QFN48 pkg
EVB-USB2642
Sheet
1
3
Rev
B2
of 3