RTL8150(M) REALTEK SINGLE-CHIP USB To FAST ETHERNET CONTROLLER WITH MII INTERFACE RTL8150L(M) 1 Features: ! RTL8150LM supports MII interface ! Supports Wake-On-LAN function and remote wakeup (Magic Packet*, LinkChg and Microsoft® wake-up frame). ! RTL8150L supports 48 pins LQFP ! RTL8150LM supports 100 pins LQFP ! Integrated Fast Ethernet MAC, Physical chip and transceiver in one chip ! Supports 10 Mb/s and 100 Mb/s N-way Auto-negotiation operation. ! Single-chip USB to Fast Ethernet controller # Compliant to USB interface ver 1.0/1.1. # Full-Speed (12 Mb/s) USB Device # Supports all USB standard commands # Supports Suspend/Resume detection logic # Supports 4 endpoints ! 1 control endpoint with maximum 8-byte packet ! 1 bulk IN endpoint with 64 bytes/packet ! 1 bulk OUT endpoint with 64 bytes/packet ! 1 interrupt IN endpoint with 8 bytes/packet 2002/2/18 Ver1.40 ! 18K bytes SRAM built in.(2k bytes for Tx buffer, and 16k bytes for Rx buffer). ! Uses 93C46 to store resource configuration, ID parameter,etc. ! Supports LED pins for various network activity indications. ! Half/Full duplex 10/100Mbps operation. ! Supports Full Duplex Flow Control (IEEE 802.3x) ! Uses 25MHz crystal as the internal clock source. ! 5 V power supply *Third-party brands and names are the property of their respective owners. 1 RTL8150(M) 2 General Description The RTL8150L controller is a 48-pin LQFP single chip that supports USB to 10/100Mbps Fast Ethernet function. To connect to Home PNA 1.0 PHY or HomePNA 2.0 PHY, the 100-pin RTL8150LM provides MII interface supporting the MII transmit clock from 0.1 MHz to 25 MHz. The Realtek RTL8150L(M) is a highly integrated and cost-effective single-chip Fast Ethernet controller that provides USB to Fast Ethernet capability, and full compliance with IEEE 802.3u 100Base-T specifications and IEEE 802.3x Full Duplex Flow Control. It also supports power management for modern operating systems that is capable of Operating System Directed Power Management (OSPM) to achieve the most efficient power management. Besides the PM feature, the RTL8150L(M) also supports remote wake-up (including AMD Magic Packet*, LinkChg, and Microsoft® wake-up frame). For sake of cost-effective, the RTL8150L(M) only requires one 25MHz crystal as its internal clock source, and requires no “glue” logic or external memory. The RTL8150L(M) keeps network maintenance cost low and eliminates usage barriers. It is the easiest way to connect a PC to the computer network without opening the cover, adding cards, reconfiguring software, or any of the other technicalities. 2002/2/18 Ver1.40 2 RTL8150(M) 25.VDD3O 26.GND 27.VDD5 28.LED2 29.LED1 30.LED0 31.GEP1 32.GEP0 33.GND 34.VDD33I 35.GND 36.VDD33 3 Pin Assignment 37.VDD5 24.VDD33I 38.DM 23.TXOP 39.DP 22.TXON 40.VDD33I 21.GND 41.GND 20.VDD33I 42.EEDO 19. RXIP RTL8150L 43.EEDI 18.RXIN 2002/2/18 Ver1.40 12.VDD33O 7. XIN 3 11.GND 13.VDD5 10.GND 48.VDD5 9. VDD33I 14.RTT3 8. XOUT 47.VDD33O 6. TEST0 15.RTT2 5. TEST1 46.GND 4. NC 16.RTSET 3. NC 45.EECS 2. NC 17.GND 1. NC 44.EESK RTL8150(M) 63 LED0 64 GEP1 65 GEP0 66 MLINK 67 MACTIVE 68 PWRSET 69 MIICOL 70 GND 71 NC 72 VDD33I 73 GND 74 NC 75 NC 76 VDD33 77 NC 78 VDD5 79 DM 80 DP 81 VDD33I 82 GND 83 T_TXC100 84 T_RXC100 85 T_VMO 86 T_VPO 87 T_OEB 88 EEDO 89 EEDI 90 EESK 91 EECS 92 TXD3 93 T_CLKIN 94 T_POR 95 T_RCV 96 T_VM 97 T_VP 98 GND 99 VDD33O 100 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 62 61 60 59 58 57 56 55 54 53 52 51 RTL8150LM 50 NC 49 NC 48 NC 47 NC 46 VDD33I 45 TXOP 44 TXON 43 GND 42 NC 41 NC 40 NC 39 NC 38 VDD33I 37 RXIP 36 RXIN 35 GND 34 RTSET 33 RTT2 32 RTT3 31 VDD5 30 NC 29 NC 28 NC 27 NC 26 VDD33O 25 24 23 22 21 20 19 18 17 16 15 14 NC NC NC VDD5 TXD2 TXD1 TXD0 TXEN TXC RXER RXC RXDV RXD0 2002/2/18 Ver1.40 LED1 LED2 T_RXC T_TXC T_CK25 T_DBG24 MDIO MDC VDD5 GND NC VDD33O 4 NC GND GND NC VDD33I XOUT XIN TEST0 TEST1 RXD3 RXD2 RXD1 RTL8150(M) 4 Pin Descriptions 4.1 RTL8150L Pin Descriptions 4.1.1 POWER PINS Type Pin No VDD5 VDD33O Symbol P P 13,27,37,48 12,25,47 VDD33I P GND P VDD33 P Description 5.0V power supply as internal regulators input 3.3V power output from internal regulators Pin 47: Digital power 9,20,24,34,40 3.3V power Pin 40: Digital power 10,11,17,21,26,33,35, Ground 41,46 36 3.3V Standby power 4.1.2 USB INTERFACE Symbol DM DP Type Pin No I/O I/O 38 39 Description Negative data line of USB differential data bus Positive data line of USB differential data bus 4.1.3 10/100 BASE-T UTP INTERFACE Symbol TXD+ TXDRXIN+ RXINX1 X2 Type Pin No O O I I I O 23 22 19 18 7 8 Description 10/100 BASE-T transmit data 10/100 BASE-T transmit data 10/100 BASE-T receive data 10/100 BASE-T receive data 25 MHz crystal input 25 MHz crystal output 4.1.4 LED Interface Symbol LED0, 1, 2 Type Pin No O 30,29,28 Description LED pins(active low) LEDS1-0 LED0 LED1 LED2 00 01 10 11 TX/RX LINK100 LINK10 TX/RX LINK10/100 FULL TX LINK10/100 RX TX/RX@ LINK10 TX/RX@ LINK100 FULL During power down mode, the LED‘s are OFF if SYSLED in configuration register 1 is set. 2002/2/18 Ver1.40 5 RTL8150(M) 4.1.5 EEPROM INTERFACE Symbol Type Pin No EECS EESK EEDI EEDO O O O I 45 44 43 42 Description 93C46 chip select 93C46 clock 93C46 data input 93C46 data output 4.1.6 TEST AND THE OTHER PINS Symbol Type Pin No RTT2-3 TEST0-1 RTSET GEP0-1 NC TEST TEST I/O I/O 15,14 6,5 16 32,31 1,2,3,4 Description Chip test pins. Chip test pins. This pin must be pulled low by a 1.69KΩ resistor. General purpose pin 0,1 Reserved 4.2 RTL8150LM Pin Descriptions 4.2.1 RTL8150LM POWER PINS Type Pin No VDD5 VDD33O Symbol P P 4,31,54,78 26,51,99 VDD33I P GND P VDD33 P Description 5.0V power supply as internal regulators input 3.3V power output from internal regulators Pin 99: Digital power 21,38,46,72,81 3.3V power Pin 81: Digital power 23,24,35,43,53,70,73, Ground 82,98 76 3.3V Standby power 4.2.2 RTL8150LM USB INTERFACE Symbol DM DP Type Pin No I/O I/O 79 80 Description Negative data line of USB differential data bus Positive data line of USB differential data bus 4.2.3 RTL8150LM 10/100 BASE-T UTP INTERFACE Symbol TXD+ TXD2002/2/18 Ver1.40 Type Pin No O O 45 44 Description 10/100 BASE-T transmit data 10/100 BASE-T transmit data 6 RTL8150(M) RXIN+ RXINX1 X2 I I I O 37 36 19 20 10/100 BASE-T receive data 10/100 BASE-T receive data 25 MHz crystal input 25 MHz crystal output 4.2.4 RTL8150LM MII INTERFACE Type Pin No Description RXD0-3 TXD0-3 TXC Symbol I O I 13,14,15,16 7,6,5,92 9 MIICOL I 69 TXEN O 8 RXC I 11 RXDV I 12 RXER I 10 MDC O 55 MDIO I/O 56 Mlink I 66 Mactiveb I 67 MII receive data 0-3 MII transmit data 0-3 MII Transmit Clock: 25 MHz or 2.5 MHz Tx clock supplied by the external PMD device. MII Collision Detected: This signal is asserted high synchronously by the external physical unit upon detection of a collision on the medium. It will remain asserted as long as the collision condition persists. MII Transmit Enable: Indicates the presence of valid nibble data on TXD[3:0]. MII Receive Clock: 25 MHz or 2.5 MHz Rx clock supplied by the external PMD device. MII Receive Data Valid: Data valid is asserted by an external PHY when receive data is present on the RXD[3:0], and it is de-asserted at the end of the packet. This signal is valid on the rising edge of the RXC. MII Receive Error: This pin is asserted to indicate that invalid symbol has been detected in 100Mbps MII mode. This signal is synchronized to RXC and can be asserted for a minimum of one receive clock. MII Management Data Clock: Synchronous clock for MDIO data transfer. MII Management Data: Bi-directional signal used to transfer management information. MII link status notification, indicates to the MAC that external PMD is link Ok or not. MII active status notification, when Mactiveb=high, Mlink is low active, and vice versa. 4.2.5 RTL8150LM LED Interface Symbol LED0, 1, 2 Type Pin No O 63,62,61 Description LED pins(active low) LEDS1-0 LED0 LED1 LED2 00 01 10 11 TX/RX LINK100 LINK10 TX/RX LINK10/100 FULL TX LINK10/100 RX TX/RX@ LINK10 TX/RX@ LINK100 FULL During power down mode, the LED‘s are OFF if SYSLED in configuration register 0 is set. 2002/2/18 Ver1.40 7 RTL8150(M) 4.2.6 RTL8150LM EEPROM INTERFACE Symbol Type Pin No EECS EESK EEDI EEDO O O O I 91 90 89 88 Description 93C46 chip select 93C46 clock 93C46 data input 93C46 data output 4.2.7 RTL8150LM TEST AND THE OTHER PINS Symbol Type Pin No RTT2-3 TEST T_*** TEST RTSET GEP0-1 PWRESETB I/O I/O O 33,32 17,18,57,58,59,60,83, 84,85,86,87,93,94,95, 96,97 34 65,64 68 1,2,3,22,25,27,28,29, 30,39,40,41,42,47,48, 49,50,52,71,74,75,77, 100 NC 2002/2/18 Ver1.40 Description Chip test pins. Chip test pins. This pin must be pulled low by a 1.69KΩ resistor. General purpose pin 0,1 Power-on reset for external PHY, active low Reserved 8 RTL8150(M) 5. SIE –USB Commands 5.1 Vender Memory Read Setup transaction: BmReq bReq wValueL wValueH wIndexL wIndexH C0 05 regoffsetL regoffsetH 00 00 Data transaction: DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 reg0 reg1 reg2 reg3 reg4 reg5 The total length response by 8150L depends on (LengH,LengL) values. wLengthL wLengthH LengL LengH DATA6 reg6 DATA7 reg7 5.2 Vender Memory Write Setup transaction: BmReq bReq wValueL wValueH wIndexL 40 05 regoffsetL regoffsetH 00 Data transaction: DATA0 DATA1 DATA2 DATA3 DATA4 reg0 reg1 reg2 reg3 reg4 Offset 0x1200 to 0x127f register must write by word mode. wIndexH 00 wLengthL wLengthH LenghL LenghH DATA5 reg5 DATA6 reg6 DATA7 reg7 5.3 Set address Setup transaction: BmReq bReq wValueL 00 05 addrL Data transaction: None wValueH addrH wIndexL 00 wIndexH 00 wLengthL wLengthH 00 00 wValueH 00 wIndexL 00 wIndexH 00 wLengthL wLengthH 00 00 5.4 Clear Feature EP0 Setup transaction: BmReq bReq wValueL 02 01 00 Data transaction: None 2002/2/18 Ver1.40 9 RTL8150(M) 5.5 Clear Feature EP1 Setup transaction: BmReq breq wValueL 02 01 00 Data transaction: None wValueH 00 wIndexL 81 wIndexH 00 wLengthL wLengthH 00 00 wValueH 00 wIndexL 02 wIndexH 00 wLengthL wLengthH 00 00 wValueH 00 wIndexL 83 wIndexH 00 wLengthL wLengthH 00 00 wValueH 00 wIndexL 81 wIndexH 00 wLengthL wLengthH 00 00 wValueH 00 wIndexL 02 wIndexH 00 wLengthL wLengthH 00 00 5.6 Clear Feature EP2 Setup transaction: BmReq bReq wValueL 02 01 00 Data transaction: None 5.7 Clear Feature EP3 Setup transaction: BmReq bReq wValueL 02 01 00 Data transaction: None 5.8 Set Feature EP1 Setup transaction: BmReq bReq wValueL 02 03 00 Data transaction: None 5.9 Set Feature EP2 Setup transaction: BmReq bReq wValueL 02 03 00 Data transaction: None 5.10 Set Feature EP3 Setup transaction: 2002/2/18 Ver1.40 10 RTL8150(M) BmReq bReq wValueL 02 03 00 Data transaction: None wValueH 00 wIndexL 00 wIndexH 83 wLengthL wLengthH 00 00 wValueH 00 wIndexL 00 wIndexH 00 wLengthL wLengthH 00 00 wValueH 00 wIndexL 00 wIndexH 00 wLengthL wLengthH 00 00 wValueH 00 wIndexL 00 wIndexH 00 wLengthL wLengthH 00 00 wValueH 00 wIndexL 00 wIndexH 00 wLengthL wLengthH 00 00 wValueH 00 wIndexL 00 wIndexH 00 wLengthL wLengthH 00 00 5.11 Set Interface 0 Setup transaction: BmReq bReq wValueL 01 0B 00 Data transaction: None 5.12 Set Feature Device Setup transaction: BmReq bReq wValueL 00 03 01 Data transaction: None 5.13 Clear Feature Device Setup transaction: BmReq bReq wValueL 00 01 01 Data transaction: None 5.14 Set Config 0 Setup transaction: BmReq bReq wValueL 00 09 00 Data transaction: None 5.15 Set Config 1 Setup transaction: BmReq bReq wValueL 00 09 01 Data transaction: None 2002/2/18 Ver1.40 11 RTL8150(M) 5.16 Get Descriptor Device Setup transaction: BmReq bReq wValueL wValueH wIndexL wIndexH 80 06 00 01 00 00 Data transaction: DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 12 01 10 01 00 00 DA 0B 50 81 00 01 03 01 The total length response by 8150L depends on (LengH,LengL) values. wLengthL wLengthH Lengh_L Lengh_H DATA6 00 01 - DATA7 08 02 - 5.17 Get Descriptor Configuration Setup transaction: BmReq bReq wValueL wValueH wIndexL wIndexH 80 06 00 02 00 00 Data transaction: DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 09 02 27 00 01 01 50 09 04 00 00 03 FF * 00 07 05 81 02 00 07 05 02 02 40 07 05 83 03 08 00 The total length response by 8150L depends on (LengH,LengL) values. *The E version is 0xFF ,before E version it is 0x00. wLengthL wLengthH Lengh_L Lengh_H DATA6 00 FF * 40 00 01 DATA7 A0 00 00 00 - 5.18 Get Descriptor String Index 0 Setup transaction: BmReq bReq wValueL wValueH wIndexL wIndexH 80 06 00 03 00 00 Data transaction: DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 04 03 04 09 The total length response by 8150L depends on (LengH,LengL) values. 5.19 Get Descriptor String Index 1 2002/2/18 Ver1.40 12 wLengthL wLengthH Lengh_L Lengh_H DATA6 - DATA7 - RTL8150(M) Setup transaction: BmReq bReq wValueL wValueH wIndexL wIndexH 80 06 01 03 09 04 Data transaction:(REALTEK) DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 10 03 52 00 45 00 4C 00 54 00 45 00 The total length response by 8150L depends on (LengH,LengL) values. wLengthL wLengthH Lengh_L Lengh_H DATA6 41 4B DATA7 00 00 5.20 Get Descriptor String Index 2 Setup transaction: BmReq bReq wValueL 80 06 02 Data transaction:(USB 10/100 LAN) DATA0 DATA1 DATA2 1E 03 55 20 00 31 31 00 30 4C 00 41 wValueH 03 wIndexL 09 wIndexH 04 wLengthL wLengthH Lengh_L Lengh_H DATA3 00 00 00 00 DATA4 53 30 30 4E DATA5 00 00 00 00 DATA6 42 2F 20 - DATA7 00 00 00 - 5.21 Get Descriptor String Index 3 Setup transaction: BmReq bReq wValueL wValueH wIndexL WindexH 80 06 03 03 09 04 Data transaction: DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 0A 03 30 00 30 00 31 00 The total length response by 8150L depends on (LengH,LengL) values. wLengthL wLengthH Lengh_L Lengh_H DATA6 30 - DATA7 00 - 5.22 Get Config Setup transaction: BmReq bReq 80 08 Data transaction: DATA0 DATA1 Value 2002/2/18 Ver1.40 wValueL 00 wValueH 00 wIndexL 00 wIndexH 00 wLengthL wLengthH 01 00 DATA2 - DATA3 - DATA4 - DATA5 - DATA6 - 13 DATA7 - RTL8150(M) 5.23 Get Status Device Setup transaction: BmReq bReq 80 00 Data transaction: DATA0 DATA1 Value Value wValueL 00 wValueH 00 wIndexL 00 wIndexH 00 wLengthL wLengthH 02 00 DATA2 - DATA3 - DATA4 - DATA5 - DATA6 - wValueL 00 wValueH 00 wIndexL 00 wIndexH 00 wLengthL wLengthH 02 00 DATA2 - DATA3 - DATA4 - DATA5 - DATA6 - wValueL 00 wValueH 00 wIndexL 81 wIndexH 00 wLengthL wLengthH 02 00 DATA2 - DATA3 - DATA4 - DATA5 - DATA6 - wValueL 00 wValueH 00 wIndexL 02 wIndexH 00 wLengthL wLengthH 02 00 DATA2 - DATA3 - DATA4 - DATA7 - 5.24 Get Status EP0 Setup transaction: BmReq bReq 82 00 Data transaction: DATA0 DATA1 Value Value DATA7 - 5.25 Get Status EP1 Setup transaction: BmReq bReq 82 00 Data transaction: DATA0 DATA1 Value value DATA7 - 5.26 Get Status EP2 Setup transaction: BmReq bReq 82 00 Data transaction: DATA0 DATA1 Value value 5.27 Get Status EP3 2002/2/18 Ver1.40 14 DATA5 - DATA6 - DATA7 - RTL8150(M) Setup transaction: BmReq bReq 82 00 Data transaction: DATA0 DATA1 Value Value wValueL 00 wValueH 00 wIndexL 83 wIndexH 00 wLengthL wLengthH 02 00 DATA2 - DATA3 - DATA4 - DATA5 - DATA6 - DATA7 - 5.28 Get Status Interface 0 Setup transaction: BmReq bReq 81 00 Data transaction: DATA0 DATA1 Value value wValueL 00 wValueH 00 wIndexL 00 wIndexH 00 wLengthL wLengthH 02 00 DATA2 - DATA3 - DATA4 - DATA5 - DATA6 - wValueL 00 wValueH 00 wIndexL 00 wIndexH 00 wLengthL wLengthH 01 00 DATA2 - DATA3 - DATA4 - DATA5 - DATA6 - DATA7 - 5.29 Get Interface 0 Setup transaction: BmReq bReq 81 0A Data transaction: DATA0 DATA1 value - 2002/2/18 Ver1.40 15 DATA7 - RTL8150(M) 6. Memory Allocation $0000H~$011FH------- Reserved $0120H~$01FFH------- RTL8150L(M) REGISTER $1200H~$127FH--------Serial EEPROM(9346) Offset 0120h-0125h 0126h-012Dh 012Eh 012Fh 0130-0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139-013Ah 013Bh 013Ch 013Dh 013Eh 0140h-0141h 0142h-0143h 0144h-0145h 0146h-0147h 0148h-0149h 014Ah-014Bh 014Ch-014Dh 014Eh-014Fh 0150h-0151h 0152h-0153h 0154h-0155h 0156h-0157h 0158h-015Fh 0160h-0167h 0168h-016Fh 0170h-0177h 0178h-017Fh 0180h-0183h 0184h 0186h-0189h 018Ah-01ff Type R/W* R/W R/W R/W R/W R/W R/W R/W R/W* R/W* R/W R/W R/W R/W R/W R/W* R/W R/W* R R/W* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R /W R/W Pin No IDR0-5 MAR0-7 CR TCR RCR TSR RSR Reserved CON0 CON1 MSR PHYADD PHYDAT PHYCNT Reserved GPPC WAKECNT BMCR BMSR ANAR ANLP AER NWAYT CSCR CRC0 CRC1 CRC2 CRC3 CRC4 BYEMASK0 BYEMASK 1 BYEMASK 2 BYEMASK 3 BYEMASK 4 PHY1 PHY2 TW1 Reserved Description Ethernet Address ,load from 93C46 Multicast register Command Register Transmit configuration register Receive configuration register Transmit status register Receive status register Configuration register0 Configuration register1 Medium status MII PHY address select MII PHY data MII PHY control General purpose pin control Wake up event control Basic mode control register Basic mode status register Auto-negotiation advertisement register Auto-negotiation link partner ability register Auto-negotiation expansion register Nway test register CS confiiguration register Power Management CRC register for wakeup frame0 Power Management CRC register for wakeup frame1 Power Management CRC register for wakeup frame2 Power Management CRC register for wakeup frame3 Power Management CRC register for wakeup frame4 Power Management wakeup frame0(64bit) bytemask Power Management wakeup frame1(64bit) bytemask Power Management wakeup frame2(64bit) bytemask Power Management wakeup frame3(64bit) bytemask Power Management wakeup frame4(64bit) bytemask PHY parameter 1 PHY parameter 2 Twister parameter 1 * : denotes auto-loaded from 93C46 during chip initialization. 2002/2/18 Ver1.40 16 RTL8150(M) 7. Register Descriptions 7.1 Command Register (Offset 012Eh, R/W) Bit Symbol Description 7-6 5 WEPROM 4 SOFT_RST 3 2 1 RE TE EP3CLREN 0 AUTOLOAD Reserved 1:EEPROM write enable 0: disable The EEPROM map from 0x1200 to 127fh. Write 0x1200 equal to program EEPROM offset 0x00. Write to EEPROM must use WORD mode access at a time. The read EEPROM have not limit. Reset: Setting to 1 forces the RTL8150L(M) to a software reset state which disables the transmitter and receiver, reinitializes the FIFOs, resets the system buffer pointer to the initial value , Rx buffer is empty). The values of IDR0-5 and MAR0-7 will have no changes. This bit is 1 during the reset operation, and is cleared to 0 by the RTL8150L(M) when the reset operation is complete. Ethernet 10/100M receive enable Ethernet 10/100M transmit enable 1: Enable clearing the performance counter of EP3 after EP3 access. 0: Disable 1: Auto-load the contents of 93c46 into RTL8150L(M)’s registers. This bit is self clearing after load complete. Default/ Attribute 0,R/W 0,R/W 0,R/W 0,R/W 0,R/W 0,R/W 7.2 Transmit Configuration Register (Offset 012Fh, R/W) Bit Symbol Description Default/ Attribute 7-6 TXRR1, 0 Tx Retry Count: These 2 bits are used to specify additional transmission retries in multiple of 16(IEEE 802.3 CSMA/CD retry count). If the TXRR is set to 0, the transmitter will re-transmit 16 times before aborting due to excessive collisions if the TXRR is set to a value greater than 0, the transmitter will re-transmit a number of times equals to the following formula before aborting: Total retries = 16 + (TXRR * 16) The ECOL bit in the TSR register will be set if transmit abort due to excessive collision. 0,R/W 5 4,3 Reserve IFG1, 0 2, 1 0 Reserved NOCRC 2002/2/18 Ver1.40 Interframe Gap Time: This field allows the user to adjust the interframe gap time below the standard: 9.6 us for 10Mbps, 960 ns for 100Mbps. The time can be programmed from 9.6 us to .8.4 us (10Mbps) and 960ns to 840ns (100Mbps). The formula for the inter frame gap is: 10 Mbps 8.4us + 0.4(IFG(1:0)) us 100 Mbps 840ns + 40(IFG(1:0)) ns 1: There’s no CRC appended at the end of a packet. 0: There’s CRC appended at the end of a packet. 17 0,R/W 0,R/W RTL8150(M) 7.3 Receive Configuration Register (Offset 0130h-0131h, R/W) Bit Symbol Description 15-8 7 TAIL 6 5 4 AER AR AM 3 AB 2 AD 1 AAM 0 AAP Reserved 0: CRC field forward to HOST 1: Rx Header forward to HOST. The first two bytes of CRC field are replaced by receive header. 1:Accept CRC error packet 1: Accept RUNT packet (<64 bytes) 1: Accept all multicast packets enumerated in the driver’s multicast address list. 0: Disabled. 1: Accept broadcast packets 0: Reject broadcast packets. 1: Packets received containing a destination address that match the MAC address of the networking device are accepted. 0: Disabled. 1: Accept all multicast frames received by the networking device, including the ones enumerated in the device’s multicast address list, 0: Disable. 1: Accept all physical frames 0: Disable. Default/ Attribute 0,R/W 0,R/W 0,R/W 0,R/W 0,R/W 0,R/W 0,R/W 0,R/W 7.4 Transmit Status Register(Offset 0132h) Bit Symbol 7-6 5 4 3 2 1 0 ECOL LCOL LOSS_CRS JBR TX_BUF_EMPTY TX_BUF_FULL Description Reserved 1: Excessive collision indication 1: Late collision indication 1: Loss of carrier indication 1: Jaber time out indication 1: Tx buffer empty indication 1: Tx buffer full indication Default/ Attribute R R R R R R Note: TSR register will be cleared to the default value after read or EP3 access. 7.5 Receive Status Register(Offset 0133h) Bit Symbol 7 WEVENT 6 2002/2/18 Ver1.40 RX_BUF_FULL Description Wake Up Event indication: 1: Wakeup event occurs Rx Buffer Full indication 18 Default/ Attribute R R RTL8150(M) 5 4 LKCHG RUNT 3 LONG 2 CRC 1 FAE 0 ROK Link Change indication Runt Packet indication 1: The received packet length is smaller than 64 bytes. Long Packet indication 1: The size of the received packet exceeds 4k bytes. CRC Error indication. 1: The received packet is checked with CRC error. Frame Alignment Error: 1: Indicates that a frame alignment error occurred on this received packet. Receive OK indication. 1: Indicate that a packet is received without error. R R R R R R Note: RSR register will be cleared to the default value after read or EP3 access. 7.6 Configuration Register 0(Offset 0135h, R/W) Bit Symbol Description 7 6 SUSLED PARM_EN 0: LED pins are driven high to turn off LED during suspend. Parameter Enable: (These parameters are used in 100Mbps mode.) 1: PHY1_PARM, PHY2_PARM, TW_PARM can be modified through access to register 0180H~0189H. 0: Disable Default/ Attribute 0,R/W 0,R/W Note: Each time 93C46 auto-load process is executed, the PHY1_PARM, PHY2_PARM, TW_PARM will be re-loaded the default value from 93C46. 4-5 3 LDPS 2 MSEL 1-0 LEDS1-0 Reserved Link Down Power Saving mode: 1: Disable. 0: Enable. When the ethernet cable is disconnected (Link Down), part of analog circuit will be powered down in order to save power. The other part of analog circuits relating to SD signal monitoring and 100M signal receiving are not powered down in case the cable is re-connected and link should be re-established again. Medium Select When write : 1:MII mode (disable internal PHY) 0:Auto-detect. The UTP mode will be the default. The RTL8150L(M) is switched to MII mode if the internal PHY is not link OK. When read 1:MII mode: The MAC MII is connected to the MII interface of the external PHY. 0:UTP mode: The MAC MII is connected to the internal PHY. Refer to LED PIN definition. The default value is auto-loaded from 93C46. 0,R/W 0,R/W 0,R/W 7.7 Configuration Register 1(Offset 0136h, R/W) Bit 2002/2/18 Ver1.40 Symbol Description 19 Default/ RTL8150(M) Attribute 7 6 BWF 5 MWF 4 UWF 2-3 1 LONGWF1 0 LONGWF0 Reserved. Broadcast Wakeup Frame Function: 1: Enable Broadcast Wakeup Frame If set_feature command with Feature Selector =DEVICE_REMOTE_WAKEUP is received from USB host and BWF=1, RTL8150L(M) will signal wakeup to the host when correctly receiving a packet with DID=FF FF FF FF FF FF (Broadcast packet),. 0: Disable. Multicast Wakeup Frame Function: 1: Enable Multicast Wakeup Frame If set_feature command with Feature Selector =DEVICE_REMOTE_WAKEUP is received from USB host and MWF=1, RTL8150L(M) will signal wakeup to the host when correctly receiving multicast packets (packets that survive the multicast hash),. 0: Disable. Unicast Wakeup Frame Function: 1: Enable Unicast Wakeup Frame f set_feature command with Feature Selector =DEVICE_REMOTE_WAKEUP is received from USB host and UWF=1, RTL8150L(M) will signal wakeup to the host when correctly receiving a packet with DID=IDR0~5. 0: Disable. Reserved 1: The Bytemask3 and Bytemask4 are cascaded to form a 128 byte long Bytemask for long wakeup frame 1, and long wakeup frame 1 use CRC3 as CRC check. When LONGWF1=1, wakeup frame 3 and wakeup frame 4 are disable. 0: Disable LOGNWF1. 1: The Bytemask1 and Bytemask2 are cascaded to form a 128 byte long Bytemask for long wakeup frame 0, and long wakeup frame 0 use CRC1 as CRC check. When LONGWF0=1, wakeup frame 1 and wakeup frame 2 are disabled. 0: Disable LOGNWF0. 0,R/W 0,R/W 0,R/W 0,R/W 0,R/W 7.8 Media Status Register (Offset 0137h, R/W) Default/ Attribute Bit Symbol Description 7 TXFCE/ LdTXFCE Tx Flow Control Enable: The flow control is valid in full-duplex mode only. This register‘s default value comes from 93C46. RTL8150L Remote ANE = 1 NWAY FLY mode ANE = 1 NWAY mode only ANE = 1 No NWAY ANE = 0 & full-duplex mode ANE = 0 & half-duplex mode 2002/2/18 Ver1.40 20 TXFCE/LdTXFCE R/O R/W R/W R/W Invalid R/W RTL8150(M) 6 RXFCE 5 4 Reserved Duplex 3 SPEED_100 2 LINK 1 TXPF 0 RXPF NWAY FLY mode : NWAY with flow control capability NWAY mode only : NWAY without flow control capability RX Flow control Enable: The flow control is enabled in full-duplex mode only. The default value comes from 93C46 . 1: Indicate that the current link is full-duplex 0: Indicate that the current link is half-duplex 1: Indicate that the current link is in 100Mbps mode. 0: Indicate that the current link is in 10Mbps mode. Link status. 1: Link OK. 0: Link Fail. 1: Indicate that RTL8150L(M) sends pause packet. 0: Indicate that RTL8150L(M) has sent timer done packet to release remote station from pause Tx state. 1: Indicate that RTL8150L(M) is in Backoff state because a pause packet from remote station has been receipt. 0: Indicate that RTL8150L(M) is not in pause state. R/W R R R R R 7.9 MII PHY Address(Offset 0138h, R/W) Bit Symbol 7-5 4-0 Reserved PHYADD Description Default/ Attribute R/W MII PHY Address select 7.10 MII PHY DATA(Offset 0139h-013Ah, R/W) Bit Symbol 15-0 MIIDAT Description Data read from MII PHY or data that is to be written to MII PHY. Default/ Attribute R/W 7.11 MII PHY Access Control(Offset 013Bh, R/W) Bit Symbol 7 6 Reserved PHYOWN 5 RWCR 4-0 PHYOFF 2002/2/18 Ver1.40 Description Own bit: RTL8150L(M) will initiate a MII management data transaction if this bit is set 1 by software. After transaction, this bit is auto cleared by RTL8150L. MII management data R/W control 1:write, 0: read PHY register offset 21 Default/ Attribute 0,R/W R/W R/W RTL8150(M) 7.12 General Purpose Register(Offset 013Dh, R/W) Bit Symbol Description/Usage 7-5 4 GEPREG1~3 GEPREG0 3 GEP1DAT 2 GEP1RW 1 GEP0DAT 0 GEP0RW Reserved General purpose bit 1: Supports external Home PNA PHY If GEP1RW is set 1, the GEP1 pin will reflect the value of GEP1DAT, else GEP1DAT will reflect the value of GEP1 pin. General purpose pin control bit: 0: The corresponding GEP1 pin is considered input 1: The corresponding GEP1 pin is considered output If GEP0RW is set 1, the GEP0 pin will reflect the value of GEP0DAT, else GEP0DAT will reflect the value of GEP0 pin. General purpose pin control bit: 0: The corresponding GEP0 pin is considered input 1: The corresponding GEP0 pin is considered output Default/ Attribute RO R/W R/W R/W R/W If GEPRW=0 ,READ only 7.13 Wake Up Event Control(Offset 013E, R/W) Bit Symbol 7 6 5 4 3 2 1 0 Reserved LKWEN MAGWEN WUF4EN WUF3EN WUF2EN WUF1EN WUF0EN Description/Usage Link change wake-up enable Magic Packet wake-up enable Wake up frame 4 enable Wake up frame 3 enable Wake up frame 2 enable Wake up frame 1 enable Wake up frame 0 enable Default/ Attribute 0, R/W 0, R/W 0, R/W 0, R/W 0, R/W 0, R/W 0, R/W Note: RTL8150L(M) will signal wakeup to the host only when the following two conditions are met: 1. The host has send set_feature_device command. 2. One of the wakeup frame function has been enabled and triggered. 7.14 Basic Mode Control Register (Offset 0140h-0141h, R/W) Bit Name Description/Usage 15 Reset 14 13 Reserved Spd_Set This bit, which is self clearing, will reset the control and status registers of PHY into the default states if it is set 1. Speed select. 1 = 100Mbps; 0 = 10Mbps. Note: The initial value of this bit comes from 93C46 2002/2/18 Ver1.40 22 Default/ Attribute 0, RW RW RTL8150(M) 12 Auto Negotiation Enable (ANE) 11-10 9 Reserved Restart Auto Negotiation 8 Duplex Mode 7-0 Reserved 0, RW This bit enables/disables the NWay auto-negotiation function. 1 = Enable auto-negotiation. If this bit is set, bit 8 and bit13 will be ignored, and the values of bit8 and bit 13 indicate the result of auto negotiation process. 0 = Disable auto-negotiation. Note: The initial value of this bit comes from 93C46 This bit allows the NWay auto-negotiation function to be re-initiated. 1 = Re-start auto-negotiation 0 = Normal operation. This bit sets the duplex mode. 1 = full-duplex 0 = normal operation. Note: This bit‘s initial value comes from 93C46 - 0, RW 0, RW - 7.15 Basic Mode Status Register (Offset 0142h-0143h, R) Bit Name 15 Description/Usage 100Base-T4 Capable: 0 = Device not able to perform 100Base-T4 mode 100Base-TX Full Duplex Capable: 100Base_TX_ FD 1 = Device able to perform 100Base-TX in full duplex mode 100Base-TX Half Duplex Capable: 100Base_TX_HD 1 = Device able to perform 100Base-TX in half duplex mode 10Base-T Full Duplex Capable: 10Base_T_FD 1 = Device able to perform 10Base-T in full duplex mode 10Base-T Half Duplex Capable: 10_Base_T_HD 1 = Device able to perform 10Base-T in half duplex mode Reserved Auto Negotiation 1 = Auto-negotiation process completed; Complete 0 = Auto-negotiation process not completed. 1 = Remote fault condition detected (clear on read); Remote Fault 0 = No remote fault condition detected. Auto Negotiation 1 = Device is able to perform Auto-Negotiation. ability 0 = Device not able to perform Auto-Negotiation. Reserved Extended 1 = Extended register capabilities; Capability 0 = Basic register set capabilities. 100Base-T4 14 13 12 11 10-6 5 4 3 2-1 0 Default/ Attribute 0, RO 1, RO 1, RO 1, RO 1, RO 0, RO 0, RO 1, RO 1, RO 7.16 Auto-negotiation Advertisement Register (Offset 0144h-0145h, R/W) Bit Name 15 NP 2002/2/18 Ver1.40 Description/Usage Next Page capability. 0 = Advertise that NP capability not supported by local mode 23 Default/ Attribute 0, RO RTL8150(M) 14 13 ACK RF 12-11 10 PAUSE 9 T4 8 TXFD 7 TX 6 10FD 5 10 4-0 Selector 1 = Advertise NP exchange capability and desire to transfer next page. 1 = Acknowledge reception of link partner’s capability data word. 1 = Advertise remote fault detection capability; 0 = Do not advertise remote fault detection capability. Reserved 1 = Advertise flow control supported by local node. 0 = Advertise flow control not supported by local mode. 1 = Advertise 100Base-T4 supported by local node; 0 = Advertise 100Base-T4 not supported by local node. 1 = Advertise 100Base-TX full duplex supported by local node; 0 = Advertise 100Base-TX full duplex not supported by local node. 1 = Advertise 100Base-TX supported by local node; 0 = Advertise 100Base-TX not supported by local node. 1 = Advertise 10Base-T full duplex supported by local node; 0 = Advertise 10Base-T full duplex not supported by local node. 1 = Advertise 10Base-T supported by local node; 0 = Advertise 10Base-T not supported by local node. Binary encoded selector supported by this node. Currently only CSMA/ CD <00001> is specified. No other protocols are supported. 0, RO 0, RW The default value comes from EEPROM, RO 0, RO 1, RW 1, RW 1, RW 1, RW <00001>, RW 7.17 Auto-Negotiation Link Partner Ability Register (Offset 0146h-0147h, R) Bit Name 15 NP 14 ACK 13 RF 12-11 10 Reserved Pause 9 T4 8 TXFD 7 TX 6 10FD 2002/2/18 Ver1.40 Description/Usage Next Page Indication: 0 = Link Partner does not desire Next Page Transfer 1 = Link Partner desires Next Page Transfer. 1 = link partner acknowledges reception of the capability data word. 0 = Not acknowledged The device’s Auto-Negotiation state machine will automatically control this bit based on the incoming FLP bursts. Remote Fault: 1 = Remote Fault indicated by Link Partner 0 = No Remote Fault indicated by Link Partner. 1 = Flow control is supported by link partner , 0 = Flow control is not supported by link partner. 100BASE-T4 Support: 1 = 100Base-T4 is supported by the link partner; 0 = 100Base-T4 not supported by the link partner. 100BASE-TX Full Duplex Support: 1 = 100Base-TX full duplex is supported by the link partner; 0 = 100Base-TX full duplex not supported by the link partner. 100BASE-TX Support: 1 = 100Base-TX is supported by the link partner; 0 = 100Base-TX not supported by the link partner. 10BASE-T Full Duplex Support: 1 = 10Base-T full duplex is supported by the link partner; 24 Default/ Attribute 0, RO 0, RO 0, RO 0, RO 0, RO 0, RO 0, RO 0, RO RTL8150(M) 5 10 4-0 Selector 0 = 10Base-T full duplex not supported by the link partner. 10BASE-T Support: 1 = 10Base-T is supported by the link partner; 0 = 10Base-T not supported by the link partner. Protocol Selection Bits: Link Partner’s binary encoded protocol selector. 0, RO 0, RO 7.18 Auto-negotiation Expansion Register (Offset 0148h-0149h, R) This register contains additional status for NWay auto-negotiation. Bit Name Description/Usage 15-5 4 MLF 3 LP_NP_ABLE 2 NP_ABLE 1 PAGE_RX 0 LP_NW_ABLE Reserved, This bit is always set to 0. Status indicating if a multiple link fault has occurred. 1 = fault occurred; 0 = no fault occurred. Status indicating if the link partner supports Next Page negotiation. 1 = supported; 0 = not supported. This bit indicates if the local node is able to send additional Next Pages. This bit is set when a new Link Code Word Page has been received. The bit is automatically cleared when the auto-negotiation link partner‘s ability register (register 146h) is read by management. 1 = link partner supports NWay auto-negotiation. Default/ Attribute 0, RO 0, RO 0, RO 0, RO 0, RO 7.19 NWay Test Register (Offset 014Ah-014Bh, R/W) Bit 15-8 7 6-4 3 2 1 0 Name NWLPBK ENNWLE FLAGABD FLAGPDF FLAGLSC Description/Usage Reserved 1 = set NWay to loopback mode. Reserved 1 = LED0 Pin indicates linkpulse 1 = Auto-neg experienced ability detect state 1 = Auto-neg experienced parallel detection fault state 1 = Auto-neg experienced link status check state Default/ Attribute 0, RW 0, RW 0, RO 0, RO 0, RO 7.20 CS Configuration Register (Offset 014Ch-014Dh, R/W) Bit Name Description/Usage 15 14-10 9 Testfun LD 1 = Speeds up internal timer for Auto-Negociation Reserved Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. 1 = HEART BEAT enable 25 8 2002/2/18 Ver1.40 HEART BEAT Default/ Attribute 0,WO 1, RW 1, RW RTL8150(M) 7 JBEN 6 F_LINK_100 5 F_Connect 4 3 Con_status 2 Con_status_En 1 0 PASS_SCR 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. 1 = enable jabber function. 0 = disable jabber function Force link-up in 100Mbps for diagnostic purposes. 1 = DISABLE 0 = ENABLE. Force connection of the link for diagnostic purposes: 1 = Fore connection 0 = Disable Reserved This bit indicates the status of the connection. 1 = valid connected link detected 0 = disconnected link detected. Assertion of this bit configures LED1 pin to indicate connection status. Reserved Bypass Scramble function 1, RW 1, RW 0, RW 0, RO 0, RW 0, RW 8 EEPROM 93C46 Contents The 93C46 is a 1K-bit EEPROM. Although it is actually addressed by words, we list its contents by bytes below for convenience. After the valid duration of the RSTB pin or auto-load command in Command Register(offset 012Eh), the RTL8150L(M) performs a series of EEPROM read operation from the 93C46. $ If you want to change the Realtek default setting of the content in EEPROM, we suggest that you have Realtek approval. Bytes Contents 00h 01h 50h 81h 02h-07h Ethernet ID 08h 09h CONFIG0 MSR/BMCR 0Ah 0Bh GEP UDP 0Ch ATTR 2002/2/18 Ver1.40 Description These 2 bytes contain ID code word for the RTL8150L(M). The RTL8150L(M) will load the contents of EEPROM into the corresponding location if the ID word (8150h) is right. Ethernet ID, After auto-load command or hardware reset, RTL8150L(M) loads Ethernet ID to IDR0-IDR5 of RTL8150L(M)'s. RTL8150L(M) Configuration register 0, operational registers offset 0135h. Bit7-6 map to the bit7-6 of Media Status register (MSR), Bit5, 4, 0 map to the bit13, 12, 8 of Basic Mode Control register (BMCR), Bit2 maps to the bit10 of Auto-negotiation Advertisement Register (ANAR), Bit3, 1 are reserved. If the network speed is set to Auto-Detect mode (i.e. Nway mode), then Bit2=0 means the local RTL8150L(M) supports flow control (IEEE 802.3x) (in this case, Bit10=1 in Auto-negotiation Advertisement Register (offset 146h-147h), and Bit2=1 means the local RTL8150L(M) does not support flow control (in this case, Bit10=0 in Auto-negotiation Advertisement). This is because that there are Nway switch hubs will keep sending flow control pause packets with no reason, if the link partner supports Nway flow control. General Purpose Pin Control Register (offset 013Dh). Reserved. Do not change this filed without Realtek approval. USB Device Parameter USB Configuration characteristics: 26 RTL8150(M) 0Dh PHY2_PARM 0Eh-11h PHY1_PARM 12h-15h TW1_PARM 16h 17h 18h-19h MAXPOR INTERVAL LanguageID 1Ah-1Bh 1Ch-1Dh 1Eh-27h 28h-4fh 50h-7dh ManufacturerID ProductID Serial number Manufacturer String Product String 7eh-7fh Reserved Bit7 is reserved and must be set to one for USB spec. A device configuration that uses power from the bus and a local source reports a non-zero value in MaxPower to indicate the amount of bus power required and sets Bit 6. Bit5 is set one to support remote wakeup. Bit4-0: Reserved and must be reset to zero for USB spec. Reserved. Do not change this filed without Realtek approval. PHY Parameter 2 for RTL8150L(M). Operational register of the RTL8150L(M) is 0184h. Reserved. Do not change this filed without Realtek approval. PHY Parameter 1 for RTL8150L(M). Operational register of the RTL8150L(M) is 0180h-0183h. Reserved. Do not change this filed without Realtek approval. Twister Parameter for RTL8150L(M). Operational registers of the RTL8150L(M) are 0186h-0189h. The maximum USB power consumption. Interval for pollin endpoint 3 for data transfers. Expressed in milliseconds. The string in a USB device may support multiple languages. A manufacturer can specify the desired language using a sixteen-bit language ID. The system manufacturer’s ID. The of a system manufacturer’s product ID. The product’s serial number. These bytes specify a manufacturer’s information for the USB standard request. Maximum string length is 40 bytes. These bytes specify a device’s information for the USB standard request. Maximum string length is 46 bytes. 8.1 Summary of RTL8150L‘s registers in the EEPROM(93C46) Offset 00h 01h 02-07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0E-11h 12h-15h 16h 17h 18h-19h Name ROMID0 ROMID1 IDR0-IDR5 Config0 MSR/ BMCR GPCP UDP ATTR PHY2_PARM PHY1_PARM TW1_PARM MAXPOR Interval Language ID Manufacture 1Ah-1Bh ID 1Ch-1Dh Product ID 1Eh-27h Serial number 2002/2/18 Ver1.40 Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 ANE LDPS - MSEL PAUSE LEDS1 LEDS0 FUDUP GEP1DAT GEP1RW GEP0DAT GEP0RW SUSLED PARM_EN TXFCE RXFCE Spd_set GEPREG3 GEPREG2 GEPREG1 GEPREG0 1 0 1 0 0 0 8 bit Read Write 0 0 8 bit Read Write 32 bit Read Write 32 bit Read Write 8 bit Read Write 0 0 16 bit Read Write R/W 16 bit Read Write R/W R/W 16 bit Read Write 10 bytes Read Write 27 0 0 0 0 0 1 RTL8150(M) Manufacture String 50h-7dh Product string 7eh-7fh Reserved 28h-4fh 2002/2/18 Ver1.40 R/W 40 bytes Read Write R/W - 46 bytes Read Write - 28 RTL8150(M) 9 Functional Description 9.1 System Block Diagram EEPROM Interface DP DM SIE Memory Management Unit MAC Controller (MMU) MII Interface TXO+ SRAM Tx/2k bytes Rx/16k bytes 10/100Mbps PHY TXORXIN+ RXIN- 9.2 USB Endpoint SIE function description The SIE employs a robust hardwired USB protocol implementation so that the entire USB interface operation could be done without firmware intervention. For all three types of EP’s, bulk in,bulk out, and interrupt, appropriate responses and handshake signals are generated by SIE. The SIE analog transceiver complies fully with driver and receiver characteristics defined in USB Spec. Rev. 1.1, 9.2.1 Endpoint0 All USB devices support a common accesses mechanism for accessing information through this 2002/2/18 Ver1.40 29 RTL8150(M) control pipe. Associated with the control pipe at endpoint zero is the information required to completely describe the USB device. This pipe also provides the register read and write to RTL8150L . 9.2.2 Endpoint 1 Bulk IN The MAXIMUM packet size of BULK IIN is 64 bytes. Every Ethernet packet are transfer to HOST by this Endpoint. If the Ethernet packet is larger than 64 bytes, the RTL8150L(M) splits the Ethernet packet into multiples of 64 bytes. The HOST treats the USB packet that less than 64 bytes or equal zero as End of Ethernet packet. 9.2.3 Endpoint 2 Bulk OUT The HOST sends the USB packet to Ethernet by maximum 64 bytes. If the Ethernet packet is larger than 64 bytes, the Host will send this Ethernet packet in multiples of 64 bytes USB packet. The USB packet less than 64 bytes (including zero byte) indicates the end of a Ethernet packet. The Ethernet packet (containing multiples of USB packets) will be queued in TX FIFO and transmitted later when possible. If the Ethernet packet is transmitted to medium without error, the TX FIFO space which was occupied by the transmitted Ethernet packet will be released again. If the 2K TX FIFO is full, the RTL8150L(M) will respond with a NAK when the host is trying to bulk out more USB packets. It is possible that there are multiples of Ethernet packets in the TX FIFO simultaneously. If a Ethernet packet is to be transmitted but experiences collisions for more than 16 times (default), this is called transmit abort and this packet will be skipped for transmission by RTL8150L(M). 9.2.4 Endpoint 3 interrupt IN The Interrupt EP (EP3) can be used to poll the current status of RTL8150L(M). The 8 bytes of EP3 contain the information listed below. After EP3 access, the information will be cleared and the counter will be reset if EP3CLREN (Reg 012Eh) is set. The NUMTXOK, RXLOST, CRCERR, COLCNT counters will saturate to 255 if the number of up count events is greater than 255. The eight bytes of EP3 Interrupt IN contains: DATA0 2002/2/18 Ver1.40 DATA1 DATA2 DATA3 DATA4 30 DATA5 DATA6 DATA7 RTL8150(M) TSR RSR Offset Name 00h TSR GEP/MSR Type WAKSR Bit7 R Bit6 - - RSR R 02h GEP/MSR R RX_BUF_F ULL GEP1DAT GEP0DAT 03h WAKSR R PARM_EN 01h 04 05h 06h 07h TXOK_CNT R RXLOST_CNT R CRCERR_CNT R COL_CNT R NUMTXOK Bit5 Bit4 RXLOST Bit3 CRCERR Bit2 ECOL LCOL LOSS_CRS JBR LKCHG RUNT LONG CRC - Duplex SPEED_100 - LINK LKWAKE_ WAKEUP_EV EV COLCNT Bit1 Bit0 TX_BUF_ TX_BUF_ EMPTY FULL FAE ROK TXPF MAGIC_ EV RXPF BMU_EV 8-bit counter that counts for valid packets transmitted. 8-bit counter that counts for packet lost due to Rx buffer overflow. 8-bit counter that counts for error packets 8-bit counter that counts for collisions. 9.3 Ethernet function description 9.3.1 Transmit operation The USB host initiates a transmission by transferring multiple USB packets into Tx buffer. When MAC receives the end of USB BULK OUT packet from USB host, the RTL8150L(M) starts Ethernet packet transmission. 9.3.2 Receive operation The incoming Ethernet packet is queued in the RTL8150L(M)’s Rx buffer. While the RTL8150L(M) is receiving the Ethernet packet, it also performs address filtering of multicast packets according to its hash algorithms. When the Ethernet packet is correctly received or the amount of data in the Rx buffer reaches the level defined in the Receive Configuration Register(Early receive function is on), the RTL8150L(M) requests the USB SIE to begin transferring the data to the USB Host memory . Rx header format (ref. Receive Configuration Register, offset 0130h) Bit 11-0: Rx bytes count Bit 12:Valid packet (Packet that is RXOK and not accept error) Bit 13: Runt packet Bit 14: Physical match packet Bit 15: Multicast packet 2002/2/18 Ver1.40 31 RTL8150(M) 9.3.3 Collision If the RTL8150L(M) is not set the full-duplex mode, a collision event occurs when the receive input is not idle while the RTL8150L(M) transmits. If the collision is detected during the preamble transmission, the jam pattern is transmitted after completing the preamble transmission (including the JK symbol pair). 9.3.4 Flow Control The RTL8150L(M) supports IEEE802.3X flow control to improve performance in full-duplex mode. It recognizes PAUSE packet sent from remote station and backoff transmission according to IEEE802.3X if RXFCE is set, or RTL8150L(M) sends PAUSE packet to remote station when the local RX FIFO exceeds some threshold if the TXFCE is set. 9.3.4.1 Control Frame Transmission When the free space of RX FIFO is less than 3K bytes. The RTL8150L(M) sends a PAUSE packet with pause_time(=FFFFh) to inform the remote station to stop transmission for the specified period of time. After the packets in the RX FIFO are consumed and the free space of RX FIFO is greater than 5K bytes, the RTL8150L(M) sends the PAUSE packet with pause_time(=0000h) to inform the remote station to restart transmission. 9.3.4.2 Control Frame Reception RTL8150L(M) backoffs transmission for the specified period of time when it receives a valid PAUSE packet with pause_time(=n). If the PAUSE packet is received while RTL8150L(M) is transmitting, RTL8150L(M) will start to backoff after current transmission completes. RTL8150L(M) is free to transmit next packets again if a valid PAUSE packet with pause_time(=0000h) is received or the backoff timer(=n*512 bit time) elapses. Note: The PAUSE operation cannot be used to inhibit transmission of MAC Control frames (e.g. PAUSE packet). The N-way flow control capability can be disabled (Refer to Section 8. EEPROM 93C46 Contents for detailed description). 2002/2/18 Ver1.40 32 RTL8150(M) 10. ELECTRICAL CHARACTERISTICS 10.1 Temperature Limit Ratings: Parameter Minimum Maximum Units -55 0 +125 70 °C °C Storage temperature Operating temperature 10.2 DC CHARACTERISTICS: 10.2.1 Supply voltage (BUS POWER) Vbus = 4.5V min. to 5,5V max. Vcc = 3.3V Symbol Parameter Conditions VOH Minimum High Level Output Voltage IOH= -2mA VOL Maximum Low Level Output Voltage IOL= 8mA VIH Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage IIN Input Current IOZ Tri-State Output Leakage Current ICC Average Operating Supply Current 2002/2/18 Ver1.40 VIN=VCC or GND VOUT=VCC or GND IOUT=0mA, 33 Minimum Maximum 0.9 * Vcc Units Vcc V 0.1 * Vcc V 0.5 * Vcc Vcc+0.5 V -0.5 0.3 * Vcc V 50 50 uA 50 50 uA 110 mA RTL8150(M) 10.3 EEPROM Interface EESK EECS EEDI 1 0 1 0 0 0 A2 A1 A0 EEDO D1 D15 D14 T1 T2 EESK T3 T4 EEDI T6 T5 EECS T7 T8 EEDO Symbol Parameter Min. Typ. Max. Unit T1 EESK high width 3.2 µs T2 EESK low width 3.2 µs T3 EEDI setup to EESK rising edge 3.0 µs T4 EEDI hold from EESK rising edge 3.0 µs T5 EECS goes high to EESK rising edge 3.0 µs T6 EECS goes low from EESK falling edge T7 EEDO setup to EESK falling edge 20 ns T8 EEDO hold from EESK falling edge 10 ns 2002/2/18 Ver1.40 0 34 ns D0 RTL8150(M) 10.4 GPIO Interface Symbol Parameter Min. Typ. Max. 2.0 Unit Vih Input high voltage V Vil Input low voltage Voh Output high voltage Vol Output low voltage 0.1Vcc V Iih Input high leakage current 50 µA Iil Input low leakage current -10 µA 0.8 0.9Vcc V V 10.5 USB interface Symbol Parameter Min. Typ. Max. Unit Tfr Rise Time 9.6 12 14.4 ns Tff Fall Time 12.8 16 19.2 ns 2002/2/18 Ver1.40 35 RTL8150(M) Note: 1.To be determined at seating plane -cSymbol Dimension in inch Min Nom Max A 0.067 － － A1 0.000 0.004 0.008 A2 0.051 0.055 0.059 b 0.006 0.009 0.011 b1 0.006 0.008 0.010 c 0.004 － 0.008 c1 0.004 － 0.006 D 0.354 BSC D1 0.276 BSC E 0.354 BSC E1 0.276 BSC 0.020 BSC e L 0.016 0.024 0.031 L1 0.039 REF θ 0° 3.5° 9° θ1 0° － － θ2 12°TYP θ3 12°TYP 2002/2/18 Ver1.40 2.Dimensions D1 and E1 do not include mold protrusion. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3.Dimension b does not include dambar protrusion. Dambar can not be located on the lower radius of the foot. 4.Exact shape of each corner is optional. 5.These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 6. A1 is defined as the distance from the seating plane to the lowest point of the package body. 7.Controlling dimension : millimeter. 8. Reference document : JEDEC MS-026 , BBC TITLE : 48LD LQFP ( 7x7x1.4mm) PACKAGE OUTLINE DRAWING , FOOTPRINT 2.0mm LEADFRAME MATERIAL: APPROVE DOC. NO. VERSION 1 PAGE OF CHECK DWG N SS048 - P1 DATE MAR. 25.1997 REALTEK SEMI-CONDUCTOR CO., LTD Dimension in mm Min Nom Max 1.70 － － 0.00 0.1 0.20 1.30 1.40 1.50 0.15 0.22 0.29 0.15 0.20 0.25 0.09 － 0.20 0.09 － 0.16 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.50 BSC 0.40 0.60 0.80 1.00 REF 0° 3.5° 9° － － 0° 12°TYP 12°TYP 36 RTL8150(M) Note: Symbol A A1 A2 B B1 C C1 D D1 E E1 e L L1 θ θ1 θ2 θ3 2002/2/18 Ver1.40 Dimension in inch Min Nom Max － － 0.067 0.000 0.004 0.008 0.051 0.055 0.059 0.006 0.009 0.011 0.006 0.008 0.010 0.004 － 0.008 0.004 － 0.006 0.630 BSC 0.551 BSC 0.630 BSC 0.551 BSC 0.020 BSC 0.016 0.024 0.031 0.039 REF 0° 3.5° 9° － － 0° 12°TYP 12°TYP Dimension in mm Min Nom Max － － 1.70 0.00 0.1 0.20 1.30 1.40 1.50 0.15 0.22 0.29 0.15 0.20 0.25 0.09 － 0.20 0.09 － 0.16 16.00 BSC 14.00 BSC 16.00 BSC 14.00 BSC 0.50 BSC 0.40 0.60 0.80 1.00 REF 0° 3.5° 9° － － 0° 12°TYP 12°TYP 1.To be determined at seating plane -c2.Dimensions D1 and E1 do not include mold protrusion. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3.Dimension b does not include dambar protrusion. Dambar can not be located on the lower radius of the foot. 4.Exact shape of each corner is optional. 5.These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 6. A1 is defined as the distance from the seating plane to the lowest point of the package body. 7.Controlling dimension : millimeter. 8. Reference document : JEDEC MS-026 , BED. TITLE : 100LD LQFP ( 14x14x1.4mm) PACKAGE OUTLINE DRAWING , FOOTPRINT 2.0mm LEADFRAME MATERIAL: APPROVE DOC. NO. VERSION 1 PAGE OF CHECK DWG NO. LQ100 - P1 DATE APR. 28.1997 REALTEK SEMI-CONDUCTOR CO., LTD 37