5 4 3 USB4640QFN48 Evaluation Platform D Functional Block Diagram USB4640 (48-PIN) Two external memory options: EEPROM configuration SPI external firmware Rev. Date Revision Summary Author 00A 20090227 Initial schematic - HSIC interface H. Magnusson 01A 20090303 Added HSIC_IMP pin H. Magnusson 02A 20090307 Revised USB4640. C. Johnson A 20090413 Renumbered & released. C. Johnson A01 20091110 Incorporated user review feedback J. Hancock A02 20091113 Split up Debug header. Named TEST net. J. Hancock A03 20091118 Replaced U3 with TPS76201 regulator. J. Hancock B 20091207 Released. J. Hancock 00C 20100917 Created dual use EEPROM/SPI Socket. Removed xD and MS circuitry. Added optional Test Only headers. Added series termination on SD signals and also added ESD protection on SD_nCD and _WP signals. Added RESET header. J. Hancock J. Hancock Ext. 1.2V supply on USB Port 1 C Ext. 5V supply 1 Revision History HSIC Upstream - 2 port hub Combo HSIC Host (Dual SMA) 2 C 01C 20100922 Removed page 4 (xD/MS adapter card interface). 02C 20100929 DNP'd 10uF tant cap on TPS regulator and added ceramic J. Hancock 10uF cap with 1Ohm in series to replace it. 03C 20101005 Renumbered design. J. Hancock C 20101006 Released J. Hancock SD D Downstream Port 2 B B Downstream Port 3 A A Austin Design Center 10900-B Stonelake Blvd., Ste. 100 Austin, TX 78759 512.502.0070 Title: Evaluation Platform for USB4640, Part Number: EVB-USB4640 Project Size: B Name: Date: Friday, October 29, 2010 5 4 3 2 QFN48 pkg Naiad Sheet 1 1 Rev C of 3 4 5V_EXT J2 1 2 2 C1 0.1uF 4.7uF R17 2 C9 0.1uF R6 330 3 2 1 4 PRTCTL3 PRTCTL2 5V DNP D1 GRN D D5 GRN "3V3 Present" "5V Present" D2 GRN D7 GRN "PPWR2" PWR3_LED "PPWR3" U5 R2 DNP 330 (*Note 1) MIC2026-1BM 8 ENA OUTA 5 ENB OUTB 330 PWR2_LED D3 GRN "VDD33 Present" FLAGA FLAGB 7 6 C38 PPWR3 PPWR2 2 3 J5 ESD Options 0.1uF BR1 C18 + C12 IN GND 0.1uF 1 3 2 PPWR2 USBDN_DP2 USBDN_DM2 4 2 VCC D+ D- 4 5 6 100uF GND SH1 SH2 C47 PRTCTL2 PRTCTL3 GND 2 FB 4 VR1 50K DNP C13 10uF R5 34.0K 1% C R10 1 C16 + 10uF Tant DNP TP18 VIA HSIC Interface 2 3 (0V66 - 1V6) J7 U.FL 1 42 HSIC_DATA 43 HSIC_STROBE 2 3 J6U.FL R12 3V3 1 U3A USB4640_QFN48 USB 100K 39 HSIC_IMP HSIC_IMP: Low: 40 Ohm Driver High: 50 Ohm Driver 3V3 USBDN_DP2 HSIC_STROBE HSIC_IMP USBDN_DM2 PRTCTL3 USBDN_DP3 USBDN_DM3 6 0.1uF USBDN_DP2 1 USBDN_DM2 7 4 USBDN_DP3 3 USBDN_DM3 3 SPI_CLK/GPIO4/SCL SPI_DO/GPIO5/SDA/SPI_SPD_SEL SPI_DI SPI_CE_N 9 10 11 8 SPI_CLK/GPIO4/SCL SPI_DO/GPIO5/SDA SPI_DI SPI_CE# R28 R24 R52 1 J8 DNP R15 10K TEST 40 p3 TEST RBIAS 47 1% RBIAS R14 ZERO ZERO 6 5 2 1 SPI SPI 3V3 R50 R47 10K 10K 3 7 10K SPI SCK SI SO CS* 8 VCC C35 0.1uF WP* HOLD* 4 GND SPI_FLASH-25X20_SO8 1K 3V3 Prog J12 2 1 3V3 12.0K GND SH1 SH2 D C 60MHz,EEprom,I2C TEST 0.1uF 2 4 5 6 BGX50A ESD EEprom,I2C RESET R51 C37 C25 + 2 VCC D+ D- 4 3V3 38 4 100uF L2 ESD* DLP11SN900SL2 2 1 Misc. RESET# BR2 C32 2 1 3 2 PPWR3 USBDN_DP3 USBDN_DM3 U4 EEPROM R40 100K RESET PRTCTL2 HSIC_DATA TP17 VIA R11 100K DNP External 5V supply required for USB Down stream ports. 3.3V required for USB4640 and Media Power. 3 J10 1 EN 0.1uF BGX50A ESD 4 3 1.0uF R7 27.4k 1% (1V2) 3 TP15 VIA Downstream 3 TP16 VIA Upstream C11 VAROUT U2 TPS76201DBVR 1 5 IN OUT CW 3V3 L1 ESD* DLP11SN900SL2 2 1 DOWN STREAM 2 C4 1 330 DOWN STREAM 3 3 R4 VDD33 J4 1 USB_A-REC RA-THRU 1 U1 3V3 MIC37100-3.3WS_SOT223-3 1 3 VIN 3.3V_OUT C7 + 10uF R1 GND Tant 1K 2 USB_A-REC RA-THRU 5V FB1 EMI* J1 3 1 5 Prog 3V3 J9 C14 18pF XTAL1 B 45 3 XTAL1/CLKIN 2 Y1 24.000MHz R8 1Meg External 1.2V supply required for HSIC I/F. C10 GPIO10/CARD_PWR R3 330 37 Q1 MMBT3904LT1 GPIO1 p3 GPIO2 p3 RESET# p3 SPI_CLK/GPIO4/SCL p3 SPI_DO/GPIO5/SDA p3 SPI_DI p3 SPI_CE#_R p3 "GPIO1" GPIO1 D6 TP20 DNP Orange XTAL2 R9 10K 44 46 PLLFILT XTAL2 PLLFILT GPIO2/RXD Power VDD12 36 "GPIO2" GPIO2 330 R27 330 SPI_CLK/GPIO4/SCL SPI_DO/GPIO5/SDA SPI_DI_R SPI_CE#_R GRN VAROUT C19 C20 C22 1.0uF 0.1uF DNP 0.1uF VDD33 VDD33 J13 R16 GRN D8 41 B SPI Programming Socket/ EEPROM, I2C CRD_PWR DNP* TP19 DNP "SUSPEND" D4 1 GPIO10/CRD_PWR 18pF GPIO1/LED1/TXD 3V3 35 U6 24C04B-DIP8 1 2 3 VDD33 7 6 5 48 C27 C21 C26 FB2 VDDA* A0 A1 A2 SDA VCC 5 EEprom,I2C GND EEprom 3 7 SCK/SCL SI/SDA SO/A1 CS*/A0 8 VCC C41 0.1uF WP*/A2 HOLD*/WP GND 4 DIP8_LEAF_Socket 8 WP SCL EEprom,I2C R45 10K R46 10K 6 5 2 1 4 EEprom,I2C R48 ZERO R49 ZERO EEprom,I2C External Memory Options (See User Manual for details) *Default configuration is for 60MHz SPI 0.1uF 0.1uF 4.7uF A A CRFILT *Note 1: Solder shorting jumper across pins 1 and 2 for default setup. C36 C33 0.1uF DNP 49 1.0uF Note: *To use the devices indicated by an *, cut shorting traces. 5 15 4 VDD33 CRFILT VSS(FLAG) VDD33 VDD33 VDD33 VDD33 12 16 25 34 C30 C34 0.1uF 0.1uF 0.1uF 0.1uF 4.7uF 3 C31 C24 Austin Design Center 10900-B Stonelake Blvd., Ste. 100 Austin, TX 78759 512.502.0070 C23 Title: Evaluation Platform for USB4640, Part Number: EVB-USB4640 Project Size: B Name: Date: Friday, October 29, 2010 2 QFN48 pkg Naiad Sheet 1 2 Rev C of 3 5 4 3 2 GPIO15/SD_nCD_S 1 GPIO15/SD_nCD_S SD_WP_RR U3B <Device> J14 Normal Mount SD/MMC4.0 (Proconn) 2 CMD VCC Media I/F: xD/MS/SD D xD_D0/SD_D6/MS_D7 xD_D1/SD_D7/MS_D6 xD_D2/SD_D0/MS_D4 xD_D3/SD_D1/MS_D5 xD_D4/GPIO6/SD_WP/MS_SCLK xD_D5/SD_D2 xD_D6/SD_D3/MS_D3 xD_D7/SD_D4/MS_D2 xD_ALE/SD_D5/MS_D1 xD_CLE/SD_CMD/MS_D0 xD_RE xD_WE xD_WP/SD_CLK/MS_BS xD_CE xD_B/R 20 19 18 17 13 33 32 30 SD_D6_R SD_D7_R SD_D0_R SD_D1_R SD_WP_R SD_D2_R SD_D3_R SD_D4_R R31 R36 R30 R35 R29 R19 R20 R23 33 33 33 33 33 33 33 33 SD_CMD 23 24 27 22 21 26 SD_D5_R SD_CMD_R xD_nRE_R xD_nWE_R SD_CLK_R xD_nCE_R R38 R33 R25 R32 R37 R26 33 33 33 33 33 33 xD_nRE xD_nWE SD_D4 SD_D5 SD_D6 SD_D7 28 xD_nB/R_R R22 33 xD_nB/R R18 R21 R34 33 33 33 MS_INS xD_nCD 31 29 14 GPIO12/MS_INS GPIO14/xD_CD GPIO15/SD_nCD GPIO12/MS_INS_R GPIO14/xD_nCD_R GPIO15/SD_nCD_R 7 8 9 1 SD_D0 SD_D1 SD_D2 SD_D3 SD_CLK 5 10 11 12 13 20 21 xD_nCE CRD_PWR R41 ZERO CRD_PWR 4 C44 D0 D1 D2 D3 0.1uF GND1 GND2 D9 Bright_GRN C28 D 4.7uF 3 6 SD_nCD CLK D4 D5 D6 D7 DET SD_WP SwGND1 SwGND2 SwGND3 SwGND4 nc1 nc2 R13 14 15 GPIO15/SD_nCD SD_WP R44 R43 R42 2.2K 4.7K 4.7K 16 17 18 19 C39 0.1uF C40 0.1uF 330 C17 0.1uF C C B B JTAG Header R39 p2 RESET# ZERO xD/MS Adapter Card Header RESET#_R J16 J11 (nTRST) 1 (TDO) 3 (TMS) 5 7 (TCK) 9 (gnd) (VCC_dcard) 11 2 4 6 8 10 12 GPIO15/SD_nCD_S p2 GPIO1 xD_nCD p2 GPIO2 (gpio) (TDI) (nRST_DUT) (TEST) (gnd) (VCC_dcard) TEST p2 CRD_PWR 2 4 6 8 10 VIA VIA VIA VIA VIA xD_nCD xD_nCE GPIO15/SD_nCD_S TP2 TP4 TP8 TP10 TP12 1 3 5 7 9 2 4 6 8 10 TP3 TP5 TP9 TP11 TP13 VIA VIA VIA VIA VIA p2 SPI_CE#_R p2 SPI_CLK/GPIO4/SCL p2 SPI_DO/GPIO5/SDA p2 SPI_DI p2 RESET# R53 (ce#) 2 (clk) 4 (si) 6 (so) 8 ZERO RESET#_P (rst#_dut) 10 1 3 5 7 9 (+5V) (+5V) (gnd) (gnd) (gnd) C45 0.1uF C46 4.7uF (2x5 RA) Perseus(Trace) 2x5RA, 2mm 3V3 A 1 3 5 7 9 5V J15 J3 *Note, remove R71 when using this adapter card. Nexys 2 I/F For Test Use Only MS_INS xD_nRE xD_nWE xD_nB/R SD_nCD MS_INS Perseus SPI Header Breadboard 5V A (5V_EXT) C29 EMI 33pF C42 EMI 33pF C43 DNP C2 EMI 0.001uF C15 EMI 0.001uF C3 EMI 33pF C5 EMI 33pF C6 EMI 0.001uF C8 EMI 0.1uF 3V3 DNP TP7 DNP TP6 DNP DNP DNP TP22 TP21 TP14 5V DNP TP1 Austin Design Center 10900-B Stonelake Blvd., Ste. 100 Austin, TX 78759 512.502.0070 Title: Evaluation Platform for USB4640, Part Number: EVB-USB4640 Project Size: B Name: Date: Friday, October 29, 2010 Optional Devices 5 4 3 2 QFN48 pkg Naiad Sheet 1 3 Rev C of 3