5 4 3 1 Revision History EVB-USB5744 Evaluation Board for USB5744-A0 D 2 Revision Date Self-powered platform from 12 VDC Can supply maximum USB current to all ports simultaneously 4 Down Stream USB 3.1 Gen 1 ports Optional SPI programming and configuration Battery Charging on all ports 2.1 A (max.) Port Power per any port. Over 5 A (total) Port Power down stream at any one time! Revision Summary Author 00A 20140604 Initial design C. Johnson 01A 20140616 Revised per initial feedback. C. Johnson 02A 20140701 Revised per final feedback. C. Johnson A 20140711 Released C. Johnson A0 20141022 Changed part number for MUX IC between the SPI and Strap Select switches. J. Hancock A1 20150924 Changed all PPCs with new Micrel part number. This also caused a change in ILIMIT resistor for each PPC. J. Hancock D Functional Block Diagram Ext. 12V supply C C 5V Regulator Down Stream 3V3 Regulator 1V2 Regulator USB5744-A0 VDD33 (QFN56) VDD12 HS USB 3.1 Port 1 SS-Tx SS-Rx HS Up Stream B USB 3.1 Port 0 HS SS-Tx SS-Rx SS-Tx SS-Rx HS USB 3.1 Port 2 B USB 3.1 Port 3 SS-Tx SS-Rx HS SPI Flash Option USB 3.1 Port 4 SS-Tx SS-Rx PRT PWR Indicators A A Microchip Technology, Inc. USB/Networking Group - UNG www.Microchip.com Description: Evaluation Board for USB5744-A0, QFN56 Page Content: Title Page Project PN: Truffle EVB-USB5744 Name: Size: Date: Thursday, September 24, 2015 Sheet 1 B 5 4 3 2 1 of 3 Rev.: A1 4 3 3V3 R42 10K U8 VCC >60 MHz R58 10K R61 10K rsv1 DO CEn_F WPn HOLDn R54 100K XTALI/CLK_IN R53 100K *Note: For best functionality, use 60MHz SPI devices 2 1 J10 CE# EN (*short) rsv2 DI CEn 2 3 5 6 11 10 14 13 1 15 SHUNT1 IA0 YA IA1 IB0 YB IB1 IC0 YC IC1 ID0 YD ID1 VCC S E GND 4 4 USBTXM_DN3 USBTXP_DN3 53 SPI_SCK SPI_DO SPI_DI SPI_CE_n 7 SPI / Config 38 39 40 41 SPI_CLK/SMCLK SPI_DO/SMDAT SPI_DI/CFG_BC_EN SPI_CE_N/CFG_NON_REM 3V3 No BC Prt1 BC Prt1-2 BC Prt1-3 BC *Prt1-4 BC reserved 8 C68 Port Power Control PRT_CTL1 PRT_CTL2 PRT_CTL3 GANG_PWR/PRT_CTL4 200K 200K 10K 10K 10 10 1 2 3 4 5 6 5 12 15 21 28 33 43 49 VDD12 7 CFG_BC SW_SIP7 1 2 3 4 5 6 7 A 4.7uF DNP USB5744 Power Decoupling C19 C20 C23 C31 C38 C42 20 19 USB_SSTXM_DN3 USB_SSTXP_DN3 C41 C34 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C62 Slide-Top SW7 6 5 4 3 2 1 GND(Flag) 30 29 USB_SSRXM_DN4 USB_SSRXP_DN4 27 26 USB_SSTXM_DN4 USB_SSTXP_DN4 36 35 34 32 PCTL1 PCTL2 PCTL3 PCTL4 C25 MMBD914 U12 2 4 74LVC1G14 R67 1K 0.1uF C40 6 4 3 ZERO VIN C30 0.1uF 0.1uF 0.1uF VOUT ILIMIT C24 C10 0.1uF C9 0.1uF 6 4 3 ZERO + + SSTXM_C_DN3 SSTXP_C_DN3 5 6 7 8 9 150uF 1 2 3 4 SSTXM_C_DN4 SSTXP_C_DN4 5 6 7 8 9 C11 0.1uF 1 2 6 4 3 VIN R20 100 1% R8 330 Vbus DD+ GND1 SSRXSSRX+ GND2 SSTXSSTX+ Vbus DD+ GND1 SSRXSSRX+ GND2 SSTXSSTX+ Vbus DD+ GND1 SSRXSSRX+ GND2 SSTXSSTX+ R7 330 R6 330 Sh1 Sh2 Port 2 R2 330 C2 0.1uF 12 13 USB 3.1 Gen 1 A-REC THRU Sh1 Sh2 Port 3 R3 330 C3 0.1uF 12 13 C USB 3.1 Gen 1 A-REC THRU Sh1 Sh2 Port 4 R4 330 C4 0.1uF 12 13 R5 330 C55 5 7 R21 100 1% 0.1uF 0.1uF 2.1A VOUT ILIMIT 1 2 C56 5 7 R22 100 1% 0.1uF Test-DNP XTALI 0.1uF XTALO EN GND FAULT EP TP13 CEn R55 CEn_F R52 2.1A VOUT ILIMIT TP7 1 2 J8 2 rsv1 (ss2/scl) 1 4 rsv2 (ss3/sda) 3 6 DI (miso) 5 8 (sclk) 7 SCK 10 ZERO (ss1) 9 ZERO Aardvark_I/F (gnd) (nc/5V) (nc/5V) (mosi) DO (gnd) C57 5 7 R23 100 1% A Microchip Technology, Inc. USB/Networking Group - UNG www.Microchip.com 0.1uF MIC2009_MLF-6 150uF C61 Description: Evaluation 0.1uF Board for USB5744-A0, QFN56 Page Content: USB5744-A0 Project PN: Truffle EVB-USB5744 Name: Size: Date: Thursday, September 24, 2015 Sheet 2 B 3 USB 3.1 Gen 1 A-REC THRU B 1 2 1.0nF 1.0nF 4 D 0.1uF *Note: MIC2009 device has an auto-discharge function. 5 12 13 PWR1 PWR2 PWR3 PWR4 C54 5 7 2.1A VOUT ILIMIT EN GND FAULT EP U7 C17 0.1uF MIC2009_MLF-6 R27 C26 VIN C60 "SPI Select" D14 Blue C12 0.1uF EN GND FAULT EP C59 0.1uF 2.1A MIC2009_MLF-6 57 330 C1 J4 EN GND FAULT EP C58 "Strap Select" D13 Br_Grn 1.0nF 1.0nF 150uF 1 2 3 4 PWR4 + 4.7uF DNP C43 VIN R1 J3 MIC2009_MLF-6 VDD33 C18 6 ZERO ZERO C21 U4 4 3 R24 R26 D31 10K 0.1uF C16 R25 (Fill the GND FLAG with at least 20 GND vias.) 3V3 R64 C7 25 24 Config. Select 3V3 C22 USB_SSRXM_DN3 USB_SSRXP_DN3 U6 (*SPI=1-2, Strap=2-3) 0.1uF PWR3 CFG_NON_REM SW_SIP7 VDD12 23 22 TP3 200K 200K 10K 10K 10 10 C8 C15 U5 5 R41 R43 R44 R45 R46 R47 *All Removable Prt1 Non-Rem Prt1-2 Non-Rem Prt1-3 Non-Rem Prt1-4 Non-Rem reserved VDD33 VDD33 VDD33 VDD33 SW6 3 1 2 3 4 5 6 VDD12 VDD12 VDD12 VDD12 VDD12 VDD12 VDD12 VDD12 16 31 44 55 VDD33 Non-Rem Select 3V3 Power SSTXM_C_DN2 SSTXP_C_DN2 5 6 7 8 9 18 17 5V 0.1uF SW5 R35 R36 R37 R38 R39 R40 USB_SSTXM_DN2 USB_SSTXP_DN2 TP1 1 2 3 4 5 6 B 11 10 16 Bat. Chg Select 3V3 USBRXM_DN4 USBRXP_DN4 USBTXM_DN4 USBTXP_DN4 PI3B3257 Strapping Option USB_SSRXM_DN2 USB_SSRXP_DN2 USBDN_DM4 pg3 USBDN_DP4 pg3 USBDM_DN4/Dis USBDP_DN4/Dis 150uF C14 14 13 Sh1 Sh2 Port 1 J2 1 2 3 4 PWR2 9 8 XTALO 9 12 USBDM_DN3/Dis USBDP_DN3/Dis USBRXM_DN3 USBRXP_DN3 1 XTALO 25MHz 0.1uF USBDN_DM3 pg3 USBDN_DP3 pg3 Clock U11 SCK 3 7 WP HOLD GND C33 16pF 6 5 2 1 SCK SI SO CS C44 TP9 2 C5 SSRXSSRX+ GND2 SSTXSSTX+ USB 3.1 Gen 1 A-REC THRU Optional 1K 74LVC1G14 Y1 USBTXM_DN2 USBTXP_DN2 SSTXM_C_DN1 SSTXP_C_DN1 Vbus DD+ GND1 "PPWR1" RBIAS TESTEN/ATEST 54 3 5 "SPI Activity" D11 Blue R57 4 C 4 Bias/Test R12 1K XTALI 0.1uF + USBRXM_DN2 USBRXP_DN2 *Note: The system should supply RESETn in an embedded hub implementation. C29 16pF U9 0.1uF Reset SPI Option 2 USBDM_DN2/Dis USBDP_DN2/Dis RESET 56 52 C6 USBDN_DM2 pg3 USBDN_DP2 pg3 USBRXM_UP USBRXP_UP 42 pg3 RESETn USB_SSTXM_DN1 USB_SSTXP_DN1 + 51 50 USB_SSRXM_UP USB_SSRXP_UP 4 3 GRN 0.1uF USBTXM_DN1 USBTXP_DN1 USBTXM_UP USBTXP_UP D1 C51 48 47 USB_SSTXM_UP USB_SSTXP_UP 5 6 7 8 9 USB_SSRXM_DN1 USB_SSRXP_DN1 GRN 0.1uF 7 6 D2 SSTXM_C_UP SSTXP_C_UP C50 R11 12.0K 1% 3V3 USBRXM_DN1 USBRXP_DN1 1.0nF RBIAS TEST 8 USBDM_UP USBDP_UP 150uF C13 "PPWR2" 46 45 *Note that the SS signal pair Tx+/ are polarity swapped on the MicroB connector for improved routing. The same is true for the SS pair Rx+/-. 3V3 Upstream GRN 7 6 8 10 9 USBDM_DN1/Dis USBDP_DN1/Dis D3 0.01uF VBUS_UP USB_DM_UP USB_DP_UP C52 VBUS_DET/GPIO16 J1 1 2 3 4 PWR1 2 1 GRN 37 USBDN_DM1 pg3 USBDN_DP1 pg3 USB5744-A0 "PPWR3" U0 D4 11 13 14 15 16 12 D 1 "PPWR4" 0.1uF C65 R62 100K TP5 C67 1 2 3 4 5 2 VBUS_DET Downstream Vbus D& TH tabs (TID#) D+ id GND1 ShL ShP1 SSTX+ ShP2 SSTXShP3 GND2 ShP4 SSRX+ ShR SSRX- 330 100K C53 2.2uF Note: Population Option Defaults are: Port 0 J12 DNP No USB 3.1 Gen 1 Unmarked Yes u-B REC, SMT R66 3 R60 TP4 5 Note: Default selections are marked with an asterisk (*) . 2 1 of 3 Rev.: A1 5 4 TP2 5V25 Regulator, <6A 12V In J9 3 TP6 1 R59 1 0.1uF 2 20 J6 VIN ENABLE VOUT TRIM 6_Amp GND C46 Ext. 12V DNP 2 C66 D30 MMBD914 3 2 1 12V_EXT 4 5 C39 R56 255 10uF 1% 3 10uF 25V D 1 Power Regulation & Reset 5V U3 2.5 mm 2 C37 0.1uF D 3V3 100K SW8 3 4 J11 2 U10 2 1K 74LVC1G14 1 C64 1.0nF "Reset" D12 Red R63 4 3 1 2 5 R65 -RESET- Ext_Rst RESETn pg2 3V3 Regulator, >200 mA with PwrGood 1 2 3 6 5V_REG_3V3 2A/0.05DCR R13 47K EN3 C36 4.7uF C35 C48 1.0uF 1.0nF U2 MCP1725-ADJ_SOIC8 8 500mA VIN1 VOUT VIN2 7 Shdn ADJ 5 Cdelay PWRGD 3V3 R16 1% C VDD33 R9 3V3 ZERO 150K R28 1K TP11 TP10 R15 21.0K 1% C45 C47 LED_P FB4 GND 5V 4 C C49 4.7uF 0.1uF 1.0nF D5 Br_Grn "3V3 Present" 1V2 Regulator, 1A *Note: VDD12 should come up before VDD33. B VDD12 B U1 FB3 2 5V_REG_1V2 EN12 1 R14 ZERO C32 2A/0.05DCR C63 VIN ENABLE 3_Amp 10uF VOUT TRIM GND 4 5 R10 1V2_REG ZERO 3 R33 1.91K 1% DNP 0.1uF R34 29.4K 1% DNP C28 C27 10uF 0.1uF TP12 TP8 Port Disable Strap Option LED_P *Note: Pull up both DP and DM on a port to disable it. D6 FB1 DNP 3V3 DNP RED (*1-2, Port Enabled, 2-3, Port Disabled) TP15 pg2 USBDN_DM1 pg2 USBDN_DP1 "Port 2 Enabled" D8 Br_Grn pg2 USBDN_DM2 pg2 USBDN_DP2 SW3 Slide-Top ON-ON pg2 USBDN_DM3 pg2 USBDN_DP3 2 Port 3 SW4 Slide-Top ON-ON "Port 3 Enabled" D9 Br_Grn 1V2_REG 4 MT2 MT1 VDD12 A Port 4 Microchip Technology, Inc. USB/Networking Group - UNG www.Microchip.com "Port 4 Enabled" D10 Br_Grn Description: Evaluation pg2 USBDN_DM4 pg2 USBDN_DP4 3 TP14 FB2 DNP Board for USB5744-A0, QFN56 Page Regulators & Configuration Content: Project Truffle PN: EVB-USB5744 Name: Size: Date: Thursday, September 24, 2015 Sheet 3 B 5 3V3 2A/0.05DCR 1K 5 3V3 2 Port 2 R32 1 3 4 6 SW2 Slide-Top ON-ON 1K 1 3 4 6 "Port 1 Enabled" D7 Br_Grn 3V3 2 Port 1 R31 5 1K 5 R30 1 3 4 6 SW1 Slide-Top ON-ON 5 3V3 2 3V3 1K 1 3 4 6 A R29 VDD33 2A/0.05DCR 2 1 of 3 Rev.: A1