EVB-USB5734 Evaluation Board Schematics, PDF

5
4
3
Revision Date
Self-powered platform from 12 VDC
Can supply maximum USB current to all ports simultaneously
4 Down Stream USB 3.1 Gen 1 ports
Optional SPI programming and configuration
Battery Charging on all ports
2.1 A (max.) Port Power per any port.
Over 5 A (total) Port Power down stream at any one time!
Functional Block Diagram
Ext. 12V supply
1
Revision History
EVB-USB5734
Evaluation Board for USB5734-Axx1
D
2
Author
00A
20140702 Initial design based on Truffle_A.
C. Johnson
01A
20140708 Incorporated feedback from final review.
C. Johnson
A
20140709 Renumbered and released
C. Johnson
A0
20140822 Replaced MUX p/n tied to the SPI/I2C pins (page 2). Changed LED colors
on the BC Mode 5 I/O Card and udpated LED labels.
J. Hancock
00B
20141016 Removed Perseus DNP Test Card. Incorporated features from EVB
Board Spec.
J. Hancock
01B
20141021 Added VBUS_DET select switch. Added LEDs to all slide switches
(orange = Flex, green = GPIO). Added Reset and VBUS_DET signals to I/O
Connector. Added GPIO4/GPIO5 config/probe headers.
J. Hancock
02B
20141022 Corrected diode positions for SPI activity. Added DTE label to DSUB9
connector. Removed VBUS_DET Sel. switch circuit. Added ID pin to IO
connector. Added GND to pin 9 of IO connector on all DCs and Main EVB.
Reversed pinout of Config Select switch for SPI/Strap options.
J. Hancock
03B
20141105 Removed all Test Points on SMBUS headers on IO cards.
J. Hancock
04B
20141216 Made changes to UART circuit to support various flow control options.
J. Hancock
B
20150108 Removed UART Mux and switches and replaced with pull-down resistors on
J. Hancock
CTS, DCD and DSR and included a 1x2 header on FORCEOFF for the transceiver.
C
B1
5V Regulator
Revision Summary
20150924 Changed all PPCs with new Micrel part number. This also caused a change
in ILIMIT resistor for each PPC.
D
C
J. Hancock
Down Stream
3V3 Regulator
1V2 Regulator
USB5734-Axx1
VDD33 (QFN64)
VDD12
HS
USB 3.1
Port 1
SS-Tx
SS-Rx
HS
Up Stream
B
USB 3.1
Port 0
HS
SS-Tx
SS-Rx
SS-Tx
SS-Rx
HS
SPI Flash
Option
Bat. Chrg
Strap Option
Non-Rem
Strap Option
A
USB 3.1
Port 2
B
USB 3.1
Port 3
SS-Tx
SS-Rx
HS
USB 3.1
Port 4
SS-Tx
SS-Rx
IO Daughter Cards
Config_Func[7:1]
Mode
Config
Function Option
Header
(default = Mode 4)
IO
Daughter
Card
Mode 1
Mode 3
Mode 5
Mode 2
Mode 6
A
Microchip Technology, Inc.
USB/Networking Group - UNG
www.Microchip.com
Description: Evaluation
Board for USB5734-Axx1, QFN64
Page
Content: Title Page
Project
PN:
Torrent
EVB-USB5734
Name:
Size:
Date: Thursday, September 24, 2015
Sheet 1
B
5
4
3
2
1
of
4
Rev.:
B1
4
D11
C33
3V3
R42
10K
VCC
R58
10K
XTALO
>60 MHz
0.1uF
4
WPn
HOLDn
R54
100K
2
3
GPIO4
5
DO
6
GPIO5
11
DI
10
14
CEn
13
SCK
CEn_F
3
7
WP
HOLD
GND
4
USBTXM_DN3
USBTXP_DN3
61
J10
2
1
CE# EN
(*short)
R53
100K
SHUNT1
*Note: For best functionality,
use 60MHz SPI devices
4
7
9
12
SPI / I2C / UART/ Config
42
43
44
45
SPI_SCK
SPI_DO
SPI_DI
SPI_CE_n
SPI_CLK/TCK/UART_RX/GPIO4
SPI_DO/UART_TX/GPIO5
SPI_DI/CFG_BC_EN/GPIO9
SPI_CE_N/CFG_NON_REM/GPIO7
1
2
3
4
5
6
B
8 C68
Bat. Chg Select
SW5
R35
R36
R37
R38
R39
R40
No BC
Prt1 BC
Prt1-2 BC
Prt1-3 BC
*Prt1-4 BC
reserved
200K
200K
10K
10K
10
10
1
2
3
4
5
6
7
USBRXM_DN4
USBRXP_DN4
16
USB_SSRXM_DN3
USB_SSRXP_DN3
22
21
USB_SSTXM_DN3
USB_SSTXP_DN3
CFG_BC
32
31
USB_SSRXM_DN4
USB_SSRXP_DN4
29
28
USB_SSTXM_DN4
USB_SSTXP_DN4
50
39
40
46
47
49
16
VDD33
18
33
52
63
SW_SIP7
38
37
36
34
LINX_DAT/OCS1/PRT_CTL1
CFG_STRAP/JTAG_TDI
LINX_CLK/OCS2/PRT_CTL2
LINX_ALERT_N/OCS3/PRT_CTL3
Prog_Func
GANG_PWR/OCS4/PRT_CTL4
PROG_FUNC1/JTAG_TDO
PROG_FUNC2/JTAG_TCK
PROG_FUNC3/JTAG_TMS
VDD12
PROG_FUNC4
VDD12
PROG_FUNC5
VDD12(PLL)
PROG_FUNC6
VDD12
PROG_FUNC7
VDD12
VDD12
VDD33(PLL)
VDD12
VDD33
VDD12
(Fill
the
GND
FLAG
with
VDD33
at
least
20
GND
vias.)
VDD33(PLL)
GND
1
PROG_FUNC1
PROG_FUNC2
PROG_FUNC3
PROG_FUNC4
PROG_FUNC5
PROG_FUNC6
PROG_FUNC7
Port Power Control
Config Strap
PCTL1
PCTL2
PCTL3
PCTL4
U4
6
4
3
R24
ZERO
6
13
17
23
30
35
51
57
6
4
3
R25
ZERO
200K
200K
10K
10K
10
10
1
2
3
4
5
6
7
C22
C20
C23
C31
C38
C42
C41
C34
C62
C25
A
4.7uF
DNP
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
0.1uF
C40
C30
0.1uF 0.1uF 0.1uF
C24
C26
1.0nF 1.0nF
6
4
3
1
SW7
5 R64
2 R67
Slide-Top
(*Strap=1-2, SPI=2-3)
5
5
7
9
11
13
15
17
19
RESETn_R
USB_ID
4
R48
Br_Grn
10K
10K
1
3
GPIO4
GPIO5
"SPI Select"
D14
Blue
D13
R50
R51
GPIO4
GPIO5
10K
1K
SMBUS/UART
Select
2
4
10K
D31
ZERO
2
3
SMBUS Slave = GPIO4 PU &
GPIO5 PU
SMBUS Master = GPIO4 open &
GPIO5 open
UART Enable = GPIO4 open &
GPIO5 PD
3V3
3V3
MMBD914
VIN
C9
0.1uF
U7
6
4
3
R27
ZERO
C17
C12
0.1uF
C11
0.1uF
SSRXSSRX+
GND2
SSTXSSTX+
USB 3.1
Vbus Gen 1
DA-REC
D+
THRU
GND1 (TID#)
SSRXSSRX+
GND2
SSTXSSTX+
+
+
150uF
1
2
3
4
Sh1
Sh2
SSTXM_C_DN4
SSTXP_C_DN4
5
6
7
8
9
USB 3.1
Vbus Gen 1
DA-REC
D+
THRU
GND1 (TID#)
SSRXSSRX+
GND2
SSTXSSTX+
C54
5
7
R20
100
1%
R2
330
C2
0.1uF
12
13
Port 3
R3
330
C3
0.1uF
12
13
C
Sh1
Sh2
Port 4
R4
330
C4
0.1uF
12
13
0.1uF
R8
330
R7
330
R6
330
R5
330
B
2.1A
VOUT
ILIMIT
1
2
C55
5
7
R21
100
1%
0.1uF
0.1uF
2.1A
VOUT
ILIMIT
1
2
C56
5
7
R22
100
1%
0.1uF
VIN
0.1uF
XTALI
2.1A
VOUT
ILIMIT
EN
GND
FAULT EP
1
2
TP7
XTALO
TP13
C57
5
7
R23
100
1%
A
Microchip Technology, Inc.
USB/Networking Group - UNG
www.Microchip.com
0.1uF
MIC2009_MLF-6
150uF
C61
0.1uF
*Note: MIC2009 device has an auto-discharge function.
"Strap Select"
Description: Evaluation
Board for USB5734-Axx1, QFN64
Page
Content: USB5734-Axx1
Project
PN:
Torrent
EVB-USB5734
Name:
Size:
Date: Thursday, September 24, 2015
Sheet 2
B
3
Sh1
Sh2
Port 2
PWR1
PWR2
PWR3
PWR4
0.1uF
EN
GND
FAULT EP
C60
1
D
MIC2009_MLF-6
GPIO4 3V3
J27
2
1
J5
GPIO5
J28
UART
6
4
3
R26
USB 3.1
Vbus Gen 1
DA-REC
D+
THRU
GND1 (TID#)
1
2
+
4.7uF
DNP
C43
key
SHUNT2
Config. Select
3V3
C18
1
1.0nF 1.0nF
VDD33
C21
2
4
6
8
10
12
14
16
18
20
Daughtercard Interface
for All IO Modes
3V3
J7
VBUS_DET_R
PROG_FUNC1
PROG_FUNC2
PROG_FUNC3
PROG_FUNC4
PROG_FUNC5
PROG_FUNC6
PROG_FUNC7
MUX_CTL
CFG_STRAP
VOUT
ILIMIT
EN
GND
FAULT EP
U6
Register Value:0x1B (Jumper pins 19-20 to enable Mode 4: *default)
USB5734 Power Decoupling
C19
0.1uF
MIC2009_MLF-6
IO Mode 4: Custom GPIO Mode
CFG_NON_REM
SW_SIP7
VDD12
VIN
C59
SW6
R41
R43
R44
R45
R46
R47
12
13
2.1A
EN
GND
FAULT EP
U5
TP3
*All Removable
Prt1 Non-Rem
Prt1-2 Non-Rem
Prt1-3 Non-Rem
Prt1-4 Non-Rem
reserved
VIN
C58
TP5
1
2
3
4
5
6
C10
MIC2009_MLF-6
VDD12
65
0.1uF
J4
Non-Rem Select
3V3
SSTXM_C_DN3
SSTXP_C_DN3
5
6
7
8
9
PWR4
5V
0.1uF
150uF
C16
USBTXM_DN4
USBTXP_DN4
CFG_STRAP
3V3
25
24
330
C1
J3
1
2
3
4
27
26
USB2DM_DN4/Dis
USB2DP_DN4/Dis
3V3
PI3B3257
Strapping Option
0.1uF
USBDN_DM4 p3
USBDN_DP4 p3
IA0 YA
IA1
IB0 YB
IB1
IC0 YC
IC1
ID0 YD
ID1
VCC
S
E GND
1
15
C7
PWR3
XTALO
U11
R61
10K
6
5
2
1
SCK
SI
SO
CS
C44
25MHz
0.1uF
C15
USBRXM_DN3
USBRXP_DN3
16pF
U8
8
2
Blue
3
74LVC1G14
TP9
1K
C8
20
19
XTALI/CLK_IN
Sh1
Sh2
R1
Optional
R57
USB_SSTXM_DN2
USB_SSTXP_DN2
GRN
"SPI Activity"
4
SSTXM_C_DN2
SSTXP_C_DN2
5
6
7
8
9
D1
Y1
12
11
USBDN_DM3 p3
USBDN_DP3 p3
1
5
2
C
USBTXM_DN2
USBTXP_DN2
USB2DM_DN3/Dis
USB2DP_DN3/Dis
Clock
62
16pF
U9
3V3
R12
1K
XTALI
C29
RBIAS
TESTEN/ATEST
USB_SSRXM_DN2
USB_SSRXP_DN2
SSRXSSRX+
GND2
SSTXSSTX+
Port 1
"PPWR1"
3V3
Bias/Test
64
60
RBIAS
TEST
15
14
GRN
*Note: The system should supply
RESETn in an embedded
hub implementation.
R11
12.0K
1%
SPI Option
USBRXM_DN2
USBRXP_DN2
ZERO
150uF
C14
RESET
USB 3.1
Vbus Gen 1
DA-REC
D+
THRU
GND1 (TID#)
J2
1
2
3
4
PWR2
D2
R52
0.1uF
10
9
USB2DM_DN2/Dis
USB2DP_DN2/Dis
Reset
SSTXM_C_DN1
SSTXP_C_DN1
"PPWR2"
RESETn_R
3
*Note that the SS signal pair Tx+/
are polarity swapped on the MicroB
connector for improved routing.
The same is true for the SS pair Rx+/-.
C5
USBDN_DM2 p3
USBDN_DP2 p3
USBRXM_UP
USBRXP_UP
48
p3 RESETn
0.1uF
+
59
58
USB_SSRXM_UP
USB_SSRXP_UP
C6
+
0.1uF
USB_SSTXM_DN1
USB_SSTXP_DN1
GRN
C51
5
4
USBTXM_DN1
USBTXP_DN1
USBTXM_UP
USBTXP_UP
5
6
7
8
9
USB_SSRXM_DN1
USB_SSRXP_DN1
D3
SSTXM_C_UP
SSTXP_C_UP
56
55
USB_SSTXM_UP
USB_SSTXP_UP
8
7
USBRXM_DN1
USBRXP_DN1
"PPWR3"
7
6
8
10
9
ShL
SSTX+
ShP1 SSTXShP2 GND2
ShP3 SSRX+
ShP4 SSRXShR
0.1uF
USBDM_UP
USBDP_UP
150uF
C13
Upstream
54
53
C50
USB2DM_DN1/Dis
USB2DP_DN1/Dis
GRN
11
13
14
15
16
12
0.01uF
VBUS_UP
USB_DM_UP
USB_DP_UP
USB_ID
C52
1.0nF
3
4
5
VBUS_DET/GPIO16
J1
1
2
3
4
PWR1
3
2
D4
D
41
VBUS_DET
USBDN_DM1 p3
USBDN_DP1 p3
USB5734-Axx1-QFN64
U0
"PPWR4"
0.1uF
R62
100K
1
VBUS_DET_R
ZERO
C65
TP4
C67
R49
2
TP1
DD+
id
GND1
u-B REC
SMT &
TH tabs
(TID#)
330
100K
C53
2.2uF
Note: Population Option Defaults are:
Port 0 J12
No
DNP
USB 3.1
1
Unmarked Yes
Vbus 2
Gen 1
R66
R60
3
Downstream
5
Note:
Default selections are marked with an asterisk (*) .
2
1
of
4
Rev.:
B1
5
4
TP2
5V25 Regulator, <6A
12V In
J9
3
TP6
1
R59
1
0.1uF
2
20
J6
VIN
ENABLE
VOUT
TRIM
6_Amp
GND
C46
Ext. 12V
DNP
2
C66
D30
MMBD914
3
2
1
12V_EXT
4
5
C39
R56
255 10uF
1%
3
10uF
25V
D
1
Power
Regulation
& Reset
5V
U3
2.5 mm
2
C37
0.1uF
D
3V3
100K
SW8
3
4
J11
2
U10
2
1K
74LVC1G14
1
C64
1.0nF
"Reset"
D12
Red
R63
4
3
1
2
5
R65
-RESET-
Ext_Rst
RESETn p2
3V3 Regulator, >200 mA
with PwrGood
1
2
3
6
5V_REG_3V3
2A/0.05DCR
R13
47K
C36
4.7uF
EN3
C35
C48
1.0uF
1.0nF
U2
MCP1725-ADJ_SOIC8
8
500mA
VIN1
VOUT
VIN2
7
Shdn
ADJ 5
Cdelay
PWRGD
3V3
R16
1%
C
VDD33
R9
3V3
ZERO
150K
R28
1K
TP11
TP10
R15
21.0K
1%
C45
C47
LED_P
FB4
GND
5V
4
C
C49
4.7uF 0.1uF 1.0nF
D5
Br_Grn
"3V3 Present"
1V2 Regulator, 1A
*Note: VDD12 should come up before VDD33.
B
VDD12
B
U1
FB3
2
5V_REG_1V2
EN12 1
R14
ZERO
C32
2A/0.05DCR
C63
VIN
ENABLE
3_Amp
10uF
VOUT
TRIM
GND
4
5
R10
1V2_REG
ZERO
3
R33
1.91K
1%
DNP 0.1uF
R34
29.4K
1%
DNP
C28
C27
10uF
0.1uF
TP12
TP8
Port Disable Strap Option
LED_P
*Note: Pull up both DP and DM on a port to disable it.
D6
FB1 DNP
3V3
DNP RED
(*1-2, Port Enabled, 2-3, Port Disabled)
TP15
p2 USBDN_DM1
p2 USBDN_DP1
"Port 2 Enabled"
D8
Br_Grn
p2 USBDN_DM2
p2 USBDN_DP2
SW3
Slide-Top
p2 USBDN_DM3
p2 USBDN_DP3
Port 3
SW4
Slide-Top
"Port 3 Enabled"
D9
Br_Grn
p2 USBDN_DM4
p2 USBDN_DP4
VDD12
A
"Port 4 Enabled"
D10
Br_Grn
FOOT1
FOOT3
FOOT4
500x250-Clear 500x250-Clear
3
MT1
Microchip Technology, Inc.
USB/Networking Group - UNG
www.Microchip.com
FOOT2
4
MT2
FB2 DNP
Port 4
500x250-Clear 500x250-Clear
5
1V2_REG
TP14
2A/0.05DCR
1K
5
3V3
R32
2
Port 2
2
5
SW2
Slide-Top
1K
1
3
4
6
"Port 1 Enabled"
D7
Br_Grn
3V3
2
Port 1
R31
5
1K
1
3
4
6
SW1
Slide-Top
R30
1
3
4
6
5
3V3
2
3V3
1K
1
3
4
6
A
R29
3V3
VDD33
2A/0.05DCR
2
Description: Evaluation
Board for USB5734-Axx1, QFN64
Page
Regulators & Configuration
Content:
Project Torrent
PN: EVB-USB5734
Name:
Size:
Date: Thursday, September 24, 2015
Sheet 3
B
1
of
4
Rev.:
B1
10K
TP26
3V3_1
Female
R68
200K
SW12
5
2
GND_1
GND_1
6
4
3
1
GND_1
C5_CONFIG
330
330
330
330
R110
1K
R111
D36
Br_Grn
D37
Br_Grn
D50
Br_Grn
"PF6"
1K
R121
"PF7"
1K
GND_5
R70
10
(PF3 LED OFF = 0, PF3 LED ON = 1
*Low (0) = 1-2, High (1) = 2-3)
SW10
5
10K 2
R108
Polarizing Key, Male
Br_Org
Polarizing Key, Male
GND_1
D51
R96
10K
5
R122
1K
2
"FLEXCMD"
SW9
Vertical, 0.1"
(Default = 0, Flexed = 1
*Low (0) = 1-2, High (1) = 2-3)
GND_5
C2_CONFIG
R69
C2_LED_P0
C2_LED_P1
3V3_2
3V3_2
200K
Female
3V3_2
R73
GND_2
Br_Org
D49
R120
10K 5
1K
SW11
2
B
Polarizing Key, Male
GND_2
"FLEXCMD"
6
4
3
1
R88
10K
FLEX_CMD
Select
R78
10K
SMBus
J16
2
4
R19
1K
GND_2
2
4
6
8
10
12
14
16
18
20
5
(RESETn)7
9
(ID)11
13
15
17
19
Female
C6_RTSn
C6_CTSn
C6_DCDn
C6_SMDAT
C6_SMCLK
C6_DTRn
C6_DSRn
C6_MUX
C6_CONFIG
R74
1K
Br_Grn
Br_Grn
GND_2
C73
1K
10
C70
R87
1K
R105
1K
D26
D27
"RXD"
TP33
C6_RXLED
C6_CTSn
C6_RXD
C6_DSRn
C6_DCDn
C6_ROUT5
20
19
18
17
16
15
2
4
1
Blu 1
2
"P0_USB3"
J31
Xvr Disable
3 D15B
Yel 2
4 D16A
"P4_USB2"
Yel 2
"P3_USB2"
Yel 2
"P2_USB2"
4 D18A
4 D17A
D28
Br_Grn
21
22
23
VS+
C2+
VS-
Yel 2
C72
0.1uF
27
C71
0.1uF
3
C69
0.1uF
GND_6
C2TIN1
TIN2
TIN3
TXOUT1
TXOUT2
TXOUT3
ROUT2B
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
INVALID
FORCEOFF
FORCEON
9
10
11
C6_TXD_out
C6_RTS_out
C6_DTR_out
4
5
6
7
8
C6_CTS_in
C6_RXD_in
C6_DSR_in
C6_DCD_in
C6_RXIN5
Note:
*Straight cable:
SHUNT5
[1-2] & [3-4]
Simple Null Modem cable:
[1-3] & [2/4]
SHUNT6
J17
1
RXD 3
J18
B
(5K PD)
RXIN1
RXIN2
RXIN3
RXIN4
RXIN5
GND
25
10
TP27
GND_6
MAX3243_TSSOP28
11
DTE
GND_6
Standoff Nylon, 2x11.1mm
GND_6
Yel 2
"P0_USB2"
1
3
A
Microchip Technology, Inc.
USB/Networking Group - UNG
www.Microchip.com
MT4
Description: Evaluation
See the USB5734 page for Mode 4.
GND_3
GND
Board for USB5734-Axx1, QFN64
Page
IO Mode Daughter Cards
Content:
Project Torrent
PN: EVB-USB5734
Name:
Size:
Date: Thursday, September 24, 2015
Sheet 4
B
4
1
6
2
7
3
8
4
9
5
(cd)
(dsr_in)
(rxd)
(rts_out)
(txd)
(cts_in)
(dtr_out)
MT3
Vertical, 0.1"
5
2 TXD
4
"RXIN Signal"
4 D15A
Blu 1
3 D16B
Blu 1
"P4_USB3"
SMBus
J14
"P3_USB3"
R77
10K
1K
10K
10K
C1-
26
Vertical, 0.1"
GND_3
Polarizing Key, Male
14
13
12
VCC
GND_6
3 D17B
R80
10K
GND_3
GND_3
C6_TXD
C6_RTSn
C6_DTRn
C1+
Polarizing Key, Male
Blu 1
3V3_3
Female
R17
10K
Yel 2
C3_LED_P1
C3_LED_P2
C3_LED_P3
C3_LED_P4
C3_LED_P0
"P2_USB3"
330
330
330
330
330
3 D18B
R99
R94
R89
R85
R81
Blu 1
5
(RESETn)7
9
(ID)11
13
15
17
19
"P1_USB3"
Br_Grn
"3V3"
D25
2
4
C3_P1_USB3_USB2n
6
C3_P2_USB3_USB2n
8
C3_P3_USB3_USB2n
10 C3_SMDAT
12 C3_SMCLK
14 C3_P4_USB3_USB2n
16 C3_P0_USB3_USB2n
18
20 C3_CONFIG
3 D20B
1
R104
1K
"P1_USB2"
J21
4 D20A
IO DC
3V3_3
1
2
R102
R95
MMBD914
0.1uF
3V3_6
GND_6
D32
0.1uF 28
24
R79
R72
R18
3V3_3
"BC 1.2"
3V3_6
U13
3V3_6
Register Value:0x02
1
3
GND_6
GND_6
IO Daughter Card
Mode 3: USB Speed LEDs Mode
SMBus
J15
2
4
C6_SMDAT
C6_SMCLK
"TXD"
1
3
R71
10K
C6_TXD
C6_RXD
GND_6
Slide-Top
GND_2
(Default = 0, Flexed = 1
*Low (0) = 1-2, High (1) = 2-3)
Vertical, 0.1"
1
Br_Grn
10K
330
330
1K
R75
10K
GND_6
J24
D29
5
(RESETn)7
9
(ID)11
13
15
17
19
C2_VBD_DC
R128
C2_P0_USB3n_USB2
R98
C2_P1_USB3n_USB2
R92
C2_FLEX_STATE_N
R117
C2_SMDAT
Br_Org
D43
C2_SMCLK
"Flexed"
C2_FLEX_CMD
C2_FLEX_STATE
TP34
10K
10K
10K
IO DC
3V3_6
"3V3"
(*1-2 Default,
2-3 Inject) GND_2
C
3V3_6
R107
R109
R112
"P1_USB3"
3 D21B Blu 1
MMBD914
"P0_USB2"
4 D19A Yel 2
Br_Grn
"3V3"
D22
2
4
6
8
10
12
14
16
18
20
4 P4A
Note: Use of this IO Daughter Card prevents the use
of the on-board SPI and SMBUS Slave.
D33
J22
1
R100
1K
3V3_2
"P1_USB2"
4 D21A Yel 2
VBUS Sel. 3V3_2
J30
1
2
3
SHUNT4
"P0_USB3"
3 D19B Blu 1
3V3_2
Yel 2
GND_5
Register Value:0x1F
IO DC
"BC 1.2"
(PF7 LED OFF = 0, PF7 LED ON = 1
*Low (0) = 1-2, High (1) = 2-3)
IO Daughter Card
Mode 6: UART Mode
GND_1
C
A
GND_5
PF7 Select
FLEX_CMD Select
Vertical, 0.1"
Register Value:0x0B
4 P3A
3V3_5
6
4
3
1
Slide-Top
6
4
3
1
Slide-Top
IO Daughter Card
Mode 2: Flex Mode
Yel 2
D
"PF5"
Female
"BC 1.2"
C5_LED_P1
C5_LED_P2
C5_LED_P3
C5_LED_P4
GND_5
PF3 Select
Slide-Top
R93
R90
R86
R83
Yel 2
"BC 1.2"
C5_P1_BC_BC12n
C5_P2_BC_BC12n
C5_P3_BC_BC12n
C5_P4_BC_BC12n
C5_GPIO8
C5_GPIO10
C5_GPIO11
Grn 1
R84
1
3
5
(RESETn)7
9
(ID)11
13
15
17
19
"BC En"
C1_CONFIG
330
2
4
"USB 2.0 Active"
3
1
D48
3V3_1
D47B
Grn
MMBD914
2
4
D47A
Yel
"USB 2.0 Suspend"
GND_1
R101
1K
2
4
6
8
10
12
14
16
18
20
3 P4B
SMBus
J13
GND_1
R119
J23
1
SHUNT3
Grn 1
R82
10K
"BC En"
R76
10K
Br_Grn
3 P3B
D52
IO DC
3V3_5
4 P2A
"PF3"
Grn 1
1K
"BC En"
R123
Br_Grn
3 P2B
5
(RESETn)7
9
(ID)11
13
15
17
19
C1_VBD_DC
C1_GPIO1
C1_GPIO2
C1_GPIO3
C1_SMDAT
C1_SMCLK
C1_FLEX_CMD
C1_SUSPEND
(*1-2 Default,
GND_1
2-3 Inject)
"PF2"
D46
2
4
6
8
10
12
14
16
18
20
3V3_1
Br_Grn
MMBD914
Register Value:0x00
4 P1A
1K
D34
3V3_5
Grn 1
R91
"PF1"
1
"BC En"
Br_Grn
D24
"3V3"
R103
1K
1K
J20
1
D
10K
R97
D45
IO DC
3V3_1
R127
2
IO Daughter Card
Mode 5: Battery Charging LEDs Mode
Br_Grn
Register Value:0x0A
VBUS Sel. 3V3_1
J29
1
2
3
D23
IO Daughter Card
Mode 1: Suspend Mode
3
3 P1B
4
"3V3"
5
3
2
1
of
4
Rev.:
B1