Hermetic Packages for Integrated Circuits Ceramic Leadless Chip Carrier Packages (CLCC) J20.C MIL-STD-1835 CQCC3-N20 (C-13) 20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE 0.010 S E H S D INCHES D3 j x 45o E3 B E h x 45o 0.010 S E F S A A1 PLANE 2 PLANE 1 -E- MIN MAX MIN MAX NOTES A 0.060 0.120 1.52 3.05 6, 7 A1 0.050 0.088 1.27 2.23 - B - - - - - B1 0.022 0.028 0.56 0.71 2, 4 B2 B1 e L -H- L3 0.072 REF - 0.006 0.022 0.15 0.56 - D 0.280 0.305 7.11 7.75 - D1 0.150 BSC 3.81 BSC - D2 0.075 BSC 1.90 BSC - D3 - 0.305 E 0.420 0.440 10.67 7.75 2 11.18 - E1 0.250 BSC 6.35 BSC E2 0.125 BSC 3.17 BSC E3 - e 0.440 0.050 BSC 0.015 - - - 11.18 1.27 BSC 0.38 2 - - 2 h 0.040 REF 1.02 REF 5 j 0.020 REF 0.51 REF 5 L 0.045 0.055 1.14 1.40 - L1 0.045 0.055 1.14 1.40 - L2 0.075 0.095 1.91 2.41 - L3 0.003 0.015 0.08 0.38 ND 4 4 3 NE 6 6 3 N 20 20 3 -F- Rev. 0 6/13/95 B3 E1 E2 1.83 REF B3 e1 0.007 M E F S H S MILLIMETERS SYMBOL 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. L2 B2 L1 D2 e1 D1 NOTES: 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol “N” is the maximum number of terminals. Symbols “ND” and “NE” are the number of terminals along the sides of length “D” and “E”, respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer’s option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension “A” controls the overall package thickness. The maximum “A” dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH. 34