HA-5147/883 100MHz, Ultra Low Noise, Precision, High Slew Rate Operational Amplifier June 1998 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The HA-5147/883 monolithic operational amplifier features an unparalleled combination of precision DC and wideband high speed characteristics. Utilizing the Intersil DI technology and advanced processing techniques, this unique design unites low noise precision instrumentation performance with high speed wideband capability. • High Slew Rate . . . . . . . . . . . . . . . . . . . . . . 28V/µs (Min) • Wide Gain Bandwidth (AV ≥ 10) . . . . . . . 100MHz (Min) This amplifier’s impressive list of features include low VOS, wide gain-bandwidth, high open loop gain, and high CMRR. Additionally, this flexible device operates over a wide supply range while consuming only 120mW of power. • Low Noise (at 1kHz) . . . . . . . . . . . . . . . 4.5nV/√Hz (Max) • Low Offset Voltage. . . . . . . . . . . . . . . . . . . .100µV (Max) • Low Offset Drift With Temperature. . . . 1.8µV/oC (Max) Using the HA-5147/883 allows designers to minimize errors while maximizing speed and bandwidth in applications requiring gains greater than ten. • High CMRR . . . . . . . . . . . . . . . . . . . . . . . . . . 100dB (Min) • High Voltage Gain . . . . . . . . . . . . . . . . . . 700kV/V (Min) This device is ideally suited for low level transducer signal amplifier circuits. Other applications which can utilize the HA-5147/883’s qualities include instrumentation amplifiers, pulse or RF amplifiers, audio preamplifiers, and signal conditioning circuits. Applications • High Speed Signal Conditioners • Wide Bandwidth Instrumentation Amplifiers • Low Level Transducer Amplifiers Ordering Information • Fast, Low Level Voltage Comparators • Highest Quality Audio Preamplifiers PART NUMBER • Pulse/RF Amplifiers TEMP. RANGE (oC) PACKAGE PKG. NO. HA4-5147/883 -55 to 125 20 Ld CLCC J20.A HA7-5147/883 -55 to 125 8 Ld CERDIP F8.3A Pinouts V+ NC 4 3 6 OUT -IN 5 4 5 NC NC 6 2 1 20 19 NC 3 18 NC 17 V+ - 16 NC + +IN 7 15 OUT NC 8 14 NC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 1 10 11 12 13 NC 9 NC +IN BAL 7 + NC 2 NC BAL BAL -IN V- 8 V- 1 NC BAL HA-5147/883 (CLCC) TOP VIEW NC HA-5147/883 (CERDIP) TOP VIEW 511009-883 File Number 3715.2 Spec Number HA-5147/883 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . . 44V Differential Input Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . 0.7V Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . . V+ to VInput Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA Output Current . . . . . . . . . . . . . . . . . . . Full Short Circuit Protection ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2000V Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 115 28 CLCC Package . . . . . . . . . . . . . . . . . . 65 15 Package Power Dissipation Limit at 75oC for TJ ≤ 175oC CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870mW CLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.54W Package Power Dissipation Derating Factor Above 75oC CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7mW/oC CLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4mW/oC Maximum Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V VINCM ≤ 1/2 (V+ - V-) RL ≥ 600Ω CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. For differential input voltages greater than 0.7V, the input current must be limited to 25mA to protect the back-to-back input diodes. 2. θJA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Tested at: VSUPPLY = ±15V, RSOURCE = 50Ω, RLOAD = 100kΩ, VOUT = 0V, Unless Otherwise Specified. PARAMETER Input Offset Voltage Input Bias Current SYMBOL VIO IB GROUP A SUBGROUPS TEMP. (oC) MIN MAX UNITS 1 25 -100 100 µV 2, 3 125, -55 -300 300 µV 1 25 - 80 nA 2, 3 125, -55 - 150 nA 1 25 -75 75 nA 2, 3 125, -55 -135 135 nA 1 25 10.3 - V 2, 3 125, -55 10.3 - V 1 25 - -10.3 V 2, 3 125, -55 - -10.3 V 4 25 700 - kV/V 5, 6 125, -55 300 - kV/V 4 25 700 - kV/V 5, 6 125, -55 300 - kV/V ∆VCM = +11V 1 25 100 - dB ∆VCM = +10V 2, 3 125, -55 100 - dB ∆VCM = -11V 1 25 100 - dB ∆VCM = -10V 2, 3 125, -55 100 - dB CONDITIONS VCM = 0V VCM = 0V, RS = 10kΩ, 50Ω +I B + – I B ----------------------------- 2 Input Offset Current Common Mode Range IIO +CMR -CMR Large Signal Voltage Gain +AVOL -AVOL Common Mode Rejection Ratio +CMRR -CMRR VCM = 0V, +RS = 10kΩ, -RS = 10kΩ V+ = +4.7V, V- = -25.3V V+ = +25.3V, V- = -4.7V VOUT = 0V and +10V, RL = 2kΩ VOUT = 0V and -10V, RL = 2kΩ Spec Number 2 511009-883 HA-5147/883 TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Tested at: VSUPPLY = ±15V, RSOURCE = 50Ω, RLOAD = 100kΩ, VOUT = 0V, Unless Otherwise Specified. PARAMETER SYMBOL Output Voltage Swing +VOUT1 -VOUT1 Output Current Quiescent Power Supply Current TEMP. (oC) MIN MAX UNITS 4 25 11.5 - V 5, 6 125, -55 11.5 - V 4 25 - -11.5 V 5, 6 125, -55 - -11.5 V RL = 2kΩ RL = 2kΩ RL = 600Ω 4 25 10 - V -VOUT2 RL = 600Ω 4 25 - -10 V +IOUT VOUT = -10V 4 25 16.5 - mA -IOUT VOUT = +10V 4 25 - -16.5 mA +ICC VOUT = 0V, IOUT = 0mA 1 25 - 4 mA 2, 3 125, -55 - 4 mA 1 25 -4 - mA 2, 3 125, -55 -4 - mA 1 25 86 - dB 2, 3 125, -55 86 - dB 1 25 86 - dB 2, 3 125, -55 86 - dB 1 25 VIO-1 - mV 2, 3 125, -55 VIO-1 - mV 1 25 VIO+1 - mV 2, 3 125, -55 VIO+1 - mV +PSRR VOUT = 0V, IOUT = 0mA ∆VSUP = +14V ∆VSUP = +13.5V -PSRR ∆VSUP = +14V ∆VSUP = +13.5V Offset Voltage Adjustment GROUP A SUBGROUPS +VOUT2 -ICC Power Supply Rejection Ratio CONDITIONS +VIOAdj -VIOAdj Note 3 Note 3 NOTE: 3. Offset adjustment range is [VIO (Measured) ±1mV] minimum referred to output. This test is for functionality only to assure adjustment through 0V. TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Tested at: VSUPPLY = ±15V, RSOURCE = 50Ω, RLOAD = 2kΩ, CLOAD = 50pF, AVCL = +10V/V, Unless Otherwise Specified. PARAMETER Slew Rate Rise and Fall Time Overshoot SYMBOL CONDITIONS GROUP A SUBGROUPS TEMP. (oC) MIN MAX UNITS +SR VOUT = -3V to +3V 7 25 28 - V/µs -SR VOUT = +3V to -3V 7 25 28 - V/µs tr VOUT = 0 to +200mV 10% ≤ tr ≤ 90% 7 25 - 50 ns tf VOUT = 0 to -200mV 10% ≤ tf ≤ 90% 7 25 - 50 ns +OS VOUT = 0 to +200mV 7 25 - 40 % -OS VOUT = 0 to -200mV 7 25 - 40 % Spec Number 3 511009-883 HA-5147/883 TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Characterized at: VSUPPLY = ±15V, RLOAD = 2kΩ, CLOAD = 50pF, AV = +10V/V, Unless Otherwise Specified. PARAMETER SYMBOL Average Offset Voltage Drift Differential Input Resistance TEMP. (oC) MIN MAX UNITS VCM = 0V 4 -55 to 125 - 1.8 µV/oC RIN VCM = 0V 4 25 0.8 - MΩ 0.1Hz to 10Hz 4 25 - 0.25 µVP-P RS = 20Ω, fO = 10Hz 4 25 - 10 nV/√Hz RS = 20Ω, fO = 100Hz 4 25 - 5.6 nV/√Hz RS = 20Ω, fO = 1kHz 4 25 - 4.5 nV/√Hz RS = 2MΩ, fO = 10Hz 4 25 - 4.0 pA/√Hz RS = 2MΩ, fO = 100Hz 4 25 - 2.3 pA/√Hz RS = 2MΩ, fO = 1kHz 4 25 - 0.6 pA/√Hz VO = 100mV, fO = 10kHz 4 25 120 - MHz VO = 100mV, fO = 1MHz 4 25 100 - MHz 4, 5 25 445 - kHz ENP-P Input Noise Voltage Density EN IN Gain Bandwidth Product NOTES VIOTC Low Frequency Peak-to-Peak Noise Input Noise Current Density CONDITIONS GBWP Full Power Bandwidth FPBW VPEAK = 10V Minimum Closed Loop Stable Gain CLSG RL = 2kΩ, CL = 50pF 4 -55 to 125 ±10 - V/V To 0.1% for a 10V Step 4 25 - 600 µs Open Loop 4 25 - 100 Ω 4, 6 -55 to 125 - 120 mW Settling Time tS Output Resistance ROUT Quiescent Power Consumption PC VOUT = 0V, IOUT = 0mA NOTES: 4. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. 5. Full Power Bandwidth guarantee based on Slew Rate measurement using FPBW = Slew Rate/(2πVPEAK). 6. Quiescent Power Consumption based upon Quiescent Supply Current test maximum. (No load on output.) TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLES 1 AND 2) Interim Electrical Parameters (Pre Burn-In) 1 Final Electrical Test Parameters 1 (Note 7), 2, 3, 4, 5, 6, 7 Group A Test Requirements 1, 2, 3, 4, 5, 6, 7 Groups C and D Endpoints 1 NOTE: 7. PDA applies to Subgroup 1 only. Spec Number 4 511009-883 HA-5147/883 Die Characteristics WORST CASE CURRENT DENSITY: DIE DIMENSIONS: 3.6 x 105A/cm2 at 15mA This device meets Glassivation Integrity Test Requirement per MIL-STD-883 Method 2021 and MIL-I-38535 Paragraph 30.5.5.4. 104.3 x 65 x 19 mils 2650 x 1650 x 483µm METALLIZATION: Type: Al, 1% Cu Thickness: 16kÅ ± 2kÅ SUBSTRATE POTENTIAL (Powered Up): V- GLASSIVATION: TRANSISTOR COUNT: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ ± 2kÅ Nitride Thickness: 3.5kÅ ± 1.5kÅ 63 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-5147/883 BAL BAL -IN V+ +IN OUT V- NC Spec Number 5 511009-883 HA-5147/883 Burn-In Circuits HA-5147/883 CERDIP R2 1 R1 8 2 - 3 + D2 C2 D1 C1 6 4 V- V+ 7 5 R3 HA-5147/883 CLCC R2 3 1 2 20 19 18 4 R1 R3 5 - 6 + 16 7 15 8 14 9 10 V+ 17 11 C2 12 C1 D1 13 D2 V- NOTE: R1 = R3 = 1kΩ, ±5%, 1/4W (Min.) R2 = 10kΩ, ±5%, 1/4W (Min.) C1 = C2 = 0.01µF/Socket or 0.1µF/Row (Min.) D1 = D2 = 1N4002 or Equivalent/Board |(V+) - (V-)| = 30V Spec Number 6 511009-883 HA-5147/883 Typical Performance Information TA = 25oC, VSUPPLY = ±15V, Unless Otherwise Specified V+ RT 10kΩ 1 8 2 - 7 3 + 6 4 5 NOTE: Tested offset adjustment range is |VOS ±1mV| minimum referred to output. Typical range is ±4mV with RT = 10kΩ. SUGGESTED OFFSET VOLTAGE ADJUSTMENT AV = +10V/V + VAC VACOUT 50Ω 1.8kΩ 50pF 200Ω LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT IN IN OUT OUT Vertical Scale: Input = 0.5V/Div. Output = 5V/Div. Horizontal Scale: 500ns/Div. Vertical Scale: Input = 10mV/Div. Output = 100mV/Div. Horizontal Scale: 100ns/Div. LARGE SIGNAL RESPONSE SMALL SIGNAL RESPONSE Spec Number 7 511009-883 HA-5147/883 Ceramic Leadless Chip Carrier Packages (CLCC) J20.A MIL-STD-1835 CQCC1-N20 (C-2) 20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE 0.010 S E H S D INCHES D3 SYMBOL j x 45o E3 B h x 45o 0.010 S E F S A PLANE 2 0.100 1.52 2.54 6, 7 0.088 1.27 2.23 - B - - - - - B1 0.022 0.028 0.56 0.71 2, 4 L -H- L3 1.83 REF - 0.006 0.022 0.15 0.56 - D 0.342 0.358 8.69 9.09 - D1 0.200 BSC 5.08 BSC D2 0.100 BSC 2.54 BSC D3 - 0.358 - E 0.342 0.358 8.69 0.200 BSC E2 0.100 BSC E3 - j e 0.072 REF B3 h B1 NOTES 0.060 e1 0.007 M E F S H S MAX 0.050 e PLANE 1 -E- MIN A E1 A1 MILLIMETERS MAX A1 B2 E MIN 0.358 0.050 BSC 0.015 - 0.040 REF 0.020 REF - 9.09 2 9.09 - 5.08 BSC - 2.54 BSC - - 9.09 2 1.27 BSC 0.38 - 2 1.02 REF 5 0.51 REF 5 L 0.045 0.055 1.14 1.40 - L1 0.045 0.055 1.14 1.40 - L2 0.075 0.095 1.91 2.41 - L3 0.003 0.015 0.08 0.38 - ND 5 5 NE 5 5 3 3 N 20 20 3 Rev. 0 5/18/94 -F- NOTES: B3 E1 E2 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. L2 B2 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) L1 3. Symbol “N” is the maximum number of terminals. Symbols “ND” and “NE” are the number of terminals along the sides of length “D” and “E”, respectively. D2 e1 D1 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer’s option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension “A” controls the overall package thickness. The maximum “A” dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH. Spec Number 8 511009-883 HA-5147/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A) LEAD FINISH 8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE -D- -A- BASE METAL INCHES (c) SYMBOL E M -Bbbb S C A-B S -C- S1 - 0.200 - 5.08 - 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.405 - 10.29 5 E 0.220 0.310 5.59 7.87 5 α eA A A b2 b ccc M C A - B S e eA/2 c e aaa M C A - B S D S D S NOTES b A L MAX A Q SEATING PLANE MIN M (b) D BASE PLANE MILLIMETERS MAX b1 SECTION A-A D S MIN NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N 8 8 8 Rev. 0 4/94 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Spec Number 9 511009-883