LTC3721-1
Push-Pull PWM Controller
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FEATURES
DESCRIPTIO
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The LTC®3721-1 push-pull PWM controller provides all of
the control and protection functions necessary for compact and highly efficient, isolated power converters. High
integration minimizes external component count, while
preserving design flexibility.
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High Efficiency Push-Pull PWM
1.5A Sink, 1A Source Output Drivers
Adjustable Push-Pull Dead-Time
Adjustable System Undervoltage Lockout and
Hysteresis
Adjustable Leading Edge Blanking
Low Start-Up and Quiescent Currents
Current Mode Operation
Single Resistor Slope Compensation
VCC UVLO and 25mA Shunt Regulator
Programmable Fixed Frequency Operation to 1MHz
Soft-Start, Cycle-by-Cycle Current Limiting and
Hiccup Mode Short-Circuit Protection
5V, 15mA Low Dropout Regulator
16-Pin SSOP and (4mm × 4mm) QFN Packages
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APPLICATIO S
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The LTC3721-1 features extremely low operating and
start-up currents and reliable short-circuit and
overtemperature protection. The LTC3721-1 is offered in
16-pin SSOP and (4mm × 4mm) QFN packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Telecommunications, Infrastructure Power Systems
Distributed Power Architectures
Server Power Supplies
High Density Power Modules
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The robust push-pull output stages switch at half the
oscillator frequency. Dead-time is independently programmed with an external resistor. A UVLO program input
provides precise system turn-on and turn off voltages. The
LTC3721-1 features peak current mode control with programmable slope compensation and leading edge
blanking.
TYPICAL APPLICATIO
Isolated Push-Pull Converter
VIN
VOUT
+
UVLO
FROM
AUXILIARY
WINDING
DRVA
DRVB
VCC
CS
DPRG
VREF
RCS
LTC3721-1
CT
RLEB
VREF
VOUT
SS
COMP
FB GND
VOUT
V+
COLL
COMP
LT1431
RTOP
RREF
RMID
GND-F GND-S
37211 TA01
sn37211 37211fs
1
LTC3721-1
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ABSOLUTE
AXI U RATI GS
(Note 1)
VCC to GND (Low Impedance Source) .......– 0.3V to 10V
(Chip Self-Regulates at 10.3V)
UVLO to GND ............................................. – 0.3V to VCC
All Other Pins to GND
(Low Impedance Source) .........................– 0.3V to 5.5V
VCC (Current Fed) ................................................. 40mA
VREF Output Current ............................... Self-Regulated
Operating Temperature (Notes 5,6)
LTC3721-1 ......................................... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 125°C
Lead Temperature (GN Package only)
(Soldering, 10sec) ............................................ 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
15 UVLO
3
14 SS
DRVB
4
13 FB
VCC
5
12 RLEB
DRVA 3
DRVA
6
11 COMP
PGND 4
GND
7
10 CS
CT
8
9
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 100°C/W
11 RLEB
17
10 COMP
6
7
8
DPRG
9 CS
5
NC
37211
LTC3721EUF-1
12 FB
CT
DPRG
16 15 14 13
DRVB 1
VCC 2
GN PART
MARKING
SS
2
NC
UVLO
NC
VREF
16 NC
NC
1
LTC3721EGN-1
ORDER PART
NUMBER
TOP VIEW
VREF
SGND
TOP VIEW
UF PART
MARKING
37211
UF PACKAGE
16-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 100°C/W
EXPOSED PAD IS GND
(PIN17) MUST BE SOLDERED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 9.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCCUV
VCC Undervoltage Lockout
Measured on VCC
10.25
10.7
V
VCCHY
VCC UVLO Hysteresis
Measured on VCC
ICCST
Start-Up Current
VCC = VUVLO – 0.3V
ICCRN
Operating Current
No Load on Outputs
VSHUNT
Shunt Regulator Voltage
Current into VCC = 10mA
RSHUNT
Shunt Resistance
Current into VCC = 10mA to 17mA
SUVLO
System UVLO Threshold
Measured on UVLO Pin, 10mA into VCC
4.8
SHYST
System UVLO Hysteresis Current
Current Flows Out of UVLO Pin, 10mA into VCC
8.5
10
Input Supply
3.8
●
4.2
V
145
230
µA
3
6
mA
10.3
10.8
V
1.4
3.5
Ω
5.0
5.2
V
11.5
µA
sn37211 37211fs
2
LTC3721-1
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 9.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Pulse Width Modulator
ROS
Ramp Offset Voltage
Measured on COMP, CS = 0V
0.65
IRMP
Ramp Discharge Current
CS = 1V, COMP = 0V, CT = 4V
50
mA
ISLP
Slope Compensation Current
Measured on CS, CT = 1V
CT = 2.25V
30
68
µA
µA
DCMAX
Maximum Duty Cycle
COMP = 4.5V
●
DCMIN
Minimum Duty Cycle
COMP = 0V
●
DTADJ
Dead-Time
47
48.2
V
50
%
0
%
130
ns
Oscillator
OSCI
Initial Accuracy
TA = 25°C, CT = 270pF
OSCT
VCC Variation
VCC = 6.5V to 9.5V
OSCV
CT Ramp Amplitude
Measured on CT
220
●
250
–3
280
kHz
3
%
2.35
V
Error Amplifier
VFB
FB Input Voltage
COMP = 2.5V, (Note 3)
1.172
FBI
FB Input Range
Measured on FB, (Note 4)
– 0.3
1.2
AVOL
Open-Loop Gain
COMP = 1V to 3V, (Note 3)
70
90
IIB
Input Bias Current
COMP = 2.5V, (Note 3)
VOH
Output High
Load on COMP = –100µA
4.7
4.92
VOL
Output Low
Load on COMP = 100µA
ISOURCE
Output Source Current
COMP = 2.5V
400
700
µA
ISINK
Output Sink Current
COMP = 2.5V
2
5
mA
4.925
5
0.27
1.22
V
2.5
V
dB
50
nA
V
0.5
V
Reference
VREF
Initial Accuracy
TA = 25°C, Measured on VREF
5.00
5.075
REFLD
Load Regulation
Load on VREF = 100µA to 5mA
2
15
mV
REFLN
Line Regulation
VCC = 6.5V to 9.5V
1
10
mV
4.900
5.000
5.100
18
30
45
REFTV
Total Variation
Line, Load and Temperature
REFSC
Short-Circuit Current
VREF Shorted to GND
●
V
V
mA
Push-Pull Outputs
DRVH(x)
Output High Voltage
IOUT(x) = –100mA
9.2
V
DRVL(x)
Output Low Voltage
IOUT(x) = 100mA
0.17
V
RDH(x)
Pull-Up Resistance
IOUT(x) = –10mA to –100mA
2.9
Ω
RDL(x)
Pull-Down Resistance
IOUT(x) = –10mA to –100mA
1.7
Ω
TDR(x)
Rise-Time
COUT(x) = 1nF
10
ns
TDF(x)
Fall-Time
COUT(x) = 1nF
10
ns
Current Limit and Shutdown
CLPP
Pulse by Pulse Current Limit Threshold
Measured on CS
280
300
320
mV
475
600
725
mV
CLSD
Shutdown Current Limit Threshold
Measured on CS
CLDEL
Current Limit Delay to Output
100mV Overdrive on CS, (Note 2)
SSI
Soft-Start Current
SS = 2.5V
80
10
13
ns
16
µA
sn37211 37211fs
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LTC3721-1
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 9.5V unless otherwise noted.
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SSR
Soft-Start Reset Threshold
PARAMETER
Measured on SS
0.7
0.4
0.1
V
FLT
Fault Reset Threshold
Measured on SS
4.5
4.2
3.5
V
Note 5: The LTC3721–1 is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 6: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Includes leading edge blanking delay, RLEB = 20k, not tested in
production.
Note 3: FB is driven by a servo loop amplifier to control VCOMP for these
tests.
Note 4: Set FB to –0.3V, 2.5V and insure that COMP does not phase invert.
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TYPICAL PERFOR A CE CHARACTERISTICS
Oscillator Frequency vs
Temperature
VCC vs ISHUNT
10.50
260
150
10.25
250
100
10.00
9.75
50
0
FREQUENCY (kHz)
200
VCC (V)
ICC (µA)
Start-Up ICC vs VCC
9.50
0
2
6
4
8
10
CT = 270pF
240
230
10
0
30
20
ISHUNT (mA)
VCC (V)
40
220
– 60 – 40 – 20 0
20 40 60
TEMPERATURE (°C)
50
372311 G02
372311 G01
Leading Edge Blanking Time
vs RLEB
80
100
372311 G03
VREF vs Temperature
VREF vs IREF
350
5.01
5.05
300
TJ = 25°C
5.00
5.00
250
TJ = 85°C
150
4.95
VREF (V)
200
VREF (V)
BLANK TIME (ns)
(TA = 25°C unless otherwise noted)
4.90
TJ = –40°C
100
4.99
4.98
4.85
50
0
4.80
0 10 20 30 40 50 60
RLEB (kΩ)
70 80 90 100
372311 G04
0
5
10
15 20 25
IREF (mA)
30
35
40
372311 G05
4.97
– 60 – 40 – 20 0
20 40 60
TEMPERATURE (°C)
80
100
372311 G06
sn37211 37211fs
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LTC3721-1
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TYPICAL PERFOR A CE CHARACTERISTICS
PHASE (DEG)
100
80
60
40
20
0
190
275
180
250
170
225
160
200
–180
DELAY (ns)
200k PREBIAS
150
140
175
150
130
125
–270
120
100
–360
110
75
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
100
–55
10M
50
–25
5
35
65
TEMPERATURE (°C)
372311 G07
95
125
10.5
80
10.4
FB Input Voltage vs Temperature
1.204
40
CT = 1V
30
1.203
10.3
FB VOLTAGE (V)
SHUNT VOLTAGE (V)
CT = 2.25V
50
10.2
10.1
10.0
0
–55
9.9
–25
5
35
65
TEMPERATURE (°C)
95
125
372311 G10
9.8
–55
1.202
1.201
1.200
1.199
20
10
50 100 150 200 250 300 350 400 450 500
RDPRG (kΩ)
1.205
ICC = 10mA
60
0
372311 G09
VCC Shunt Voltage vs
Temperature
90
70
NO 200k PREBIAS
372311 G08
Slope Current vs Temperature
CURRENT (µA)
Deadtime vs RDPRG
Start-Up ICC vs Temperature
ICC (µA)
GAIN (dB)
Error Amplifier Gain/Phase
(TA = 25°C unless otherwise noted)
1.198
–25
5
35
65
TEMPERATURE (°C)
95
125
372311 G11
1.197
–55
–25
5
35
65
TEMPERATURE (°C)
95
125
372311 G12
sn37211 37211fs
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LTC3721-1
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PI DESCRIPTIO S
(GN Package/UF Package)
VREF (Pin 1/Pin 15): Output of the 5.0V Reference. VREF is
capable of supplying up to 18mA to external circuitry. VREF
should be decoupled to GND with a 1µF ceramic capacitor.
DRVB (Pin 4/Pin 1): High Speed 1.5A Sink, 1A Source
Totem Pole MOSFET Driver. Connect to gate of external
push-pull MOSFET with as short a PCB trace as practical
to preserve drive signal integrity. A low value resistor
connected between DRVA and the MOSFET gate is optional and will improve the gate drive signal quality if the
PCB trace from the driver to the MOSFET cannot be made
short.
VCC (Pin 5/Pin 2): Supply Voltage Input to the LTC3721-1
and 10.25V Shunt Regulator. The chip is enabled after VCC
has risen high enough to allow the VCC shunt regulator to
conduct current and the UVLO comparator threshold is
exceeded. Once the VCC shunt regulator has turned on,
VCC can drop to as low as 6V (typical) and maintain
operation. Bypass VCC to GND with a high quality 1µF or
larger ceramic capacitor to supply the transient currents
caused by the high speed switching and capacitive loads
presented by the on chip totem pole drivers.
DRVA (Pin 6/Pin 3): High Speed 1.5A Sink, 1A Source
Totem Pole MOSFET Driver. Connect to gate of external
push-pull MOSFET with as short a PCB trace as practical
to preserve drive signal integrity. A low value resistor
connected between DRVA and the MOSFET gate is optional and will improve the gate drive signal quality if the
PCB trace from the driver to the MOSFET cannot be made
short.
GND (Pin 7/Pin 4, Pin 5, Pin 17): All circuits in the
LTC3721-1 are referenced to GND. Use of a ground plane
is highly recommended. VIN and VREF bypass capacitors
must be terminated with a star configuration as close to
GND as practical for best performance. For the 4mm ×
4mm QFN package only, the internal power (PGND) and
signal (SGND) buses are connected separately to pins 4
and 5 respectively, and the exposed pad must be soldered
to PCB ground.
CT (Pin 8/Pin 6): Timing Capacitor for the Oscillator. Use
a ±5% or better low ESR ceramic capacitor for best
results. CT ramp amplitude is 2.35V peak-to-peak
(typical).
DPRG (Pin 9/Pin 8): Programming Input for Push-Pull
Dead-Time. Connect a resistor between DPRG and VREF to
program the dead-time. The nominal voltage on DPRG is
2V.
CS (Pin 10/Pin 9): Input to Pulse-by-Pulse and Overload
Current Limit Comparators, Output of Slope Compensation Circuitry. The pulse-by-pulse comparator has a nominal 300mV threshold, while the overload comparator has
a nominal 600mV threshold. An internal switch discharges
CS to GND after every timing period. Slope compensation
current flows out of CS during the PWM period.
An external resistor connected from CS to the external
current sense resistor programs the amount of slope
compensation.
COMP (Pin 11/Pin 10): Error Amplifier Output, Inverting
Input to Phase Modulator.
RLEB (Pin 12/Pin 11): Timing Resistor for Leading Edge
Blanking. Use a 10k to 100k resistor connected between
RLEB and GND to program from 40ns to 310ns of leading
edge blanking of the current sense signal on CS for the
LTC3721-1. A ±1% tolerance resistor is recommended.
The nominal voltage on RLEB is 2V. If leading edge blanking is not required, tie RLEB to VREF to disable.
sn37211 37211fs
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LTC3721-1
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PI DESCRIPTIO S
(GN Package/UF Package)
FB (Pin 13/Pin 12): Error Amplifier Inverting Input. This is
the voltage feedback input for the LTC3721-1. The nominal regulation voltage at FB is 1.2V.
SS (Pin 14/Pin 13): Soft-Start/Restart Delay Circuitry
Timing Capacitor. A capacitor from SS to GND provides a
controlled ramp of the current command. During overload
conditions, SS is discharged to ground initiating a softstart cycle. SS charging current is approximately 13µA. SS
will charge up to approximately 5V in normal operation.
During a constant overload current fault, SS will oscillate
at a low frequency between approximately 0.5V and 4V.
UVLO (Pin 15/Pin 14): Input to Program System Turn-On
and Turn-Off Voltages. The nominal threshold of the UVLO
comparator is 5.0V. UVLO is connected to the main DC
system feed through a resistor divider. When the UVLO
threshold is exceeded, the LTC3721-1 commences a softstart cycle and a 10µA (nominal) current is fed out of UVLO
to program the desired amount of system hysteresis. The
hysteresis level can be adjusted by changing the resistance of the divider. UVLO can also be used to terminate
all switching by pulling UVLO down to less than 4V. An
open drain or collector switch can perform this function
without changing the system turn on or turn off voltages.
NC (Pin 2, Pin 3, Pin 16/Pin 7, Pin 16): Not Connected.
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UW
TI I G DIAGRA
PROGRAMMABLE
DEAD-TIME
DRVA
DRVB
CURRENT
SENSE
OR CT RAMP
PWM
COMPARATOR
(–)
37211 TD01
sn37211 37211fs
7
8
RLEB
CS
SS
COMP
FB
–
+
1.2V
BLANK
600mV
650mV
+
–
300mV
–
+
–
+
50k
UVLO
5V
–
+
–
+
VCC
14.9k
VCC
GOOD
S
R
SLOPE
COMPENSATOR
FAULT
LOGIC
Q
5V
VREF
REF GOOD
REF, LDO
PULSE WIDTH
MODULATOR
1.2V
13µA
VREF
+
–
SYSTEM
UVLO
10µA
PULSE-BY-PULSE
CURRENT LIMIT
SHUTDOWN
CURRENT
LIMIT
ERROR
AMPLIFIER
10.25V “ON”
6V “OFF”
VCC UVLO
VCC
S
R
OSCILLATOR
CT
GND
DPRG
Q
LTC3721-1 Block Diagram
T
Q
Q
1.5A SINK
1A SOURCE
1.5A SINK
1A SOURCE
37211 BD01
DRVB
DRVA
LTC3721-1
BLOCK DIAGRA S
sn37211 37211fs
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LTC3721-1
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OPERATIO
Please refer to the detailed Block Diagram for this discussion. The LTC3721-1 is a PWM push-pull controller that
operates with pulse-by-pulse peak current mode control.
It is best suited for moderate to high power isolated power
systems where small size and high efficiency are required.
The push-pull topology delivers excellent transformer
utilization and requires only two low side power MOSFET
switches. The controller generates 180° out of phase
0% to < 50% duty cycle drive signals on DRVA and DRVB.
The external MOSFETs are driven directly by these powerful on-chip drivers. The external MOSFETs typically control opposite primary windings of a centertapped power
transformer. The centertap primary winding is connected
to the input DC feed. The secondary of the transformer can
be configured in different synchronous or nonsynchronous
configurations depending on the application needs.
The duty ratio is controlled by the voltage on COMP. A
switching cycle commences with the falling edge of the
internal oscillator clock pulse. The LTC3721-1 attenuates
the voltage on COMP and compares it to the current sense
signal to terminate the switching cycle. If the voltage on CS
exceeds 300mV, the present cycle is terminated. If the
voltage on CS exceeds 600mV, all switching stops and a
soft-start sequence is initiated.
A host of other features including an error amplifier,
system UVLO programming, adjustable leading edge blanking, slope compensation and programmable dead-time
provide flexibility for a variety of applications.
Programming Driver Dead-Time
The LTC3721-1 includes a feature to program the minimum time between the output signals on DRVA and DRVB
commonly referred to as the driver dead-time. This function will come into play if the controller is commanded for
maximum duty cycle. The dead-time is set with an
external resistor connected between DPRG and VREF (see
Figure 1). The nominal regulated voltage on DPRG is 2V.
The external resistor programs a current which flows into
DPRG. The dead-time can be adjusted from 90ns to 300ns
with this resistor. The dead-time can also be modulated
based on an external current source that feeds current into
DPRG. Care must be taken to limit the current fed into
DPRG to 350µA or less. An internal 10µA current source
sets a maximum deadtime if DPRG is floated. The internal
current source causes the programmed deadtime to vary
non-linearly with increasing values of RDPRG (see Typical
Performance Characteristics). An external 200k resistor
connected from DPRG to GND will compensate for the
internal 10µA current source and linearize the deadtime
delay vs RDPRG characteristic.
VREF
RDPRG
DPRG
OPTIONAL
200k
+
+
V 2V
2.5V
–
–
TURN-ON
OUTPUT
37211 F01
Figure 1. Deadtime Adjust
Powering the LTC3721-1
The LTC3721-1 utilizes an integrated VCC shunt regulator
to serve the dual purposes of limiting the voltage applied
to VCC as well as signaling that the chip’s bias voltage is
sufficient to begin switching operation (under voltage
lockout). With its typical 10.2V turn-on voltage and 4.2V
UVLO hysteresis, the LTC3721-1 is tolerant of loosely
regulated input sources such as an auxiliary transformer
winding. The VCC shunt is capable of sinking up to 40mA
of externally applied current. The UVLO turn-on and turnoff thresholds are derived from an internally trimmed
reference making them extremely accurate. In addition,
the LTC3721-1 exhibits very low (145µA typ) start-up
current that allows the use of 1/8W to 1/4W trickle charge
start-up resistors.
The trickle charge resistor should be selected as follows:
RSTART(MAX) = VIN(MIN) – 10.7V/250µA
Adding a small safety margin and choosing standard
values yields:
APPLICATION
VIN RANGE
RSTART
DC/DC
36V to 72V
100k
Off-Line
85V to 270VRMS
430k
390VDC
1.4M
PFC Preregulator
sn37211 37211fs
9
LTC3721-1
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OPERATIO
VCC should be bypassed with a 0.1µF to 1µF multilayer
ceramic capacitor to decouple the fast transient currents
demanded by the output drivers and a bulk tantalum or
electrolytic capacitor to hold up the VCC supply before the
bootstrap winding, or an auxiliary regulator circuit takes
over.
CHOLDUP = (ICC + IDRIVE) • tDELAY/3.8V
(minimum UVLO hysteresis)
Regulated bias supplies as low as 7V can be utilized to
provide bias to the LTC3721-1. Refer to Figure 2 for
various bias supply configurations.
Programming Undervoltage Lockout
The LTC3721-1 provides undervoltage lockout (UVLO)
control for the input DC voltage feed to the power converter in addition to the VCC UVLO function described in the
preceding section. Input DC feed UVLO is provided with
the UVLO pin. A comparator on UVLO compares a divided
down input DC feed voltage to the 5V precision reference.
When the 5V level is exceeded on UVLO, the SS pin is
released and output switching commences. At the same
time a 10µA current is enabled which flows out of UVLO
into the voltage divider connected to UVLO. The amount of
DC feed hysteresis provided by this current is: 10µA •
RTOP, (Figure 3). The system UVLO threshold is: 5V •
{(RTOP + RBOTTOM)/RBOTTOM}. If the voltage applied to
UVLO is present and greater than 5V prior to the VCC UVLO
circuitry activation, then the internal UVLO logic will
prevent output switching until the following three conditions are met: (1) VCC UVLO is enabled, (2) VREF is in
regulation and (3) UVLO pin is greater than 5V.
UVLO can also be used to enable and disable the power
converter. An open drain transistor connected to UVLO as
shown in Figure 3 provides this capability.
Off-Line Bias Supply Generation
If a regulated bias supply is not available to provide VCC
voltage to the LTC3721-1 and supporting circuitry, one
must be generated. Since the power requirement is small,
approximately 1W, and the regulation is not critical, a
simple open-loop method is usually the easiest and lowest
cost approach. One method that works well is to add a
winding to the main power transformer, and post regulate
the resultant square wave with an L-C filter (see Figure 4a).
The advantage of this approach is that it maintains decent
regulation as the supply voltage varies, and it does not
require full safety isolation from the input winding of the
transformer. Some manufacturers include a primary winding for this purpose in their standard product offerings as
well. A different approach is to add a winding to the output
inductor and peak detect and filter the square wave signal
(see Figure 4b). The polarity of this winding is designed so
VIN
VIN
VBIAS < VUVLO
12V ±10%
1.5k
1N5226
3V
1N914
RSTART
2k
+
15V*
+
1µF
1µF
VCC
RSTART
1µF
CHOLD
CHOLD
19211 F04a
VCC
VCC
*OPTIONAL
37211 F02
Figure 2. Bias Configurations
Figure 4a. Auxiliary Winding Bias Supply
VIN
VOUT
LOUT
RTOP
RSTART
ISO BARRIER
+
UVLO
ON OFF
1µF
RBOTTOM
37211 F03
Figure 3. System UVLO Setup
VCC
CHOLD
19211 F04b
Figure 4b. Output Inductor Bias Supply
sn37211 37211fs
10
LTC3721-1
U
OPERATIO
CT = 1/(14.8k • FOSC)
Note that this is the frequency seen on CT. The output
drivers switch at 1/2 of this frequency. Also note that
higher switching frequency and added driver dead-time
via DPRG will reduce the maximum duty cycle.
The LTC3721-1 derives a compensating slope current
from the oscillator ramp waveform and sources this
current out of CS. The desired level of slope compensation
is selected with an external resistor connected between CS
and the external current sense resistor, (Figure 5).
The pulse-by-pulse comparator has a 300mV nominal
threshold. If the 300mV threshold is exceeded, the PWM
cycle is terminated. The overcurrent comparator is set
approximately 2x higher than the pulse-by-pulse level. If
the current signal exceeds this level, the PWM cycle is
terminated, the soft-start capacitor is quickly discharged
and a soft-start cycle is initiated. If the overcurrent condition persists, the LTC3721-1 halts PWM operation and
waits for the soft-start capacitor to charge up to approximately 4V before a retry is allowed. The soft-start capacitor is charged by an internal 13µA current source. If the
fault condition has not cleared when soft-start reaches 4V,
the soft-start pin is again discharged and a new cycle is
initiated. This is referred to as hiccup mode operation. In
normal operation and under most abnormal conditions,
the pulse-by-pulse comparator is fast enough to prevent
hiccup mode operation. In severe cases, however, with
high input voltage, very low RDS(ON) MOSFETs and a
shorted output, or with saturating magnetics, the
overcurrent comparator provides a means of protecting
the power converter.
PULSE BY PULSE
CURRENT LIMIT
+
CS
RCS
CT
I=
33k
V(CT)
33k
SWITCH
CURRENT
CS
ADDED
SLOPE
RCS
S Q
S
–
OVERLOAD
CURRENT LIMIT
+
650mV
Q
R
S Q
–
UVLO
ENABLE
RSLOPE
Q
H = SHUTDOWN
OUTPUTS
UVLO
PWM ENABLE
LOGIC
R
4.1V
13µA
SS
0.4V
CSS
–
LTC3721-1
300mV
PWM
PWM
LATCH
+
The high accuracy LTC3721-1 oscillator circuit provides
flexibility to program the switching frequency and slope
compensation required for current mode control. The
oscillator circuit produces a 2.35V peak-to-peak amplitude ramp waveform on CT. Typical maximum duty cycles
of 49% are possible. The oscillator is capable of operation
up to 1MHz by the following equation:
Current sensing provides feedback for the current mode
control loop and protection from overload conditions. The
LTC3721-1 is compatible with either resistive sensing or
current transformer methods. Internally connected to CS
are two comparators that provide pulse-by-pulse and
overcurrent shutdown functions respectively, (Figure 6).
–
Programming the LTC3721-1 Oscillator
Current Sensing and Overcurrent Protection
+
that the positive voltage square wave is produced while the
output inductor is freewheeling. An advantage of this
technique over the previous is that it does not require a
separate filter inductor and since the voltage is derived
from the well-regulated output voltage, it is also well
controlled. One disadvantage is that this winding will
require the same safety isolation that is required for the
main transformer. Another disadvantage is that a much
larger VCC filter capacitor is needed, since it does not
generate a voltage as the output is first starting up, or
during short-circuit conditions.
Q
CURRENT SENSE
WAVEFORM
37211 F06
37211 F05
Figure 5. Slope Compensation Circuitry
Figure 6. Current Sense/Fault Circuitry Detail
sn37211 37211fs
11
LTC3721-1
U
OPERATIO
Leading Edge Blanking
The LTC3721-1 provides programmable leading edge
blanking to prevent nuisance tripping of the current sense
circuitry. Leading edge blanking relieves the filtering requirements for the CS pin, greatly improving the response
to real overcurrent conditions. It also allows the use of a
ground referenced current sense resistor or transformer(s),
further simplifying the design. With a single 10k to 100k
resistor from RLEB to GND, blanking times of approximately 40ns to 320ns are programmed. If not required,
connecting RLEB to VREF can disable leading edge blanking. Keep in mind that the use of leading edge blanking will
slightly reduce the linear control range for the pulse width
modulator.
High Current Drivers
The LTC3721-1 high current, high speed drivers provide
direct drive of external power N-channel MOSFET switches.
The drivers swing from rail to rail. Due to the high pulsed
current nature of these drivers (1.5A sink, 1A source), care
must be taken with the board layout to obtain advertised
performance. Bypass VCC with a 1µF minimum, low ESR,
ESL ceramic capacitor. Connect this capacitor with minimal length PCB leads to both VCC and GND. A ground plane
is highly recommended. The driver output pins (DRVA,
DRVB) connect to the gates of the external MOSFET
switches. The PCB traces making these connections should
also be as short as possible to minimize overshoot and
undershoot of the drive signal.
Transformer Configurations
The LTC3721-1 used in a typical isolated push-pull converter application will need a transformer to provide the
voltage translation and galvanic isolation. The push-pull
transformer employs a center tapped primary winding
configuration. The transformer secondary can be center
tapped or a single winding depending on the configuration
and application needs.
Center tapped secondary configurations apply alternating
<50% duty cycle square waves to a single inductor/
capacitor combination. This L-C circuit filters the square
wave and produces the regulated output voltage. The
secondary square wave amplitude is given by:
VSEC = VIN • N, where N = Ns/Np, transformer turns
ratio, # of secondary turns divided by # of primary
turns.
sn37211 37211fs
12
LTC3721-1
U
OPERATIO
The duty cycle of these square waves is guaranteed to
never exceed 50% by the LTC3721-1. In steady state
operation, the duty ratio is given by:
D = VOUT/(2 • VIN • N)
To calculate the transformer turns ratio, first determine
the minimum input voltage (VIN(MIN)) and the maximum
duty ratio (D(MAX)) of the controller IC. This will be the
worst case condition. An example is provided below:
VIN = 32V to 75V, use VIN(MIN) = 30V to account for
system voltage drops.
VOUT = 7V
Maximum duty cycle (DMAX) = 47% (per datasheet),
use 45% for margin.
The required transformer turns ratio is given by:
Turns ratio (Ns/Np) = VOUT/(VIN(MIN) • 2 • D(MAX))
= 7V/(30V • 2 • 0.45)
Ns/Np = (1/3.86)
Note that this is a simplified equation that does not take
into account primary and secondary side voltage drops
due to diodes, power MOSFETs, and resistive elements in
the power paths. By margining down VIN(MIN) and DMAX as
suggested above, the equation becomes closer to reality.
An alternative secondary winding configuration uses a
single non-center tapped winding and two filter inductors.
Each end of the secondary winding alternately drives an
inductor with <50% duty cycle square wave. The two
inductors are connected together at the opposite ends to
common output filter capacitor(s). This configuration is
also called the current doubler rectifier. The current doubler utilizes half of the secondary windings compared to
the center tapped case. The two out of phase inductors
reduce the ripple current seen by the output and input
capacitors, possibly allowing fewer capacitors in some
applications. In addition, each output inductor carries half
of the total load current, making them physically smaller,
which can help to optimize the power stage layout. However, the total combined size may be slightly larger than
the single inductor configuration.
sn37211 37211fs
13
LTC3721-1
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ± .0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
2 3
4
5 6
7
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN16 (SSOP) 0204
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
sn37211 37211fs
14
LTC3721-1
U
PACKAGE DESCRIPTIO
UF Package
16-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1692)
0.72 ±0.05
4.35 ± 0.05
2.15 ± 0.05
2.90 ± 0.05 (4 SIDES)
PACKAGE OUTLINE
0.30 ±0.05
0.65 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
4.00 ± 0.10
(4 SIDES)
R = 0.115
TYP
0.75 ± 0.05
PIN 1
TOP MARK
(NOTE 6)
0.55 ± 0.20
15
16
1
2.15 ± 0.10
(4-SIDES)
2
(UF) QFN 1103
0.200 REF
0.00 – 0.05
0.30 ± 0.05
0.65 BSC
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
sn37211 37211fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC3721-1
U
TYPICAL APPLICATIO
+VS
12
+VOUT
MBRB20200CT
•
1nF
200V
5.1Ω
1/2W
C2, C3, C4, C5
4x33µF
16V
12VIN
1nF
200V
C6
56µF
35V
11
3
4
6
+VIN
+
160Ω
2W
•
5.1Ω
1/2W
L1
22µH
4
C8
0.1µF
100V
C64
180pF
200V
1
+
MBRB20200CT
–VIN
C7
56µF
35V
8
•
R1
0.01Ω
1.5W
5V
R2
0.01Ω
1.5W
EFFICIENCY (%)
4.7Ω
1/4W
330pF
FMMT718
VIN
–VOUT
10.6VIN
13.2VIN
91
73.2k
48V/3.65A
C9
39µF
100V
92
L2
22µH
7
4.7Ω
1/4W
+
T2
0.59mH
PULSE
P0353
–VS
9
•
2xSi7370DP
1.21k
2
10
24V
2xSi7370DP
C1
1µF
100V
3
•
•
1
VIN
180pF
200V
160Ω
2W
•
COEV MGPWG-00001
EFD25 (1.28" x 1" x 0.504")
4T (42µH) CT: 10T CT: 10T CT
(PINS 1 TO 6, 7 TO 9, 11 TO 12)
12VIN
90
89
FMMT718
470Ω
1.5k
1/4W
MMBT3904LT1
6
470Ω
5
10
DRVA
VCC
4
CS
LTC3721EGN-1
15
UVLO
CT RLEB
8
1nF
12
GND FB
7
13
COMP
VREF
SS DPRG
14
9
MOC207
10k
3
33k
68nF
5
1µF
2
10k
1nF
100V
4
V+
D1
9.1V
270pF
46.1k
10nF
6
1.2k
100k
1.5
2k
1
11
1
1µF
1.0
2.0
2.5
3.0
LOAD CURRENT (A)
3.5
4.0
+VS
DRVB
1k
107k
88
24V
1.5nF
2
C10
2.2nF
250V
1
D2
9.1V
100k
COMP RTOP
LT1431CS8
COLL
REF
8
GND-F GND-S RMID
6
5
2.49k
7
NOTES:
T2, C1, C9 ARE OPTIONAL AND
REDUCE OUTPUT RIPPLE TO LESS
THAN 50mVP-P.
10mA MINIMUM LOAD REQUIRED.
START VOLTAGE 10.8V MAX.
C2-C5: TDK C4532X7R1336M (1812)
C10: MURATA DE2E3KH222MB3B
C1: TDK C3225X7R2A105M (1210)
C6, C7: SANYO 35MV56WX
C9: SANYO 100MV39AX
C8: TDK C3216X7R2A104M (X7R 1206)
D1, D2: MMBZ5239B
R1, R2: IRC LRC-LR2512-01-R010-G
L1, L2: TDK SLF12575T-220M4R0
–VS
37211 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1431
Reference and Opto-Driver
Drives Opto-Coupler
LT1681/LT3781
Synchronous Forward Controllers
High Efficiency 2-Switch Forward Control
LTC1693-1
Dual MOSFET Gate Drivers
High Speed MOSFET Gate Drivers
LT1950
Single Switch Forward Converter Controller
Auxillary Boost Converter, Programmable Volt-SPC Clamp
LTC3722-1/LTC3722-2 Dual Mode Phase Modulated Full-Bridge Controllers
ZVS Full-Bridge Controllers
LT3804
Secondary Side Dual Output Controller with Opto Driver
Regulates Two Secondary Outputs; Optocoupler Feedback Driver and
Second Output Synchronous Driver Controller
LTC3901
Secondary Side Synchronous Driver for Push-Pull
and Full Bridge Converters
Fault Timer, Reverse Current Sense, SO8
LTC3723-1/LTC3723-2 Synchronous Push-Pull Controllers
Highest Efficiency Push-Pull Controllers
LTC4440
SOT-23 and MSOP; 1.6Ω Pull-Down, 2.4A Pull-Up
100V High Side MOSFET Driver
sn37211 37211fs
16
Linear Technology Corporation
LT/TP 0504 1K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004