[AK4617] AK4617 192kHz 24-bit 2ch/12ch Audio CODEC 1. General Description The AK4617 is a single chip audio CODEC that includes 2-channel ADC and 12-channel DAC. The stereo ADC supports differential/single-ended analog inputs. The high performance 12-channel DAC integrates full-range digital volume control and achieves 106dB dynamic range. A car audio system can be easily designed with an audio DSP and the AK4617. The AK4617 is housed in a space saving 48-pin LQFP package. 2. Features 2ch ADC - Sampling Frequency: 8kHz~48kHz - ADC S/N: 97dB, S/ (N+D): 87dB - I/F format: MSB justified, I2S or TDM 12ch DAC - Sampling Frequency: 8kHz~192kHz - DAC S/N: 106dB, S/ (N+D): 85dB - I/F format: MSB justified, LSB justified (16bit, 24bit), I2S or TDM Channel Independent Digital Attenuator (Linear 256 steps) Master / Slave mode Master clock - Slave mode: 256fs, 384fs or 512fs (Normal Speed Mode: fs=8kHz 48kHz) 256fs (Double Speed Mode: fs=64kHz 96kHz) 128fs (Quad Speed Mode: fs=128kHz 192kHz) - Master mode: 256fs, 384fs or 512fs (Normal Speed Mode: fs=8kHz 48kHz) 256fs (Double Speed Mode: fs=64kHz 96kHz) 128fs (Quad Speed Mode: fs=128kHz 192kHz) μP I/F: I2C or 3-wire Power supply - Analog Power Supply: 3.0V ~ 3.6V (typ.3.3V) - Digital I/O Power Supply: 3.0V ~ 3.6V (typ.3.3V) Operating temperature range: -40C ~ 105C Package: 48pin LQFP MS1582-E-00 2013/11 -1- [AK4617] 3. Table of Contents 1. General Description ................................................................................................................................... - 1 2. Features ..................................................................................................................................................... - 1 3. Table of Contents ...................................................................................................................................... - 2 4. Block Diagram and Functions ................................................................................................................... - 3 ■ Block Diagram ....................................................................................................................................... - 3 ■ Ordering Guide ...................................................................................................................................... - 4 ■ Pin Layout .............................................................................................................................................. - 4 ■ Handling of Unused Pin ......................................................................................................................... - 4 5. Pin Configurations and Functions ............................................................................................................. - 5 6. Absolute Maximum Ratings ...................................................................................................................... - 7 7. Recommended Operating Conditions ........................................................................................................ - 7 8. Analog Characteristics............................................................................................................................... - 8 9. ADC Filter Characteristics (fs=48kHz) ..................................................................................................... - 9 10. DAC Filter Characteristics (fs=48kHz) ................................................................................................. - 10 11. DAC Filter Characteristics (fs=96kHz) ................................................................................................. - 11 12. DAC Filter Characteristics (fs=192kHz) ............................................................................................... - 12 13. DC Characteristics ................................................................................................................................. - 13 14. Switching Characteristics ...................................................................................................................... - 14 ■ Timing Diagram ................................................................................................................................... - 19 15. Functional Descriptions ......................................................................................................................... - 26 ■ System Clock ....................................................................................................................................... - 26 ■ De-emphasis Filter ............................................................................................................................... - 28 ■ Digital High Pass Filter ........................................................................................................................ - 28 ■ Master Mode and Slave Mode ............................................................................................................. - 28 ■ Audio Serial Interface Format .............................................................................................................. - 29 ■ TDM Cascade Mode ............................................................................................................................ - 40 ■ Digital Attenuator ................................................................................................................................ - 41 ■ Soft Mute Operation ............................................................................................................................. - 42 ■ System Reset ........................................................................................................................................ - 42 ■ Power-Down ........................................................................................................................................ - 43 ■ Reset Function...................................................................................................................................... - 45 ■ DAC Partial Power-Down Function .................................................................................................... - 46 ■ Parallel Mode ....................................................................................................................................... - 47 ■ Serial Control Interface ........................................................................................................................ - 47 ■ Register Map ........................................................................................................................................ - 51 ■ Register Definitions ............................................................................................................................. - 52 16. Recommended External Circuits ........................................................................................................... - 56 ■ Grounding and Power Supply Decoupling........................................................................................... - 59 ■ Voltage Reference ................................................................................................................................ - 59 ■ Analog Inputs ....................................................................................................................................... - 59 ■ Analog Outputs .................................................................................................................................... - 59 ■ External Analog Inputs Circuit ............................................................................................................ - 60 ■ External Analog Outputs Circuit .......................................................................................................... - 61 17. Package .................................................................................................................................................. - 62 ■ Package & Lead frame material ........................................................................................................... - 62 ■ Marking ................................................................................................................................................ - 63 18. Revision History .................................................................................................................................... - 63 IMPORTANT NOTICE .............................................................................................................................. - 64 - MS1582-E-00 2013/11 -2- [AK4617] 4. Block Diagram and Functions ■ Block Diagram Audio I/F PDN IN1/IN1P IN1N IN2/IN2P ADC HPF IN2N ADC HPF SDOUT LOUT1 LPF SCF SCF DAC DATT ROUT1 LPF SCF DAC DATT LOUT2 LPF SCF DAC DATT ROUT2 LOUT3 LPF SCF DAC DATT LPF SCF DAC DATT ROUT3 LPF SCF DAC DATT LOUT4 LPF SCF DAC DATT ROUT4 LPF SCF DAC DATT SDTO MCLK MCLK LRCK BICK LRCK BICK SDIN1 SDTI1 SDIN2 SDTI2 SDIN3 SDTI3 SDIN4 SDTI4 SDIN5 SDTI5 SDIN6 SDTI6 Reg LOUT5 LPF SCF SCF DAC DATT ROUT5 LPF SCF DAC DATT LOUT6 LPF SCF DAC DATT ROUT6 LPF SCF DAC DATT uP I/F (I2C/SPI) REGO CSN/PS SCL/SCLK/MS SDA/CDTI/DIF SPI CAD1/TDM0 VCOM AVDD1 VSS1 AVDD2 VSS2 TVDD VSS3 Figure 1. Block Diagram MS1582-E-00 2013/11 -3- [AK4617] ■ Ordering Guide AK4617VQ AKD4617 40 +105C 48pin LQFP (0.5mm pitch) Evaluation Board for AK4617 LOUT1 ROUT1 LOUT2 ROUT2 LOUT3 ROUT3 LOUT4 ROUT4 LOUT5 ROUT5 LOUT6 ROUT6 36 35 34 33 32 31 30 29 28 27 26 25 ■ Pin Layout AVDD2 37 24 NC VSS3 38 23 NC SPI 39 22 NC CAD1/TDM0 40 21 NC CSN/PS 41 20 VCOM CDTI/SDA/DIF 42 19 VSS2 CCLK/SCL/MS 43 18 AVDD1 17 NC AK4617VQ Top View 11 SMUTEN 12 10 TST2 PDN 9 IN1N SDTO 13 8 48 TVDD SDTI2 7 IN1/IN1P VSS1 14 6 47 REGO SDTI3 5 IN2N TST1 15 4 46 BICK SDTI4 3 IN2/IN2P MCLK 16 2 45 LRCK SDTI5 1 44 SDTI1 SDTI6/TDMI ■ Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Pin Name IN1/IN1P, IN1N, IN2/IN2P, IN2N Analog LOUT1-6, ROUT1-6 SDTI1-6 Digital SDTO MS1582-E-00 Setting Open Open Connect to VSS1 Open 2013/11 -4- [AK4617] 5. Pin Configurations and Functions No. 5 Pin Name SDTI1 LRCK MCLK BICK TST1 6 REGO O 7 8 9 10 VSS1 TVDD SDTO TST2 O O 11 SMUTEN I 12 PDN I 13 IN1N I IN1 I IN1P I IN2N I IN2 I IN2P I 17 18 19 NC AVDD1 VSS2 - 20 VCOM O 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 NC NC NC NC ROUT6 LOUT6 ROUT5 LOUT5 ROUT4 LOUT4 ROUT3 LOUT3 ROUT2 LOUT2 ROUT1 O O O O O O O O O O O 1 2 3 4 I/O I I/O I I/O I 14 15 16 Function Audio Serial Data Input 1 Pin Input Channel Clock Pin External Master Clock Input Pin Audio Serial Data Clock Pin This pin must be connected to ground. Regulator Output Pin This pin should be connected to ground with 1.0uF. Ground Pin, 0V Digital Power Supply Pin, 3.0V3.6V Audio Serial Data Output Pin This pin must be open. All Analog Outputs Soft Mute Pin L: Mute H: Normal Operation Power-Down & Reset Pin When “L”, the AK4617 is powered-down and the control registers are reset to default state. (MDIE1 bit = “1”) Differential Analog Negative input 1 pin (MDIE1 bit = “0”) Single-ended Analog Input 1 pin (MDIE1 bit = “1”) Differential Analog Positive input 1 pin (MDIE2 bit = “1”) Differential Analog Negative input 2 pin (MDIE2 bit = “0”) Single-ended Analog Input 2 pin (MDIE2 bit = “1”) Differential Analog Positive input 2 pin This pin must be open. Analog Power Supply Pin, 3.0V3.6V Ground Pin, 0V Common Voltage Output Pin, AVDD1x1/2 Large external capacitor around 1µF is used to reduce power-supply noise. This pin must be open. This pin must be open. This pin must be open. This pin must be open. Rch Analog Output 6 Pin Lch Analog Output 6 Pin Rch Analog Output 5 Pin Lch Analog Output 5 Pin Rch Analog Output 4 Pin Lch Analog Output 4 Pin Rch Analog Output 3 Pin Lch Analog Output 3 Pin Rch Analog Output 2 Pin Lch Analog Output 2 Pin Rch Analog Output 1 Pin MS1582-E-00 2013/11 -5- [AK4617] 36 37 38 LOUT1 AVDD2 VSS3 O - Lch Analog Output 1 Pin Analog Power Supply Pin, 3.0V3.6V Ground Pin, 0V Control Mode Select Pin 39 SPI I “L”: I2C Bus or Parallel control mode, “H”: 3-wire serial control mode I (SPI pin = “H”) CAD1 (SPI pin = “L”, PS pin= “L”) Chip Address Pin in serial control mode 40 I (SPI pin = “L”, PS pin= “H”) TDM0 TDM I/F Format Mode 0 Pin in parallel control mode “L”: Normal mode, “H”: TDM mode I (SPI pin = “H”) CSN Chip Select Pin in 3-wire serial control mode 41 I (SPI pin = “L”) PS Control Mode Select Pin “L”: I2C Bus serial control mode, “H”: Parallel control mode I (SPI pin = “H”) CDTI Control Data Input Pin in 3-wire serial control mode I/O (SPI pin = “L”, PS pin= “L”) SDA 42 Control Data Input Pin in I2C Bus Serial control mode I (SPI pin = “L”, PS pin= “H”) DIF Audio Data Interface Format Pin in parallel control mode “L”:24bit, Left justified, “H”: 24bit, I2S I (SPI pin = “H”) CCLK Control Data Clock Pin in 3-wire serial control mode I (SPI pin = “L”, PS pin= “L”) SCL 43 Control Data Clock Pin in I2C Bus serial control mode I (SPI pin = “L”, PS pin= “H”) MS Master Mode Select Pin “L”: Slave Mode “H”: Master Mode I (TDM1-0 bit = “00”) SDTI6 Audio Serial Data Input 6 Pin/ 44 I (TDM1-0 bit = “01” or “10”) TDMI TDM Data Input Pin 45 SDTI5 I Audio Serial Data Input 5 Pin 46 SDTI4 I Audio Serial Data Input 4 Pin 47 SDTI3 I Audio Serial Data Input 3 Pin 48 SDTI2 I Audio Serial Data Input 2 Pin Note 1. All digital input pins must not be allowed to float. MS1582-E-00 2013/11 -6- [AK4617] 6. Absolute Maximum Ratings (VSS1 ~ 3 = 0V; Note 2) Parameter Symbol min max Unit Power Supplies Analog1 AVDD1, -0.3 6.0 V Analog2 AVDD2 -0.3 6.0 V Digital1 TVDD -0.3 6.0 V Input Current (any pins except for supplies) IIN mA 10 Analog Input Voltage VINA -0.3 AVDD1+0.3 V Digital Input Voltage (SDTI1-6, SPI, CSN/PS, CCLK/ SCL/MS, VIND -0.3 TVDD+0.3 V CDTI/SDA/DIF, CAD1/TDM0, PDN pins) Ambient Temperature (power applied)(Note 3) Ta -40 105 C Storage Temperature Tstg -65 150 C Note 2. All voltages with respect to ground. VSS1 ~ 3 must be connected to the same analog ground plane. Note 3. In case that PCB wiring density is 100%. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 7. Recommended Operating Conditions (VSS1 ~ 3 = 0V; Note 2) Parameter Symbol min typ max Unit Power Analog AVDD1, AVDD2 3.0 3.3 3.6 V Supplies Digital TVDD 3.0 3.3 3.6 V (Note 4) Difference AVDD1, AVDD2 – TVDD -0.1 0 +0.1 V Note 4. The power up sequence between AVDD1, AVDD2 and TVDD is not critical. Each power supplies should be powered up during the PDN pin = “L”. The PDN pin should be “H” after all power supplies are powered up. All power supplies should be powered on, only a part of these power supplies cannot be powered off. (Power off means power supplies equal to ground or power supplies are floating.) Do not turn off only the AK4617 under the condition that a surrounding device is powered on and the I2C bus is in use. AVDD1 and AVDD2 must be connected with the same power supply. WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS1582-E-00 2013/11 -7- [AK4617] 8. Analog Characteristics (Ta=25ºC; AVDD1, AVDD2=TVDD=3.3V, VSS1 ~ 3 =0V, BICK=64fs; Signal frequency 1kHz; Measurement frequency = 20Hz~20kHz @fs=48kHz, 20Hz~40kHz at fs=96kHz, 20Hz~40kHz at fs=192kHz; Unless otherwise specified.) Parameter min typ max Unit ADC Analog Input Characteristics(Single-ended inputs) Resolution 24 bit S/(N+D) (-1dBFS) 77 87 dB DR (-60dBFS with A-weighted) 87 97 dB S/N (A-weighted) 87 97 dB Interchannel Isolation 110 dB Interchannel Gain Mismatch 0 0.5 dB Gain Drift 20 ppm/C Input Voltage Single-ended (AIN=0.81x AVDD1) 2.40 2.67 2.94 Vpp Power Supply Rejection (Note 5) 60 dB DAC Analog Output Characteristics (Single-ended outputs) Resolution 24 bit S/(N+D) (0dBFS) fs=48kHz BW=20kHz 85 95 dB fs=96kHz BW=40kHz 93 fs=192kHz BW=40kHz 93 DR (-60dBFS with A-weighted) 100 106 dB S/N (A-weighted) 100 106 dB Interchannel Isolation 100 dB Interchannel Gain Mismatch (Note 6) 0 0.7 dB Gain Drift 20 ppm/C Output Voltage AOUT=0.76 x AVDD2 2.25 2.51 2.77 Vpp Load Resistance (AC Load) 5 k Load Capacitance 30 pF Power Supply Rejection (Note 5) 60 dB Note 5. PSR is applied to AVDD1, AVDD2 and TVDD with 1kHz, 50mVpp. Note 6. Channel gain mismatch between all output channels (LOUT1-6, ROUT1-6). Parameter min typ max Power Supplies Power Supply Current Normal Operation (PDN pin = “H”) AVDD1+AVDD2 fs=48kHz 45 59 AVDD1+AVDD2 fs=96kHz, 192kHz 40 TVDD fs=48kHz 6 8 TVDD fs=96kHz 7 TVDD fs=192kHz 9 Power-down mode (PDN pin = “L”) (Note 7) AVDD1+AVDD2+TVDD 10 200 Note 7. In the power-down mode, all digital input pins including clock pins are held VSS1. Unit MS1582-E-00 2013/11 -8- mA mA mA mA mA µA [AK4617] 9. ADC Filter Characteristics (fs=48kHz) (Ta= -40 +105C; AVDD1, AVDD2= TVDD=3.0 3.6V) Parameter Symbol min typ ADC Digital Filter (Decimation LPF): SHARP ROLL-OFF(SD_AD bit=“0”) Passband (Note 8) ±0.16dB PB 0 - max Unit 18.8 kHz 0.28dB 3.0dB 20.0 kHz 22.8 kHz Stopband(Note 8) SB 28.4 kHz Stopband Attenuation SA 71 dB Group Delay Distortion 0 ~ 20.0kHz 0 1/fs GD Group Delay (Note 10) GD 15.5 1/fs ADC Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF FILTER(SD_AD bit=“1”) Passband (Note 8) ±0.16dB PB 0 18.8 kHz 20.0 kHz 0.28dB 22.8 kHz 3.0dB Stopband (Note 8) SB 28.4 Stopband Attenuation SA 72 Group Delay Distortion 0 ~ 20.0kHz 2.4 1/fs GD Group Delay (Note 10) GD 5.5 1/fs ADC Digital Filter (HPF): Frequency Response FR 3.7 Hz 3.0dB (Note 8) 10.9 Hz 0.5dB 24.0 Hz 0.1dB MS1582-E-00 2013/11 -9- [AK4617] 10. DAC Filter Characteristics (fs=48kHz) (Ta= -40 +105C; AVDD1, AVDD2= TVDD=3.0 3.6V) Parameter Symbol min typ max Unit DAC Digital Filter (LPF): SHARP ROLL-OFF(DEM=OFF; SD_DA bit=“0” ; SLOW bit=“0”) ±0.06dB PB 0 21.8 kHz Passband (Note 8) 24.0 kHz 6.0dB Stopband SB 26.2 kHz Passband Ripple (Note 12) PR dB -0.06 +0.06 Stopband Attenuation SA 52 dB Group Delay Distortion 0 ~ 20.0kHz 0 1/fs GD Group Delay (Note 10) GD 21.4 1/fs DAC Digital Filter + Analog Filter: Frequency Response 0 ~ 20.0kHz (Note 11) FR -0.1 dB DAC Digital Filter (LPF): SLOW ROLL-OFF(DEM=OFF; SD_DA bit=“0” ; SLOW bit=“1”) ±0.06dB 0 9.8 Passband (Note 9) PB kHz kHz 6.0dB 22.5 Stopband SB kHz 40.1 Passband Ripple (Note 12) PR dB -0.06 +0.06 Stopband Attenuation SA dB 50 Group Delay Distortion 0 ~ 20.0kHz 0 1/fs GD Group Delay (Note 10) GD 9.0 1/fs DAC Digital Filter + Analog Filter: Frequency Response 0 ~ 20.0kHz (Note 11) FR -4.0 dB DAC Digital Filter (LPF): SHORT DELAY SHARP ROLL-OFF (DEM=OFF; SD_DA bit=“1”; SLOW bit=“0”) ±0.06dB Passband (Note 8) PB 0 21.8 kHz 24.0 kHz 6.0dB Stopband SB 26.2 kHz Passband Ripple (Note 12) PR dB -0.06 +0.06 Stopband Attenuation SA 52 dB Group Delay Distortion 0 ~ 20.0kHz 1.7 1/fs GD Group Delay (Note 10) GD 8.3 1/fs DAC Digital Filter + Analog Filter: Frequency Response 0 ~ 20.0kHz (Note 11) FR -0.1 dB DAC Digital Filter (LPF): SHORT DELAY SLOW ROLL-OFF FILTER (DEM=OFF; SD_DA bit=“1”; SLOW bit=“1”) ±0.06dB Passband (Note 9) PB 0 9.8 kHz 22.5 kHz 6.0dB Stopband SB 40.1 kHz Passband Ripple (Note 12) PR dB -0.06 +0.06 Stopband Attenuation SA 50 dB Group Delay Distortion 0~20.0kHz 0.5 1/fs GD Group Delay (Note 10) GD 7.8 1/fs DAC Digital Filter + Analog Filter: Frequency Response 0 ~ 20.0kHz (Note 11) FR -4.0 dB MS1582-E-00 2013/11 - 10 - [AK4617] 11. DAC Filter Characteristics (fs=96kHz) (Ta= -40 +105C; AVDD1, AVDD2= TVDD=3.0 3.6V) Parameter Symbol min typ max Unit DAC Digital Filter (LPF): SHARP ROLL-OFF(DEM=OFF; SD_DA bit=“0” ; SLOW bit=“0”) ±0.06dB PB 0 43.6 kHz Passband (Note 8) 48.0 kHz 6.0dB Stopband SB 52.4 kHz Passband Ripple (Note 12) PR dB -0.06 +0.06 Stopband Attenuation SA 52 dB Group Delay Distortion 0 ~ 40.0kHz 0 1/fs GD Group Delay (Note 10) GD 21.4 1/fs DAC Digital Filter + Analog Filter: Frequency Response 0 ~ 40.0kHz (Note 11) FR -0.3 dB DAC Digital Filter (LPF): SLOW ROLL-OFF(DEM=OFF; SD_DA bit=“0” ; SLOW bit=“1”) 0 19.6 Passband (Note 9) ±0.06dB PB kHz kHz 6.0dB 45.0 Stopband SB kHz 80.2 Passband Ripple (Note 12) PR dB -0.06 +0.06 Stopband Attenuation SA dB 50 Group Delay Distortion 0 ~ 40.0kHz 0 1/fs GD Group Delay (Note 10) GD 9.0 1/fs DAC Digital Filter + Analog Filter: Frequency Response 0 ~ 40.0kHz (Note 11) FR -4.2 dB DAC Digital Filter (LPF): SHORT DELAY SHARP ROLL-OFF (DEM=OFF; SD_DA bit=“1”; SLOW bit=“0”) Passband (Note 8) ±0.06dB PB 0 43.6 kHz 48.0 kHz 6.0dB Stopband SB 52.4 kHz Passband Ripple (Note 12) PR dB -0.06 +0.06 Stopband Attenuation SA 52 dB Group Delay Distortion 0 ~ 40.0kHz 1.7 1/fs GD Group Delay (Note 10) GD 8.3 1/fs DAC Digital Filter + Analog Filter: Frequency Response 0 ~ 40.0kHz (Note 11) FR -0.3 dB DAC Digital Filter (LPF): SHORT DELAY SLOW ROLL-OFF FILTER (DEM=OFF; SD_DA bit=“1” ; SLOW bit=“1”) Passband (Note 9) ±0.06dB PB 0 19.6 kHz 45.0 kHz 6.0dB Stopband SB 80.2 kHz Passband Ripple (Note 12) PR dB -0.06 +0.06 Stopband Attenuation SA 50 dB Group Delay Distortion 0 ~ 40.0kHz 0.5 1/fs GD Group Delay (Note 10) GD 7.8 1/fs DAC Digital Filter + Analog Filter: Frequency Response 0 ~ 40.0kHz (Note 11) FR -4.2 dB MS1582-E-00 2013/11 - 11 - [AK4617] 12. DAC Filter Characteristics (fs=192kHz) (Ta= -40 +105C; AVDD1, AVDD2= TVDD=3.0 3.6V) Parameter Symbol min typ max Unit DAC Digital Filter (LPF): SHARP ROLL-OFF(DEM=OFF; SD_DA bit=“0” ; SLOW bit=“0”) ±0.06dB PB 0 87.2 kHz Passband (Note 8) 96.0 kHz 6.0dB Stopband SB 104.8 kHz Passband Ripple (Note 12) PR dB -0.06 +0.06 Stopband Attenuation SA 52 dB Group Delay Distortion 0 ~ 80.0kHz 0 1/fs GD Group Delay (Note 10) GD 21.4 1/fs DAC Digital Filter + Analog Filter: Frequency Response 0 ~ 80.0kHz (Note 11) FR -1.0 dB DAC Digital Filter (LPF): SLOW ROLL-OFF(DEM=OFF; SD_DA bit=“0” ; SLOW bit=“1”) 0 39.2 Passband (Note 9) ±0.06dB PB kHz kHz 6.0dB 90.0 Stopband SB kHz 160.4 Passband Ripple (Note 12) PR dB -0.06 +0.06 Stopband Attenuation SA dB 50 Group Delay Distortion 0 ~ 80.0kHz 0 1/fs GD Group Delay (Note 10) GD 9.0 1/fs DAC Digital Filter + Analog Filter: Frequency Response 0 ~ 80.0kHz (Note 11) FR -5.0 dB DAC Digital Filter (LPF): SHORT DELAY SHARP ROLL-OFF (DEM=OFF; SD_DA bit=“1”; SLOW bit=“0”) Passband (Note 8) ±0.06dB PB 0 87.2 kHz 96.0 kHz 6.0dB Stopband SB 104.8 kHz Passband Ripple (Note 12) PR dB -0.06 +0.06 Stopband Attenuation SA 52 dB Group Delay Distortion 0 ~ 80.0kHz 1.7 1/fs GD Group Delay (Note 10) GD 8.3 1/fs DAC Digital Filter + Analog Filter: Frequency Response 0 ~ 80.0kHz (Note 11) FR -1.0 dB DAC Digital Filter (LPF): SHORT DELAY SLOW ROLL-OFF FILTER (DEM=OFF; SD_DA bit=“1” ; SLOW bit=“1”) Passband (Note 9) ±0.06dB PB 0 39.2 kHz 90.0 kHz 6.0dB Stopband SB 160.4 kHz Passband Ripple (Note 12) PR dB -0.06 +0.06 Stopband Attenuation SA 50 dB Group Delay Distortion 0 ~ 80.0kHz 0.5 1/fs GD Group Delay (Note 10) GD 7.8 1/fs DAC Digital Filter + Analog Filter: Frequency Response 0 ~ 80.0kHz (Note 11) FR -5.0 dB Note 8. The passband and stopband frequencies scale with fs (sampling frequency). For example, ADC: Passband (0.1dB) = 0.375 x fs, DAC: Passband (0.06dB) = 0.454 x fs. Note 9. The passband and stopband frequencies scale with fs (sampling frequency). For example, DAC: Passband (0.06dB) = 0.204 x fs. MS1582-E-00 2013/11 - 12 - [AK4617] Note 10. The calculated delay time is resulting from digital filtering. For the ADC, this time is from the input of an analog signal to the setting of 24bit data for both channels to the ADC output register. For the DAC, this time is from setting the 24 bit data both channels at the input register to the output of an analog signal. Note 11. The reference frequency is 1kHz. Note 12. It is the gain amplitude in passband. 13. DC Characteristics (Ta=-40+105C; AVDD1, AVDD2= TVDD=3.0 3.6V) Parameter Symbol min High-Level Input Voltage VIH 70% TVDD (MCLK, LRCK, BICK, SDTI1-6/TDMI, SPI, CSN/PS, CCLK/SCL/MS, CDTI/SDA/DIF, VIL CAD1/TDM0, PDN pins) Low-Level Input Voltage (MCLK, LRCK, BICK, SDTI1-6/TDMI, SPI, CSN/PS, CCLK/SCL/MS, CDTI/SDA/DIF, CAD1/TDM0, PDN pins) High-Level Output Voltage (LRCK, BICK, SDTO pins: Iout=-100µA) VOH TVDD-0.5 Low-Level Output Voltage (LRCK, BICK, SDTO pins: Iout= 100µA) VOL (SDA pin: Iout= 3mA) VOL Input Leakage Current Iin - MS1582-E-00 typ - max - Unit V - 30% TVDD V - - V - 0.5 0.4 10 V V µA 2013/11 - 13 - [AK4617] 14. Switching Characteristics (Ta=-40+105C; AVDD1, AVDD2= TVDD=3.0 3.6V; CL=20pF; unless otherwise specified) Parameter Symbol min typ max Master Clock Timing External Clock 256fsn: fCLK 2.048 12.288 Pulse Width Low tCLKL 32 Pulse Width High tCLKH 32 384fsn: fCLK 3.072 18.432 Pulse Width Low tCLKL 22 Pulse Width High tCLKH 22 512fsn: fCLK 4.096 24.576 Pulse Width Low tCLKL 16 Pulse Width High tCLKH 16 256fsd, 128fsq: fCLK 16.384 24.576 Pulse Width Low tCLKL 16 Pulse Width High tCLKH 16 LRCK Timing (Slave mode) Stereo mode (Figure 2) (TDM1-0 bit = “00”) Normal Speed Mode fsn 8 48 Double Speed Mode fsd 64 96 Quad Speed Mode fsq 128 192 Duty Cycle Duty 45 55 TDM512 mode (Figure 3),(Note 13) (TDM1-0 bit = “01”) LRCK frequency fsn 8 48 “H” time tLRH 1/512fs “L” time tLRL 1/512fs TDM256 mode (Figure 3),(Note 14) (TDM1-0 bit = “10”) LRCK frequency fsn 8 48 fsd 64 96 “H” time tLRH 1/256fs “L” time tLRL 1/256fs TDM128 mode (Figure 3),(Note 15) (TDM1-0 bit = “11”) LRCK frequency fsq 128 192 “H” time tLRH 1/128fs “L” time tLRL 1/128fs MS1582-E-00 Unit MHz ns ns MHz ns ns MHz ns ns MHz ns ns kHz kHz kHz % kHz ns ns kHz kHz ns ns kHz ns ns 2013/11 - 14 - [AK4617] LRCK Timing (Master Mode) Stereo mode (Figure 4) (TDM1-0 bit = “00”) Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle TDM512 mode (Figure 5),(Note 13) (TDM1-0 bit = “01”) LRCK frequency “H” time (Note 16) TDM256 mode (Figure 5),(Note 14) (TDM1-0 bit = “10”) LRCK frequency fsn fsd fsq Duty 8 64 128 - fsn tLRH 8 fsn fsd tLRH 8 64 50 48 96 192 - kHz kHz kHz % 48 kHz ns 48 96 kHz kHz ns 1/16fs “H” time (Note 16) 1/8fs TDM128 mode (Figure 5),(Note 15) (TDM1-0 bit = “11”) LRCK frequency fsq 128 192 kHz “H” time (Note 16) tLRH 1/4fs ns Note 13. Please use for Normal Speed mode. Master clock should be input the 512fs in Master mode. Note 14. Please use for Normal Speed mode, Double Speed mode. Master clock should be input the 256fs or 512fs in Master mode. Note 15. Please use for Quad Speed mode. Master clock should be input the 128fs in Master mode. Note 16. If the format is I2S, it is “L” time. MS1582-E-00 2013/11 - 15 - [AK4617] Parameter Audio Interface Timing (Slave mode) Stereo mode (TDM1-0 bit = “00”) for Normal Speed mode (Figure 2, Figure 6) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “” (Note 17) BICK “” to LRCK Edge (Note 17) LRCK to SDTO(MSB) (Except I2S mode) BICK “” to SDTO SDTI Hold Time SDTI Setup Time Stereo mode (TDM1-0 bit = “00”) for Double and Quad Speed mode (Figure 2, Figure 6) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “” (Note 17) BICK “” to LRCK Edge (Note 17) SDTI Hold Time SDTI Setup Time TDM512 mode (TDM1-0 bit = “01”) (Note 13) (Figure 3, Figure 7) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “” (Note 17) BICK “” to LRCK Edge (Note 17) SDTO Setup time BICK “” SDTO Hold time BICK “” SDTI Hold Time SDTI Setup Time TDM256 mode (TDM1-0 bit = “10”) (Note 14) (Figure 3, Figure 7) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “” (Note 17) BICK “” to LRCK Edge (Note 17) SDTO Setup time BICK “” SDTO Hold time BICK “” SDTI Hold Time SDTI Setup Time TDM128 mode (TDM1-0 bit = “11”) (Note 15) (Figure 3, Figure 7) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “” (Note 17) BICK “” to LRCK Edge (Note 17) SDTI Hold Time SDTI Setup Time MS1582-E-00 Symbol min typ max tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tSDH tSDS 324 130 130 20 20 50 50 ns ns ns ns ns ns ns ns ns tBCK tBCKL tBCKH tLRB tBLR tSDH tSDS 81 33 33 23 23 10 10 ns ns ns ns ns ns ns tBCK tBCKL tBCKH tLRB tBLR tBSS tBSH tSDH tSDS 40 16 16 10 10 6 5 10 10 ns ns ns ns ns ns ns ns ns ns tBCK tBCKL tBCKH tLRB tBLR tBSS tBSH tSDH tSDS 40 16 16 10 10 6 5 10 10 ns ns ns ns ns ns ns ns ns ns tBCK tBCKL tBCKH tLRB tBLR tSDH tSDS 40 16 16 10 10 10 10 ns ns ns ns ns ns ns 80 80 Unit 2013/11 - 16 - [AK4617] Parameter Symbol min Audio Interface Timing (Master mode) Stereo mode (TDM1-0 bit = “00”) for Normal Speed mode (Figure 4, Figure 8) BICK Frequency fBCK BICK Duty dBCK tMBLR BICK “” to LRCK 80 tBSD BICK “” to SDTO 80 tSDH SDTI Hold Time 50 tSDS SDTI Setup Time 50 Stereo mode (TDM1-0 bit = “00”) for Double and Quad Speed mode (Figure 4, Figure 8) BICK Frequency fBCK BICK Duty (Table 17) dBCK SDTI Hold Time tSDH 10 SDTI Setup Time tSDS 10 TDM512 mode (TDM1-0 bit = “01”) (Note 13) (Figure 5, Figure 9) BICK Frequency fBCK BICK Duty (Table 17) dBCK BICK “” to LRCK tMBLR -10 tBSS 6 SDTO Setup time BICK “” tBSH 5 SDTO Hold time BICK “” tSDH 5 SDTI Hold Time tSDS 6 SDTI Setup Time TDM256 mode (TDM1-0 bit = “10”) (Note 14) (Figure 5, Figure 9) BICK Frequency fBCK BICK Duty (Table 17) dBCK BICK “” to LRCK tMBLR 10 tBSS SDTO Setup time BICK “” 6 tBSH 5 SDTO Hold time BICK “” tSDH 5 SDTI Hold Time tSDS 6 SDTI Setup Time TDM128 mode (TDM1-0 bit = “11”) (Note 15) (Figure 5, Figure 9) BICK Frequency fBCK BICK Duty (Table 17) dBCK tMBLR BICK “” to LRCK 10 tSDH SDTI Hold Time 10 tSDS SDTI Setup Time 10 Note 17. BICK rising edge must not occur at the same time as LRCK edge. Note 18. In the case that the duty of MCLK is 50%. MS1582-E-00 typ max Unit 64fs 50 - 80 80 - Hz % ns ns ns ns 64fs 50 - - Hz % ns ns 512fs 50 10 - Hz % ns ns ns ns ns 256fs 50 - 10 -- Hz % ns ns ns ns ns 128fs 50 - 10 - Hz % ns ns ns - 2013/11 - 17 - [AK4617] Parameter Control Interface Timing (3-wire Serial mode): CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CSN “” to CCLK “” CCLK “” to CSN “” Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 19) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Capacitive load on bus Power-down & Reset Timing PDN Pulse Width (Note 20) PDN “” to SDTO valid (Note 21) Symbol min tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 80 80 40 40 150 50 50 fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP Cb 1.3 0.6 1.3 0.6 0.6 0 0.1 0.6 0 - tPD tPDV 150 typ max Unit ns ns ns ns ns ns ns ns 400 1.0 0.3 50 400 kHz s s s s s s s s s ns pF ns 32768/MCLK s +1059/fs Note 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 20. The AK4617 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must held “L” for more than 150ns for a certain reset. The AK4617 is not reset by the “L” pulse less than 30ns. Note 21. These cycles are the numbers of MCLK and LRCK rising from the PDN pin rising. Note 22. I2C is a trademark of NXP B.V. MS1582-E-00 2013/11 - 18 - [AK4617] ■ Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fsn, 1/fsd, 1/fsq VIH LRCK VIL tdLRKH tdLRKL Duty = tdLRKH (or tdLRKL) x fs x 100 tBCK VIH BICK VIL tBCKH tBCKL Figure 2. Clock Timing (TDM1-0 bit = “00” & Slave mode) 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fs VIH LRCK VIL tLRH tLRL tBCK VIH BICK VIL tBCKH tBCKL Figure 3. Clock Timing (Except TDM1-0 bit = “00” & Slave mode) MS1582-E-00 2013/11 - 19 - [AK4617] 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fs LRCK 50%TVDD tdLRKH tdLRKL dLRK = tdLRKH (or tdLRKL) x fs x 100 1/fBCK 50%TVDD BICK tdBCKH tdBCKL dBCK = tdBCKH (or tdBCKL) x fs x 100 Figure 4. Clock Timing (TDM1-0 bit = “00” & Master mode) 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fs LRCK 50%TVDD tLRH 1/fBCK 50%TVDD BICK tdBCKH tdBCKL dBCK = tdBCKH (or tdBCKL) x fs x 100 Figure 5. Clock Timing (Except TDM1-0 bit = “00” & Master mode) MS1582-E-00 2013/11 - 20 - [AK4617] VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD SDTO 50%TVDD tSDS tSDH VIH SDTI VIL Figure 6. Audio Interface Timing (TDM1-0 bit = “00” & Slave mode) VIH LRCK VIL tBLR tLRB VIH BICK VIL tBSS tBSH SDTO 50%TVDD tSDS tSDH VIH SDTI VIL Figure 7. Audio Interface Timing (Except TDM1-0 bit = “00” & Slave mode) MS1582-E-00 2013/11 - 21 - [AK4617] LRCK 50%TVDD tMBLR 50%TVDD BICK tBSD 50%TVDD SDTO tSDS tSDH VIH SDTI VIL Figure 8. Audio Interface Timing (TDM1-0 bit = “00” & Master mode) LRCK 50%TVDD tMBLR 50%TVDD BICK tBSS tBSH 50%TVDD SDTO tSDS tSDH VIH SDTI VIL Figure 9. Audio Interface Timing (Except TDM1-0 bit = “00” & Master mode) MS1582-E-00 2013/11 - 22 - [AK4617] VIH CSN VIL tCSH tCSS tCCKL tCCKH VIH CCLK VIL tCDS tCDH VIH CDTI C1 C0 R/W VIL Figure 10. WRITE Command Input Timing (3-wire Serial mode) tCSW VIH CSN VIL tCSH tCSS VIH CCLK VIL VIH CDTI D2 D1 D0 VIL Figure 11. WRITE Data Input Timing (3-wire Serial mode) MS1582-E-00 2013/11 - 23 - [AK4617] VIH CSN VIL VIH CCLK VIL VIH CDTI A1 A0 VIL Figure 12. Read Data Output Timing1(3-wire Serial mode) tCSW VIH CSN VIL tCSH tCSS VIH CCLK VIL VIH CDTI VIL Figure 13. Read Data Output Timing2(3-wire Serial mode) MS1582-E-00 2013/11 - 24 - [AK4617] VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop Start Figure 14. I2C Bus mode Timing tPD VIH PDN VIL tPDV SDTO 50%TVDD Figure 15. Power-down & Reset Timing MS1582-E-00 2013/11 - 25 - [AK4617] 15. Functional Descriptions ■ System Clock The external clocks which are required to operate the AK4617 in slave mode are MCLK, LRCK and BICK. MCLK should be synchronized with LRCK but the phase is not critical. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS bit= “0”: Default), the sampling speed is set by DFS0, DFS1 (Table 1). The frequency of MCLK at each sampling speed is set automatically. (Table 3, Table 4, Table 5). In Auto Setting Mode (ACKS bit= “1”), as MCLK frequency is detected automatically (Table 6) and the internal master clock attains the appropriate frequency (Table 7), so it is not necessary to set DFS. In master mode, only MCLK is required. Master Clock Input Frequency should be set with the CKS1-0 bit, and the sampling speed should be set by the DFS1-0 bit. The frequencies and the duties of the clocks (LRCK, BICK) are not stabile immediately after setting CKS1-0 bit and DFS1-0 bit up. After exiting reset at power-up in slave mode, the AK4617 is in power-down mode until MCLK and LRCK are input. If the clock is stopped, click noise occurs when restarting the clock. Mute the digital output externally. Note: ADC is automatically powered-down in Double Speed Mode and Quad Speed Mode. DFS1 0 0 1 1 DFS0 0 1 0 1 Sampling Speed Mode (fs) (default) Normal Speed Mode 8kHz~48kHz Double Speed Mode 64kHz~96kHz Quad Speed Mode 128kHz~192kHz N/A (N/A: Not available) Table 1. Sampling Speed (Manual Setting Mode) CKS1 CKS0 0 0 1 1 0 1 0 1 Normal Speed Mode 256fs 384fs 512fs 512fs Double Speed Mode 256fs 256fs 256fs 256fs Quad Speed Mode 128fs 128fs 128fs 128fs (default) Table 2. Master Clock Input Frequency Select (Master Mode) Note: In Normal Speed Mode, TDM mode (TDM1-0 bit =”01) can be used when CKS1 bit = “1”. LRCK fs 32.0kHz 44.1kHz 48.0kHz 256fs 8.1920 11.2896 12.2880 MCLK (MHz) 384fs 12.2880 16.9344 18.4320 512fs 16.3840 22.5792 24.5760 BICK (MHz) 64fs 2.0480 2.8224 3.0720 Table 3. System Clock Example (Normal Speed Mode @Manual Setting Mode) MS1582-E-00 2013/11 - 26 - [AK4617] LRCK fs 88.2kHz 96.0kHz MCLK (MHz) 256fs 22.5792 24.5760 BICK (MHz) 64fs 5.6448 6.1440 Table 4. System Clock Example (Double Speed Mode @Manual Setting Mode) LRCK fs 176.4kHz 192.0kHz MCLK (MHz) 128fs 22.5792 24.5760 BICK (MHz) 64fs 11.2896 12.2880 Table 5. System Clock Example (Quad Speed Mode @Manual Setting Mode) MCLK 512fs 256fs 128fs Sampling Speed Mode Normal Speed Mode Double Speed Mode Quad Speed Mode Table 6. Sampling Speed (Auto Setting Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 128fs 22.5792 24.5760 MCLK (MHz) 256fs 512fs 16.3840 22.5792 24.5760 22.5792 24.5760 - Sampling Speed Mode Normal Speed Mode Double Speed Mode Quad Speed Mode Table 7. System Clock Example (Auto Setting Mode) MS1582-E-00 2013/11 - 27 - [AK4617] ■ De-emphasis Filter The AK4617 has a digital de-emphasis filter (tc=50/15µs) by an IIR filter. The de-emphasis filter supports only Normal Speed Mode. This filter corresponds to three sampling frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis of each DAC can be set individually by registers, DAC1(SDTI1), DAC2(SDTI2), DAC3(SDTI3), DAC4(SDTI4), DAC5(SDTI5), DAC6(SDTI6). Mode Sampling Speed Mode 0 1 2 3 Normal Speed Mode Normal Speed Mode Normal Speed Mode Normal Speed Mode DEM11 (DEM61-21) 0 0 1 1 DEM10 (DEM60-20) 0 1 0 1 DEM 44.1kHz OFF 48kHz 32kHz (default) Table 8. De-emphasis control ■ Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 3.7Hz at fs=48kHz and scales with the sampling rate (fs). ■ Master Mode and Slave Mode Master Mode and Slave Mode are selected by setting the MS pin in Parallel control mode. (Master Mode= “H”, Slave Mode= “L”) LRCK and BICK pins are outputs in Master Mode (MS pin= “H”) LRCK and BICK pins are inputs in Slave Mode (MS pin= “L”) In the serial control mode, BICK and LRCK pins are Hi-z before an internal power up and MS bit = “1”. In the parallel control mode, BICK and LRCK pins are Hi-z before an internal power up. When a problem is occurred by this, pull down BICK and LRCK pins by external resistance (ex. 100kohm). PDN L H MS pin L H L H LRCK pin Input Hi-z Input Output BICK pin Input Hi-z Input Output Table 9. LRCK and BICK pins MS1582-E-00 2013/11 - 28 - [AK4617] ■ Audio Serial Interface Format (1) Stereo Mode When TDM1-0 bit = “00”, ten modes can be selected by the DIF2-0 bit as shown in Table 10. In all modes the serial data is MSB-first, 2’s compliment format. The data SDTO is clocked out on the falling edge of BICK and the SDTI1-6 is latched on the rising edge of BICK. Mode3/4/8/9/13/14/18/19/23/24/28/29/33/34/38/39 in SDTI input formats can be used for 16-20bit data by zeroing the unused LSBs. Mode M/S TDM1 TDM0 DIF2 DIF1 DIF0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 2 0 0 0 0 1 0 3 0 0 0 0 1 1 4 0 0 0 1 0 0 5 1 0 0 0 0 0 6 1 0 0 0 0 1 7 1 0 0 0 1 0 8 1 0 0 0 1 1 9 1 0 0 1 0 0 SDTO SDTI1-6 24bit, Left justified (*) 24bit, Left justified 24bit, Left justified 24bit, Left justified 16bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 24bit, I2S 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 16bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S LRCK I/O BICK I/O 32fs I 64fs 48fs I 64fs 48fs I 64fs 48fs I 64fs 48fs I 64fs H/L I H/L I H/L I H/L I L/H I H/L O 64fs O H/L O 64fs O H/L O 64fs O H/L O 64fs O L/H O 64fs O (default) Table 10. Audio data formats (Stereo mode) (*)When the BICK is less than 48fs, the output data length from SDTO is limited to the clock number of BICK in the half LRCK period. MS1582-E-00 2013/11 - 29 - [AK4617] (2) TDM Mode The audio serial interface format is set in TDM mode by the TDM1-0 bit = “01”. Five modes can be selected by the DIF2-0 bit as shown in Table 11. In all modes the serial data is MSB-first, 2’s compliment format. The SDTO is clocked out on the rising edge of BICK and the SDTI1/2/3 are latched on the rising edge of BICK. In the TDM512 mode (fs = 48kHz), the serial data of all ADC (four channels) is output to the SDTO pin. And the serial data of all DAC (twelve channels) is input to the SDTI1 pin. The input data to SDTI2-6 pins are ignored and the SDTI6 pin is used as the TDMI pin. BICK should be fixed to 512fs. “H” time and “L” time of LRCK should be 1/512fs at least. TDM256 mode can be set by TDM1-0 bit as show in Table 12. In the TDM256 mode (fs =48, 96kHz), SDTO pin = “L” @96kHz. And the serial data of DAC (eight channels; L1, R1, L2, R2, L3, R3, L4, R4) is input to the SDTI1 pin. Other four data (L5, R5, L6, R6) are input to the SDTI2 pin. The input data to SDTI3-6 pins are ignored and the SDTI6 pin is used as the TDMI pin. BICK should be fixed to 256fs. “H” time and “L” time of LRCK should be 1/256fs at least. TDM128 mode can be set by TDM1-0 bit as show in Table 13. In TDM128 mode (fs=192kHz), SDTO pin = “L”. And the serial data of DAC (four channels; L1, R1, L2, R2) is input to the SDTI1 pin and the serial data of DAC (four channels; L3, R3, L4, R4) is input to the SDTI2 pin, the serial data of DAC (four channels; L5, R5, L6, R6) is input to the SDTI3 pin. The input data to SDTI4-6 pins are ignored. BICK should be fixed to 128fs. “H” time and “L” time of LRCK should be 1/128fs at least. Mode M/S TDM 1 TDM0 10 0 0 1 11 0 0 1 12 0 0 1 13 0 0 1 14 0 0 1 15 1 0 1 16 1 0 1 17 1 0 1 18 1 0 1 19 1 0 1 DIF2 DIF1 DIF0 SDTO SDTI1 24bit, Left 16bit, Right justified justified 24bit, Left 20bit, Right 0 0 1 justified justified 24bit, Left 24bit, Right 0 1 0 justified justified 24bit, Left 24bit, Left 0 1 1 justified justified 1 0 0 24bit, I2S 24bit, I2S 24bit, Left 16bit, Right 0 0 0 justified justified 24bit, Left 20bit, Right 0 0 1 justified justified 24bit, Left 24bit, Right 0 1 0 justified justified 24bit, Left 24bit, Left 0 1 1 justified justified 2 1 0 0 24bit, I S 24bit, I2S Table 11. Audio data formats (TDM512 mode) 0 0 0 MS1582-E-00 LRCK I/O BICK I/O I 512fs I I 512fs I I 512fs I I 512fs I I 512fs I O 512fs O O 512fs O O 512fs O O 512fs O O 512fs O 2013/11 - 30 - [AK4617] Mode M/S TDM1 TDM0 20 0 1 0 21 0 1 0 22 0 1 0 23 0 1 0 24 0 1 0 25 1 1 0 26 1 1 0 27 1 1 0 28 1 1 0 29 1 1 0 Mode M/S TDM1 TDM0 DIF2 DIF1 DIF0 SDTO SDTI1-2 24bit, Left 16bit, Right justified justified 24bit, Left 20bit, Right 0 0 1 justified justified 24bit, Left 24bit, Right 0 1 0 justified justified 24bit, Left 24bit, Left 0 1 1 justified justified 1 0 0 24bit, I2S 24bit, I2S 24bit, Left 16bit, Right 0 0 0 justified justified 24bit, Left 20bit, Right 0 0 1 justified justified 24bit, Left 24bit, Right 0 1 0 justified justified 24bit, Left 24bit, Left 0 1 1 justified justified 2 1 0 0 24bit, I S 24bit, I2S Table 12. Audio data formats (TDM256 mode) 0 DIF2 0 DIF1 0 DIF0 SDTO 30 0 1 1 0 0 0 L 31 0 1 1 0 0 1 L 32 0 1 1 0 1 0 L 33 0 1 1 0 1 1 L 34 0 1 1 1 0 0 L 35 1 1 1 0 0 0 L 36 1 1 1 0 0 1 L 37 1 1 1 0 1 0 L 38 1 1 1 0 1 1 L 39 1 1 1 1 0 0 L SDTI1-3 16bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 16bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S LRCK I/O BICK I/O I 256fs I I 256fs I I 256fs I I 256fs I I 256fs I O 256fs O O 256fs O O 256fs O O 256fs O O 256fs O LRCK I/O BICK I/O I 128fs I I 128fs I I 128fs I I 128fs I I 128fs I O 128fs O O 128fs O O 128fs O O 128fs O O 128fs O Table 13. Audio data formats (TDM128 mode) MS1582-E-00 2013/11 - 31 - [AK4617] LRCK 0 1 2 16 17 18 24 25 31 0 1 2 16 17 18 24 25 31 0 1 BICK(64fs) SDTO(o) 23 22 SDTI(i) 8 7 Don’t Care 6 0 15 14 8 23 22 7 1 8 7 Don’t Care 0 6 0 15 14 SDTO-23:MSB, 0:LSB; SDTI-15:MSB, 0:LSB Lch Data 23 8 7 1 0 Rch Data Figure 16. Mode 0/5 Timing (Stereo Mode) LRCK 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 1 BICK(64fs) SDTO(o) 23 22 SDTI(i) 12 11 10 0 19 18 8 Don’t Care 23 22 7 1 12 11 10 Don’t Care 0 0 19 18 SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB Lch Data 23 8 7 1 0 Rch Data Figure 17. Mode 1/6 Timing (Stereo Mode) LRCK 0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0 1 BICK(64fs) SDTO(o) 23 22 SDTI(i) 16 15 14 Don’t Care 0 23 22 23:MSB, 0:LSB 23 22 8 7 1 16 15 14 Don’t Care 0 0 23 22 Lch Data 23 8 7 1 0 Rch Data Figure 18. Mode 2/7 Timing (Stereo Mode) LRCK 0 1 2 21 22 23 24 28 29 30 31 0 1 2 22 23 24 28 29 30 31 0 1 BICK(64fs) SDTO(o) 23 22 2 1 0 SDTI(i) 23 22 2 1 0 23:MSB, 0:LSB Don’t Care Lch Data 23 22 2 1 0 23 22 2 1 0 23 Don’t Care 23 Rch Data Figure 19. Mode 3/8 Timing (Stereo Mode) MS1582-E-00 2013/11 - 32 - [AK4617] LRCK 0 1 2 3 22 23 24 25 29 30 31 0 1 2 3 22 23 24 25 29 30 31 0 1 BICK(64fs) SDTO(o) SDTI(i) 23 22 2 1 0 23 22 2 1 0 23:MSB, 0:LSB Don’t Care 23 22 2 1 0 23 22 2 1 0 Lch Data Don’t Care Rch Data Figure 20. Mode 4/9 Timing (Stereo Mode) 512BICK LRCK(Mode15) LRCK(Mode10) BICK(512fs) * SDTO(o) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK SDTI1(i) 15 14 0 15 14 0 15 14 R1 L1 15 14 0 0 15 14 R2 L2 0 15 14 0 15 14 R3 L3 15 14 0 15 14 0 R4 L4 0 15 14 0 15 14 R5 L5 15 14 0 0 15 R6 L6 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK TDMI(i) * 23 22 0 23 22 0 23 22 0 23 22 23 22 0 0 23 22 0 23 22 0 23 22 23 22 0 0 23 22 0 23 22 0 23 22 23 22 0 0 23 22 0 23 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK (*: Optional) Figure 21. Mode 10/15 Timing (TDM512 Mode) 512BICK LRCK(Mode16) LRCK(Mode11) BICK(512fs) * SDTO(o) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 23 22 0 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK SDTI1(i) 19 18 0 L1 19 18 0 R1 19 18 0 L2 19 18 0 R2 19 18 0 19 18 0 R3 L3 19 18 0 19 18 0 R4 L4 19 18 0 19 18 0 R5 L5 19 18 0 19 18 0 19 R6 L6 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK TDMI(i) * 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK (*: Optional) Figure 22. Mode 11/16 Timing (TDM512 Mode) MS1582-E-00 2013/11 - 33 - [AK4617] 512BICK LRCK(Mode17) LRCK(Mode12) BICK(512fs) * SDTO(o) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 23 22 0 0 23 22 0 23 22 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK SDTI1(i) 23 22 0 23 22 0 23 22 R1 L1 23 22 0 0 23 22 R2 L2 0 23 22 0 23 22 R3 L3 23 22 0 23 22 0 R4 L4 0 23 22 0 23 22 R5 L5 23 22 0 0 23 R6 L6 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK * TDMI(i) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK (*: Optional) Figure 23. Mode 12/17 Timing (TDM512 Mode) 512BICK LRCK(Mode18) LRCK(Mode13) BICK(512fs) * SDTO(o) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 23 22 0 0 23 22 0 23 22 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK SDTI1(i) 23 22 0 23 22 0 23 22 R1 L1 0 23 22 0 23 22 R2 L2 0 23 22 0 23 22 R3 L3 0 23 22 0 23 22 R4 L4 0 23 22 0 23 22 R5 L5 0 23 22 0 23 22 R6 L6 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK * TDMI(i) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 23 0 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK (*: Optional) Figure 24. Mode 13/18 Timing (TDM512 Mode) 512BICK LRCK(Mode19) LRCK(Mode14) BICK(512fs) * SDTO(o) 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK SDTI1(i) 23 0 L1 23 0 R1 23 0 L2 23 0 23 R2 0 L3 23 0 23 R3 0 L4 23 0 R4 23 0 L5 23 0 23 R5 0 23 0 23 R6 L6 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK TDMI(i) * 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK (*: Optional) Figure 25. Mode 14/19 Timing (TDM512 Mode) MS1582-E-00 2013/11 - 34 - [AK4617] 256 BICK LRCK (Mode25) LRCK (Mode20) BICK(256fs) * SDTO(o) 23 0 23 TDMI (i) * 23 0 23 0 23 0 23 0 23 0 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 0 15 14 0 15 14 0 15 14 0 15 14 0 15 14 0 15 14 0 15 14 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 15 14 23 0 Data 1 4 SDTI2(i) 23 32 BICK 15 14 SDTI1(i) 0 0 15 14 0 15 14 0 15 14 L5 R5 L6 R6 32 BICK 32 BICK 32 BICK 23 0 23 0 23 0 15 0 32 BICK 0 23 0 19 23 0 23 0 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 (*: Optional) Figure 26. Mode 20/25 Timing (TDM256 Mode) 256 BICK LRCK (Mode26) LRCK (Mode21) BICK(256fs) * SDTO (o) 23 23 23 23 0 23 0 23 0 23 0 23 0 23 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 0 19 18 0 19 18 0 19 18 0 19 18 0 19 18 0 19 18 0 19 18 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 19 18 SDTI2(i) 0 32 BICK 19 18 SDTI1(i) TDMI (i) * 0 0 19 18 0 19 18 0 19 18 L5 R5 L6 R6 32 BICK 32 BICK 32 BICK 32 BICK 0 23 0 23 0 23 0 23 0 19 0 19 23 0 23 0 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 (*: Optional) Figure 27. Mode 21/26 Timing (TDM256 Mode) MS1582-E-00 2013/11 - 35 - [AK4617] 256 BICK LRCK (Mode27) LRCK (Mode22) BICK(256fs) SDTO (o) * 23 22 0 23 0 23 0 23 0 23 23 0 0 23 0 23 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 22 SDTI2(i) 23 22 32 BICK 23 22 SDTI1(i) TDMI (i) * 0 0 23 22 0 23 22 0 23 22 0 L5 R5 L6 R6 32 BICK 32 BICK 32 BICK 32 BICK 23 0 23 0 23 0 23 23 0 23 23 0 23 0 23 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK (*: Optional) Figure 28. Mode 22/27 Timing (TDM256 Mode) 256 BICK LRCK (Mode28) LRCK (Mode23) BICK(256fs) * SDTO (o) SDTI1(i) SDTI2(i) TDMI (i) * 23 0 0 23 0 23 0 23 0 23 0 23 0 23 0 23 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 22 23 23 0 23 22 0 23 22 0 23 22 0 L5 R5 L6 R6 32 BICK 32 BICK 32 BICK 32 BICK 0 23 0 23 0 23 0 23 22 23 22 23 0 23 0 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 (*: Optional) Figure 29. Mode 23/28 Timing (TDM256 Mode) MS1582-E-00 2013/11 - 36 - [AK4617] 256 BICK LRCK (Mode29) LRCK (Mode24) BICK(256fs) * SDTO (o) SDTI1(i) SDTI2(i) TDMI (i) * 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 0 23 0 23 0 23 23 L5 R5 L6 R6 32 BICK 32 BICK 32 BICK 0 23 0 23 0 23 0 32 BICK 23 23 23 0 23 0 23 0 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 (*: Optional) Figure 30. Mode 24/29 Timing (TDM256 Mode) 128 BICK LRCK (Mode35) LRCK (Mode30) BICK(128fs) SDTI1(i) SDTI2(i) SDTI3(i) 15 14 0 0 15 14 15 14 0 15 14 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 15 14 0 15 14 0 15 14 0 15 14 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 0 15 14 0 15 14 15 14 0 15 14 L5 R5 L6 R6 32 BICK 32 BICK 32 BICK 32 BICK 0 15 0 15 0 15 Figure 31. Mode 30/35 Timing (TDM128 Mode) MS1582-E-00 2013/11 - 37 - [AK4617] 128 BICK LRCK (Mode36) LRCK (Mode31) BICK(128fs) SDTI1(i) SDTI2(i) SDTI3(i) 19 18 0 0 19 18 19 18 0 19 18 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 19 18 0 19 18 0 19 18 0 19 18 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 0 19 18 0 19 18 19 18 0 19 18 L5 R5 L6 R6 32 BICK 32 BICK 32 BICK 32 BICK 0 19 0 19 0 19 0 23 0 23 0 23 Figure 32. Mode 31/36 Timing (TDM128 Mode) 128 BICK LRCK (Mode37) LRCK (Mode32) BICK(128fs) SDTI1(i) SDTI2(i) SDTI3(i) 23 22 0 0 23 22 23 22 0 23 22 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 23 22 0 23 22 0 23 22 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 0 23 22 0 23 22 23 22 0 23 22 L5 R5 L6 R6 32 BICK 32 BICK 32 BICK 32 BICK Figure 33. Mode 32/37 Timing (TDM128 Mode) MS1582-E-00 2013/11 - 38 - [AK4617] 128 BICK LRCK (Mode38) LRCK (Mode33) BICK(128fs) SDTI1(i) SDTI2(i) SDTI3(i) 23 22 0 0 23 22 23 22 0 L1 R1 L2 32 BICK 32 BICK 32 BICK 0 23 22 0 23 22 23 22 0 23 22 R2 32 BICK 23 22 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 0 23 22 0 23 22 23 22 0 23 22 L5 R5 L6 R6 32 BICK 32 BICK 32 BICK 32 BICK 0 23 22 0 23 22 0 23 22 0 23 0 23 0 23 Figure 34. Mode 33/38 Timing (TDM128 Mode) 128 BICK LRCK (Mode39) LRCK (Mode34) BICK(128fs) SDTI1(i) SDTI2(i) SDTI3(i) 23 0 23 0 0 23 23 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 0 23 0 23 0 23 23 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 0 23 0 23 0 23 23 L5 R5 L6 R6 32 BICK 32 BICK 32 BICK 32 BICK Figure 35. Mode 34/39 Timing (TDM128 Mode) MS1582-E-00 2013/11 - 39 - [AK4617] ■ TDM Cascade Mode The AK4617 can be connected with other ADCs or CODECs in cascades in TDM mode. In Figure 36, the SDTO pin of ADC or CODEC is connected with the TDMI pin of the AK4617. It is possible to output 8channel TDM data from the SDTO pin of the AK4617 as shown in Figure 26 and Figure 30 in TDM256 mode, and it is possible to output 16channel TDM data in TDM 512 mode. ADC or CODEC 256fs or 512fs MCLK 48kHz LRCK 256fs or 512fs BICK SDTO1 AK4617 MCLK TDMI LRCK BICK SDTO 8ch TDM Figure 36. Cascade TDM Connection Diagram MS1582-E-00 2013/11 - 40 - [AK4617] ■ Digital Attenuator AK4617 has a channel-independent digital attenuator (256 levels, 0.5dB steps). Attenuation level of each DAC1-6 can be set by DAATL1/R1 7-0 bit, DAATL2/R2 7-0 bit, DAATL3/R3 7-0 bit, DAATL4/R4 7-0 bit, DAATL5/R5 7-0 bit, DAATL6/R6 7-0 bit, respectively (Table 14). DAATL1/R1 7-0bit DAATL2/R2 7-0 bit DAATL3/R3 7-0 bit Attenuation Level DAATL4/R4 7-0 bit DAATL5/R5 7-0 bit DAATL6/R6 7-0 bit 00H +0dB (default) 01H -0.5dB 02H -1.0dB : : 7DH -62.5dB 7EH -63.0dB 7FH -63.5dB : : FEH -127.0dB FFH MUTE (-∞) Table 14. Attenuation level of DAC Digital Attenuator Transition time between set values of DAATL1/R1 7-0, DAATL2/R2 7-0, DAATL3/R3 7-0, DAATL4/R4 7-0, DAATL5/R5 7-0, DAATL6/R6 bit can be selected by the DAATS1-0 bit (Table 15). Transition between set values is the soft transition in Mode1/2/3 eliminating switching noise in the transition. Mode 0 1 2 3 DAATS1 0 0 1 1 DAATS0 0 1 0 1 ATT speed 4080/fs 2040/fs 510/fs 255/fs (default) Table 15. Transition Time between Set Values of DAATL1/R1 7-0, DAATL2/R2 7-0, DAATL3/R3 7-0, DAATL4/R4 7-0, DAATL5/R5 7-0, DAATL6/R6 7-0 bit The transition between set values is a soft transition of 4080 levels in mode 0. It takes 4080/fs (85ms@fs=48kHz) from 00H to FFH. If the PDN pin goes to “L”, DAATL1/R1 7-0, DAATL2/R2 7-0, DAATL3/R3 7-0, DAATL4/R4 7-0, DAATL5/R5 7-0, DAATL6/R6 7-0 bit are initialized to 00H. These bit are also set to 00H respectively when RSTN bit = “0”, and fade to their current value when RSTN bit returns to “1”. MS1582-E-00 2013/11 - 41 - [AK4617] ■ Soft Mute Operation Soft mute operation is performed in the digital domain. When the SMUTEN pin is set to “L” or SMUTEN bit is set “0”, the output signal is attenuated to - in the cycle set by ATS bit (Table 15) from the current ATT level. When the SMUTEN bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level in the cycle set by ATS bit. If the soft mute is cancelled before attenuating to - after starting the operation, attenuation is discontinued and it is returned to ATT level by the same cycle. Soft mute is effective for changing the signal source without stopping the signal transmission. SMUTEN pin or SMUTEN bit ATT Level (1) (2) (4) Attenuation - GD (3) GD AOUT Notes: (1) The time for input data attenuation to - (Table 15). For example, this time is 4080LRCK cycles (4080/fs) at ATT_DATA=00H. ATT transition of the soft-mute is from 00H to FFH (2) The time for input data recovery to ATT level (Table 15). For example, this time is 4080LRCK cycles (4080/fs) at ATT-DATA=FFH. ATT transition of soft-mute is from FFH to 00H. (3) The analog output corresponding to the digital input has group delay, GD. (4) If the soft mute is cancelled before attenuating to -, the attenuation is discontinued and returned to ATT level by the same cycle. Figure 37. Soft Mute ■ System Reset The AK4617 should be reset once by bringing the PDN pin = “L” upon power-up. The AK4617 is powered up and the internal timing starts clocking by MCLK or LRCK “” after exiting the power down state of reference voltage (such as VCOM) by the PDN pin. The AK4617 is in power-down mode until MCLK and LRCK, BICK are input. MS1582-E-00 2013/11 - 42 - [AK4617] ■ Power-Down All ADCs and DACs of the AK4617 are placed in power-down mode by bringing the PDN pin “L” which resets both digital filters at the same time. The PDN pin “L” also resets the control registers to their default values. In power-down mode, the SDTO goes to “L”, and the analog outputs go to Hi-Z. This reset should always be executed after power-up. For the ADC, an analog initialization cycle (1056/fs) starts 3~4/fs after exiting power-down mode. The output data, SDTO is available after 1059~1060 cycles of the LRCK clock. For the DAC, an analog initialization cycle (516/fs) starts 3~4/fs after exiting power-down mode. The analog outputs go to Hi-Z during the initialization. Figure 38 shows the power-down and power-up sequences. AVDD1/AVD D2/DVDD (11) PDN VCOM 150ns REGO 3~4/fs Internal PDN (9) (10) 1056/fs ADC Internal State (1) Init Cycle Normal Operation Power-down Normal Operation Power-down 516/fs (2) DAC Internal State Init Cycle GD (3) GD ADC In (Analog) ADC Out (Digital) “0”data DAC In (Digital) “0”data (6) (4) “0”data “0”data GD(3) DAC Out (Analog) (5) (7) GD (7) (7) Clock In Don’t care Don’t care MCLK,LRCK,BICK External Mute Mute ON Mute ON (8) Notes: (1) The analog part of ADC is initialized after exiting internal power-down state. When start-up the AK4617, ADC input voltage should be operating common voltage. It is necessary to wait for the charge up time of HPF which consists of analog inputs. When the external capacitor is 1uF and the input impedance is 60kΩ(typ), τ = 0.06 sec. (2) The analog part of DAC is initialized after exiting internal power-down state. (3) Digital output corresponds to analog input and analog output corresponds to digital input have group delay (GD). (4) ADC output is “0” data at power-down state. (5) The analog outputs go to Hi-Z in power-down mode. (6) Click noise occurs at the end of initialization of the analog part. Mute the digital output externally. (7) Click noise occurs at the falling edge of PDN and at 519~520/fs after exiting internal power-down state. (8) Mute the analog output externally. (9) There is a delay, 3~4/fs from internal power up to the start of initial cycle. (10) The PDN pin must be “L” when power up the AK4617 and set to “H” after all poweres are supplied. (11) The internal power-down state is released when MCLK counter rise.Do not write to the registers for 32768/MCLK(2.67ms@MCLK=12.288MHz, until internal power down is released after the PDN pin = “H”. Figure 38. Pin power-down/Pin Power-up Sequence Example MS1582-E-00 2013/11 - 43 - [AK4617] All ADCs and all DACs can be powered-down individually through the PMADC bit and PMDAC bit. DAC1-6 can be power-down individually by PMDA6-1 bit. In this case, the internal register values are not initialized. When PMADC bit = “0”, SDTO goes to “L”. When PMDAC bit = “0”, the analog outputs go to Hi-Z. As some click noise occurs, the analog output should be muted externally if the click noise influences system applications. Figure 39 shows the power-down and power-up sequences. 4~5/fs (9) 3~4/fs (10) PMADC/PMDAC bit (1) ADC Internal State Normal Operation DAC Internal State Normal Operation Power-down Init Cycle Normal Operation 516/fs (2) Power-down Init Cycle Normal Operation GD (3) GD ADC In (Analog) ADC Out (Digital) “0”data DAC In (Digital) “0”data GD Clock In GD (5) (7) Don’t care MCLK,LRCK,BICK External Mute (6) (3) (7) DAC Out (Analog) (4) (8) Mute ON Notes: (1) The analog section of ADC is initialized after exiting power-down state. (2) The analog section of DAC is initialized after exiting power-down state. (3) Digital output corresponding to the analog inputs and analog outputs corresponding to the digital inputs have group delay (GD). (4) ADC output is “0” data at power-down state. (5) DAC output is Hi-Z in power-down state. (6) Click noise occurs at the end of initialization of the analog part. Mute the digital output externally. (7) Click noise occurs at 45/fs after PMDAC bit becomes “0”, and occurs at 519520/fs after PMDAC bit becomes “1”. (8) Mute the analog output externally. (9) There is a delay, 4~5/fs from PMDAC bit becomes “0” to the applicable ADC power-down. There is a delay, 4~5/fs from PMDAC bit becomes “0” to the applicable DAC power-down. (10) There is a delay, 3~4/fs from PMADC and PMDAC bit become “1” to the start of initial cycle. Figure 39. Bit power-down/Bit power-up sequence example MS1582-E-00 2013/11 - 44 - [AK4617] ■ Reset Function When RSTN bit= “0”, the analog and digital part of ADC and DACs are powered-down, but the internal register are not initialized. The analog outputs go to Hi-Z, the SDTO pin goes to “L”. As some click noise occurs, the analog output should be muted externally if the click noise influences system application. Figure 40 shows the power-up sequence. RSTN bit 4~5/fs (8) 3~4/fs (9) Internal RSTN bit (1) ADC Internal State Normal Operation DAC Internal State Normal Operation Power-down Normal Operation Init Cycle (2) Digital Block Power-down Init Cycle Normal Operation GD (3) GD ADC In (Analog) ADC Out (Digital) “0”data DAC In (Digital) (4) (5) “0”data (3) GD DAC Out (Analog) Clock In MCLK,LRCK,BICK GD (7) (7) (6) (7) Don’t care Notes: (1) The analog section of the ADC is initialized after exiting reset state. The initializing cycle is 1056fs. When start-up the AK4617, ADC input voltage should be operating common voltage. (2) The analog section of DAC is initialized after exiting exiting reset state. (3) Digital output corresponding to the analog inputs, and analog outputs corresponding to the digital inputs have group delay (GD). (4) ADC output is “0” data at power-down state. (5) Click noise occurs when the initializing cycle is finished. Mute the digital output externally. (6) The analog outputs go to Hi-Z when RSTN bit becomes “0”. (7) Click noise occurs at 45/fs after RSTN bit becomes “0”, and it occurs at 34/fs after RSTN bit becomes “1”. (8) There is a delay, 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”. (9) There is a delay, 3~4/fs from RSTN bit “1” to the start of initial cycle. Figure 40. Reset Sequence Example MS1582-E-00 2013/11 - 45 - [AK4617] ■ DAC Partial Power-Down Function All of the DACs can be powered-down individually by PMDA6-1 bit. The analog section and the digital section of the DAC are placed in power-down mode when the PMDA6-1 bit = “0”. The analog output of the powered-down channels, which are set by PMDA6-1 bit, go to Hi-Z. Some click noise occurs in both set-up and release of power-down. Mute the analog output externally or set PMDA6-1 bit when PMDAC bit = “0” or RSTN bit = “0”. Figure 41 shows the sequence of the power-down and the power-up by PMDA6-1 bit. PMDA6-1 bit 4~5/fs (4) Power Down Channel DAC Digital Internal State Normal Operation 2~3/fs (5) Power-down 2~3/fs (5) 4~5/fs (4) Power-down Normal Operation 516/fs (6) DAC Analog Internal State Normal Operation Power-down DAC In (Digital) Init Cycle Normal Operation 516/fs (6) Normal Operation Power-down Init Cycle Normal Operation “0”data (1) GD GD (3) (2) DAC Out (Analog) (3) (3) (2) (3) Normal Operation Channel DAC In (Digital) “0”data GD GD DAC Out (Analog) Notes: (1) Analog outputs corresponding to the digital inputs have group delay (GD). (2) Analog output of the DAC is powered down by PMDA6-1 = “0” and goes to Hi-Z. (3) Click noise occurs in 45/fs after PMDA6-1 bit are set to “0”, and it occurs in 518519/fs after PMDA6-1 bit are set to “1”. (4) The DACs will be powered-down 4~5fs after PMDA6-1 bit = “0” (5) The initialization stars 2~3fs after PMDA6-1 bit are set to “1”. (6) The analog parts of DACs are initialized after exiting power down mode. Figure 41. DAC Partial Power-down Example MS1582-E-00 2013/11 - 46 - [AK4617] ■ Parallel Mode The AK4617 can be in parallel mode which does not use internal registers by setting the SPI pin = “L” and PS pin= “H”. The parallel mode operation is set by the MS, TDM0, and DIF pins. The AK4617 cannot be changed to Serial mode from parallel mode during operation. MS pin 0 0 1 1 0 0 1 1 TDM0 pin 0 0 0 0 1 1 1 1 DIF pin 0 1 0 1 0 1 0 1 Mode Mode3 (Table 10) Mode4 (Table 10) Mode8 (Table 10) Mode9 (Table 10) Mode13 (Table 11) Mode14 (Table 11) Mode18 (Table 11) Mode19 (Table 11) MS, TDM0, DIF2/1/0 00011 00100 10011 10100 01011 01100 11011 11100 ■ Serial Control Interface The AK4617’s functions are controlled through registers or pins. The registers may be written by two types of control modes. The chip address is determined by the state of the CAD1 input. The PDN pin = “L” initializes the registers to their default values. Writing “0” to the RSTN bit can initialize the internal timing circuit, but the register data will not be initialized. *When the PDN pin = “L”, control register writings are not valid. (1) 3-wire Serial Control Mode (SPI pin = “H”) The internal registers may be written through the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface consists of a 2-bit Chip address, Read/Write (1bit, Fixed to “1”, Write only), Register address (MSB first, 5-bit) and Control data (MSB first, 8-bit). The chip address high bit is set by the CAD1 pin and the lower bit is fixed to “0”. Address and data are clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched after a low-to-high transition of CSN. The clock speed of CCLK is 5MHz(max). * The AK4617 does not support read commands in 3wire serial control mode. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: Chip Address (C1=CAD1 pin, C0= “L”) R/W: Read/Write (Fixed to “1”, Write only) A4-A0: Register Address D7-D0: Control Data Figure 42. 3-wire Serial Control I/F Timing MS1582-E-00 2013/11 - 47 - [AK4617] (2) I2C-bus Control Mode (SPI pin = “L”, PS pin =”L”) The AK4617 supports the fast-mode I2C-bus (max: 400kHz). 1. WRITE Operations Figure 43 shows the data transfer sequence of the I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 49). After the START condition, a slave address is sent. This address is 7-bit long followed by the eighth bit that is a data direction bit (R/W). The most significant seven bit of the slave address are fixed as “00100”. The next bit is CAD1 (device address bit). This bit identifies the specific device on the bus. The hard-wired input pin (CAD1 pin) sets these device address bit (Figure 44). If the slave address matches that of the AK4617, the AK4617 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 50). R/W bit = “1” indicates that the read operation is to be executed. “0” indicates that the write operation is to be executed. The second byte consists of the control register address of the AK4617. The format is MSB first, and those most significant 3-bit are fixed to zeros (Figure 45). The data after the second byte contains control data. The format is MSB first, 8-bit (Figure 46). The AK4617 generates an acknowledge after each byte is received. Data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines STOP condition (Figure 49). The AK4617 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4617 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 13H prior to generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 51) except for the START and STOP conditions. S T A R T SDA S T O P R/W="0" Slave S Address Sub Address(n) A C K Data(n) A C K Data(n+1) A C K Data(n+x) A C K A C K P A C K Figure 43. Data Transfer Sequence at the I2C-Bus Mode 0 0 1 0 0 CAD1 0 R/W A1 A0 D1 D0 (That CAD1 should match with CAD1 pin) Figure 44. The First Byte 0 0 0 A4 A3 A2 Figure 45. The Second Byte D7 D6 D5 D4 D3 D2 Figure 46. Byte Structure after the second byte MS1582-E-00 2013/11 - 48 - [AK4617] 2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4617. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 0EH prior to generating stop condition, the address counter will “roll over” to 00H and the data of 13H will be read out. The AK4617 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ. 2-1. CURRENT ADDRESS READ The AK4617 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address “n”, the next CURRENT READ operation would access data from the address “n+1”. After receipt of the slave address with R/W bit “1”, the AK4617 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the AK4617 ceases transmission. S T A R T SDA S T O P R/W="1" Slave S Address Data(n) Data(n+1) MA AC SK T E R A C K Data(n+2) MA AC SK T E R Data(n+x) MA AC SK T E R MA AC SK T E R P MN AA SC T EK R Figure 47. CURRENT ADDRESS READ 2-2. RANDOM ADDRESS READ The random read operation allows the master to access any memory location at random. Prior to issuing a slave address with the R/W bit =“1”, the master must execute a “dummy” write operation first. The master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit =“1”. The AK4617 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the AK4617 ceases transmission. S T A R T SDA S T A R T R/W="0" Slave S Address Sub Address(n) A C K Slave S Address A C K S T O P R/W="1" Data(n) A C K Data(n+1) MA AC S K T E R Data(n+x) MA AC S T K E R MA AC S T K E R P MN A A S T C E K R Figure 48. RANDOM ADDRESS READ MS1582-E-00 2013/11 - 49 - [AK4617] SDA SCL S P start condition stop condition Figure 49. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 50. Acknowledge on the I2C-Bus SDA SCL data line stable; data valid change of data allowed Figure 51. Bit Transfer on the I2C-Bus MS1582-E-00 2013/11 - 50 - [AK4617] ■ Register Map Add 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H Register Name Power Management 1 Power Management 2 System Clock Filter setting1 Filter setting2 Audio Interface Format Soft Mute DAC1L Volume DAC1R Volume DAC2L Volume DAC2R Volume DAC3L Volume DAC3R Volume DAC4L Volume DAC4R Volume DAC5L Volume DAC5R Volume DAC6L Volume DAC6R Volume Input Selector D7 0 0 CKS1 DEM41 SLOW 0 0 D6 0 0 CKS0 DEM40 SD_DA 0 0 D5 PMADC PMDA6 DFS1 DEM31 0 TDM1 DAATS1 D4 PMDAC PMDA5 DFS0 DEM30 SD_AD TDM0 DAATS0 D3 0 PMDA4 0 DEM21 DEM61 0 0 D2 0 PMDA3 0 DEM20 DEM60 DIF2 0 D1 MS PMDA2 0 DEM11 DEM51 DIF1 0 D0 RSTN PMDA1 ACKS DEM10 DEM50 DIF0 SMUTEN DAATL17 DAATR17 DAATL27 DAATR27 DAATL37 DAATR37 DAATL47 DAATR47 DAATL57 DAATR67 DAATL67 DAATR67 DAATL16 DAATR16 DAATL26 DAATR26 DAATL36 DAATR36 DAATL46 DAATR56 DAATL56 DAATR66 DAATL66 DAATR66 DAATL15 DAATR15 DAATL25 DAATR25 DAATL35 DAATR35 DAATL45 DAATR45 DAATL55 DAATR55 DAATL65 DAATR65 DAATL14 DAATR14 DAATL24 DAATR24 DAATL34 DAATR34 DAATL44 DAATR44 DAATL54 DAATR54 DAATL64 DAATR64 DAATL13 DAATR13 DAATL23 DAATR23 DAATL33 DAATR33 DAATL43 DAATR43 DAATL53 DAATR53 DAATL63 DAATR63 DAATL12 DAATR12 DAATL22 DAATR22 DAATL32 DAATR32 DAATL42 DAATR42 DAATL52 DAATR52 DAATL62 DAATR62 DAATL11 DAATR11 DAATL21 DAATR21 DAATL31 DAATR31 DAATL41 DAATR41 DAATL51 DAATR51 DAATL61 DAATR61 DAATL10 DAATR10 DAATL20 DAATR20 DAATL30 DAATR30 DAATL40 DAATR40 DAATL50 DAATR50 DAATL60 DAATR60 0 0 0 0 0 0 DIE2 DIE1 Note: For addresses from 14H to 1FH, data must not be written. The bit defined as 0 must contain a “0” value. When the PDN pin goes to “L”, the registers are initialized to their default values. When RSTN bit goes to “0”, the internal timing is reset, but registers are not initialized to their default values. MS1582-E-00 2013/11 - 51 - [AK4617] ■ Register Definitions Addr 00H Register Name Power Management 1 R/W Default D7 0 RD 0 D6 0 RD 0 D5 PMADC R/W 1 D4 PMDAC R/W 1 D3 0 RD 0 D2 0 RD 0 D1 MS R/W 0 D0 RSTN R/W 1 RSTN: Internal timing reset 0: Reset. 1: Normal operation (default) MS: Master Mode Select 0: Slave Mode (default) 1: Master Mode PMDAC: Power management of DAC1-6 0: All DAC’s Power-down. PMDA1-6 bit are invalid. 1: Normal operation. (default) PMDA1-6 bit are valid. PMADC: Power management of mono-stereo 0: All ADC’s Power-down. 1: Normal operation. (default) Addr 01H Register Name D7 D6 D5 D4 D3 D2 D1 D0 Power Management 3 0 RD 0 RD PMDA6 PMDA5 PMDA4 PMDA3 PMDA2 PMDA1 0 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 D1 0 RD 0 D0 ACKS R/W 0 R/W Default PMDA6-1: Power management of DAC1-6 (0: Power-down, 1: Normal operation) PMDA1: Power management control of DAC1 PMDA2: Power management control of DAC2 PMDA3: Power management control of DAC3 PMDA4: Power management control of DAC4 PMDA5: Power management control of DAC5 PMDA6: Power management control of DAC6 Addr 02H Register Name System Clock R/W Default D7 CKS1 R/W 1 D6 CKS0 R/W 0 D5 DFS1 R/W 0 D4 DFS0 R/W 0 D3 0 RD 0 D2 0 RD 0 ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS are ignored. When this bit is “0”, DFS0, 1 set the sampling speed mode. DFS1-0: Sampling speed mode (Table 1) The setting of DFS is ignored at ACKS bit =“1”. CKS1-0: Master Clock Input Frequency Select (Table 2) MS1582-E-00 2013/11 - 52 - [AK4617] Addr 03H Register Name Filter setting1 R/W Default D7 DEM41 R/W 0 D6 DEM40 R/W 1 D5 DEM31 R/W 0 D4 DEM30 R/W 1 D3 DEM21 R/W 0 D2 DEM20 R/W 1 D1 DEM11 R/W 0 D0 DEM10 R/W 1 D1 DEM51 R/W 0 D0 DEM50 R/W 1 DEM11-10: De-emphasis response control for DAC1 data on SDTI1 (Table 8) Initial: “01”, OFF DEM21-20: De-emphasis response control for DAC2 data on SDTI2 (Table 8) Initial: “01”, OFF DEM31-30: De-emphasis response control for DAC3 data on SDTI3 (Table 8) Initial: “01”, OFF DEM41-40: De-emphasis response control for DAC4 data on SDTI4 (Table 8) Initial: “01”, OFF Addr 04H Register Name Filter setting2 R/W Default D7 SLOW R/W 0 D6 SD_DA R/W 1 D5 0 RD 0 D4 SD_AD R/W 1 D3 DEM61 R/W 0 D2 DEM60 R/W 1 DEM51-50: De-emphasis response control for DAC5 data on SDTI5 (Table 8) Initial: “01”, OFF DEM61-60: De-emphasis response control for DAC6 data on SDTI6 (Table 8) Initial: “01”, OFF SD_AD: Digital filter Setting for ADC 0: Sharp roll off filter 1: Short delay Sharp roll off filter (default) SD_DA: Digital filter Setting for DAC 0: Sharp roll off filter or Slow roll off filter 1: Short delay Sharp roll off filter or Short delay Slow roll off filter (default) SLOW: Slow Roll-off Filter Enable for DAC 0: Sharp Roll-off Filter (default) 1: Slow Roll-off Filter SD_DA bit 0 0 1 1 SLOW bit Mode 0 Sharp roll-off filter 1 Slow roll-off filter 0 Short delay Sharp roll-off filter 1 Short delay Slow roll-off filter Table 16 Digital Filter setting for DAC MS1582-E-00 (default) 2013/11 - 53 - [AK4617] Addr 05H Register Name Audio Interface Format R/W Default D7 0 RD 0 D6 0 RD 0 D5 TDM1 R/W 0 D4 TDM0 R/W 0 D3 0 RD 0 D2 DIF2 R/W 1 D1 DIF1 R/W 0 D0 DIF0 R/W 0 DIF2-0: Audio Data Interface Modes (Table 10, Table 11, Table 12, Table 13) Initial: “100”, mode 4 TDM1-0: TDM Format Select (Table 10, Table 11, Table 12, Table 13) Mode TDM1 TDM0 0 0 0 1 0 1 2 1 0 3 1 1 Addr 06H Register Name Soft Mute R/W Default SDTI 1-6 1 1-2 1-3 D7 0 RD 0 Sampling Speed Stereo mode (Normal, Double, Quad Speed Mode) TDM512 mode (Normal Speed Mode) TDM256 mode (Normal, Double Speed Mode) TDM128 mode (Quad Speed Mode) D6 0 RD 0 D5 DAATS1 R/W 0 D4 DAATS0 R/W 0 D3 0 RD 0 D2 0 RD 0 D1 0 RD 0 D0 SMUTEN R/W 1 SMUTEN: Soft Mute Enable SMUTEN pin SMUTEN bit All Analog Outputs Status 0 Mute 1 Mute 0 Mute 1 Unmute Table 17. Soft Mute Control L H (default) (default) DAATS1-0: DAC Digital attenuator transition time setting (Table 15) Initial: “00”, mode 0 Add 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H Register Name DAC1L Volume DAC1R Volume DAC2L Volume DAC2R Volume DAC3L Volume DAC3R Volume DAC4L Volume DAC4R Volume DAC5L Volume DAC5R Volume DAC6L Volume DAC6R Volume R/W Default D7 D6 D5 D4 D3 D2 D1 D0 DAATL17 DAATR17 DAATL27 DAATR27 DAATL37 DAATR37 DAATL47 DAATR47 DAATL57 DAATR67 DAATL67 DAATR67 DAATL16 DAATR16 DAATL26 DAATR26 DAATL36 DAATR36 DAATL46 DAATR56 DAATL56 DAATR66 DAATL66 DAATR66 DAATL15 DAATR15 DAATL25 DAATR25 DAATL35 DAATR35 DAATL45 DAATR45 DAATL55 DAATR55 DAATL65 DAATR65 DAATL14 DAATR14 DAATL24 DAATR24 DAATL34 DAATR34 DAATL44 DAATR44 DAATL54 DAATR54 DAATL64 DAATR64 DAATL13 DAATR13 DAATL23 DAATR23 DAATL33 DAATR33 DAATL43 DAATR43 DAATL53 DAATR53 DAATL63 DAATR63 DAATL12 DAATR12 DAATL22 DAATR22 DAATL32 DAATR32 DAATL42 DAATR42 DAATL52 DAATR52 DAATL62 DAATR62 DAATL11 DAATR11 DAATL21 DAATR21 DAATL31 DAATR31 DAATL41 DAATR41 DAATL51 DAATR51 DAATL61 DAATR61 DAATL10 DAATR10 DAATL20 DAATR20 DAATL30 DAATR30 DAATL40 DAATR40 DAATL50 DAATR50 DAATL60 DAATR60 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 DAATL1/R1 7-0, DAATL2/R2 7-0, DAATL3/R3 7-0, DAATL4/R4 7-0, DAATL5/R5 7-0, DAATL6/R6 7-0: Attenuation Level (Table 14) MS1582-E-00 2013/11 - 54 - [AK4617] Addr 13H Register Name Input Selector R/W Default D7 0 RD 0 D6 0 RD 0 D5 0 RD 0 D4 0 RD 0 D3 0 RD 0 D2 0 RD 0 D1 DIE2 R/W 0 D0 DIE1 R/W 0 DIE2-1: Single-ended/Differential Input Select 0: Single-ended input to the IN1/IN1P and IN2/IN2P pins. Leave the IN1N and IN2N pins open. (default) 1: Differential Input (IN1P/IN2P and IN1N/IN2N pins) MS1582-E-00 2013/11 - 55 - [AK4617] 16. Recommended External Circuits Figure 52, Figure 53 and Figure 54 show the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. 3-wire Serial Control Mode (SPI pin = “H”). Slave Mode (MS bit = “0”). Single-ended Input Mode (DIE2-1 bit = “00”) + 0.1u LOUT6 26 ROUT6 25 LOUT5 28 ROUT5 27 LOUT4 30 ROUT4 29 LOUT3 32 ROUT3 31 ROUT2 33 1u LOUT2 34 LOUT1 36 3.3V Analog ROUT1 35 *1 37 AVDD2 NC 24 38 VSS3 NC 23 39 SPI NC 22 NC 21 40 CAD1 VCOM 20 41 CSN AK4617 42 CDTI AVDD1 18 43 CCLK 44 SDTI6/TDMI 0.1u 1u DSP Digital Ground *2 12 PDN 11 SMUTEN 10 TST2 SDTO 9 + 1u 3.3V Digital 0.1u TVDD VSS1 8 7 TST1 5 REGO BICK 6 MCLK 4 IN1N 13 3 IN1/IN1P 14 48 SDTI2 LRCK 47 SDTI3 SDTI1 IN2N 15 2 IN2/IN2P 16 46 SDTI4 1 45 SDTI5 + 3.3V Analog NC 17 1u µP 1u VSS2 19 Analog Ground Figure 52. Typical Connection Diagram1 (SPI mode) *1: Refer to Figure 57. *2: Refer to Figure 55 and Figure 56. MS1582-E-00 2013/11 - 56 - [AK4617] 3-wire Serial Control Mode (SPI pin = “L”). Slave Mode (MS bit = “0”). Single-ended Input Mode (DIE2-1 bits = “00”) I2C Bus serial control mode (PS pin = “L”) + 0.1u LOUT6 26 ROUT6 25 LOUT5 28 ROUT5 27 LOUT4 30 ROUT4 29 LOUT3 32 ROUT3 31 ROUT2 33 1u LOUT2 34 LOUT1 36 3.3V Analog ROUT1 35 *1 37 AVDD2 NC 24 38 VSS3 NC 23 39 SPI NC 22 NC 21 40 CAD1 VCOM 20 41 PS AK4617 42 SDA AVDD1 18 43 SCL 44 SDTI6/TDMI 0.1u + 1u 3.3V Analog NC 17 IN2/IN2P 16 45 SDTI5 1u DSP Digital Ground 12 PDN 11 SMUTEN 10 TST2 SDTO 9 + *2 3.3V Digital 0.1u TVDD VSS1 8 7 TST1 5 REGO BICK 4 6 MCLK 3 IN1N 13 LRCK 48 SDTI2 SDTI1 IN1/IN1P 14 2 IN2N 15 47 SDTI3 1 46 SDTI4 1u µP 1u VSS2 19 Analog Ground Figure 53. Typical Connection Diagram2 (I2C mode) *1: Refer to Figure 57. *2: Refer to Figure 55 and Figure 56. MS1582-E-00 2013/11 - 57 - [AK4617] 3-wire Serial Control Mode (SPI pin = “L”). Slave Mode (MS pin = “L”). Single-ended Input Mode (DIE2-1 bits = “00”) Parallel Control Mode (PS pin = “H”) Normal I/F Format Mode (TDM pin = “L”) 24-bit I2S Mode (DIF pin = “H”) + 0.1u LOUT6 26 ROUT6 25 LOUT5 28 ROUT5 27 LOUT4 30 ROUT4 29 LOUT3 32 ROUT3 31 ROUT2 33 1u LOUT2 34 LOUT1 36 3.3V Analog ROUT1 35 *1 37 AVDD2 NC 24 38 VSS3 NC 23 39 SPI NC 22 NC 21 40 TDM0 VCOM 20 41 PS AK4617 42 DIF AVDD1 18 43 MS 44 SDTI6/TDMI 0.1u 1u DSP Digital Ground *2 12 PDN 11 SMUTEN 10 TST2 SDTO 9 + 1u 3.3V Digital 0.1u TVDD VSS1 8 7 TST1 5 REGO BICK 6 MCLK 4 IN1N 13 3 IN1/IN1P 14 48 SDTI2 LRCK 47 SDTI3 SDTI1 IN2N 15 2 IN2/IN2P 16 46 SDTI4 1 45 SDTI5 + 3.3V Analog NC 17 1u µP 1u VSS2 19 Analog Ground Figure 54. Typical Connection Diagram3 (Parallel mode) *1: Refer to Figure 57. *2: Refer to Figure 55 and Figure 56. MS1582-E-00 2013/11 - 58 - [AK4617] ■ Grounding and Power Supply Decoupling The AK4617 requires careful attention to power supply and grounding arrangements. AVDD1, AVDD2 and TVDD are usually supplied from analog supply in system. Alternatively if AVDD1, AVDD2 and TVDD are supplied separately, the power up sequence is not critical. VSS1 ~ 3 of the AK4617 must be connected to analog ground plane. System analog ground and digital ground should be wired separately and connected together as close as possible to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4617 as possible, with the small value ceramic capacitor being the nearest. ■ Voltage Reference VCOM is a signal ground of this chip and output the voltage AVDD1x1/2. A ceramic capacitor 1µF attached to the VCOM pin eliminates the effects of high frequency noise. This capacitor should be as close to the pin as possible. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK4617. ■ Analog Inputs The Stereo ADC supports single-ended input. The single-ended input signal range scales with the supply voltage and nominally 0.81xAVDD1 Vpp (typ). The differential input signal range between IN+ and IN scales with the supply voltage and nominally ±0.81xAVDD1 Vpp (typ). The power supply voltage range of the AK4617 is from VSS2 to AVDD1. The ADC output data format is 2’s complement. The internal HPF removes the DC offset. The AK4617 samples the analog inputs at 64fs (@ fs=48kHz). The digital filter removes noise above the stop band except for multiples of the sampling frequency of analog inputs. The AK4617 includes an anti-aliasing filter (RC filter) to attenuate a noise around the sampling frequency of analog inputs. ■ Analog Outputs The single-ended output signal range is nominally 0.76 x AVDD2 Vpp centered around the VCOM voltage. The DAC input data format is 2’s complement. The output voltage is a positive full scale for 7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal output is VCOM voltage for 000000H(@24bit). The internal analog filters remove most of the noise generated by the delta-sigma modulator of DAC beyond the audio passband, in single-ended input mode. There are no internal analog filters for differential output mode, therefore this noise should be removed by the external analog filters. The DAC outputs have DC offsets of a few millivolts to VCOM voltage. MS1582-E-00 2013/11 - 59 - [AK4617] ■ External Analog Inputs Circuit Analog In 2.67Vpp INP 1 AK4617 Analog In 2.67Vpp INN Figure 55. Input Buffer Circuit Example 2 (AC coupled differential input) (IN1P/IN1N, IN2P/IN2N pins) Analog In 2.67Vpp IN AK4617 Figure 56. Input Buffer Circuit Example 3 (AC coupled single-ended input) (IN1, IN2 pins) MS1582-E-00 2013/11 - 60 - [AK4617] ■ External Analog Outputs Circuit AK4617 AOUT Analog Out C=1F R=100k 2.51Vpp (typ) Figure 57. External Circuit Example (LOUT1-6, ROUT1-6 pins) Note: The cut-off frequency (fc) of HPF is determined by following equation. fc= 1/(2 × π × R × C) [Hz] Where the C is the external AC coupling capacitor and the R is load resistance. When C = 1μF and R = 100kΩ, then fs = 1.6Hz. MS1582-E-00 2013/11 - 61 - [AK4617] 17. Package 48pin LQFP(Unit: mm) 1.70Max 9.0 0.2 0.13 0.13 7.0 0.2 36 1.40 0.05 24 48 13 7.0 37 1 9.0 25 12 0.09 0.20 0.5 0.22 0.08 0.10 M 0° 10° S 0.10 S 0.30 ~ 0.75 ■ Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy resin, Halogen (Br, Cl) free Cu Solder (Pb free) plate MS1582-E-00 2013/11 - 62 - [AK4617] ■ Marking AK4617VQ XXXXXXX 1 1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK4617VQ 18. Revision History Date (Y/M/D) 13/11/12 Revision 00 Reason First Edition Page Contents MS1582-E-00 2013/11 - 63 - [AK4617] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. 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The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact, including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. Do not use Product for the above use unless specifically agreed by AKM in writing. 3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. Do not use or otherwise make available the Product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. The Products and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner whatsoever, any liability of AKM. 7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. MS1582-E-00 2013/11 - 64 -