FUJITSU SEMICONDUCTOR
DATA SHEET
DS704-00012-0v01-E
16-bit Proprietary Microcontroller
CMOS
2
F MC-16FX MB96630 Series
MB96F636/F637*
DESCRIPTION
MB96630 series is based on FUJITSU’s advanced 16FX architecture (16-bit with instruction pipeline for
RISC-like performance). The CPU uses the same instruction set as the established 16LX series - thus
allowing for easy migration of 16LX Software to the new 16FX products.
16FX improvements compared to the previous generation include significantly improved performance even at the same operation frequency, reduced power consumption and faster start-up time.
For high processing speed at optimized power consumption an internal PLL can be selected to supply the
CPU with up to 32MHz operation frequency from an external 4MHz resonator. The result is a minimum
instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power is
minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree
allows selecting suitable operation frequencies for peripheral resources independent of the CPU speed.
*: These devices are under development and specification is preliminary.
These products under development may change its specification without notice.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
For the information for microcontroller supports, see the following website.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2011.7
r2.0
MB96630 Series
FEATURES
z Technology
0.18μm CMOS
z CPU
2
F MC-16FX CPU
Optimized instruction set for controller applications
(bit, byte, word and long-word data types, 23 different addressing modes, barrel shift, variety of
pointers)
8-byte instruction execution queue
Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available
z System clock
On-chip PLL clock multiplier (×1 to ×8, ×1 when PLL stop)
4 MHz to 8 MHz external crystal oscillator clock
(maximum frequency when using ceramic resonator depends on Q-factor)
Up to 16 MHz external clock for devices with fast clock input feature
32.768 kHz subsystem quartz clock
100kHz/2MHz internal RC clock for quick and safe startup, oscillator stop detection, watchdog
Clock source selectable from mainclock oscillator, subclock oscillator and on-chip RC oscillator,
independently for CPU and 2 clock domains of peripherals
The subclock oscillator is enabled by the Boot ROM program controlled by a configuration marker after
a Power or External reset
Low Power Consumption - 13 operating modes (different Run, Sleep, Timer modes, Stop mode)
z On-chip voltage regulator
Internal voltage regulator supports reduced internal MCU voltage, offering low EMI and low power
consumption figures
z Low voltage reset
Reset is generated when supply voltage is below minimum
z Code Security
Protects Flash Memory content from unintended read-out
z DMA
Automatic transfer function independent of CPU, can be assigned freely to resources
z Interrupts
Fast Interrupt processing
8 programmable priority levels
Non-Maskable Interrupt (NMI)
2
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS704-00012-0v01-E
MB96630 Series
z CAN
Supports CAN protocol version 2.0 part A and B
ISO16845 certified
Bit rates up to 1 Mbit/s
32 message objects
Each message object has its own identifier mask
Programmable FIFO mode (concatenation of message objects)
Maskable interrupt
Disabled Automatic Retransmission mode for Time Triggered CAN applications
Programmable loop-back mode for self-test operation
z USART
Full duplex USARTs (SCI/LIN)
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
Extended support for LIN-Protocol to reduce interrupt load
z I2C
Up to 400 kbps
Master and Slave functionality, 7-bit and 10-bit addressing
z A/D converter
SAR-type
8/10-bit resolution
Signals interrupt on conversion end, single conversion mode, continuous conversion mode,
stop conversion mode, activation by software, external trigger, reload timers and PPGs
Range Comparator Function
Scan Disable Function
z Source Clock Timers
Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer)
z Hardware Watchdog Timer
Hardware watchdog timer is active after reset
Window function of Watchdog Timer is used to select the lower window limit of the watchdog interval
z Reload Timers
16-bit wide
1
2
3
4
5
6
Prescaler with 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 of peripheral clock frequency
Event count function
z Free Running Timers
Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4)
1
2
3
4
5
6
7
8
Prescaler with 1, 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 of peripheral clock frequency
z Input Capture Units
16-bit wide
Signals an interrupt upon external event
Rising edge, Falling edge or Both (rising&falling) edges sensitive
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
3
MB96630 Series
z Output Compare Units
16-bit wide
Signals an interrupt when a match with 16-bit I/O Timer occurs
A pair of compare registers can be used to generate an output signal
z Programmable Pulse Generator
16-bit down counter, cycle and duty setting registers
Can be used as 2 × 8-bit PPG
Interrupt at trigger, counter borrow and/or duty match
PWM operation and one-shot operation
Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock or of selected Reload
timer underflow as clock input
Can be triggered by software or reload timer
Can trigger ADC conversion
Timing point capture
Start delay
z Quadrature Position/Revolution Counter (QPRC)
Edge count mode, Phase count mode, Level count mode
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers with interrupt
Detection edge of the three external event input pins AIN, BIN and ZIN is configurable
z Real Time Clock
Operational on main oscillation (4MHz), sub oscillation (32kHz) or RC oscillation (100kHz/2MHz)
Capable to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration)
Read/write accessible second/minute/hour registers
Can signal interrupts every half second/second/minute/hour/day
Internal clock divider and prescaler provide exact 1s clock
z External Interrupts
Edge or Level sensitive
Interrupt mask and pending bit per channel
Each available CAN channel RX has an external interrupt for wake-up
Selected USART channels SIN have an external interrupt for wake-up
z Non Maskable Interrupt
Disabled after reset, can be enabled by Boot-ROM depending on ROM configuration block
Once enabled, can not be disabled other than by reset
High or Low level sensitive
Pin shared with external interrupt 0
z I/O Ports
Most of the external pins can be used as general purpose I/O
2
All push-pull outputs (except when used as I C SDA/SCL line)
Bit-wise programmable as input/output or peripheral signal
Bit-wise programmable input enable
One input level per GP-IO-pin (either Automotive or CMOS-Schmitt trigger)
Bit-wise programmable pull-up resistor
4
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS704-00012-0v01-E
MB96630 Series
z Built-in OCD (On Chip Debugger)
One-wire debug tool interface
Break function:
- Hardware break: 6 points (shared with code event)
- Software break: 4096 points
Event function
- Code event: 6 points (shared with hardware break)
- Data event: 6 points
- Event sequencer: 2 levels
Execution time measurement function
Trace function: 42 branches
Security function
z Flash Memory
Dual operation flash allowing reading of one Flash bank while programming or erasing the other bank
Command sequencer for automatic execution of programming algorithm and for supporting DMA for
programming of the Flash Memory
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Erase can be performed on each sector individually
Sector protection
Flash Security feature to protect the content of the Flash
Low voltage detection during Flash erase
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
5
MB96630 Series
PRODUCT LINEUP
Features
Product type
Subclock
Dual Operation Flash memory
256.5KB + 32KB
384.5KB + 32KB
MB96F63x
RAM
24KB
28KB
Package
DMA
USART
with automatic LIN-Header
transmisstion/reception
with 16 byte RX- and TX-FIFO
MB96F636
MB96F637
LQFP-80
FPT-80P-M21
4ch
5ch
LIN-USART 0/2/4/5/7
Yes (only 1ch)
LIN-USART 0
IC
No
2ch
10-bit A/D Converter
21ch
2
with Data Buffer
with Range Comparator
with Scan Disable
with ADC Pulse Detection
16-bit Free-Running Timer (FRT)
16-bit Input Capture Unit (ICU)
3ch
3ch
7ch
(1 channels for LIN-USART)
16-bit Output Compare Unit (OCU)
8/16-bit Programmable Pulse Generator
(PPG)
with Timing point capture
with Start delay
with Ramp
Quadrature position/revolution counter
(QPRC)
7ch
15ch (16-bit) / 20ch (8-bit)
Clock Calibration Unit (CAL)
Clock Output Function
2ch
1ch
15ch
1ch
1ch
62 (Dual clock mode)
64 (Single clock mode)
1ch
2ch
Low Voltage Reset
Yes
Hardware Watchdog Timer
On-chip RC-oscillator
On-chip Debugger
Yes
Yes
Yes
Notes:
RLT 0/1/6
Only RLT6 can be used as
PPG clock source.
FRT 0/1/2
ICU 0/1/4/5/6/7/9
ICU 9 for LIN-USART
OCU 0/1/2/3/4/6/7
(OCU 4 for FRT clear)
PPG 0 to 4/6 to 15
Yes
Yes
No
CAN Interface
I/O Ports
2
I C 0/1
AN 2 to 4/6 to 8/
10 to 12/15 to 17/20 to 28
No
Yes
Yes
No
16-bit Reload Timer (RLT)
External Interrupts (INTerrupt)
Non-Maskable Interrupt (NMI)
Real Time Clock (RTC)
Remark
Flash product
Subclock can be set by software
QPRC 0/1
CAN 0
32 Message Buffers
INT 0 to 13/15
Low voltage reset can be
disabled by software
All signals of the peripheral function in each product cannot be allocated by limiting the pins of
package. It is necessary to use the port relocate function of the General I/O port according to your
function use.
These devices are under development and specification is preliminary.
These products under development may change its specification without notice.
6
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS704-00012-0v01-E
MB96630 Series
BLOCK DIAGRAM
DEBUG I/F
CKOT0_R, CKOT1, CKOT1_R
CKOTX0, CKOTX1, CKOTX1_R
X0, X1
X0A, X1A
RSTX
MD
NMI
Interrupt
Controller
16FX
CPU
OCD
Flash
Memory A
Clock &
Mode Controller
16FX Core Bus (CLKB)
Peripheral
Bus Bridge
Watchdog
AVCC
AVSS
AVRH
AN2 to AN4, AN6 to AN8
AN10 to AN12, AN15 to AN17,
AN20 to AN28
ADTG
TIN0, TIN1
TOT0, TOT1
FRCK0, FRCK0_R
IN0, IN0_R, IN1_R
OUT0 to OUT3,
OUT0_R, OUT2_R
FRCK1
IN6, IN7,
IN4_R, IN5_R, IN7_R
OUT6, OUT7
FRCK2
INT0, INT4 to INT13, INT15
INT1_R to INT3_R,
INT6_R, INT7_R
I2C
2 ch.
Peripheral
Bus Bridge
Peripheral Bus 2 (CLKP2)
SDA0, SDA1
SCL0, SCL1
10-bit ADC
21 ch.
CAN
Interface
1 ch.
16-bit Reload
Timer
2 ch.
I/O Timer 0
FRT0
ICU 0/1
OCU 0/1/2/3
I/O Timer 1
FRT1
ICU 4/5/6/7
OCU 4/6/7
USART
5 ch.
Peripheral Bus 1 (CLKP1)
DMA
Controller
Boot ROM
TX0
Voltage
Regulator
VCC
VSS
C
RX0
SIN0, SIN2, SIN4, SIN5, SIN7, SIN5_R, SIN7_R
SOT0, SOT2, SOT4, SOT7, SOT5_R, SOT7_R
SCK0, SCK2, SCK4, SCK5_R. SCK7_R
PPG
15 ch.16-bit/
20 ch 8 bit
TTG0, TTG2 to TTG4, TTG6, TTG7, TTG12 to TTG14
RLT6
PPG6_B to PPG11_B, PPG14_B, PPG15_B
PPG0, PPG1, PPG3, PPG4, PPG6
PPG0_R to PPG2_R, PPG8_R to PPG13_R
AIN0, AIN1
QPRC
2 Ch
I/O Timer 2
FRT2
ICU 9
External
Interrupt
15ch
RAM
BIN0, BIN1
ZIN0, ZIN1
Real Time
Clock
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
WOT, WOT_R
7
MB96630 Series
PIN ASSIGNMENTS
Vss
Vss
DEBUG I/F
P17_0
MD
X0
X1
Vss
P04_1 / X1A *3
P04_0 / X0A *3
RSTX
P11_1 / PPG0_R
P11_2 / PPG1_R
P11_3 / PPG2_R
P11_6 / FRCK0_R / ZIN1
P11_7 / IN0_R / AIN1
P12_0 / IN1_R / BIN1
P12_3 / OUT2_R
P12_7 / INT1_R
P00_0 / INT3_R / FRCK2
Vcc
(Top view)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
40
61
Vcc
P00_3 / INT6_R / PPG8_B
62
39
P10_2 / SCK2 / PPG6 *1
P00_4 / INT7_R / PPG9_B
63
38
P10_1 / SOT2
P00_5 / IN6 / TTG2 / TTG6 / PPG10_B
64
37
P10_0 / SIN2 / INT11 / AN28 *1
P00_6 / IN7 / TTG3 / TTG7 / PPG11_B
65
36
P17_2 / PPG13_R
P01_1 / CKOT1 / OUT0 / SOT7
66
35
P17_1 / PPG12_R
P01_2 / CKOTX1 / OUT1 / INT15 / SIN7 *1
67
34
P09_3 / PPG11_R / AN27
P01_4 / SIN4 / INT8 *1
68
33
P09_2 / PPG10_R / AN26
P01_5 / SOT4
69
32
P09_1 / PPG9_R / AN25
P01_6 / SCK4 / TTG12 *1
70
31
P09_0 / PPG8_R / AN24
P01_7 / CKOTX1_R / INT9 / TTG13 / ZIN0 / SCK7_R *1
71
30
P08_7 / AN23 / PPG7_B
P02_0 / CKOT1_R / INT10 / TTG14 / AIN0 / SOT7_R
72
29
P08_6 / AN22 / PPG6_B
P02_2 / IN7_R / CKOT0_R / INT12 / BIN0 / SIN7_R *1
73
28
P08_5 / AN21 / OUT7
P02_5 / OUT0_R / INT13 / SIN5_R *1
74
27
P04_7 / SCL1 *2
P03_2 / PPG14_B / SOT5_R
75
26
P04_6 / SDA1 *2
P03_3 / PPG15_B / SCK5_R *1
76
25
P08_4 / AN20 / OUT6
P03_4 / RX0 / INT4 *1
77
24
P08_1 / AN17
P03_5 / TX0
78
23
P08_0 / AN16
P03_6 / INT0 / NMI
79
22
P05_7 / AN15
Vcc
80
21
P05_4 / AN12 / INT2_R / WOT_R
P05_3 / AN11 / OUT3
P05_2 / AN10 / OUT2
P05_0 / AN8
AVss
P13_5 / SOT0 / ADTG / INT7
AVRH
P13_4 / SIN0 / INT6 *1
10 11 12 13 14 15 16 17 18 19 20
AVcc
P13_3 / PPG1 / TOT0 / WOT
9
P06_7 / AN7 / TOT1 / IN5_R
P13_2 / PPG0 / TIN0 / FRCK1
8
P06_6 / AN6 / TIN1 / IN4_R
C
7
P06_4 / AN4 / IN0 / TTG0 / TTG4
6
P06_3 / AN3 / FRCK0
5
P06_2 / AN2 / INT5 / SIN5 *1
4
P04_5 / PPG4 / SCL0 *2
3
P04_4 / PPG3 / SDA0 *2
2
P13_6 / SCK0 / CKOTX0 *1
1
Vss
LQFP - 80
(FPT-80P-M21)
*1: CMOS input level only
2
*2: CMOS input level only for I C
*3: Please set Rom Configuration Block (RCB) to use the subclock.
All other general-purpose pins have only Automotive input level.
8
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS704-00012-0v01-E
MB96630 Series
PIN FUNCTION DESCRIPTION
Pin name
Feature
Description
ADTG
AINn
ANn
AVcc
AVRH
AVss
BINn
C
CKOTn
CKOTn_R
CKOTXn
CKOTXn_R
FRCKn
FRCKn_R
INn
INn_R
INTn
INTn_R
MD
NMI
Pnn_m
OUTn
OUTn_R
PPGn
PPGn_R
PPGn_B
RSTX
RXn
SCKn
SCKn_R
SCLn
SDAn
SINn
SINn_R
SOTn
SOTn_R
TINn
TOTn
TTGn
TXn
Vcc
Vss
WOT
WOT_R
ADC
QPRC
ADC
Supply
ADC
Supply
QPRC
Voltage regulator
Clock output function
Clock output function
Clock output function
Clock output function
Free Running Timer
Free Running Timer
ICU
ICU
External Interrupt
External Interrupt
Core
External Interrupt
GPIO
OCU
OCU
PPG
PPG
PPG
Core
CAN
USART
USART
2
IC
2
IC
USART
USART
USART
USART
Reload Timer
Reload Timer
PPG
CAN
Supply
Supply
RTC
RTC
A/D converter trigger input
Quadrature Position/Revolution Counter Unit n input
A/D converter channel n input
Analog circuits power supply
A/D converter high reference voltage input
Analog circuits power supply
Quadrature Position/Revolution Counter Unit n input
Internally regulated power supply stabilization capacitor pin
Clock Output function n output
Relocated Clock Output function n output
Clock Output function n inverted output
Relocated Clock Output function n inverted output
Free Running Timer n input
Relocated Free Running Timer n input
Input Capture Unit n input
Relocated Input Capture Unit n input
External Interrupt n input
Relocated External Interrupt n input
Input pin for specifying the operating mode
Non-Maskable Interrupt input
General purpose I/O
Output Compare Unit n waveform output
Relocated Output Compare Unit n waveform output
Programmable Pulse Generator n output (16bit/8bit)
Relocated Programmable Pulse Generator n output (16bit/8bit)
Programmable Pulse Generator n output (8bit)
Reset input
CAN interface n RX input
USART n serial clock input/output
Relocated USART n serial clock input/output
2
I C interface n clock I/O input/output
2
I C interface n serial data I/O input/output
USART n serial data input
Relocated USART n serial data input
USART n serial data output
Relocated USART n serial data output
Reload Timer n event input
Reload Timer n output
Programmable Pulse Generator n trigger input
CAN interface n TX output
Power supply
Power supply
Real Time clock output
Relocated Real Time clock output
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
9
MB96630 Series
Pin name
Feature
X0
X0A
X1
X1A
ZINn
DEBUG I/F
Clock
Clock
Clock
Clock
QPRC
OCD
Description
Oscillator input
Subclock Oscillator input
Oscillator output
Subclock Oscillator output
Quadrature Position/Revolution Counter Unit n input
On Chip Debugger input/output
10
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS704-00012-0v01-E
MB96630 Series
PIN CIRCUIT TYPE
Pin no.
I/O circuit type*
Pin name
1
Supply
Vss
2
F
C
3
H
P13_2 / PPG0 / TIN0 / FRCK1
4
H
P13_3 / PPG1 / TOT0 / WOT
5
M
P13_4 / SIN0 / INT6
6
H
P13_5 / SOT0 / ADTG / INT7
7
M
P13_6 / SCK0 / CKOTX0
8
9
N
N
P04_4 / PPG3 / SDA0
P04_5 / PPG4 / SCL0
10
I
P06_2 / AN2 / INT5 / SIN5
11
K
P06_3 / AN3 / FRCK0
12
K
P06_4 / AN4 / IN0 / TTG0 / TTG4
13
K
P06_6 / AN6 / TIN1 / IN4_R
14
K
P06_7 / AN7 / TOT1 / IN5_R
15
Supply
AVcc
16
G
AVRH
17
Supply
AVss
18
K
P05_0 / AN8
19
K
P05_2 / AN10 / OUT2
20
K
P05_3 / AN11 / OUT3
21
K
P05_4 / AN12 / INT2_R / WOT_R
22
K
P05_7 / AN15
23
K
P08_0 / AN16
24
K
P08_1 / AN17
25
K
P08_4 / AN20 / OUT6
26
N
P04_6 / SDA1
27
N
P04_7 / SCL1
28
K
P08_5 / AN21 / OUT7
29
K
P08_6 / AN22 / PPG6_B
30
K
P08_7 / AN23 / PPG7_B
31
K
P09_0 / AN24 / PPG8_R
32
K
P09_1 / AN25 / PPG9_R
33
K
P09_2 / AN26 / PPG10_R
34
K
P09_3 / AN27 / PPG11_R
35
H
P17_1 / PPG12_R
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
11
MB96630 Series
Pin no.
I/O circuit type*
Pin name
36
H
P17_2 / PPG13_R
37
I
P10_0 / SIN2 / AN28 / INT11
38
H
P10_1 / SOT2
39
M
P10_2 / SCK2 / PPG6
40
Supply
Vcc
41
Supply
Vss
42
O
DEBUG I / F
43
H
P17_0
44
C
MD
45
A
X0
46
A
X1
47
Supply
Vss
48
B
P04_0 / X0A
49
B
P04_1 / X1A
50
51
C
H
RSTX
P11_1 / PPG0_R
52
H
P11_2 / PPG1_R
53
H
P11_3 / PPG2_R
54
H
P11_6 / FRCK0_R / ZIN1
55
H
P11_7 / IN0_R / AIN1
56
H
P12_0 / IN1_R / BIN1
57
H
P12_3 / OUT2_R
58
H
P12_7 / INT1_R
59
H
P00_0 / INT3_R / FRCK2
60
Supply
Vcc
61
Supply
Vss
62
H
P00_3 / INT6_R / PPG8_B
63
H
P00_4 / INT7_R / PPG9_B
64
H
P00_5 / IN6 / TTG2 / TTG6 / PPG10_B
65
H
P00_6 / IN7 / TTG3 / TTG7 / PPG11_B
66
H
P01_1 / CKOT1 / OUT0 / SOT7
67
M
P01_2 / CKOTX1 / OUT1 / INT15 / SIN7
68
M
P01_4 / SIN4 / INT8
69
H
P01_5 / SOT4
70
M
P01_6 / SCK4 / TTG12
12
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS704-00012-0v01-E
MB96630 Series
Pin no.
I/O circuit type*
Pin name
71
M
P01_7 / CKOTX1_R / INT9 / TTG13 / ZIN0 / SCK7_R
72
H
P02_0 / CKOT1_R / INT10 / TTG14 / AIN0 / SOT7_R
73
M
P02_2 / IN7_R / CKOT0_R / INT12 / BIN0 / SIN7_R
74
M
P02_5 / OUT0_R / INT13 / SIN5_R
75
H
P03_2 / PPG14_B / SOT5_R
76
M
P03_3 / PPG15_B / SCK5_R
77
M
P03_4 / RX0 / INT4
78
H
P03_5 / TX0
79
H
P03_6 / INT0 / NMI
80
Supply
Vcc
*: Please refer to “
■ I/O CIRCUIT TYPE” for details on the I/O circuit types.
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
13
MB96630 Series
I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
X1
R
0
1
FCI
X0
FCI or osc disable
14
FUJITSU SEMICONDUCTOR CONFIDENTIAL
X out
High-speed oscillation circuit:
Programmable between
oscillation mode (external
crystal or resonator
connected to X0/X1 pins)
and Fast external Clock Input
(FCI) mode (external clock
connected to X0 pin)
Feedback resistor = approx.
1.0 MΩ. Feedback resistor is
grounded in the center when
the oscillator is disabled or in
FCI mode
The amplitude: 1.8V±0.15V
to operate by the internal
supply voltage
DS704-00012-0v01-E
MB96630 Series
Type
Circuit
Remarks
B
Pull-up control
P-ch
P-ch
N-ch
Standby
control
for input
shutdown
Pout
Nout
R
Low-speed oscillation circuit
shared with GPIO functionality:
Feedback resistor = approx.
5.0 MΩ. Feedback resistor is
grounded in the center when
the oscillator is disabled
GPIO functionality selectable
(CMOS hysteresis input with
input shutdown function,
IOL = 4mA, IOH = -4mA,
Programmable pull-up
resistor)
Hysteresis input
X1A
R
X out
0
1
FCI
X0A
FCI or Osc disable
Pull-up control
P-ch
Standby
control
for input
shutdown
P-ch
N-ch
Pout
Nout
R
Hysteresis input
C
CMOS hysteresis input pin
R
Hysteresis
inputs
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
15
MB96630 Series
Type
Circuit
Remarks
Power supply input
protection circuit
F
P-ch
N-ch
G
ANE
P-ch
AVR
N-ch
ANE
H
Pull-up control
P-ch
A/D converter ref+ (AVRH)
power supply input pin with
protection circuit
Without protection circuit
against VCC for pins AVRH
P-ch
N-ch
Pout
CMOS level output (IOL =
4mA, IOH = -4mA)
Automotive input with input
shutdown function
Programmable pull-up
resistor
Nout
R
Automotive input
Standby control
for input shutdown
I
Pull-up control
P-ch
P-ch
Pout
N-ch
Nout
R
CMOS level output (IOL =
4mA, IOH = -4mA)
CMOS hysteresis input with
input shutdown function
Programmable pull-up
resistor
Analog input
Hysteresis input
Standby control
for input shutdown
Analog input
16
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS704-00012-0v01-E
MB96630 Series
Type
Circuit
Remarks
K
Pull-up control
P-ch
P-ch
Pout
N-ch
CMOS level output (IOL =
4mA, IOH = -4mA)
Automotive input with input
shutdown function
Programmable pull-up
resistor
Analog input
Nout
R
Automotive input
Standby control
for input shutdown
Analog input
M
Pull-up control
P-ch
P-ch
N-ch
R
Pout
CMOS level output (IOL =
4mA, IOH = -4mA)
CMOS hysteresis input with
input shutdown function
Programmable pull-up
resistor
Nout
Hysteresis input
Standby control
for input shutdown
N
Pull-up control
P-ch
P-ch
N-ch
R
Pout
Nout*
CMOS level output (IOL =
3mA, IOH = -3mA)
CMOS hysteresis input with
input shutdown function
Programmable pull-up
resistor
*: N-channel transistor has slew
2
rate control according to I C
spec, irrespective of usage.
Hysteresis input
Standby control
for input shutdown
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
17
MB96630 Series
Type
Circuit
Remarks
O
IOL: 25mA @ 2.7V
TTL input
N-ch
Nout
R
Standby control
for input shutdown
18
FUJITSU SEMICONDUCTOR CONFIDENTIAL
TTL input
DS704-00012-0v01-E
MB96630 Series
MEMORY MAP
MB96F63x
FF:FFF F
H
USER ROM*1
DE:000 0
H
DD:FFF F
H
Reserved
10:000 0
H
0F:E000
0E:900 0
Boot-ROM
H
Peripheral
H
Reserved
01:000 0
00:800 0
H
ROM/RAM
MIRROR
H
RAMSTART0*
2
Internal RAM
bank0
Reserved
00:0C00
H
Peripheral
00:038 0
H
00:018 0
H
00:010 0
H
GPR*3
DMA
00:00F0
H
Reserved
00:000 0
H
Peripheral
*1: For details about USER ROM area, see the “ USER ROM MEMORY MAP FOR FLASH
DEVICES” on the following pages.
*2: For RAMSTART/END addresses, please refer to the table on the next page.
*3: Unused GPR banks can be used as RAM area.
The DMA area is only available if the device contains the corresponding resource.
The available RAM and ROM area depends on the device.
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
19
MB96630 Series
RAMSTART ADDRESSES
Devices
Bank 0
RAM size
RAMSTART0
MB96F636
24KByte
00:2200H
MB96F637
28KByte
00:1200H
20
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS704-00012-0v01-E
MB96630 Series
USER ROM MEMORY MAP FOR FLASH DEVICES
Alternative mode
CPU address
Flash memory
mode address
FF:FFFFH
3F:FFFFH
FF:0000H
FE:FFFFH
3F:0000H
3E:FFFFH
FE:0000H
FD:FFFFH
3E:0000H
3D:FFFFH
FD:0000H
FC:FFFFH
3D:0000H
3C:FFFFH
FC:0000H
FB:FFFFH
FB:0000H
FA:FFFFH
3C:0000H
3B:FFFFH
3B:0000H
3A:FFFFH
FA:0000H
3A:0000H
F9:FFFFH
39:FFFFH
MB96F636
Flash size
256.5KB + 32KB
MB96F637
Flash size
384.5KB + 32KB
SA39-64KB
SA39-64KB
SA38-64KB
SA38-64KB
SA37-64KB
SA37-64KB
SA36-64KB
SA36-64KB
Bank A of Flash A
SA35-64KB
SA34-64KB
Reserved
Reserved
DF:A000H
1F:A000H
DF:9FFFH
DF:8000H
DF:7FFFH
1F:9FFFH
1F:8000H
1F:7FFFH
DF:6000H
DF:5FFFH
1F:6000H
1F:5FFFH
DF:4000H
DF:3FFFH
1F:4000H
1F:3FFFH
DF:2000H
DF:1FFFH
DF:0000H
DE:FFFFH
DE:0000H
1F:2000H
1F:1FFFH
1F:0000H
1E:FFFFH
SA4-8KB
SA4-8KB
SA3-8KB
SA3-8KB
SA2-8KB
SA2-8KB
SA1-8KB
SA1-8KB
SAS-512B*
SAS-512B*
Reserved
Reserved
Bank B of Flash A
Bank A of Flash A
*: Phiysical address area of SAS-512B is from DF:0000H to DF:01FFH.
Others (from DF:0200H to DF:1FFFH) are all ROM Mirror area for SAS-512B.
Sector SAS contains the ROM configuration block RCBA at CPU address DF:0000H -DF:01FFH.
2
SAS can not be used for E PROM emulation.
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
21
MB96630 Series
SERIAL PROGRAMMING COMMUNICATION INTERFACE
USART pins for Flash serial programming (MD = 0, DEBUG I/F = 0, Serial Communication mode)
MB96F63x
Pin Number
USART Number
5
6
Normal Function
SIN0
USART0
SOT0
7
SCK0
37
SIN2
38
USART2
SOT2
39
SCK2
68
SIN4
69
USART4
70
22
FUJITSU SEMICONDUCTOR CONFIDENTIAL
SOT4
SCK4
DS704-00012-0v01-E
MB96630 Series
INTERRUPT VECTOR TABLE
Vector
number
Offset in
vector table
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
3FC
3F8
3F4
3F0
3EC
3E8
3E4
3E0
3DC
3D8
3D4
3D0
3CC
3C8
3C4
3C0
3BC
3B8
3B4
3B0
3AC
3A8
3A4
3A0
39C
398
394
390
38C
388
384
380
37C
378
374
370
36C
368
364
360
35C
Vector name
Cleared by
DMA
Index in
ICR to
program
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
CALLV0
CALLV1
CALLV2
CALLV3
CALLV4
CALLV5
CALLV6
CALLV7
RESET
INT9
EXCEPTION
NMI
DLY
RC_TIMER
MC_TIMER
SC_TIMER
LVDI
EXTINT0
EXTINT1
EXTINT2
EXTINT3
EXTINT4
EXTINT5
EXTINT6
EXTINT7
EXTINT8
EXTINT9
EXTINT10
EXTINT11
EXTINT12
EXTINT13
EXTINT15
CAN0
PPG0
PPG1
PPG2
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Non-Maskable Interrupt
Delayed Interrupt
RC clock timer
Main Clock Timer
Sub Clock Timer
Low Voltage Detector
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
External Interrupt 7
External Interrupt 8
External Interrupt 9
External Interrupt 10
External Interrupt 11
External Interrupt 12
External Interrupt 13
Reserved
External Interrupt 15
CAN Controller 0
Reserved
Reserved
Reserved
Reserved
Programmable Pulse Generator 0
Programmable Pulse Generator 1
Programmable Pulse Generator 2
23
MB96630 Series
Vector
number
Offset in
vector table
Vector name
Cleared by
DMA
Index in
ICR to
program
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
358
354
350
34C
348
344
340
33C
338
334
330
32C
328
324
320
31C
318
314
310
30C
308
304
300
PPG3
PPG4
PPG6
PPG7
PPG8
PPG9
PPG10
PPG11
PPG12
PPG13
PPG14
PPG15
RLT0
RLT1
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
2FC
PPGRLT
Yes
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
2F8
2F4
2F0
2EC
2E8
2E4
2E0
2DC
2D8
2D4
2D0
2CC
2C8
2C4
2C0
2BC
ICU0
ICU1
ICU4
ICU5
ICU6
ICU7
ICU9
OCU0
OCU1
OCU2
OCU3
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
24
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Description
Programmable Pulse Generator 3
Programmable Pulse Generator 4
Reserved
Programmable Pulse Generator 6
Programmable Pulse Generator 7
Programmable Pulse Generator 8
Programmable Pulse Generator 9
Programmable Pulse Generator 10
Programmable Pulse Generator 11
Programmable Pulse Generator 12
Programmable Pulse Generator 13
Programmable Pulse Generator 14
Programmable Pulse Generator 15
Reserved
Reserved
Reserved
Reserved
Reload Timer 0
Reload Timer 1
Reserved
Reserved
Reserved
Reserved
Reload Timer 6 can be used as
PPG clock source
Input Capture Unit 0
Input Capture Unit 1
Reserved
Reserved
Input Capture Unit 4
Input Capture Unit 5
Input Capture Unit 6
Input Capture Unit 7
Reserved
Input Capture Unit 9
Reserved
Reserved
Output Compare Unit 0
Output Compare Unit 1
Output Compare Unit 2
Output Compare Unit 3
DS704-00012-0v01-E
MB96630 Series
Vector
number
Offset in
vector table
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
2B8
2B4
2B0
2AC
2A8
2A4
2A0
29C
298
294
290
28C
288
284
280
27C
278
274
270
26C
268
264
260
25C
258
254
250
24C
248
244
240
23C
238
234
230
22C
228
224
220
21C
Vector name
Cleared by
DMA
Index in
ICR to
program
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
OCU4
OCU6
OCU7
FRT0
FRT1
FRT2
RTC0
CAL0
IIC0
IIC1
ADC0
LINR0
LINT0
LINR2
LINT2
LINR4
LINT4
LINR5
LINT5
LINR7
LINT7
-
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Description
Output Compare Unit 4
Reserved
Output Compare Unit 6
Output Compare Unit 7
Reserved
Reserved
Reserved
Reserved
Free Running Timer 0
Free Running Timer 1
Free Running Timer 2
Reserved
Real Time Clock
Clock Calibration Unit
Reserved
I2C interface0
I2C interface1
A/D Converter
Reserved
Reserved
LIN USART 0 RX
LIN USART 0 TX
Reserved
Reserved
LIN USART 2 RX
LIN USART 2 TX
Reserved
Reserved
LIN USART 4 RX
LIN USART 4 TX
LIN USART 5 RX
LIN USART 5 TX
Reserved
Reserved
LIN USART 7 RX
LIN USART 7 TX
Reserved
Reserved
Reserved
Reserved
25
MB96630 Series
Vector
number
Offset in
vector table
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
218
214
210
20C
208
204
200
1FC
1F8
1F4
1F0
1EC
1E8
1E4
1E0
1DC
1D8
1D4
1D0
1CC
1C8
1C4
1C0
Vector name
Cleared by
DMA
Index in
ICR to
program
Yes
Yes
Yes
No
-
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
FLASHA
QPRC0
QPRC1
ADCRC0
-
26
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Flash memory A interrupt
Reserved
Reserved
Reserved
Quad Possition/Revolution counter 0
Quad Possition/Revolution counter 1
A/D Converter 0 - Range Comparator
Reserved
Reserved
Reserved
Reserved
DS704-00012-0v01-E
MB96630 Series
HANDLING DEVICES
Special care is required for the following when handling the device:
• Latch-up prevention
• Unused pins handling
• External clock usage
• Notes on PLL clock mode operation
• Power supply pins (VCC/VSS)
• Crystal oscillator circuit
• Turn on sequence of power supply to A/D converter and analog inputs
• Pin handling when not using the A/D converter
• Notes on Power-on
• Stabilization of power supply voltage
• Serial communication
1. Latch-up prevention
CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC pins and VSS pins.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current dramatically, causing thermal damages to the device.
For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed
the digital power-supply voltage.
2. Unused pins handling
Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register
PIER = 0).
Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent
damage of the device. They must therefore be pulled up or pulled down through resistors. To prevent latch-up,
those resistors should be more than 2 kΩ.
Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with
either input disabled or external pull-up/pull-down resistor as described above.
3. External clock usage
The permitted frequency range of an external clock depends on the oscillator type and configuration.
See AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must
be connected as follows:
1. Single phase external clock for Main oscillator
• When using a single phase external clock for the Main oscillator, X0 pin must be driven and X1 pin left
open. And supply 1.8V power to the external clock.
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
27
MB96630 Series
2. Single phase external clock for Sub oscillator
• When using a single phase external clock for the Sub oscillator, ‘External clock mode’ must be selected and
X0A/GP04_0 must be driven. X1A/GP04_1 must be configured as GPIO.
4. Notes on PLL clock mode operation
If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the
microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot
be guaranteed.
5. Power supply pins (VCC/VSS)
It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is
more than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed
operating range.
VCC and VSS must be connected to the device from the power supply with lowest possible impedance.
As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 μF between
Vcc and Vss as close as possible to Vcc and Vss pins.
6. Crystal oscillator and ceramic resonator circuit
Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass
capacitors with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic
resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of
other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A
pins with a ground area for stabilizing the operation.
It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator
manufacturer, especially when using low-Q resonators at higher frequencies.
7. Turn on sequence of power supply to A/D converter and analog inputs
It is required to turn the A/D converter power supply (AVCC, AVRH) and analog inputs (ANn) on after turning
the digital power supply (VCC) on.
It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In
this case, the voltage must not exceed AVRH or AVCC (turning the analog and digital power supplies
simultaneously on or off is acceptable).
8. Pin handling when not using the A/D converter
It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = VSS.
9. Notes on Power-on
To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply
on should be slower than 50μs from 0.2V to 2.7V.
10. Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply
voltage, a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization
guidelines, the power supply voltage must be stabilized in such a way that Vcc ripple fluctuations (peak to peak
value) in the commercial frequencies (50 Hz to 60 Hz) fall within 10% of the standard Vcc power supply voltage
and the transient fluctuation rate becomes 0.1V/μs or less in instantaneous fluctuation for power supply
switching.
28
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS704-00012-0v01-E
MB96630 Series
11. Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit
the data if an error occurs.
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
29
MB96630 Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Power supply voltage*1
Analog power supply
voltage*1
Analog reference
voltage*1
Input voltage*1
Output voltage*1
Maximum Clamp Current
Rating
Min
Max
Symbol
Condition
Unit
Vcc
-
Vss - 0.3
Vss + 6.0
V
AVcc
-
Vss - 0.3
Vss + 6.0
V
AVRH
-
Vss - 0.3
Vss + 6.0
V
VI
VO
-
Vss - 0.3
Vss - 0.3
Vss + 6.0
Vss + 6.0
V
V
ICLAMP
-
-4.0
+4.0
mA
Remarks
Vcc = AVcc*2
AVCC ≥ AVRH,
AVRH≥ AVSS
VI ≤ VCC + 0.3V*3
VO ≤ VCC + 0.3V*3
Applicable to general
purpose I/O pins *4
Applicable to general
purpose I/O pins *4
Total Maximum Clamp
21
mA
Σ|ICLAMP|
Current
"L" level maximum
IOL
15
mA
output current
"L" level average output
IOLAV
4
mA
current
"L" level maximum
52
mA
ΣIOL
overall output current
"L" level average overall
26
mA
ΣIOLAV
output current
"H" level maximum
IOH
-15
mA
output current
"H" level average output
IOHAV
-4
mA
current
"H" level maximum
-52
mA
ΣIOH
overall output current
"H" level average overall
-26
mA
ΣIOHAV
output current
Power consumption*5
PD
TA=+125°C
396 *6
mW
Operating ambient
*7
TA
-40
125
°C
temperature
Storage temperature
TSTG
-55
150
°C
*1: This parameter is based on VSS = AVSS = 0V.
*2: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the
voltage at the analog inputs does not exceed AVCC when the power is switched on.
*3: VI and VO should not exceed VCC + 0.3 V. VI should also not exceed the specified ratings. However if the
maximum current to/from an input is limited by some means with external components, the ICLAMP rating
supersedes the VI rating. Input/output voltages of standard ports depend on VCC.
30
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS704-00012-0v01-E
MB96630 Series
*4: • Applicable to all general purpose I/O pins (Pnn_m).
• Use within recommended operating conditions.
• Use at DC voltage (current).
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may
affect other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +Binput is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the Power reset (except devices with persistent low
voltage reset in internal vector mode).
• Sample recommended circuits:
Protective diode
VCC
P-ch
Limiting
resistance
+B input (0 V to 16 V)
N-ch
R
*5: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the
thermal conductance of the package on the PCB.
The actual power dissipation depends on the customer application and can be calculated as follows:
PD = PIO + PINT
PIO = Σ (VOL × IOL + VOH × IOH) (I/O load power dissipation, sum is performed on all I/O ports)
PINT = VCC × (ICC + IA) (internal power dissipation)
ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the
selected operation mode and clock frequency and the usage of functions like Flash programming.
IA is the analog current consumption into AVCC.
*6: Worst case value for a package mounted on single layer PCB at specified TA without air flow.
*7: Flash Memory Write/Erase to Large Sector is guaranteed under Ta≦105℃.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
31
MB96630 Series
2. Recommended Operating Conditions
(VSS = AVSS = 0V)
Parameter
Power supply
voltage
Smoothing
capacitor at C pin
Symbol
Vcc
CS
Min
Value
Typ
Max
2.7
-
5.5
0.5
1.0
1.5
Unit
Remarks
V
μF
(Target value)
1.0µF (Allowance within ± 50%)
Please use the ceramic capacitor or the
capacitor of the frequency response of
this level.
The smoothing capacitor at VCC must
use the one of a capacity value that is
larger than Cs.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
32
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS704-00012-0v01-E
MB96630 Series
3. DC Characteristics
1. Current rating of MB96F630
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Parameter
Pin
Symbol
name
Max
-
27
-
mA
-
-
37.5
mA
-
-
39
mA
-
3.5
-
mA
-
-
9
mA
-
-
10.5
mA
-
0.1
-
mA
-
-
6
mA
-
-
7.5
mA
PLL Sleep mode with
CLKS1/2 = CLKP1/2 =
32MHz
(CLKRC and CLKSC
stopped)
-
10
-
mA
-
-
15
mA
-
-
16.5
mA
Main Sleep mode with
CLKS1/2 = CLKP1/2 =
4MHz
(CLKPLL, CLKRC and
CLKSC stopped)
-
1.0
-
mA
-
-
7
mA
-
-
8.5
mA
Sub Sleep mode with
CLKS1/2 = CLKP1/2 =
32kHz,
(CLKMC, CLKPLL
and CLKRC stopped)
-
0.08
-
mA
-
-
4
mA
-
-
5.5
mA
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 32MHz
(CLKRC and CLKSC
stopped)
ICCPLL
Power supply
current in Run
modes*1
Min
Value
Typ
Conditions
Main Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 4MHz
(CLKPLL, CLKSC and
CLKRC stopped)
ICCMAIN
Sub Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 32kHz
(CLKMC, CLKPLL and
CLKRC stopped)
ICCSUB
Unit
Vcc
ICCSPLL
Power supply
current in
Sleep modes*1
ICCSMAIN
ICCSSUB
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Remarks
TA = +25°C
TA = +105°C
(Target value)
TA = +125°C
(Target value)
TA = +25°C
TA = +105°C
(Target value)
TA = +125°C
(Target value)
TA = +25°C
TA = +105°C
(Target value)
TA = +125°C
(Target value)
TA = +25°C
TA = +105°C
(Target value)
TA = +125°C
(Target value)
TA = +25°C
TA = +105°C
(Target value)
TA = +125°C
(Target value)
TA = +25°C
TA = +105°C
(Target value)
TA = +125°C
(Target value)
33
MB96630 Series
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Parameter
Symbol
Pin
name
Main Timer mode
with
CLKMC = 4MHz
(CLKPLL, CLKRC
and CLKSC stopped)
ICCTMAIN
Power supply
current in
Timer
modes*2
RC Timer mode
with
CLKRC = 2MHz
ICCTRCH
RC Timer mode
with
CLKRC = 100kHz
ICCTRCL
Vcc
ICCTSUB
Power supply
current in
Stop mode*3
ICCH
Conditions
Sub Timer mode
with
CLKSC = 32kHz
(CLKMC, CLKPLL
and CLKRC stopped)
-
Min
Value
Typ Max
Unit
Remarks
-
285
355
μA
TA = +25°C
-
-
1300
μA
TA = +105°C
(Target value)
-
-
2310
μA
TA = +125°C
(Target value)
-
160
245
μA
-
-
1215
μA
-
-
2215
μA
-
35
105
μA
-
-
1010
μA
-
-
2015
μA
-
25
90
μA
-
-
985
μA
-
-
1990
μA
-
20
90
μA
-
-
985
μA
-
-
1985
μA
TA = +25°C
TA = +105°C
(Target value)
TA = +125°C
(Target value)
TA = +25°C
TA = +105°C
(Target value)
TA = +125°C
(Target value)
TA = +25°C
TA = +105°C
(Target value)
TA = +125°C
(Target value)
TA = +25°C
TA = +105°C
(Target value)
TA = +125°C
(Target value)
Power supply
current
for active
Low voltage
5
15
μA
ICCLVD
Low
detector enabled
Voltage
detector*4
Flash Write/
Erase
12.5
20
mA
ICCFLASH
current*5
*1: The power supply current is measured with a 4MHz external clock connected to the Main oscillator and
a 32kHz external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator
control circuit” of the Hardware Manual for further details about voltage regulator control. Power supply for
"On Chip Debugger" part is not included. Power supply current in Run mode does not include Flash Write /
Erase current.
*2: The power supply current in Timer mode is the value when Flash is in Power-down / reset mode.
The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a
32kHz external clock connected to the Sub oscillator.
*3: The power supply current in Stop mode is the value when Flash is in Power-down / reset mode.
*4: When low voltage detector is enabled, ICCLVD must be added to Power supply current.
*5: When Flash Write / Erase program is executed, ICCFLASH must be added to Power supply current.
34
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS704-00012-0v01-E
MB96630 Series
2. Pin characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Parameter Symbol Pin name
VIH
"H" level
input
voltage
"L" level
input
voltage
Port inputs
Pnn_m
External clock in
"oscillation mode"
External clock in
"oscillation mode"
VIHX0S
X0
VIHX0AS
X0A
VIHR
RSTX
-
VIHM
MD
-
VIHD
DEBUG I/F
-
VIL
Port inputs
Pnn_m
External clock in
"oscillation mode"
External clock in
"oscillation mode"
VILX0S
X0
VILX0AS
X0A
VILR
RSTX
-
VILM
MD
-
VILD
DEBUG I/F
-
VOH4
4mA type
VOH3
3mA type
VOL4
4mA type
VOL3
3mA type
Input leak
current
IIL
Pnn_m
Pull-up
resistance
value
RPU
Pnn_m
"H" level
output
voltage*
"L" level
output
voltage*
Conditions
4.5V ≤ Vcc ≤ 5.5V
IOH = -4mA
2.7V ≤ Vcc < 4.5V
IOH = -1.5mA
4.5V ≤ Vcc ≤ 5.5V
IOH = -3mA
2.7V ≤ Vcc < 4.5V
IOH = -1.5mA
4.5V ≤ Vcc ≤ 5.5V
IOL = +4mA
2.7V ≤ Vcc < 4.5V
IOL = +1.7mA
2.7V ≤ Vcc < 5.5V
IOL = +3mA
Vss < VI < Vcc
AVss < VI <
AVcc, AVRH
Vcc = 5.0V ±10%
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Min
VCC
× 0.7
VCC
× 0.8
VD
× 0.8
Vcc
× 0.8
Vcc
× 0.8
Vcc
- 0.3
2.0
Vss
- 0.3
Vss
- 0.3
Vss
Vss
- 0.3
Vss
- 0.3
Vss
- 0.3
Vss
- 0.3
Value
Typ Max
-
VCC
+ 0.3
VCC
+ 0.3
VD
Vcc
+ 0.3
Vcc
+ 0.3
Vcc
+ 0.3
Vcc
+ 0.3
VCC
× 0.3
VCC
× 0.5
VD
× 0.2
Vcc
× 0.2
VCC
× 0.2
Vss
+ 0.3
Unit
V
V
V
Remarks
CMOS
Hysteresis input
AUTOMOTIVE
Hysteresis input
VD=1.8V±0.15V
V
V
V
V
V
V
V
CMOS
Hysteresis input
CMOS
Hysteresis input
TTL Input
CMOS
Hysteresis input
AUTOMOTIVE
Hysteresis input
VD=1.8V±0.15V
V
V
V
-
0.8
V
Vcc
- 0.5
-
Vcc
V
Vcc
- 0.5
-
Vcc
V
-
-
0.4
V
-
-
0.4
V
-1
-
1
μA
25
50
100
kΩ
CMOS
Hysteresis input
CMOS
Hysteresis input
TTL Input
35
MB96630 Series
Parameter Symbol Pin name
Other than
Vcc, Vss,
Input
CIN
AVcc,
capacitance
AVss,
AVRH
*: IOH and IOL are target value.
Conditions
-
36
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Min
-
Value
Typ Max
5
15
Unit
Remarks
pF
DS704-00012-0v01-E
MB96630 Series
4. AC Characteristics
(1) Main Clock Input Characteristics
(VCC = AVCC = 2.7V to 5.5V, VD=1.8V±0.15V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Parameter
Input frequency
Input frequency
Symbol
fC
fFCI
Pin
name
Min
Value
Typ
Max
4
-
8
MHz
-
-
8
MHz
4
-
8
MHz
-
-
16
MHz
4
-
16
MHz
X0,
X1
Unit
X0
Input clock cycle
tCYLH
-
62.5
-
-
ns
Input clock pulse
width
PWH,
PWL
-
30
-
70
%
Remarks
When using a crystal
oscillator, PLL off
When using an opposite
phase external
clock, PLL off
When using a crystal
oscillator or opposite
phase external clock,
PLL on
When using a single
phase external
clock in “Fast Clock
Input mode”, PLL off
When using a single
phase external
clock in “Fast Clock
Input mode”, PLL on
tCYLH
Reference value:
1.8V±0.15V
The amplitude changes by resistance, capacity which added outside or the difference of the device.
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
37
MB96630 Series
(2) Sub Clock Input Characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Parameter
Symbol
Min
Value
Typ
Max
-
-
32.768
-
kHz
-
-
-
100
kHz
X0A
-
-
-
50
kHz
Pin
Conditions
name
X0A,
X1A
Input frequency
FCL
Unit
Input clock cycle
tCYLL
-
-
10
-
-
μs
Input clock pulse
width
-
-
PWH/tCYLL
PWL/tCYLL
30
-
70
%
Remarks
When using an
oscillation circuit
When using an
opposite phase
external clock
When using a
single phase
external clock
tCYLL
0.8×Vcc
X0A
0.8×Vcc
0.8×Vcc
0.2×Vcc
PWH
0.2×Vcc
P WL
(3) Built-in RC Oscillation Characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Parameter
Symbol
Clock frequency
Min
Value
Typ
Max
50
100
200
kHz
1
2
4
MHz
Unit
FRC
Remarks
When using slow frequency of
RC oscillator
When using fast frequency of
RC oscillator
(4) Internal Clock timing
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Parameter
Symbol
Value
Min
Max
Unit
Internal System clock frequency
(CLKS1 and CLKS2)
fCLKS1, fCLKS2
-
54
MHz
Internal CPU clock frequency (CLKB),
Internal peripheral clockfrequency (CLKP1)
fCLKB, fCLKP1
-
32
MHz
Internal peripheral clock frequency (CLKP2)
fCLKP2
-
32
MHz
38
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS704-00012-0v01-E
MB96630 Series
(5) Operating Conditions of PLL
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Parameter
Symbol
Value
Unit
Min Typ Max
PLL oscillation stabilization wait time
(LOCK UP time)
tLOCK
1
-
4
ms
PLL input clock frequency
fPLLI
4
-
16
MHz
PLL macro oscillation clock frequency
fPLLO
56
-
108
MHz
Remarks
Time from when the PLL
starts operating until the
oscillation stabilizes
(6) Reset Input Characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Parameter
Reset input time
Rejection of reset input time
Symbol
Pin name
TRSTL
RSTX
Value
Unit
Min
Max
10
-
μs
1
-
μs
(7) Power-on Reset Timing
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Parameter
Symbol
Power on rise time
Power off time
Tr
Toff
Tr
Min
Value
Typ
Max
0.05
1
-
30
-
Unit
ms
ms
Toff
2.7V
0.2V
0.2V
0.2V
If the power supply is changed too rapidly, a power-on reset may occur.
We recommend a smooth startup by restraining voltages when changing the
power supply voltage during operation, as shown in the figure below.
2.7V
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Rising edge of 50 mV/ms
maximum is allowed
39
MB96630 Series
(8) USART Timing
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Parameter
Symbol
4.5V ≤ Vcc < 5.5V
Pin
Conditions
Min
Max
name
2.7V ≤ Vcc < 4.5V
Min
Max
SCKn
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
SCKn
SOTn
SCKn Internal shift
tOVSHI
clock
SOTn
operation
SCKn
tIVSHI
SINn
SCKn
tSHIXI
SINn
tSLOVI
SOT → SCK ↑ delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
Serial clock "L" pulse width
tSLSH
SCKn
Serial clock "H" pulse width
tSHSL
SCKn
Unit
4 tCLKP1
-
4 tCLKP1
-
ns
- 20
+ 20
- 30
+ 30
ns
-
ns
-
ns
-
ns
-
ns
-
ns
N×tCLKP1
– 20*
tCLKP1
+ 45
0
tCLKP1
+ 10
tCLKP1
+ 10
-
N×tCLKP1
– 30*
tCLKP1
+ 55
0
tCLKP1
+ 10
tCLKP1
+ 10
SCKn
2 tCLKP1
2 tCLKP1
ns
External shift
SOTn
+ 45
+ 55
clock
SCKn
tCLKP1/2
tCLKP1/2
operation
ns
tIVSHE
SIN → SCK ↑ setup time
SINn
+ 10
+ 10
SCKn
tCLKP1
tCLKP1
ns
tSHIXE
SCK ↑ → SIN hold time
SINn
+ 10
+ 10
SCK fall time
tF
SCKn
ns
20
20
SCK rise time
tR
SCKn
ns
20
20
Notes: • The above characteristics apply to CLK synchronous mode.
• CL is the load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by
some parameters. These parameters are shown in “MB96630 series HARDWARE MANUAL”
• tCLKP1 indicates the peripheral clock 1 (CLKP1), Unit: ns
• These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKn_0 and SOTn_1 is not guaranteed.
SCK ↓ → SOT delay time
tSLOVE
*: Parameter N depends on tSCYC and can be calculated as follows:
• If tSCYC = 2 × k × tCLKP1, then N = k, where k is an integer > 2
• If tSCYC = (2 × k + 1) × tCLKP1, then N = k + 1, where k is an integer > 1
Examples:
tSCYC
N
4 × tCLKP1
2
5 × tCLKP1, 6 × tCLKP1
3
7 × tCLKP1, 8 × tCLKP1
4
...
...
40
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS704-00012-0v01-E
MB96630 Series
tSCYC
VOH
SCK
VOL
tSLOVI
VOH
SOT
VOL
tIVSHI
tSHIXI
VIH
VIH
VIL
VIL
SIN
MS bit = 0
tSHSL
tSLSH
SCK
VIH
VIH
VIL
VIL
tR
tF
SOT
tSLOVE
VOH
VOL
tIVSHE
SIN
tSHIXE
VIH
VIH
VIL
VIL
MS bit = 1
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
41
MB96630 Series
(9) External input timing
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Parameter
Symbol
Value
Min
Max
Pin name
Unit
Pnn_m
Remarks
General Purpose I/O
A/D converter trigger
input
ADTG
FRCKn,
Free-Running Timer
FRCKn_R
2tCLKP1 +200
TINn
Reload Timer
(tCLKP1=
ns
tINH
1/f
)*
TTGn
Input pulse width
CLKP1
PPG Trigger input
tINL
INn, INn_R
Input capture
AINn
Quadrature
BINn
position/revolution
ZINn
counter
INTn, INTn_R,
External interrupt
200
ns
NMI
NMI
*: tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time except stop when in stop mode.
tINH
VILS
tINL
VILS
42
FUJITSU SEMICONDUCTOR CONFIDENTIAL
VIHS
VIHS
DS704-00012-0v01-E
MB96630 Series
2
(10) I C timing
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Parameter
Symbol
Conditions
Typical mode
Min
Max
High-speed
mode*4
Min
Max
Unit
SCL clock frequency
fSCL
0
100
0
400
kHz
(Repeated) START condition
hold time
tHDSTA
4.0
0.6
μs
SDA ↓ → SCL ↓
SCLclock "L" width
tLOW
4.7
1.3
μs
SCLclock "H" width
tHIGH
4.0
0.6
μs
(Repeated) START setup time
tSUSTA
4.7
0.6
μs
SCL ↑ → SDA ↓
CL = 50pF,
Data hold time
1
tHDDAT R = (Vp/IOL)*
0
3.45*2
0
0.9*3
μs
SCL ↓ → SDA ↓ ↑
Data setup time
tSUDAT
250
100
ns
SDA ↓ ↑ → SCL ↑
STOP condition setup time
tSUSTO
4.0
0.6
μs
SCL ↑ → SDA ↑
Bus free time between
"STOP condition" and
tBUS
4.7
1.3
μs
"START condition"
*1: R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp
indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it doesn't extend at least "L" period (tLOW) of device's SCL signal.
*3: A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4: tCLKP1 is the peripheral clock1 (CLKP1) cycle time. To use I2C, set the peripheral bus clock at 6 MHz or
more.
SDA
tSUDAT
tLOW
tSUSTA
tBUS
SCL
tHDSTA
tHDDAT
tHIGH
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
tHDSTA
tSUSTO
43
MB96630 Series
z 10bit A/D Converter
Electrical characteristics for the A/D converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Parameter
Symbol Pin name
Min
Value
Typ
Max
Unit
Resolution
-
-
-
-
10
bit
Total error
-
-
- 3.0
-
+ 3.0
LSB
Nonlinearity error
-
-
- 2.5
-
+ 2.5
LSB
-
-
- 1.9
-
+ 1.9
LSB
VOT
ANx
Typ - 20
Typ + 20
mV
VFST
ANx
Typ - 20
Typ + 20
mV
Compare time
-
-
Sampling time
-
-
5.0
8.0
3.1
μs
μs
μs
μs
mA
Differential
Nonlinearity error
Zero transition
voltage
Full transition
voltage
Power supply
current
Reference power
supply current
(between AVRH to
AVSS)
Analog input
capacity
Analog port input
current
Analog input
voltage
Reference voltage
range
IA
IAH
AVCC
IR
1.0
2.2
0.5
1.2
-
AVSS
+ 0.5LSB
AVRH
- 1.5LSB
2.0
-
-
3.3
μA
-
520
810
μA
A/D Converter active
-
-
1.0
μA
A/D Converter not
operated
AVRH
IRH
Remarks
CVIN
ANx
-
-
15.9
pF
IAIN
ANx
- 0.3
-
+ 0.3
μA
VAIN
ANx
AVSS
-
AVRH
V
-
AVRH
AVCC
- 0.1
-
AVCC
V
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
4.5V ≤ ΑVCC ≤ 5.5V
2.7V ≤ ΑVCC < 4.5V
4.5V ≤ ΑVCC ≤ 5.5V
2.7V ≤ ΑVCC < 4.5V
A/D Converter active
A/D Converter not
operated
AVSS < VAIN <
AVCC, AVRH
(TA = +125°C)
DS704-00012-0v01-E
MB96630 Series
Accuracy and setting of the A/D Converter sampling time
If the external impedance is too high or the sampling time too short, the analog voltage charged to the
internal sample and hold capacitor is insufficient, adversely affecting the A/D conversion precision.
To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling
time depends on the external driving impedance Rext, the board capacitance of the A/D converter input pin
Cext and the AVcc voltage level. The following replacement model can be used for the calculation:
MCU
Rext
Analog
input
RVIN
Source
Comparetor
Cext
CVIN
Sampling switch
Rext: External driving impedance
Cext: Capacitance of PCB at A/D converter input
CVIN: Capacitance of MCU input pin (I/O, analog switch and ADC are contained)
RVIN: Analog input impedance (I/O, analog switch and ADC are contained)
2050Ω (4.5V ≤ AVcc ≤ 5.5V), 3600Ω (2.7V ≤ AVcc < 4.5V)
The following approximation formula for the replacement model above can be used:
Tsamp [min] = 7.62 × (Rext × Cext + (Rext + RVIN) × CVIN)
Do not select a sampling time below the absolute minimum permitted value.
(0.5μs for 4.5V ≤ AVcc ≤ 5.5V, 1.2 μs for 2.7V ≤ AVcc < 4.5V)
If the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
A big external driving impedance also adversely affects the A/D conversion precision due to the pin
input leakage current IIL (static current before the sampling switch) or the analog input leakage current
IAIN (total leakage current of pin input and comparator during sampling). The effect of the pin input
leakage current IIL cannot be compensated by an external capacitor.
The accuracy gets worse as |AVRH - AVSS| becomes smaller.
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
45
MB96630 Series
• Definition of 10-bit A/D Converter Terms
Resolution
Linearity error
: Analog variation that is recognized by an A/D converter.
: Deviation of the line between the zero-transition point (0b0000000000←→
0b0000000001) and the full-scale transition point (0b1111111110 ←→
0b1111111111) from the actual conversion characteristics.
Differential linearity error : Deviation from the ideal value of the input voltage that is required to change the
output code by 1 LSB.
Total error
: Difference between the actual value and the theoretical value. The total error
includes zero transition error, full-scale transition error, and linearity error.
Linearity error
0x3FF
Actual conversion
characteristics
0x3FE
Actual conversion
characteristics
0x(N+1)
{1 LSB(N-1) + VOT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0x3FD
Differential linearity error
Actual conversion
characteristics
Ideal characteristics
0x002
0x001
0xN
Ideal characteristics
(Actually-measured
value)
VNT
(Actually-measured
value)
0x(N-2)
VOT (Actually-measured value)
AVss
V(N+1)T
0x(N-1)
Actual conversion characteristics
AVRH
AVss
AVRH
Analog input
Linearity error of digital output N =
Analog input
VNT - {1LSB × (N - 1) + VOT}
1LSB’
Differential linearity error of digital output N =
1LSB =
N
VOT
VFST
VNT
:
:
:
:
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST - VOT
1022
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0x3FE to 0x3FF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS704-00012-0v01-E
MB96630 Series
Total error
0x3FF
1.5 LSB'
Digital output
0x3FE
Actual conversion
characteristics
0x3FD
{1 LSB'(N-1) + 0.5 LSB'}
0x004
VNT
0x003
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
0x002
0x001
0.5 LSB'
AVss
AVRH
Analog input
1LSB' (Ideal value) =
AVRH - AVSS
1024
Total error of digital output N =
[V]
VNT - {1LSB' × (N - 1) + 0.5LSB'}
1LSB'
N
: A/D converter digital output value.
VNT : Voltage at which the digital output changes from 0x(N + 1) to 0xN.
VOT' (Ideal value) = AVSS + 0.5LSB[V]
VFST' (Ideal value) = AVRH - 1.5LSB[V]
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
47
MB96630 Series
z Low voltage detection characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Parameter
Min
Value
Typ
Max
CILCR:LVL = 0000B
CILCR:LVL = 0001B
CILCR:LVL = 0010B
CILCR:LVL = 0011B
CILCR:LVL = 0100B
CILCR:LVL = 0111B
CILCR:LVL = 1001B
2.70
2.79
2.98
3.26
3.45
3.73
3.91
2.90
3.00
3.20
3.50
3.70
4.00
4.20
3.10
3.21
3.42
3.74
3.95
4.27
4.49
-
-0.004
-
-
Symbol
Conditions
Detected voltage
VDL0
VDL1
VDL2
VDL3
VDL4
VDL5
VDL6
Change ration of
power supply
voltage
dV/dt
Unit
Remarks
V
V
V
V
V
V
V
Detected voltage
V/μs (VDL) must be
within standards.
Voltage
Vcc
VDLx, max
VDLx, min
dV
dt
Time
48
FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS704-00012-0v01-E
MB96630 Series
z Flash Memory Write/Erase Characteristics(Target value)
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C)
Parameter
Sector erase time
Half word(16 bit)
write time
Large Sector
Min
-
Small Sector
Value
Typ Max
Unit
Conditions
0.6
3.1
s
TA ≤ + 105°C
0.3
1.6
s
-
Large Sector
-
25
400
μs
TA ≤ + 105°C
Small Sector
-
25
400
μs
-
-
2.7
14.2
s
TA ≤ + 105°C
Chip erase time
Remarks
Excludes write time
prior to internal erase
Not including
system-level overhead
time.
Excludes write time
prior to internal erase
Erase / write cycles and data hold time (targeted value)
Erase / write cycles
(cycle)
Data hold time
(year)
1,000
20 *
10,000
10 *
100,000
5*
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85°C).
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
49
MB96630 Series
ORDERING INFORMATION
Part number
MB96F636RAPMC-GSE1*
MB96F636RAPMC-GSE2*
MB96F637RAPMC-GSE1*
MB96F637RAPMC-GSE2*
Flash memory
Package
Flash A
(288.5KB)
Flash A
(416.5KB)
80-pin plastic LQFP
(FPT-80P-M21)
*: These devices are under development and specification is preliminary.
These products under development may change its specification without notice.
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS704-00012-0v01-E
MB96630 Series
PACKAGE DIMENSION
80-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
12 mm × 12 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Weight
0.47 g
Code
(Reference)
P-LFQFP80-12×12-0.50
(FPT-80P-M21)
80-pin plastic LQFP
(FPT-80P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00± 0.20(.551±.008)SQ
* 12.00± 0.10(.472±.004)SQ
60
0.145± 0.055
(.006±. 002)
41
40
61
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004
INDEX
0°~8°
21
80
"A"
LEAD No.
1
0 2
0.50(.020)
C
0.10± 0.05
(.004±.002)
(Stand off)
0.20± 0.05
(.008±.002)
0.50±0.20
(.020±.008)
0.60± 0.15
(.024±.006)
0.25(.010)
0.08(.003) M
2006-2010 FUJITSU SEMICONDUCTOR LIMITED F80035S-c-2-4
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
51
MB96630 Series
REVISION HISTORY
Revision
Date
Prelim 1
29-Jul-2011
Modification
Creation
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MB96630 Series
DS704-00012-0v01-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
55
MB96630 Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600
Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://sg.fujitsu.com/semiconductor/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fss/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fsk/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely
for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU
SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising
out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as
license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of
FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of
any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR
assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would
result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use
requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
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