MB96670 Series
F2MC-16FX 16-Bit Microcontroller
MB96670 series is based on Cypress’s advanced F2MC-16FX architecture (16-bit with instruction pipeline for RISC-like
performance). The CPU uses the same instruction set as the established F2MC-16LX family thus allowing for easy migration of
F2MC-16LX Software to the new F2MC-16FX products.
F2MC-16FX product improvements compared to the previous generation include significantly improved performance - even at the
same operation frequency, reduced power consumption and faster start-up time.
For high processing speed at optimized power consumption an internal PLL can be selected to supply the
CPU with up to 32MHz operation frequency from an external 4MHz to 8MHz resonator. The result is a minimum instruction cycle
time of 31.2ns going together with excellent EMI behavior. The emitted power is minimized by the on-chip voltage regulator that
reduces the internal CPU voltage. A flexible clock tree allows selecting suitable operation frequencies for peripheral resources
independent of the CPU speed.
Features
Technology
DMA
0.18m CMOS
Automatic transfer function independent of CPU, can be
assigned freely to resources
CPU
F
2
MC-16FX CPU
instruction set for controller applications
(bit, byte, word and long-word data types, 23 different
addressing modes, barrel shift, variety of pointers)
8-byte instruction queue
Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit)
instructions available
Interrupts
Fast
Interrupt processing
programmable priority levels
Non-Maskable Interrupt (NMI)
Optimized
8
CAN
Supports
CAN protocol version 2.0 part A and B
certified
Bit rates up to 1Mbps
32 message objects
Each message object has its own identifier mask
Programmable FIFO mode (concatenation of message
objects)
Maskable interrupt
Disabled Automatic Retransmission mode for Time
Triggered CAN applications
Programmable loop-back mode for self-test operation
ISO16845
System clock
PLL clock multiplier (1 to 8, 1 when PLL stop)
to 8MHz crystal oscillator
(maximum frequency when using ceramic resonator
depends on Q-factor)
Up to 8MHz external clock for devices with fast clock input
feature
32.768kHz subsystem quartz clock
100kHz/2MHz internal RC clock for quick and safe startup,
clock stop detection function, watchdog
Clock source selectable from mainclock oscillator, subclock
oscillator and on-chip RC oscillator, independently for CPU
and 2 clock domains of peripherals
The subclock oscillator is enabled by the Boot ROM
program controlled by a configuration marker after a Power
or External reset
Low Power Consumption - 13 operating modes (different
Run, Sleep, Timer, Stop modes)
On-chip
4MHz
USART
Full
duplex USARTs (SCI/LIN)
range of baud rate settings using a dedicated reload
timer
Special synchronous options for adapting to different
synchronous serial protocols
LIN functionality working either as master or slave LIN
device
Extended support for LIN-Protocol to reduce interrupt load
Wide
On-chip voltage regulator
Internal voltage regulator supports a wide MCU supply
voltage range (Min=2.7V), offering low power consumption
I2 C
Low voltage detection function
Up
to 400kbps
and Slave functionality, 7-bit and 10-bit addressing
Master
Reset is generated when supply voltage falls below
programmable reference voltage
Code Security
Protects Flash Memory content from unintended read-out
Cypress Semiconductor Corporation
Document Number: 002-04703 Rev.*A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 18, 2016
MB96670 Series
A/D converter
SAR-type
8/10-bit
resolution
Signals interrupt on conversion end, single conversion
mode, continuous conversion mode,
stop conversion mode, activation by software, external
trigger, reload timers and PPGs
Range Comparator Function
Scan Disable Function
ADC Pulse Detection Function
Source Clock Timers
Three independent clock timers (23-bit RC clock timer,
23-bit Main clock timer, 17-bit Sub clock timer)
Hardware Watchdog Timer
Hardware
watchdog timer is active after reset
function of Watchdog Timer is used to select the
lower window limit of the watchdog interval
Window
Reload Timers
16-bit
wide
with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral
clock frequency
Event count function
Prescaler
Free-Running Timers
Signals
an interrupt on overflow
with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27, 1/28
of peripheral clock frequency
Prescaler
Input Capture Units
16-bit
wide
an interrupt upon external event
Rising edge, Falling edge or Both (rising & falling) edges
sensitive
Signals
Programmable Pulse Generator
16-bit
down counter, cycle and duty setting registers
be used as 2 × 8-bit PPG
Interrupt at trigger, counter borrow and/or duty match
PWM operation and one-shot operation
Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral
clock as counter clock or of selected Reload timer
underflow as clock input
Can be triggered by software or reload timer
Can trigger ADC conversion
Timing point capture
Can
Stepping Motor Controller
Stepping
Motor Controller with integrated high current
output drivers
Four high current outputs for each channel
Two synchronized 8/10-bit PWMs per channel
Internal prescaling for PWM clock: 1, 1/4, 1/5, 1/6, 1/8, 1/10,
1/12, 1/16 of peripheral clock
Dedicated power supply for high current output drivers
Document Number: 002-04703 Rev.*A
LCD Controller
LCD
controller with up to 4COM × 24SEG
or external voltage generation
Duty cycle: Selectable from options: 1/2, 1/3 and 1/4
Fixed 1/3 bias
Programmable frame period
Clock source selectable from four options (main clock,
peripheral clock, subclock or RC oscillator clock)
Internal divider resistors or external divider resistors
On-chip data memory for display
LCD display can be operated in Timer Mode
Blank display: selectable
All SEG, COM and V pins can be switched between
general and specialized purposes
Internal
Sound Generator
8-bit
PWM signal is mixed with tone frequency from 16-bit
reload counter
PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8 of
peripheral clock
Real Time Clock
Operational
on main oscillation (4MHz), sub oscillation
(32kHz) or RC oscillation (100kHz/2MHz)
Capable to correct oscillation deviation of Sub clock or RC
oscillator clock (clock calibration)
Read/write accessible second/minute/hour registers
Can signal interrupts every half
second/second/minute/hour/day
Internal clock divider and prescaler provide exact 1s clock
External Interrupts
Edge
or Level sensitive
mask bit per channel
Each available CAN channel RX has an external interrupt
for wake-up
Selected USART channels SIN have an external interrupt
for wake-up
Interrupt
Non Maskable Interrupt
Disabled
after reset, can be enabled by Boot-ROM
depending on ROM configuration block
Once enabled, can not be disabled other than by reset
High or Low level sensitive
Pin shared with external interrupt 0
I/O Ports
Most
of the external pins can be used as general purpose
I/O
All push-pull outputs (except when used as I2C SDA/SCL
line)
Bit-wise programmable as input/output or peripheral signal
Bit-wise programmable input enable
One input level per GPIO-pin (either Automotive or CMOS
hysteresis)
Bit-wise programmable pull-up resistor
Page 2 of 68
MB96670 Series
Built-in On Chip Debugger (OCD)
One-wire
debug tool interface
Break function:
• Hardware break: 6 points (shared with code event)
• Software break: 4096 points
Event function
• Code event: 6 points (shared with hardware break)
• Data event: 6 points
• Event sequencer: 2 levels + reset
Execution time measurement function
Trace function: 42 branches
Security function
Document Number: 002-04703 Rev.*A
Flash Memory
Dual
operation flash allowing reading of one Flash bank
while programming or erasing the other bank
Command sequencer for automatic execution of
programming algorithm and for supporting DMA for
programming of the Flash Memory
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the automatic algorithm
Erase can be performed on each sector individually
Sector protection
Flash Security feature to protect the content of the Flash
Low voltage detection during Flash erase or write
Page 3 of 68
MB96670 Series
Contents
1. Product Lineup .................................................................................................................................................................. 6
2. Block Diagram ................................................................................................................................................................... 7
3. Pin Assignment ................................................................................................................................................................. 8
4. Pin Description .................................................................................................................................................................. 9
5. Pin Circuit Type ............................................................................................................................................................... 11
6. I/O Circuit Type ............................................................................................................................................................... 13
7. Memory Map .................................................................................................................................................................... 19
8. RAMSTART Addresses................................................................................................................................................... 20
9. User ROM Memory Map For Flash Devices .................................................................................................................. 21
10. Serial Programming Communication Interface ............................................................................................................ 22
11. Interrupt Vector Table ..................................................................................................................................................... 23
12. Handling Precautions ..................................................................................................................................................... 27
12.1 Precautions for Product Design ................................................................................................................................... 27
12.2 Precautions for Package Mounting .............................................................................................................................. 28
12.3 Precautions for Use Environment ................................................................................................................................ 29
13. Handling Devices ............................................................................................................................................................ 30
13.1 Latch-up prevention ..................................................................................................................................................... 30
13.2 Unused pins handling .................................................................................................................................................. 30
13.3 External clock usage ................................................................................................................................................... 31
13.3.1 Single phase external clock for Main oscillator............................................................................................................. 31
13.3.2 Single phase external clock for Sub oscillator .............................................................................................................. 31
13.3.3 Opposite phase external clock ..................................................................................................................................... 31
13.4 Notes on PLL clock mode operation ............................................................................................................................ 31
13.5 Power supply pins (Vcc/Vss) ....................................................................................................................................... 31
13.6 Crystal oscillator and ceramic resonator circuit ........................................................................................................... 32
13.7 Turn on sequence of power supply to A/D converter and analog inputs ..................................................................... 32
13.8 Pin handling when not using the A/D converter ........................................................................................................... 32
13.9 Notes on Power-on ...................................................................................................................................................... 32
13.10 Stabilization of power supply voltage .......................................................................................................................... 32
13.11 SMC power supply pins ............................................................................................................................................... 32
13.12 Serial communication .................................................................................................................................................. 32
13.13 Mode Pin (MD) ............................................................................................................................................................ 32
14. Electrical Characteristics ............................................................................................................................................... 33
14.1 Absolute Maximum Ratings ......................................................................................................................................... 33
14.2 Recommended Operating Conditions ......................................................................................................................... 35
14.3 DC Characteristics ...................................................................................................................................................... 36
14.3.1 Current Rating .............................................................................................................................................................. 36
14.3.2 Pin Characteristics ....................................................................................................................................................... 39
14.4 AC Characteristics ....................................................................................................................................................... 42
14.4.1 Main Clock Input Characteristics .................................................................................................................................. 42
14.4.2 Sub Clock Input Characteristics ................................................................................................................................... 43
14.4.3 Built-in RC Oscillation Characteristics .......................................................................................................................... 44
14.4.4 Internal Clock Timing ................................................................................................................................................... 44
14.4.5 Operating Conditions of PLL ........................................................................................................................................ 45
14.4.6 Reset Input ................................................................................................................................................................... 45
14.4.7 Power-on Reset Timing ................................................................................................................................................ 46
Document Number: 002-04703 Rev.*A
Page 4 of 68
MB96670 Series
14.4.8 USART Timing ............................................................................................................................................................. 47
14.4.9 External Input Timing ................................................................................................................................................... 49
14.4.10 I2C Timing ................................................................................................................................................................. 50
14.5 A/D Converter .............................................................................................................................................................. 51
14.5.1 Electrical Characteristics for the A/D Converter ........................................................................................................... 51
14.5.2 Accuracy and Setting of the A/D Converter Sampling Time ......................................................................................... 52
14.5.3 Definition of A/D Converter Terms ............................................................................................................................... 53
14.6 High Current Output Slew Rate ................................................................................................................................... 55
14.7 Low Voltage Detection Function Characteristics ......................................................................................................... 56
14.8 Flash Memory Write/Erase Characteristics ................................................................................................................. 58
15. Example Characteristics ................................................................................................................................................ 59
16. Ordering Information ...................................................................................................................................................... 62
17. Package Dimension ........................................................................................................................................................ 63
18. Major Changes ................................................................................................................................................................ 65
Document History ................................................................................................................................................................. 67
Document Number: 002-04703 Rev.*A
Page 5 of 68
MB96670 Series
1. Product Lineup
Features
Product Type
Subclock
Dual Operation Flash Memory
RAM
MB96670
Flash Memory Product
Subclock can be set by software
-
64.5KB + 32KB
4KB
MB96F673R, MB96F673A
128.5KB + 32KB
4KB
MB96F675R, MB96F675A
Product Options
R: MCU with CAN
A: MCU without CAN
LQFP-64
FPT-64P-M23/M24
2ch
2ch
LIN-USART 0/1
Yes (only 1ch)
LIN-USART 0
Package
DMA
USART
with automatic LIN-Header
transmission/reception
with 16 byte RX- and
TX-FIFO
2
IC
8/10-bit A/D Converter
with Data Buffer
with Range Comparator
with Scan Disable
with ADC Pulse Detection
16-bit Reload Timer (RLT)
16-bit Free-Running Timer (FRT)
No
8/16-bit Programmable Pulse Generator (PPG)
with Timing point capture
with Start delay
with Ramp
1ch
12ch
No
Yes
Yes
Yes
3ch
2ch
4ch
(2 channels for LIN-USART)
4ch (16-bit) / 8ch (8-bit)
Yes
No
No
CAN Interface
1ch
Stepping Motor Controller (SMC)
External Interrupts (INT)
Non-Maskable Interrupt (NMI)
Sound Generator (SG)
2ch
7ch
1ch
1ch
LCD Controller
4COM × 24SEG
Real Time Clock (RTC)
Clock Calibration Unit (CAL)
Clock Output Function
1ch
48 (Dual clock mode)
50 (Single clock mode)
1ch
2ch
Low Voltage Detection Function
Yes
Hardware Watchdog Timer
On-chip RC-oscillator
On-chip Debugger
Yes
Yes
Yes
16-bit Input Capture Unit (ICU)
I/O Ports
Remark
I2C 0
AN 8/9/12/13/16 to 23
RLT 1/2/6
FRT 0/1
ICU 0/1/4/5
ICU 0/1 for LIN-USART
PPG 0 to 3
CAN 0
32 Message Buffers
SMC 0/1
INT 0 to 4/6/7
SG 0
COM 0 to 3
SEG 3 to 6/8 to 11/
19 to 21/23/30/36 to 39/42/45 to
47/54 to 56
Low voltage detection function
can be
disabled by software
Note:
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the general I/O port according to your function use.
Document Number: 002-04703 Rev.*A
Page 6 of 68
MB96670 Series
2. Block Diagram
DEBUG I/F
CKOT0_R, CKOT1
CKOTX0
X0, X1
X0A, X1A
RSTX
MD
NMI
Flash
Memory A
Interrupt
Controller
16FX
CPU
OCD
Clock &
Mode Controller
16FX Core Bus (CLKB)
Peripheral
Bus Bridge
Watchdog
AVcc
AVss
AVRH
AN8, AN9
AN12, AN13
AN16 to AN23
ADTG
TIN1, TIN1_R, TIN2_R
TOT1, TOT1_R, TOT2_R
IN0_R, IN1, IN1_R
IN4_R, IN5_R
INT0 to INT4
INT6, INT7
INT1_R, INT2_R
I 2C
1ch
8/10-bit ADC
12ch
16-bit
Reload Timer
1/2/6
3ch
I/O Timer 0
FRT 0
ICU 0/1
I/O Timer 1
FRT 1
ICU 4/5
External
Interrupt
7ch
SEG3 to SEG6, SEG8 to SEG11
SEG19 to SEG21, SEG23
SEG30,SEG36 to SEG39
SEG42,SEG45 to SEG47
SEG54 to SEG56
Document Number: 002-04703 Rev.*A
RAM
CAN
Interface
1ch
USART
2ch
PPG
4ch (16-bit) /
8ch (8-bit)
Boot ROM
RX0
Voltage
Regulator
Vcc
Vss
C
TX0
Sound
Generator
1ch
SGO0
SGA0
SIN0, SIN1
SOT0, SOT1
SCK0, SCK1
TTG1
PPG0_R, PPG1_R, PPG2_R, PPG3
PPG0_B, PPG1_B, PPG2_B, PPG3_B
Stepping
Motor
Controller
2ch
Real Time
Clock
V0 to V3
COM0 to COM3
Peripheral
Bus Bridge
Peripheral Bus 2 (CLKP2)
SDA0
SCL0
Peripheral Bus 1 (CLKP1)
DMA
Controller
DVcc
DVss
PWM1P0, PWM1P1
PWM1M0, PWM1M1
PWM2P0, PWM2P1
PWM2M0, PWM2M1
WOT_R
LCD
controller/
driver
4COMÍ24SEG
Page 7 of 68
MB96670 Series
3. Pin Assignment
Vss
X1
X0
MD
P17_0
DEBUG I/F
P04_5 / SCL0*2
44
P04_0 / X0A*3
45
P04_1 / X1A*3
P11_1 / COM1 / PPG0_R
46
RSTX
P11_2 / COM2 / PPG1_R
47
P11_7 / SEG3 / IN0_R
P11_3 / COM3 / PPG2_R
48
P11_0 / COM0
P12_0 / SEG4 / IN1_R
(Top view)
43
42
41
40
39
38
37
36
35
34
33
P12_1 / SEG5 / TIN1_R / PPG0_B
49
32
P04_4 / PPG3 / SDA0*2
P12_2 / SEG6 / TOT1_R / PPG1_B
50
31
P13_6 / SCK0 / CKOTX0 / SEG47*1
P12_4 / SEG8
51
30
P13_5 / SOT0 / ADTG / INT7 / SEG46
P12_5 / SEG9 / TIN2_R / PPG2_B
52
29
P13_4 / SIN0 / INT6 / SEG45*1
P12_6 / SEG10 / TOT2_R / PPG3_B
53
28
P08_7 / PWM2M1 / AN23
P12_7 / SEG11 / INT1_R
54
27
P08_6 / PWM2P1 / AN22
P01_1 / SEG21 / CKOT1
55
26
P08_5 / PWM1M1 / AN21
P01_3 / SEG23
56
25
P08_4 / PWM1P1 / AN20
P03_0 / SEG36 / V0
57
24
DVss
P03_1 / SEG37 / V1
58
23
DVcc
P03_2 / SEG38 / V2
59
22
P08_3 / PWM2M0 / AN19
P03_3 / SEG39 / V3
60
21
P08_2 / PWM2P0 / AN18
P03_4 / RX0 / INT4*1
61
20
P08_1 / PWM1M0 / AN17
P03_5 / TX0
62
19
P08_0 / PWM1P0 / AN16
P03_6 / INT0 / NMI
63
18
P05_5 / AN13
Vcc
64
17
P05_4 / AN12 / INT2_R / WOT_R
10
11
12
13
14
15
16
P05_0 / AN8
P05_1 / AN9
AVcc
AVRH
AVss
9
P06_6 / TIN1 / SEG55 / IN4_R
8
P06_7 / TOT1 / SEG56 / IN5_R
SEG42*1
7
P06_5 / IN1 / SEG54 / TTG1
P13_0 / INT2 / SOT1
6
P02_2 / SEG30 / CKOT0_R
5
P01_0 / SEG20 / SGA0
4
P00_7 / SEG19 / SGO0
3
P13_1 / INT3 / SCK1 /
2
C
Vss
1
P03_7 / INT1 / SIN1*1
LQFP-64
(FPT-64P-M23/M24)
*1: CMOS input level only
*2: CMOS input level only for I2C
*3: Please set ROM Configuration Block (RCB) to use the subclock.
Other than those above, general-purpose pins have only Automotive input level.
Document Number: 002-04703 Rev.*A
Page 8 of 68
MB96670 Series
4. Pin Description
Pin name
Feature
Description
ADTG
ADC
A/D converter trigger input pin
ANn
ADC
A/D converter channel n input pin
AVcc
Supply
Analog circuits power supply pin
AVRH
ADC
A/D converter high reference voltage input pin
AVss
Supply
Analog circuits power supply pin
C
Voltage regulator
Internally regulated power supply stabilization capacitor pin
CKOTn
Clock Output function
Clock Output function n output pin
CKOTn_R
Clock Output function
Relocated Clock Output function n output pin
CKOTXn
Clock Output function
Clock Output function n inverted output pin
COMn
LCD
LCD Common driver pin
DEBUG I/F
OCD
On Chip Debugger input/output pin
DVcc
Supply
SMC pins power supply
DVss
Supply
SMC pins power supply
INn
ICU
Input Capture Unit n input pin
INn_R
ICU
Relocated Input Capture Unit n input pin
INTn
External Interrupt
External Interrupt n input pin
INTn_R
External Interrupt
Relocated External Interrupt n input pin
MD
Core
Input pin for specifying the operating mode
NMI
External Interrupt
Non-Maskable Interrupt input pin
Pnn_m
GPIO
General purpose I/O pin
PPGn
PPG
Programmable Pulse Generator n output pin (16bit/8bit)
PPGn_R
PPG
Relocated Programmable Pulse Generator n output pin (16bit/8bit)
PPGn_B
PPG
Programmable Pulse Generator n output pin (16bit/8bit)
PWMn
SMC
SMC PWM high current output pin
RSTX
Core
Reset input pin
RXn
CAN
CAN interface n RX input pin
SCKn
USART
USART n serial clock input/output pin
2
SCLn
IC
I2C interface n clock I/O input/output pin
SDAn
I2 C
I2C interface n serial data I/O input/output pin
SEGn
LCD
LCD Segment driver pin
SGAn
Sound Generator
Sound Generator amplitude output pin
SGOn
Sound Generator
Sound Generator sound/tone output pin
SINn
USART
USART n serial data input pin
SOTn
USART
USART n serial data output pin
TINn
Reload Timer
Reload Timer n event input pin
TINn_R
Reload Timer
Relocated Reload Timer n event input pin
TOTn
Reload Timer
Reload Timer n output pin
TOTn_R
Reload Timer
Relocated Reload Timer n output pin
TTGn
PPG
Programmable Pulse Generator n trigger input pin
TXn
CAN
CAN interface n TX output pin
Document Number: 002-04703 Rev.*A
Page 9 of 68
MB96670 Series
Pin name
Feature
Description
Vn
LCD
LCD voltage reference pin
Vcc
Supply
Power supply pin
Vss
Supply
Power supply pin
WOT_R
RTC
Relocated Real Time clock output pin
X0
Clock
Oscillator input pin
X0A
Clock
Subclock Oscillator input pin
X1
Clock
Oscillator output pin
X1A
Clock
Subclock Oscillator output pin
Document Number: 002-04703 Rev.*A
Page 10 of 68
MB96670 Series
5. Pin Circuit Type
Pin no.
I/O circuit type*
Pin name
1
Supply
Vss
2
F
C
3
M
P03_7 / INT1 / SIN1
4
H
P13_0 / INT2 / SOT1
5
P
P13_1 / INT3 / SCK1 / SEG42
6
J
P00_7 / SEG19 / SGO0
7
J
P01_0 / SEG20 / SGA0
8
J
P02_2 / SEG30 / CKOT0_R
9
J
P06_5 / IN1 / SEG54 / TTG1
10
J
P06_6 / TIN1 / SEG55 / IN4_R
11
J
P06_7 / TOT1 / SEG56 / IN5_R
12
K
P05_0 / AN8
13
K
P05_1 / AN9
14
Supply
AVcc
15
G
AVRH
16
Supply
AVss
17
K
P05_4 / AN12 / INT2_R / WOT_R
18
K
P05_5 / AN13
19
R
P08_0 / PWM1P0 / AN16
20
R
P08_1 / PWM1M0 / AN17
21
R
P08_2 / PWM2P0 / AN18
22
R
P08_3 / PWM2M0 / AN19
23
Supply
DVcc
24
Supply
DVss
25
R
P08_4 / PWM1P1 / AN20
26
R
P08_5 / PWM1M1 / AN21
27
R
P08_6 / PWM2P1 / AN22
28
R
P08_7 / PWM2M1 / AN23
29
P
P13_4 / SIN0 / INT6 / SEG45
30
J
P13_5 / SOT0 / ADTG / INT7 / SEG46
31
P
P13_6 / SCK0 / CKOTX0 / SEG47
32
N
P04_4 / PPG3 / SDA0
Document Number: 002-04703 Rev.*A
Page 11 of 68
MB96670 Series
Pin no.
I/O circuit type*
Pin name
33
N
P04_5 / SCL0
34
O
DEBUG I/F
35
H
P17_0
36
C
MD
37
A
X0
38
A
X1
39
Supply
Vss
40
B
P04_0 / X0A
41
B
P04_1 / X1A
42
C
RSTX
43
J
P11_7 / SEG3 / IN0_R
44
J
P11_0 / COM0
45
J
P11_1 / COM1 / PPG0_R
46
J
P11_2 / COM2 / PPG1_R
47
J
P11_3 / COM3 / PPG2_R
48
J
P12_0 / SEG4 / IN1_R
49
J
P12_1 / SEG5 / TIN1_R / PPG0_B
50
J
P12_2 / SEG6 / TOT1_R / PPG1_B
51
J
P12_4 / SEG8
52
J
P12_5 / SEG9 / TIN2_R / PPG2_B
53
J
P12_6 / SEG10 / TOT2_R / PPG3_B
54
J
P12_7 / SEG11 / INT1_R
55
J
P01_1 / SEG21 / CKOT1
56
J
P01_3 / SEG23
57
L
P03_0 / SEG36 / V0
58
L
P03_1 / SEG37 / V1
59
L
P03_2 / SEG38 / V2
60
L
P03_3 / SEG39 / V3
61
M
P03_4 / RX0 / INT4
62
H
P03_5 / TX0
63
H
P03_6 / INT0 / NMI
64
Supply
Vcc
*: See “I/O CIRCUIT TYPE” for details on the I/O circuit types.
Document Number: 002-04703 Rev.*A
Page 12 of 68
MB96670 Series
6. I/O Circuit Type
Type
A
Circuit
X1
R
0
1
X out
Remarks
High-speed oscillation circuit:
• Programmable between
oscillation mode (external
crystal or resonator connected
to X0/X1 pins) and Fast
external Clock Input (FCI)
mode (external clock
connected to X0 pin)
• Feedback resistor = approx.
1.0MΩ
• The amplitude: 1.8V±0.15V
to operate by the internal
supply voltage
FCI
X0
FCI or Osc disable
Document Number: 002-04703 Rev.*A
Page 13 of 68
MB96670 Series
Type
B
Circuit
Pull-up control
P-ch
Standby
control
for input
shutdown
P-ch
Pout
N-ch
Nout
Remarks
Low-speed oscillation circuit
shared with GPIO functionality:
• Feedback resistor = approx.
5.0MΩ
• GPIO functionality selectable
(CMOS level output (IOL =
4mA, IOH = -4mA), Automotive
input with input shutdown
function and programmable
pull-up resistor)
R
Automotive input
X1A
R
X out
0
1
FCI
X0A
FCI or Osc disable
Pull-up control
P-ch
Standby
control
for input
shutdown
P-ch
Pout
N-ch
Nout
R
C
Document Number: 002-04703 Rev.*A
Automotive input
CMOS hysteresis input pin
Page 14 of 68
MB96670 Series
Type
F
Circuit
Remarks
Power supply input protection
circuit
P-ch
N-ch
• A/D converter ref+ (AVRH)
power supply input pin with
protection circuit
• Without protection circuit
against VCC for pins AVRH
G
P-ch
N-ch
H
Pull-up control
P-ch
P-ch
Pout
N-ch
Nout
• CMOS level output
(IOL = 4mA, IOH = -4mA)
• Automotive input with input
shutdown function
• Programmable pull-up resistor
R
Standby control
for input shutdown
Automotive input
J
Pull-up control
P-ch
P-ch
Pout
N-ch
Nout
• CMOS level output
(IOL = 4mA, IOH = -4mA)
• Automotive input with input
shutdown function
• Programmable pull-up resistor
• SEG or COM output
R
Automotive input
Standby control
for input shutdown
SEG or COM output
Document Number: 002-04703 Rev.*A
Page 15 of 68
MB96670 Series
Type
K
Circuit
Remarks
Pull-up control
P-ch
P-ch
Pout
N-ch
Nout
• CMOS level output
(IOL = 4mA, IOH = -4mA)
• Automotive input with input
shutdown function
• Programmable pull-up resistor
• Analog input
R
Automotive input
Standby control
for input shutdown
Analog input
L
Pull-up control
P-ch
P-ch
Pout
N-ch
Nout
• CMOS level output
(IOL = 4mA, IOH = -4mA)
• Automotive input with input
shutdown function
• Programmable pull-up resistor
• Vn input or SEG output
R
Automotive input
Standby control
for input shutdown
Vn input or SEG output
M
Pull-up control
P-ch
R
P-ch
Pout
N-ch
Nout
• CMOS level output
(IOL = 4mA, IOH = -4mA)
• CMOS hysteresis input with
input shutdown function
• Programmable pull-up resistor
Hysteresis input
Standby control
for input shutdown
Document Number: 002-04703 Rev.*A
Page 16 of 68
MB96670 Series
Type
N
Circuit
Remarks
Pull-up control
P-ch
P-ch
Pout
N-ch
Nout*
R
• CMOS level output
(IOL = 3mA, IOH = -3mA)
• CMOS hysteresis input with
input shutdown function
• Programmable pull-up resistor
*: N-channel transistor has slew
rate control according to I2C
spec, irrespective of usage.
Hysteresis input
Standby control
for input shutdown
• Open-drain I/O
• Output 25mA, Vcc = 2.7V
• TTL input
O
N-ch
Nout
R
Standby control
for input shutdown
TTL input
P
Pull-up control
P-ch
P-ch
Pout
N-ch
Nout
• CMOS level output
(IOL = 4mA, IOH = -4mA)
• CMOS hysteresis inputs with
input shutdown function
• Programmable pull-up resistor
• SEG or COM output
R
Hysteresis input
Standby control
for input shutdown
SEG or COM output
Document Number: 002-04703 Rev.*A
Page 17 of 68
MB96670 Series
Type
R
Circuit
Remarks
Pull-up control
P-ch
N-ch
P-ch
Pout
N-ch
Nout
• CMOS level output
(programmable IOL = 4mA,
IOH = -4mA and IOL = 30mA,
IOH = -30mA)
• Automotive input with input
shutdown function
• Programmable pull-up /
pull-down resistor
• Analog input
Pull-down control
R
Automotive input
Standby control
for input shutdown
Analog input
Document Number: 002-04703 Rev.*A
Page 18 of 68
MB96670 Series
7. Memory Map
FF:FFFFH
USER ROM*1
DE:0000H
DD:FFFFH
Reserved
10:0000H
0F:C000H
Boot-ROM
Peripheral
0E:9000H
Reserved
01:0000H
00:8000H
RAMSTART0*2
ROM/RAM
MIRROR
Internal RAM
bank0
Reserved
00:0C00H
00:0380H
Peripheral
00:0180H
GPR*3
00:0100H
DMA
00:00F0H
Reserved
00:0000H
Peripheral
*1: For details about USER ROM area, see “User ROM Memory Map For Flash Devices” on the following pages.
*2: For RAMSTART addresses, see the table on the next page.
*3: Unused GPR banks can be used as RAM area.
GPR: General-Purpose Register
The DMA area is only available if the device contains the corresponding resource.
The available RAM and ROM area depends on the device.
Document Number: 002-04703 Rev.*A
Page 19 of 68
MB96670 Series
8. RAMSTART Addresses
Bank 0
RAM size
Devices
MB96F673
MB96F675
4KB
Document Number: 002-04703 Rev.*A
RAMSTART0
00:7200H
Page 20 of 68
MB96670 Series
9. User ROM Memory Map For Flash Devices
CPU mode
address
FF:FFFF H
FF:0000 H
FE:FFFF H
FE:0000 H
FD:FFFF H
Flash memory
mode address
3F:FFFF H
3F:0000 H
3E:FFFF H
3E:0000 H
MB96F673
MB96F675
Flash size
64.5KB + 32KB
Flash size
128.5KB + 32KB
SA39 - 64KB
SA39 - 64KB
Bank A of Flash A
SA38 - 64KB
Reserved
Reserved
DF:A000 H
DF:9FFF H
DF:8000 H
DF:7FFF H
DF:6000 H
DF:5FFF H
DF:4000 H
DF:3FFF H
DF:2000 H
DF:1FFF H
DF:0000 H
DE:FFFF H
DE:0000 H
1F:9FFF H
1F:8000 H
1F:7FFF H
1F:6000 H
1F:5FFF H
1F:4000 H
1F:3FFF H
1F:2000 H
1F:1FFF H
1F:0000 H
SA4 - 8KB
SA4 - 8KB
SA3 - 8KB
SA3 - 8KB
SA2 - 8KB
SA2 - 8KB
SA1 - 8KB
SA1 - 8KB
SAS - 512B*
Reserved
SAS - 512B*
Bank B of Flash A
Bank A of Flash A
Reserved
*: Physical address area of SAS-512B is from DF:0000H to DF:01FFH.
Others (from DF:0200H to DF:1FFFH) is mirror area of SAS-512B.
Sector SAS contains the ROM configuration block RCBA at CPU address DF:0000H -DF:01FFH.
SAS can not be used for E2PROM emulation.
Document Number: 002-04703 Rev.*A
Page 21 of 68
MB96670 Series
10. Serial Programming Communication Interface
USART pins for Flash serial programming (MD = 0, DEBUG I/F = 0, Serial Communication mode)
MB96670
Pin Number
USART Number
29
30
Normal Function
SIN0
USART0
SOT0
31
SCK0
3
SIN1
4
USART1
5
Document Number: 002-04703 Rev.*A
SOT1
SCK1
Page 22 of 68
MB96670 Series
11. Interrupt Vector Table
Vector
number
Offset in
vector table
Index in
ICR to
program
Cleared by
DMA
Vector name
Description
0
3FCH
CALLV0
No
-
CALLV instruction
1
3F8H
CALLV1
No
-
CALLV instruction
2
3F4H
CALLV2
No
-
CALLV instruction
3
3F0H
CALLV3
No
-
CALLV instruction
4
3ECH
CALLV4
No
-
CALLV instruction
5
3E8H
CALLV5
No
-
CALLV instruction
6
3E4H
CALLV6
No
-
CALLV instruction
7
3E0H
CALLV7
No
-
CALLV instruction
8
3DCH
RESET
No
-
Reset vector
9
3D8H
INT9
No
-
INT9 instruction
10
3D4H
EXCEPTION
No
-
Undefined instruction execution
11
3D0H
NMI
No
-
Non-Maskable Interrupt
12
3CCH
DLY
No
12
Delayed Interrupt
13
3C8H
RC_TIMER
No
13
RC Clock Timer
14
3C4H
MC_TIMER
No
14
Main Clock Timer
15
3C0H
SC_TIMER
No
15
Sub Clock Timer
16
3BCH
LVDI
No
16
Low Voltage Detector
17
3B8H
EXTINT0
Yes
17
External Interrupt 0
18
3B4H
EXTINT1
Yes
18
External Interrupt 1
19
3B0H
EXTINT2
Yes
19
External Interrupt 2
20
3ACH
EXTINT3
Yes
20
External Interrupt 3
21
3A8H
EXTINT4
Yes
21
External Interrupt 4
22
3A4H
-
-
22
Reserved
23
3A0H
EXTINT6
Yes
23
External Interrupt 6
24
39CH
EXTINT7
Yes
24
External Interrupt 7
25
398H
-
-
25
Reserved
26
394H
-
-
26
Reserved
27
390H
-
-
27
Reserved
28
38CH
-
-
28
Reserved
29
388H
-
-
29
Reserved
30
384H
-
-
30
Reserved
31
380H
-
-
31
Reserved
32
37CH
-
-
32
Reserved
33
378H
CAN0
No
33
CAN Controller 0
34
374H
-
-
34
Reserved
35
370H
-
-
35
Reserved
36
36CH
-
-
36
Reserved
37
368H
-
-
37
Reserved
38
364H
PPG0
Yes
38
Programmable Pulse Generator 0
39
360H
PPG1
Yes
39
Programmable Pulse Generator 1
Document Number: 002-04703 Rev.*A
Page 23 of 68
MB96670 Series
Vector
number
Offset in
vector table
Index in
ICR to
program
Cleared by
DMA
Vector name
Description
40
35CH
PPG2
Yes
40
Programmable Pulse Generator 2
41
358H
PPG3
Yes
41
Programmable Pulse Generator 3
42
354H
-
-
42
Reserved
43
350H
-
-
43
Reserved
44
34CH
-
-
44
Reserved
45
348H
-
-
45
Reserved
46
344H
-
-
46
Reserved
47
340H
-
-
47
Reserved
48
33CH
-
-
48
Reserved
49
338H
-
-
49
Reserved
50
334H
-
-
50
Reserved
51
330H
-
-
51
Reserved
52
32CH
-
-
52
Reserved
53
328H
-
-
53
Reserved
54
324H
-
-
54
Reserved
55
320H
-
-
55
Reserved
56
31CH
-
-
56
Reserved
57
318H
-
-
57
Reserved
58
314H
-
-
58
Reserved
59
310H
RLT1
Yes
59
Reload Timer 1
60
30CH
RLT2
Yes
60
Reload Timer 2
61
308H
-
-
61
Reserved
62
304H
-
-
62
Reserved
63
300H
-
-
63
Reserved
64
2FCH
RLT6
Yes
64
Reload Timer 6
65
2F8H
ICU0
Yes
65
Input Capture Unit 0
66
2F4H
ICU1
Yes
66
Input Capture Unit 1
67
2F0H
-
-
67
Reserved
68
2ECH
-
-
68
Reserved
69
2E8H
ICU4
Yes
69
Input Capture Unit 4
70
2E4H
ICU5
Yes
70
Input Capture Unit 5
71
2E0H
-
-
71
Reserved
72
2DCH
-
-
72
Reserved
73
2D8H
-
-
73
Reserved
74
2D4H
-
-
74
Reserved
75
2D0H
-
-
75
Reserved
76
2CCH
-
-
76
Reserved
77
2C8H
-
-
77
Reserved
78
2C4H
-
-
78
Reserved
79
2C0H
-
-
79
Reserved
80
2BCH
-
-
80
Reserved
Document Number: 002-04703 Rev.*A
Page 24 of 68
MB96670 Series
Vector
number
Offset in
vector table
Index in
ICR to
program
Cleared by
DMA
Vector name
Description
81
2B8H
-
-
81
Reserved
82
2B4H
-
-
82
Reserved
83
2B0H
-
-
83
Reserved
84
2ACH
-
-
84
Reserved
85
2A8H
-
-
85
Reserved
86
2A4H
-
-
86
Reserved
87
2A0H
-
-
87
Reserved
88
29CH
-
-
88
Reserved
89
298H
FRT0
Yes
89
Free-Running Timer 0
90
294H
FRT1
Yes
90
Free-Running Timer 1
91
290H
-
-
91
Reserved
92
28CH
-
-
92
Reserved
93
288H
RTC0
No
93
Real Time Clock
94
284H
CAL0
No
94
Clock Calibration Unit
95
280H
SG0
No
95
Sound Generator 0
96
27CH
IIC0
Yes
96
I2C interface 0
97
278H
-
-
97
Reserved
98
274H
ADC0
Yes
98
A/D Converter 0
99
270H
-
-
99
Reserved
100
26CH
-
-
100
Reserved
101
268H
LINR0
Yes
101
LIN USART 0 RX
102
264H
LINT0
Yes
102
LIN USART 0 TX
103
260H
LINR1
Yes
103
LIN USART 1 RX
104
25CH
LINT1
Yes
104
LIN USART 1 TX
105
258H
-
-
105
Reserved
106
254H
-
-
106
Reserved
107
250H
-
-
107
Reserved
108
24CH
-
-
108
Reserved
109
248H
-
-
109
Reserved
110
244H
-
-
110
Reserved
111
240H
-
-
111
Reserved
112
23CH
-
-
112
Reserved
113
238H
-
-
113
Reserved
114
234H
-
-
114
Reserved
115
230H
-
-
115
Reserved
116
22CH
-
-
116
Reserved
117
228H
-
-
117
Reserved
118
224H
-
-
118
Reserved
119
220H
-
-
119
Reserved
120
21CH
-
-
120
Reserved
Document Number: 002-04703 Rev.*A
Page 25 of 68
MB96670 Series
121
218H
-
-
Index in
ICR to
program
121
122
214H
-
-
122
Reserved
123
210H
-
-
123
Reserved
124
20CH
-
-
124
Reserved
125
208H
-
-
125
Reserved
126
204H
-
-
126
Reserved
127
200H
-
-
127
Reserved
128
1FCH
-
-
128
Reserved
129
1F8H
-
-
129
Reserved
130
1F4H
-
-
130
Reserved
131
1F0H
-
-
131
Reserved
132
1ECH
-
-
132
Reserved
133
1E8H
FLASHA
Yes
133
Flash memory A interrupt
134
1E4H
-
-
134
Reserved
135
1E0H
-
-
135
Reserved
136
1DCH
-
-
136
Reserved
137
1D8H
-
-
137
Reserved
138
1D4H
-
-
138
Reserved
139
1D0H
ADCRC0
No
139
A/D Converter 0 - Range Comparator
140
1CCH
ADCPD0
No
140
A/D Converter 0 - Pulse detection
141
1C8H
-
-
141
Reserved
142
1C4H
-
-
142
Reserved
143
1C0H
-
-
143
Reserved
Vector
number
Offset in
vector table
Document Number: 002-04703 Rev.*A
Cleared by
DMA
Vector name
Description
Reserved
Page 26 of 68
MB96670 Series
12. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
12.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-04703 Rev.*A
Page 27 of 68
MB96670 Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
12.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-04703 Rev.*A
Page 28 of 68
MB96670 Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
12.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin
to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-04703 Rev.*A
Page 29 of 68
MB96670 Series
13. Handling Devices
Special care is required for the following when handling the device:
•
•
•
•
•
•
•
•
•
•
•
•
•
Latch-up prevention
Unused pins handling
External clock usage
Notes on PLL clock mode operation
Power supply pins (Vcc/Vss)
Crystal oscillator and ceramic resonator circuit
Turn on sequence of power supply to A/D converter and analog inputs
Pin handling when not using the A/D converter
Notes on Power-on
Stabilization of power supply voltage
SMC power supply pins
Serial communication
Mode Pin (MD)
13.1 Latch-up prevention
CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between Vcc pins and Vss pins.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current dramatically, causing thermal damages to the device.
For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed the digital
power-supply voltage.
13.2 Unused pins handling
Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register
PIER = 0).
Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent
damage of the device. To prevent latch-up, they must therefore be pulled up or pulled down through resistors which should be more
than 2k.
Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with
either input disabled or external pull-up/pull-down resistor as described above.
Document Number: 002-04703 Rev.*A
Page 30 of 68
MB96670 Series
13.3 External clock usage
The permitted frequency range of an external clock depends on the oscillator type and configuration.
See AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be connected as
follows:
13.3.1 Single phase external clock for Main oscillator
When using a single phase external clock for the Main oscillator, X0 pin must be driven and X1 pin left open.
And supply 1.8V power to the external clock.
X0
X1
13.3.2 Single phase external clock for Sub oscillator
When using a single phase external clock for the Sub oscillator, “External clock mode” must be selected and
X0A/P04_0 pin must be driven. X1A/P04_1 pin can be configured as GPIO.
13.3.3 Opposite phase external clock
When using an opposite phase external clock, X1 (X1A) pins must be supplied with a clock signal which has
the opposite phase to the X0 (X0A) pins. Supply level on X0 and X1 pins must be 1.8V.
X0
X1
13.4 Notes on PLL clock mode operation
If the microcontroller is operated with PLL clock mode and no external oscillator is operating or no external clock is supplied, the
microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed.
13.5 Power supply pins (Vcc/Vss)
It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or
VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range.
Vcc and Vss pins must be connected to the device from the power supply with lowest possible impedance.
The smoothing capacitor at Vcc pin must use the one of a capacity value that is larger than Cs.
Besides this, as a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1F between Vcc
and Vss pins as close as possible to Vcc and Vss pins.
Document Number: 002-04703 Rev.*A
Page 31 of 68
MB96670 Series
13.6 Crystal oscillator and ceramic resonator circuit
Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest
possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost
effort, that the lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area
for stabilizing the operation.
It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer, especially
when using low-Q resonators at higher frequencies.
13.7 Turn on sequence of power supply to A/D converter and analog inputs
It is required to turn the A/D converter power supply (AVCC, AVRH) and analog inputs (ANn) on after turning the digital power supply
(VCC) on.
It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, AVRH must
not exceed AVCC . Input voltage for ports shared with analog input ports also must not exceed AVCC (turning the analog and digital
power supplies simultaneously on or off is acceptable).
13.8 Pin handling when not using the A/D converter
If the A/D converter is not used, the power supply pins for A/D converter should be connected such as AVCC = VCC , AVSS = AVRH =
VSS.
13.9 Notes on Power-on
To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower
than 50s from 0.2V to 2.7V.
13.10 Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation safety range of the VCC power supply voltage, a malfunction may
occur. The VCC power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must be
stabilized in such a way that VCC ripple fluctuations (peak to peak value) in the commercial frequencies (50Hz to 60Hz) fall within
10% of the standard VCC power supply voltage and the transient fluctuation rate becomes 0.1V/s or less in instantaneous
fluctuation for power supply switching.
13.11 SMC power supply pins
All DVcc /DVss pins must be set to the same level as the Vcc /Vss pins.
Note that the SMC I/O pin state is undefined if DVCC is powered on and VCC is below 3V. To avoid this, VCC must always be powered
on before DVCC.
DVcc/DVss must be applied when using SMC I/O pin as GPIO.
13.12 Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit
the data if an error occurs.
13.13 Mode Pin (MD)
Connect the mode pin directly to Vcc or Vss pin. To prevent the device unintentionally entering test mode due to noise, lay out the
printed circuit board so as to minimize the distance from the mode pin to Vcc or Vss pin and provide a low-impedance connection.
Document Number: 002-04703 Rev.*A
Page 32 of 68
MB96670 Series
14. Electrical Characteristics
14.1 Absolute Maximum Ratings
Parameter
Power supply
voltage*1
Analog power supply
voltage*1
Analog reference
voltage*1
SMC Power supply*1
LCD power supply
voltage*1
Input voltage*1
Output voltage*1
Maximum Clamp
Current
Total Maximum
Clamp Current
"L" level maximum
output current
Symbol
"L" level maximum
overall output current
"L" level average
overall output current
"H" level maximum
output current
"H" level maximum
overall output current
"H" level average
overall output current
Power
consumption*5
Operating ambient
temperature
Storage temperature
Max
Unit
Remarks
-
VSS - 0.3
VSS + 6.0
V
AVCC
-
VSS - 0.3
VSS + 6.0
V
AVRH
-
VSS - 0.3
VSS + 6.0
V
DVCC
-
VSS - 0.3
VSS + 6.0
V
V0 to V3
-
VSS - 0.3
VSS + 6.0
V
VI
VO
-
VSS - 0.3
VSS - 0.3
VSS + 6.0
VSS + 6.0
V
V
ICLAMP
-
-4.0
+4.0
mA
Σ|ICLAMP|
-
-
16
mA
IOL
TA= -40°C
TA= +25°C
TA= +85°C
TA= +105°C
TA= -40°C
TA= +25°C
TA= +85°C
TA= +105°C
TA= -40°C
TA= +25°C
TA= +85°C
TA= +105°C
TA= -40°C
TA= +25°C
TA= +85°C
TA= +105°C
-
-
15
52
39
32
30
4
40
30
25
23
34
180
17
90
-15
-52
-39
-32
-30
-4
-40
-30
-25
-23
-34
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-
-
-180
mA
High current port
-
-
-17
mA
Normal port
-
-
-90
mA
High current port
IOLSMC
IOLAVSMC
ΣIOL
ΣIOLSMC
ΣIOLAV
ΣIOLAVSMC
IOH
IOHSMC
IOHAV
"H" level average
output current
Min
VCC
IOLAV
"L" level average
output current
Rating
Condition
IOHAVSMC
ΣIOH
ΣIOHSMC
ΣIOHAV
ΣIOHAVSMC
*6
PD
TA= +105°C
-
281
mW
TA
-
-40
+105
°C
TSTG
-
-55
+150
°C
Document Number: 002-04703 Rev.*A
VCC = AVCC*2
AVCC ≥ AVRH,
AVRH ≥ AVSS
VCC = AVCC= DVCC*2
V0 to V3 must not
exceed VCC
VI ≤ (D)VCC + 0.3V*3
VO ≤ (D)VCC + 0.3V*3
Applicable to general
purpose I/O pins *4
Applicable to general
purpose I/O pins *4
Normal port
High current port
Normal port
High current port
Normal port
High current port
Normal port
High current port
Normal port
High current port
Normal port
High current port
Normal port
Page 33 of 68
MB96670 Series
*1
: This parameter is based on VSS = AVSS = DVSS = 0V.
*2
: AVCC and VCC and DVCC must be set to the same voltage. It is required that AVCC does not exceed VCC, DVCC and that the
voltage at the analog inputs does not exceed AVCC when the power is switched on.
*3
: VI and VO should not exceed VCC + 0.3V. VI should also not exceed the specified ratings. However if the maximum current
to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/Output
voltages of high current ports depend on DVCC. Input/Output voltages of standard ports depend on VCC.
*4
: Applicable to all general purpose I/O pins (Pnn_m).
•
•
•
•
•
•
•
•
•
Use within recommended operating conditions.
Use at DC voltage (current).
The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the
microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass
through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0V), the power supply is provided
from the pins, so that incomplete operation may result.
Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply
voltage may not be sufficient to operate the Power reset.
The DEBUG I/F pin has only a protective diode against VSS. Hence it is only permitted to input a negative clamping current
(4mA). For protection against positive input voltages, use an external clamping diode which limits the input voltage to
maximum 6.0V.
Sample recommended circuits:
Protective diode
VCC
Limiting
resistance
P-ch
+B input (0V to 16V)
N-ch
R
*5
: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal
conductance of the package on the PCB.
The actual power dissipation depends on the customer application and can be calculated as follows:
PD = PIO + PINT
PIO = Σ (VOL IOL + VOH IOH) (I/O load power dissipation, sum is performed on all I/O ports)
PINT = VCC (ICC + IA) (internal power dissipation)
ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the selected operation
mode and clock frequency and the usage of functions like Flash programming.
IA is the analog current consumption into AVCC.
*6
: Worst case value for a package mounted on single layer PCB at specified TA without air flow.
WARNING
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-04703 Rev.*A
Page 34 of 68
MB96670 Series
14.2 Recommended Operating Conditions
(VSS = AVSS = DVSS = 0V)
Parameter
Symbol
Power supply
voltage
VCC,
AVCC,
DVCC
Smoothing capacitor
at C pin
CS
Value
Min
2.7
Typ
-
Max
5.5
2.0
-
5.5
0.5
1.0 to 3.9
4.7
Unit
Remarks
V
V
Maintains RAM data in stop mode
F
1.0F (Allowance within ± 50%)
3.9µF (Allowance within ± 20%)
Please use the ceramic capacitor or the
capacitor of the frequency response of this
level.
The smoothing capacitor at VCC must use the
one of a capacity value that is larger than CS.
WARNING
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the
device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may
adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or
combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Document Number: 002-04703 Rev.*A
Page 35 of 68
MB96670 Series
14.3 DC Characteristics
14.3.1
Current Rating
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
Conditions
PLL Run mode with CLKS1/2 =
CLKB = CLKP1/2 = 32MHz
ICCPLL
Main Run mode with CLKS1/2 =
CLKB = CLKP1/2 = 4MHz
ICCMAIN
Unit
Remarks
-
25
-
mA
TA = +25°C
-
-
34
mA
TA = +105°C
-
3.5
-
mA
TA = +25°C
-
-
7.5
mA
TA = +105°C
-
1.7
-
mA
TA = +25°C
-
-
5.5
mA
TA = +105°C
-
0.15
-
mA
TA = +25°C
-
-
3.2
mA
TA = +105°C
-
0.1
-
mA
TA = +25°C
-
-
3
mA
TA = +105°C
Flash 0 wait
(CLKPLL, CLKSC and CLKRC
stopped)
RC Run mode with CLKS1/2 =
CLKB = CLKP1/2 = CLKRC =
2MHz
ICCRCH
Max
Flash 0 wait
(CLKRC and CLKSC stopped)
Power supply
current in Run
*1
modes
Value
Typ
Min
Vcc
Flash 0 wait
(CLKMC, CLKPLL and CLKSC
stopped)
RC Run mode with CLKS1/2 =
CLKB = CLKP1/2 = CLKRC =
100kHz
ICCRCL
Flash 0 wait
(CLKMC, CLKPLL and CLKSC
stopped)
Sub Run mode with CLKS1/2 =
CLKB = CLKP1/2 = 32kHz
ICCSUB
Flash 0 wait
(CLKMC, CLKPLL and CLKRC
stopped)
Document Number: 002-04703 Rev.*A
Page 36 of 68
MB96670 Series
Parameter
Symbol
Pin
name
PLL Sleep mode with
CLKS1/2 = CLKP1/2 =
32MHz
(CLKRC and CLKSC
stopped)
ICCSPLL
ICCSRCH
ICCSRCL
ICCSSUB
Vcc
ICCTPLL
ICCTMAIN
Power supply
current in
Timer modes*2
ICCTRCH
ICCTRCL
ICCTSUB
Document Number: 002-04703 Rev.*A
Value
Typ
Min
Max
Unit
Remarks
-
6.5
-
mA
TA = +25°C
-
-
13
mA
TA = +105°C
-
0.9
-
mA
TA = +25°C
-
-
4
mA
TA = +105°C
-
0.5
-
mA
TA = +25°C
-
-
3.5
mA
TA = +105°C
-
0.06
-
mA
TA = +25°C
-
-
2.7
mA
TA = +105°C
-
0.04
-
mA
TA = +25°C
-
-
2.5
mA
TA = +105°C
-
1800
2245
A
TA = +25°C
-
-
3140
A
TA = +105°C
-
285
325
A
TA = +25°C
-
-
1055
A
TA = +105°C
-
160
210
A
TA = +25°C
-
-
970
A
TA = +105°C
RC Timer mode with
CLKRC = 100kHz
(CLKPLL, CLKMC and
CLKSC stopped)
-
30
70
A
TA = +25°C
-
-
820
A
TA = +105°C
Sub Timer mode with
CLKSC = 32kHz
(CLKMC, CLKPLL and
CLKRC stopped)
-
25
55
A
TA = +25°C
-
-
800
A
TA = +105°C
Main Sleep mode with
CLKS1/2 = CLKP1/2 =
4MHz,
SMCR:LPMSS = 0
(CLKPLL, CLKRC and
CLKSC stopped)
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
CLKRC = 2MHz,
SMCR:LPMSS = 0
(CLKMC, CLKPLL and
CLKSC stopped)
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
CLKRC = 100kHz
(CLKMC, CLKPLL and
CLKSC stopped)
ICCSMAIN
Power supply
current in Sleep
modes*1
Conditions
Sub Sleep mode with
CLKS1/2 = CLKP1/2 =
32kHz,
(CLKMC, CLKPLL and
CLKRC stopped)
PLL Timer mode with
CLKPLL = 32MHz (CLKRC
and CLKSC stopped)
Main Timer mode with
CLKMC = 4MHz,
SMCR:LPMSS = 0
(CLKPLL, CLKRC and
CLKSC stopped)
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 0
(CLKPLL, CLKMC and
CLKSC stopped)
Page 37 of 68
MB96670 Series
Parameter
Symbol
Power supply current
in Stop mode*3
ICCH
Flash Power Down
current
ICCFLASHPD
Power supply current
for active Low
Voltage detector*4
ICCLVD
Flash Write/
Erase current*5
ICCFLASH
Pin
name
Conditions
Max
Unit
Remarks
-
20
55
A
TA = +25°C
-
-
800
A
TA = +105°C
-
-
36
70
A
Low voltage detector
enabled
-
5
-
A
TA = +25°C
-
-
12.5
A
TA = +105°C
-
12.5
-
mA
TA = +25°C
-
-
20
mA
TA = +105°C
-
Vcc
Value
Typ
Min
-
*1
: The power supply current is measured with a 4MHz external clock connected to the Main oscillator and
a 32kHz external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of the
Hardware Manual for further details about voltage regulator control. Current for "On Chip Debugger" part is not included. Power
supply current in Run mode does not include Flash Write / Erase current.
*2
: The power supply current in Timer mode is the value when Flash is in Power-down / reset mode.
When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current.
The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock
connected to the Sub oscillator. The current for "On Chip Debugger" part is not included.
*3
: The power supply current in Stop mode is the value when Flash is in Power-down / reset mode.
When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current.
*4
: When low voltage detector is enabled, ICCLVD must be added to Power supply current.
*5
: When Flash Write / Erase program is executed, ICCFLASH must be added to Power supply current.
Document Number: 002-04703 Rev.*A
Page 38 of 68
MB96670 Series
14.3.2
Pin Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
"H" level
input voltage
"L" level input
voltage
Symbol
Pin name
VIH
Port
inputs
Pnn_m
Conditions
External clock in
"Fast Clock Input mode"
External clock in
"Oscillation mode"
VIHX0S
X0
VIHX0AS
X0A
VIHR
RSTX
-
VIHM
MD
-
VIHD
DEBUG
I/F
-
VIL
Port
inputs
Pnn_m
External clock in "Fast Clock
Input mode"
External clock in
"Oscillation mode"
VILX0S
X0
VILX0AS
X0A
VILR
RSTX
-
VILM
MD
-
VILD
DEBUG
I/F
-
Document Number: 002-04703 Rev.*A
Min
VCC
0.7
VCC
0.8
VD
0.8
VCC
0.8
VCC
0.8
VCC
- 0.3
2.0
VSS
- 0.3
VSS
- 0.3
VSS
VSS
- 0.3
VSS
- 0.3
VSS
- 0.3
VSS
- 0.3
Value
Typ
-
Max
VCC
+ 0.3
VCC
+ 0.3
VD
VCC
+ 0.3
VCC
+ 0.3
VCC
+ 0.3
VCC
+ 0.3
VCC
0.3
VCC
0.5
VD
0.2
VCC
0.2
VCC
0.2
VSS
+ 0.3
0.8
Unit
V
V
V
Remarks
CMOS Hysteresis
input
AUTOMOTIVE
Hysteresis input
VD=1.8V±0.15V
V
V
V
V
V
V
V
CMOS Hysteresis
input
CMOS Hysteresis
input
TTL Input
CMOS Hysteresis
input
AUTOMOTIVE
Hysteresis input
VD=1.8V±0.15V
V
V
V
V
CMOS Hysteresis
input
CMOS Hysteresis
input
TTL Input
Page 39 of 68
MB96670 Series
Parameter
Symbol
VOH4
"H" level
output
voltage
"L" level
output
voltage
VOH30
Pin name
4mA type
High
Drive
type*
VOH3
3mA type
VOL4
4mA type
VOL30
High
Drive
*
type
VOL3
3mA type
VOLD
DEBUG
I/F
Document Number: 002-04703 Rev.*A
Conditions
4.5V ≤ (D)VCC ≤ 5.5V
IOH = -4mA
2.7V ≤ (D)VCC < 4.5V
IOH = -1.5mA
4.5V ≤ DVCC ≤ 5.5V
IOH = -52mA
2.7V ≤ DVCC < 4.5V
IOH = -18mA
4.5V ≤ DVCC ≤ 5.5V
IOH = -39mA
2.7V ≤ DVCC < 4.5V
IOH = -16mA
4.5V ≤ DVCC ≤ 5.5V
IOH = -32mA
2.7V ≤ DVCC < 4.5V
IOH = -14.5mA
4.5V ≤ DVCC ≤ 5.5V
IOH = -30mA
2.7V ≤ DVCC < 4.5V
IOH = -14mA
4.5V ≤ VCC ≤ 5.5V
IOH = -3mA
2.7V ≤ VCC < 4.5V
IOH = -1.5mA
4.5V ≤ (D)VCC ≤ 5.5V
IOL = +4mA
2.7V ≤ (D)VCC < 4.5V
IOL = +1.7mA
4.5V ≤ DVCC ≤ 5.5V
IOL = +52mA
2.7V ≤ DVCC < 4.5V
IOL = +22mA
4.5V ≤ DVCC ≤ 5.5V
IOL = +39mA
2.7V ≤ DVCC < 4.5V
IOL = +18mA
4.5V ≤ DVCC ≤ 5.5V
IOL = +32mA
2.7V ≤ DVCC < 4.5V
IOL = +14mA
4.5V ≤ DVCC ≤ 5.5V
IOL = +30mA
2.7V ≤ DVCC < 4.5V
IOL = +13.5mA
2.7V ≤ VCC < 5.5V
IOL = +3mA
VCC = 2.7V
IOL = +25mA
Min
(D)VCC
- 0.5
Value
Typ
-
Max
(D)VCC
Unit
Remarks
V
TA = -40°C
TA = +25°C
DVCC
- 0.5
-
DVCC
V
TA = +85°C
TA = +105°C
VCC
- 0.5
-
VCC
V
-
-
0.4
V
TA = -40°C
TA = +25°C
-
-
0.5
V
TA = +85°C
TA = +105°C
-
-
0.4
V
0
-
0.25
V
Page 40 of 68
MB96670 Series
Parameter
Symbol
Pin name
Conditions
Min
Value
Typ
Max
Unit
Remarks
Single port pin
except high current
output I/O for SMC
Pnn_m
VSS < VI < VCC
AVSS < VI <
AVCC, AVRH
-1
-
+1
A
P08_m
DVSS < VI < DVCC
AVSS < VI <
AVCC, AVRH
-3
-
+3
A
Σ|IILCD|
All SEG/
COM pin
VCC = 5.0V
-
0.5
10
A
Internal LCD
divide
resistance
RLCD
Between
V3 and V2,
V2 and V1,
V1 and V0
VCC = 5.0V
6.25
12.5
25
k
Pull-up
resistance
value
RPU
Pnn_m
VCC = 5.0V ±10%
25
50
100
k
Pull-down
resistance
value
RDOWN
P08_m
VCC = 5.0V ±10%
25
50
100
k
Other than
C,
Vcc,
Vss,
DVcc
DVss,
AVcc,
AVss,
AVRH,
P08_m
-
-
5
15
pF
P08_m
-
-
15
30
pF
Input leak
current
Total LCD
leak current
Input
capacitance
IIL
CIN
Maximum leakage
current of all LCD
pins
*: In the case of driving stepping motor directly or high current outputs, set "1" to the bit in the Port High Drive Register
(PHDRnn:HDx="1").
Document Number: 002-04703 Rev.*A
Page 41 of 68
MB96670 Series
14.4 AC Characteristics
14.4.1
Main Clock Input Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VD=1.8V±0.15V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input frequency
Symbol
fC
Pin name
X0,
X1
fFCI
Unit
Max
4
-
8
MHz
-
-
8
MHz
4
-
8
MHz
Input frequency
Value
Typ
Min
-
8
When using a crystal
oscillator, PLL off
When using an opposite
phase external
clock, PLL off
When using a crystal
oscillator or opposite
phase external clock, PLL
on
MHz
When using a single phase
external
clock in “Fast Clock Input
mode”, PLL off
When using a single phase
external
clock in “Fast Clock Input
mode”, PLL on
X0
4
-
8
MHz
Input clock cycle
tCYLH
-
125
-
-
ns
Input clock pulse width
PWH,
PWL
-
55
-
-
ns
Document Number: 002-04703 Rev.*A
Remarks
Page 42 of 68
MB96670 Series
14.4.2
Sub Clock Input Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input frequency
Pin
name
Symbol
fCL
Value
Conditions
Min
Typ
Max
Unit
-
-
32.768
-
kHz
-
-
-
100
kHz
X0A
-
-
-
50
kHz
X0A,
X1A
Input clock cycle
tCYLL
-
-
10
-
-
s
Input clock pulse
width
-
-
PWH/tCYLL,
PWL/tCYLL
30
-
70
%
Document Number: 002-04703 Rev.*A
Remarks
When using an
oscillation circuit
When using an
opposite phase
external clock
When using a single
phase external clock
Page 43 of 68
MB96670 Series
14.4.3
Built-in RC Oscillation Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Clock frequency
RC clock stabilization
time
14.4.4
Value
Symbol
Min
Typ
Unit
Max
50
100
200
kHz
1
2
4
MHz
80
160
320
s
64
128
256
s
Remarks
When using slow frequency of RC
oscillator
When using fast frequency of RC
oscillator
When using slow frequency of RC
oscillator
(16 RC clock cycles)
When using fast frequency of RC
oscillator
(256 RC clock cycles)
fRC
tRCSTAB
Internal Clock Timing
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Value
Symbol
Min
Max
Unit
Internal System clock frequency
(CLKS1 and CLKS2)
fCLKS1, fCLKS2
-
54
MHz
Internal CPU clock frequency (CLKB),
Internal peripheral clock frequency (CLKP1)
fCLKB, fCLKP1
-
32
MHz
Internal peripheral clock frequency (CLKP2)
fCLKP2
-
32
MHz
Document Number: 002-04703 Rev.*A
Page 44 of 68
MB96670 Series
14.4.5
Operating Conditions of PLL
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Min
Typ
Unit
Max
Remarks
PLL oscillation stabilization wait time
tLOCK
1
-
4
ms
PLL input clock frequency
fPLLI
4
-
8
MHz
PLL oscillation clock frequency
fCLKVCO
56
-
108
MHz
Permitted VCO output
frequency of PLL (CLKVCO)
PLL phase jitter
tPSKEW
-5
-
+5
ns
For CLKMC (PLL input clock)
≥ 4MHz
14.4.6
For CLKMC = 4MHz
Reset Input
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Reset input time
tRSTL
Value
Pin name
Min
10
-
s
1
-
s
RSTX
Rejection of reset input time
Unit
Max
tRSTL
RSTX
0.2VCC
Document Number: 002-04703 Rev.*A
0.2VCC
Page 45 of 68
MB96670 Series
14.4.7
Power-on Reset Timing
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Power on rise time
Power off time
Symbol
tR
tOFF
Document Number: 002-04703 Rev.*A
Pin name
Vcc
Vcc
Value
Min
0.05
1
Typ
-
Unit
Max
30
-
ms
ms
Page 46 of 68
MB96670 Series
14.4.8
USART Timing
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C, CL=50pF)
Serial clock cycle time
Symbo
l
tSCYC
SCK SOT delay time
tSLOVI
SOT SCK delay time
tOVSHI
SIN SCK setup time
tIVSHI
SCK SIN hold time
tSHIXI
Serial clock "L" pulse width
tSLSH
SCKn
Serial clock "H" pulse width
tSHSL
SCKn
SCK SOT delay time
tSLOVE
Parameter
SIN SCK setup time
tIVSHE
SCK SIN hold time
tSHIXE
SCK fall time
SCK rise time
tF
tR
Pin
name
SCKn
SCKn
,
SOTn
SCKn
,
SOTn
SCKn
,
SINn
SCKn
,
SINn
SCKn
,
SOTn
SCKn
,
SINn
SCKn
,
SINn
SCKn
SCKn
Conditions
Internal shift
clock mode
4.5V VCC 5.5V
Min
Max
4tCLKP1
-
2.7V VCC 4.5V
Min
Max
4tCLKP1
-
Uni
t
ns
- 20
+ 20
- 30
+ 30
ns
NtCLKP1
– 20*
-
NtCLKP1
– 30*
-
ns
tCLKP1
+ 45
-
tCLKP1
+ 55
-
ns
0
-
0
-
ns
-
ns
-
ns
tCLKP1
+ 10
tCLKP1
+ 10
External
shift
clock mode
-
tCLKP1
+ 10
tCLKP1
+ 10
-
2tCLKP1
+ 45
-
2tCLKP1
+ 55
ns
tCLKP1/2
+ 10
-
tCLKP1/2
+ 10
-
ns
tCLKP1
+ 10
-
tCLKP1
+ 10
-
ns
-
20
20
-
20
20
ns
ns
Notes:
• AC characteristic in CLK synchronized mode.
• CL is the load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by
some parameters. These parameters are shown in “MB96600 series HARDWARE MANUAL”.
• tCLKP1 indicates the peripheral clock 1 (CLKP1), Unit: ns
• These characteristics only guarantee the same relocate port number.
For example, the combination of SCKn and SOTn_R is not guaranteed.
*: Parameter N depends on tSCYC and can be calculated as follows:
• If tSCYC = 2 k tCLKP1, then N = k, where k is an integer > 2
• If tSCYC = (2 k + 1) tCLKP1, then N = k + 1, where k is an integer > 1
Examples:
tSCYC
N
4 tCLKP1
2
5 tCLKP1, 6 tCLKP1
3
7 tCLKP1, 8 tCLKP1
4
…
…
Document Number: 002-04703 Rev.*A
Page 47 of 68
MB96670 Series
tSCYC
VOH
SCK
VOL
VOL
tOVSHI
tSLOVI
VOH
SOT
VOL
tIVSHI
SIN
tSHIXI
VIH
VIH
VIL
VIL
Internal shift clock mode
SCK
tSHSL
tSLSH
VIH
VIH
VIL
tF
SOT
VIL
VIH
tR
tSLOVE
VOH
VOL
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
External shift clock mode
Document Number: 002-04703 Rev.*A
Page 48 of 68
MB96670 Series
14.4.9
External Input Timing
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Pin name
Min
Max
Unit
Pnn_m
General Purpose I/O
ADTG
A/D Converter trigger input
2tCLKP1 +200
(tCLKP1=
1/fCLKP1)*
-
TINn, TINn_R
TTGn
INn, INn_R
INTn, INTn_R
200
NMI
*: tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time except stop when in stop mode.
Input pulse width
tINH,
tINL
tINH
External input timing
VIH
ns
ns
Reload Timer
PPG trigger input
Input Capture
External Interrupt
Non-Maskable Interrupt
tINL
VIH
VIL
Document Number: 002-04703 Rev.*A
Remarks
VIL
Page 49 of 68
MB96670 Series
14.4.10 I2C Timing
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
fSCL
Typical mode
Min
Max
0
100
High-speed mode*4
Min
Max
0
400
kHz
tHDSTA
4.0
-
0.6
-
s
tLOW
tHIGH
4.7
4.0
-
1.3
0.6
-
s
s
4.7
-
0.6
-
s
0
3.45*2
0
0.9*3
s
tSUDAT
250
-
100
-
ns
tSUSTO
4.0
-
0.6
-
s
tBUS
4.7
-
1.3
-
s
0
(1-1.5)
tCLKP1*5
0
(1-1.5)
tCLKP1*5
ns
Symbol
SCL clock frequency
(Repeated) START condition hold
time
SDA SCL
SCL clock "L" width
SCL clock "H" width
(Repeated) START condition setup
time
SCL SDA
Data hold time
SCL SDA
Data setup time
SDA SCL
STOP condition setup time
SCL SDA
Bus free time between
"STOP condition" and
"START condition"
Pulse width of spikes which will be
suppressed by input noise filter
Conditions
tSUSTA
CL = 50pF,
R = (Vp/IOL)*1
tHDDAT
tSP
-
*1
: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2
: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal.
*3
: A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the
requirement of "tSUDAT ≥ 250ns".
*4
: For use at over 100kHz, set the peripheral clock1 (CLKP1) to at least 6MHz.
*5
: tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time.
Unit
SDA
tSUDAT
tSUSTA
tBUS
tLOW
SCL
tHDSTA
Document Number: 002-04703 Rev.*A
tHDDAT
tHIGH
tHDSTA
tSP
tSUSTO
Page 50 of 68
MB96670 Series
14.5 A/D Converter
14.5.1
Electrical Characteristics for the A/D Converter
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Value
Typ
Symbol
Pin name
Resolution
-
-
-
-
10
bit
Total error
-
-
- 3.0
-
+ 3.0
LSB
Nonlinearity error
-
-
- 2.5
-
+ 2.5
LSB
Differential
Nonlinearity error
-
-
- 1.9
-
+ 1.9
LSB
Zero transition
voltage
VOT
ANn
Typ - 20
AVSS
+ 0.5LSB
Typ + 20
mV
Full scale transition
voltage
VFST
ANn
Typ - 20
Typ + 20
mV
Compare time*
-
-
Sampling time*
-
-
5.0
8.0
3.1
s
s
s
s
mA
Power supply
current
Reference power
supply current
(between AVRH
and AVSS )
Unit
-
-
3.3
A
-
520
810
A
A/D Converter active
-
-
1.0
A
A/D Converter not
operated
-
-
15.5
pF
Normal outputs
-
-
17.4
pF
High current outputs
-
-
1450
2700
4.5V ≤ AVCC ≤ 5.5V
2.7V ≤ AVCC < 4.5V
- 1.0
-
+ 1.0
A
- 3.0
-
+ 3.0
A
ANn
AVSS
-
AVRH
V
AVRH
AVCC
- 0.1
-
AVCC
V
ANn
-
-
4.0
LSB
AVCC
IR
AVRH
IRH
AN8, 9,
12, 13
AN16 to
23
CVIN
Analog impedance
RVIN
ANn
IAIN
AN8, 9,
12, 13
AN16 to
23
Analog input
VAIN
voltage
Reference voltage
range
Variation between
channels
*: Time for each channel.
Document Number: 002-04703 Rev.*A
Remarks
1.0
2.2
0.5
1.2
-
Analog input
capacity
Analog port input
current (during
conversion)
Max
AVRH
- 1.5LSB
2.0
IA
IAH
Min
4.5V ≤ ΑVCC ≤ 5.5V
2.7V ≤ ΑVCC 4.5V
4.5V ≤ ΑVCC ≤ 5.5V
2.7V ≤ ΑVCC 4.5V
A/D Converter active
A/D Converter not
operated
AVSS VAIN
AVCC, AVRH
Page 51 of 68
MB96670 Series
14.5.2 Accuracy and Setting of the A/D Converter Sampling Time
If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal sample and hold
capacitor is insufficient, adversely affecting the A/D conversion precision.
To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling time (Tsamp) depends
on the external driving impedance Rext, the board capacitance of the A/D converter input pin Cext and the AVCC voltage level. The
following replacement model can be used for the calculation:
MCU
Rext
Analog
input
RVIN
Source
Comparator
Cext
CVIN
Sampling switch
(During sampling:ON)
Rext: External driving impedance
Cext: Capacitance of PCB at A/D converter input
CVIN: Analog input capacity (I/O, analog switch and ADC are contained)
RVIN: Analog input impedance (I/O, analog switch and ADC are contained)
The following approximation formula for the replacement model above can be used:
Tsamp = 7.62 × (Rext × Cext + (Rext + RVIN) × CVIN)
• Do not select a sampling time below the absolute minimum permitted value.
(0.5s for 4.5V ≤ AVCC ≤ 5.5V, 1.2s for 2.7V ≤ AVCC < 4.5V)
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1F to the analog input pin.
• A big external driving impedance also adversely affects the A/D conversion precision due to the pin input leakage current IIL
(static current before the sampling switch) or the analog input leakage current IAIN (total leakage current of pin input and
comparator during sampling). The effect of the pin input leakage current IIL cannot be compensated by an external capacitor.
• The accuracy gets worse as |AVRH - AVSS| becomes smaller.
Document Number: 002-04703 Rev.*A
Page 52 of 68
MB96670 Series
14.5.3
Definition of A/D Converter Terms
• Resolution
• Nonlinearity error
transition point
•
•
•
•
: Analog variation that is recognized by an A/D converter.
: Deviation of the actual conversion characteristics from a straight line that connects the zero
(0b0000000000 ←→ 0b0000000001) to the full-scale transition point
(0b1111111110 ←→ 0b1111111111).
Differential nonlinearity error : Deviation from the ideal value of the input voltage that is required to change the
output code by 1LSB.
Total error
: Difference between the actual value and the theoretical value. The total error includes zero
transition error, full-scale transition error and nonlinearity error.
Zero transition voltage
: Input voltage which results in the minimum conversion value.
Full scale transition voltage: Input voltage which results in the maximum conversion value.
Nonlinearity error of digital output N =
VNT - {1LSB (N - 1) + VOT}
1LSB
Differential nonlinearity error of digital output N =
1LSB =
N
VOT
VFST
VNT
:
:
:
:
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST - VOT
1022
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0x3FE to 0x3FF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Document Number: 002-04703 Rev.*A
Page 53 of 68
MB96670 Series
1LSB (Ideal value) =
Total error of digital output N =
AVRH - AVSS
1024
[V]
VNT - {1LSB (N - 1) + 0.5LSB}
1LSB
N
: A/D converter digital output value.
VNT
: Voltage at which the digital output changes from 0x(N + 1) to 0xN.
VOT (Ideal value) = AVSS + 0.5LSB[V]
VFST (Ideal value) = AVRH - 1.5LSB[V]
Document Number: 002-04703 Rev.*A
Page 54 of 68
MB96670 Series
14.6 High Current Output Slew Rate
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Output rise/fall
time
Symbol
tR30,
tF30
Pin
name
Conditions
P08_m
Outputs
driving
strength set
to "30mA"
Value
Typ
Min
15
-
Max
75
Voltage
Unit
ns
Remarks
CL=85pF
VH=VOL30+0.9 × (V OH30-VOL30)
VL=VOL30+0.1 × (V OH30-VOL30)
VH
VH
VL
VL
tR30
tF30
Time
Document Number: 002-04703 Rev.*A
Page 55 of 68
MB96670 Series
14.7 Low Voltage Detection Function Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Conditions
Value
Typ
2.90
3.00
3.20
3.50
3.70
4.00
4.20
Max
3.10
3.21
3.42
3.74
3.95
4.27
4.49
V
V
V
V
V
V
V
Unit
Detected voltage*1
VDL0
VDL1
VDL2
VDL3
VDL4
VDL5
VDL6
CILCR:LVL = 0000B
CILCR:LVL = 0001B
CILCR:LVL = 0010B
CILCR:LVL = 0011B
CILCR:LVL = 0100B
CILCR:LVL = 0111B
CILCR:LVL = 1001B
Min
2.70
2.79
2.98
3.26
3.45
3.73
3.91
Power supply voltage
change rate*2
dV/dt
-
- 0.004
-
+ 0.004
V/s
Hysteresis width
VHYS
CILCR:LVHYS=0
-
-
50
mV
CILCR:LVHYS=1
80
100
120
mV
Stabilization time
TLVDSTAB
-
-
-
75
s
Detection delay time
td
-
-
-
30
s
*1
: If the power supply voltage fluctuates within the time less than the detection delay time (td), there is a possibility that the low
voltage detection will occur or stop after the power supply voltage passes the detection range.
*2
: In order to perform the low voltage detection at the detection voltage (VDLX), be sure to suppress fluctuation of the power supply
voltage within the limits of the change ration of power supply voltage.
Document Number: 002-04703 Rev.*A
Page 56 of 68
MB96670 Series
Voltage
Vcc
dV
Detected Voltage
dt
VDLX max
VDLX min
Time
RCR:LVDE
···Low voltage detection
function enable
Document Number: 002-04703 Rev.*A
Low voltage detection
function disable
Stabilization time
TLVDSTAB
Low voltage detection
function enable···
Page 57 of 68
MB96670 Series
14.8 Flash Memory Write/Erase Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
-
-
Value
Typ
Max
1.6
7.5
0.4
2.1
0.31
1.65
Word (16-bit) write time
-
-
25
400
s
Chip erase time
-
-
5.11
25.05
s
Parameter
Sector erase time
Large Sector
Small Sector
Security Sector
Conditions
Min
Unit
s
s
s
Remarks
Includes write time prior to
internal erase.
Not including system-level
overhead
time.
Includes write time prior to
internal erase.
Note:
While the Flash memory is written or erased, shutdown of the external power (VCC) is prohibited. In the application system where the
external power (VCC) might be shut down while writing or erasing, be sure to turn the power off by using a low voltage detection
function.
To put it concrete, change the external power in the range of change ration of power supply voltage (-0.004V/s to +0.004V/s) after
the external power falls below the detection voltage (VDLX)*1.
Write/Erase cycles and data hold time
Write/Erase cycles
(cycle)
1,000
10,000
100,000
*1
Data hold time
(year)
20 *2
10 *2
5 *2
: See "Low Voltage Detection Function Characteristics".
*2
: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85C).
Document Number: 002-04703 Rev.*A
Page 58 of 68
MB96670 Series
15. Example Characteristics
This characteristic is an actual value of the arbitrary sample. It is not the guaranteed value.
MB96F675
Run Mode
(VCC = 5.5V)
100.00
PLL clock (32MHz)
10.00
ICC [mA]
Main osc. (4MHz)
1.00
RC clock (2MHz)
RC clock (100kHz)
0.10
Sub osc. (32kHz)
0.01
-50
0
50
100
150
TA [ºC]
Sleep Mode
100.000
PLL clock (32MHz)
10.000
ICC [mA]
(VCC = 5.5V)
Main osc. (4MHz)
1.000
RC clock (2MHz)
0.100
RC clock (100kHz)
0.010
Sub osc. (32kHz)
0.001
-50
0
50
100
150
TA [ºC]
Document Number: 002-04703 Rev.*A
Page 59 of 68
MB96670 Series
MB96F675
Timer Mode
(VCC = 5.5V)
10.000
PLL clock (32MHz)
1.000
ICC [mA]
Main osc. (4MHz)
0.100
RC clock (2MHz)
RC clock (100kHz)
0.010
Sub osc. (32kHz)
0.001
-50
0
50
100
150
TA [ºC]
Stop Mode
(VCC = 5.5V)
1.000
ICC [mA]
0.100
0.010
0.001
-50
0
50
100
150
TA [ºC]
Document Number: 002-04703 Rev.*A
Page 60 of 68
MB96670 Series
Used setting
Selected Source
Clock
Mode
Run mode
Sleep mode
PLL
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32MHz
Main osc.
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 4MHz
RC clock fast
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 2MHz
RC clock slow
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 100kHz
Sub osc.
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32kHz
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32MHz
Regulator in High Power Mode,
(CLKB is stopped in this mode)
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 4MHz
Regulator in High Power Mode,
(CLKB is stopped in this mode)
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 2MHz
Regulator in High Power Mode,
(CLKB is stopped in this mode)
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 100kHz
Regulator in Low Power Mode,
(CLKB is stopped in this mode)
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32kHz
Regulator in Low Power Mode,
(CLKB is stopped in this mode)
CLKMC = 4MHz, CLKPLL = 32MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode,
FLASH in Power-down / reset mode
CLKMC = 4MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode,
FLASH in Power-down / reset mode
CLKMC = 2MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode,
FLASH in Power-down / reset mode
CLKMC = 100kHz
(System clocks are stopped in this mode)
Regulator in Low Power Mode,
FLASH in Power-down / reset mode
CLKMC = 32 kHz
(System clocks are stopped in this mode)
Regulator in Low Power Mode,
FLASH in Power-down / reset mode
(All clocks are stopped in this mode)
Regulator in Low Power Mode,
FLASH in Power-down / reset mode
PLL
Main osc.
RC clock fast
RC clock slow
Sub osc.
Timer mode
PLL
Main osc.
RC clock fast
RC clock slow
Sub osc.
Stop mode
Clock/Regulator and FLASH Settings
stopped
Document Number: 002-04703 Rev.*A
Page 61 of 68
MB96670 Series
16. Ordering Information
MCU with CAN controller
Part number
Flash memory
MB96F673RBPMC-GSE1
MB96F673RBPMC-GSE2
Flash A
(96.5KB)
MB96F673RBPMC1-GSE1
MB96F673RBPMC1-GSE2
MB96F675RBPMC-GSE1
MB96F675RBPMC-GSE2
Flash A
(160.5KB)
MB96F675RBPMC1-GSE1
MB96F675RBPMC1-GSE2
*: For details about package, see "PACKAGE DIMENSION".
Package*
64-pin plastic LQFP
(FPT-64P-M23)
64-pin plastic LQFP
(FPT-64P-M24)
64-pin plastic LQFP
(FPT-64P-M23)
64-pin plastic LQFP
(FPT-64P-M24)
MCU without CAN controller
Part number
Flash memory
MB96F673ABPMC-GSE1
MB96F673ABPMC-GSE2
Flash A
(96.5KB)
MB96F673ABPMC1-GSE1
MB96F673ABPMC1-GSE2
MB96F675ABPMC-GSE1
Flash A
MB96F675ABPMC-GSE2
(160.5KB)
MB96F675ABPMC1-GSE1
MB96F675ABPMC1-GSE2
*: For details about package, see "PACKAGE DIMENSION".
Document Number: 002-04703 Rev.*A
Package*
64-pin plastic LQFP
(FPT-64P-M23)
64-pin plastic LQFP
(FPT-64P-M24)
64-pin plastic LQFP
(FPT-64P-M23)
64-pin plastic LQFP
(FPT-64P-M24)
Page 62 of 68
MB96670 Series
17. Package Dimension
64-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
12.0 × 12.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.47 g
Code
(Reference)
P-LQFP64-12 × 12-0.65
(FPT-64P-M23)
64-pin plastic LQFP
(FPT-64P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00± 0.20(.551± .008)SQ
0.145± 0.055
(.006 ± .002)
*12.00± 0.10(.472± .004)SQ
48
33
49
32
0.10(.004)
Details of "A" part
+0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004
0.25(.010)
INDEX
0~8°
64
17
0.65(.026)
C
"A"
16
1
0.32 ± 0.05
(.013 ± .002)
0.13(.005)
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F64034S-c-1-4
Document Number: 002-04703 Rev.*A
0.50 ± 0.20
(.020 ± .008)
0.60 ± 0.15
(.024 ± .006)
0.10 ± 0.10
(.004 ± .004)
(Stand off)
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Page 63 of 68
MB96670 Series
64-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
10.0 × 10.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.32 g
Code
(Reference)
P-LFQFP64-10×10-0.50
(FPT-64P-M24)
64-pin plastic LQFP
(FPT-64P-M24)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
*10.00±0.10(.394±.004)SQ
48
0.145±0.055
(.006±.002)
33
32
49
Details of "A" part
0.08(.003)
+0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004
INDEX
64
0°~8°
17
0.10±0.10
(.004±.004)
(Stand off)
"A"
LEAD No.
1
16
0.50(.020)
0.20±0.05
(.008±.002)
C
0.08(.003)
2005-2010 FUJITSU SEMICONDUCTOR LIMITED F64036S-c-1-3
Document Number: 002-04703 Rev.*A
M
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Page 64 of 68
MB96670 Series
18. Major Changes
Spansion Publication Number: MB96670_DS704-00001
Page
Section
Revision 2.0
4
FEATURES
9
27 to 30
PIN DESCRIPTION
HANDLING PRECAUTIONS
HANDLING DEVICES
33
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
35
3. DC Characteristics
(1) Current Rating
39
Document Number: 002-04703 Rev.*A
Change Results
Changed the description of “LCD Controller”
On-chip drivers for internal divider resistors or external divider
resistors
→
Internal divider resistors or external divider resistors
Changed the description of “External Interrupts”
Interrupt mask and pending bit per channel
→
Interrupt mask bit per channel
Deleted Pin name
WOT
Added a section
Changed the description in “11. SMC power supply pins”
To avoid this, VCC must always be powered on before DVCC.
→
To avoid this, VCC must always be powered on before DVCC.
DVcc/DVss must be applied when using SMC I/O pin as
GPIO.
Changed the annotation *2
It is required that AVCC does not exceed VCC and that the
voltage at the analog inputs does not exceed AVCC when the
power is switched on.
→
It is required that AVCC does not exceed VCC, DVCC and
that the voltage at the analog inputs does not exceed AVCC
when the power is switched on.
Changed the Conditions for ICCSRCH
CLKS1/2 = CLKB = CLKP1/2 = CLKRC = 2MHz,
→
CLKS1/2 = CLKP1/2 = CLKRC = 2MHz,
Changed the Conditions for ICCSRCL
CLKS1/2 = CLKB = CLKP1/2 = CLKRC = 100kHz
→
CLKS1/2 = CLKP1/2 = CLKRC = 100kHz
Changed the Conditions for ICCTPLL
PLL Timer mode with CLKP1 = 32MHz
→
PLL Timer mode with CLKPLL = 32MHz
Changed the Value of “Power supply current in Timer modes”
ICCTPLL
Typ: 2480μA → 1800μA (TA = +25°C)
Max: 2710μA → 2245μA (TA = +25°C)
Max: 3955μA → 3140μA (TA = +105°C)
Changed the Conditions for ICCTRCL
RC Timer mode with CLKRC = 100kHz,
SMCR:LPMSS = 0 (CLKPLL, CLKMC and CLKSC stopped)
→
RC Timer mode with CLKRC = 100kHz
(CLKPLL, CLKMC and CLKSC stopped)
Page 65 of 68
MB96670 Series
Page
Section
ELECTRICAL CHARACTERISTICS
3. DC Characteristics
(1) Current Rating
40
52
54
4. AC Characteristics
(10) I2C timing
5. A/D Converter
(2) Accuracy and Setting of the A/D
Converter Sampling Time
6. High Current Output Slew Rate
57
8. Flash Memory Write/Erase
Characteristics
60
Revision 2.1
-
Change Results
Changed the annotation *2
Power supply for "On Chip Debugger" part is not included.
Power supply current in Run mode does not include
Flash Write / Erase current.
→
The current for "On Chip Debugger" part is not included.
Added the description to annotation *2, *3
When Flash is not in Power-down / reset mode, ICCFLASHPD
must be added to the Power supply current.
Added parameter, “Noise filter” and an annotation *5 for it
Added tSP to the figure
Deleted the unit “[Min]” from approximation formula of
Sampling time
Changed the condition
(VCC = AVCC = DVCC = 2.7V to 5.5V, VD=1.8V±0.15V, VSS =
AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
→
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V,
TA = - 40°C to + 105°C)
Changed the condition
(VCC = AVCC = DVCC = 2.7V to 5.5V, VD=1.8V±0.15V, VSS =
AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
→
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V,
TA = - 40°C to + 105°C)
Changed the Note
While the Flash memory is written, shutdown of the external
power (VCC) is prohibited. In the application system where the
external power (VCC) might be shut down while writing, be
sure to turn the power off by using an external voltage
detector.
→
While the Flash memory is written or erased, shutdown of the
external power (VCC) is prohibited. In the application system
where the external power (VCC) might be shut down while
writing or erasing, be sure to turn the power off by using a low
voltage detection function.
Company name and layout design change
NOTE: Please see “Document History” about later revised information.
Document Number: 002-04703 Rev.*A
Page 66 of 68
MB96670 Series
Document History
Document Title: MB96670 Series F2MC-16FX 16-Bit Microcontroller
Document Number: 002-04703
Revision
ECN
**
-
Orig. of
Submission
Change
Date
TORS
01/31/2014
Description of Change
Migrated to Cypress and assigned document number 002-04703.
No change to document contents or format.
*A
5135634
TORS
Document Number: 002-04703 Rev.*A
02/18/2016
Updated to Cypress format.
Page 67 of 68
MB96670 Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the
office closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
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cypress.com/go/automotive
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cypress.com/go/clocks
Interface
Lighting & Power Control
cypress.com/go/interface
cypress.com/go/powerpsoc
Memory
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/touch
USB Controllers
cypress.com/go/USB
Wireless/RF
Spansion Products
psoc.cypress.com/solutions
cypress.com/go/wireless
cypress.com/spansionproducts
Cypress, the Cypress logo, Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM, ORNANDTM, Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered
trademarks of Cypress Semiconductor Corp. ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries. All other trademarks or registered trademarks referenced
herein are the property of their respective owners.
© Cypress Semiconductor Corporation, 2014-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a
Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is
prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 002-04703 Rev.*A
February 18, 2016
Page 68 of 68