Plastic Packages for Integrated Circuits Small Outline Transistor Plastic Packages (SC70-6) 0.20 (0.008) M VIEW C C P6.049 CL 6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE e b 6 INCHES 5 4 CL CL E 1 2 8 PIN 1 INDEX AREA A E1 3 e1 MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.031 0.043 0.80 1.10 - A1 0.000 0.004 0.00 0.10 - A2 0.031 0.039 0.79 1.00 - b 0.006 0.012 0.15 0.30 b1 0.006 0.010 0.15 0.25 c 0.003 0.009 0.08 0.22 6 D c1 0.003 0.009 0.08 0.20 6 CL D 0.073 0.085 1.85 2.15 3 E 0.071 0.094 1.80 2.40 - E1 0.045 0.053 1.15 1.35 3 C A2 SEATING PLANE A1 -C- e e1 L 0.10 (0.004) C WITH b PLATING b1 0.0256 Ref 0.0512 Ref 0.010 c1 0.018 - 1.30 Ref 0.26 - 0.46 L1 0.017 Ref. 0.420 Ref. L2 0.006 BSC 0.15 BSC N c 0.65 Ref 6 4 5 6 R 0.004 - 0.10 - R1 0.004 0.010 0.15 0.25 α 0o 8o 0o 8o Rev. 4 12/12 BASE METAL NOTES: 1. Dimensioning and tolerance per ASME Y14.5M-1994. 4X θ1 2. Package conforms to EIAJ SC70 and JEDEC MO203AB. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. R GAUGE PLANE SEATING PLANE L C L1 4X θ1 VIEW C 1 α L2 5. “N” is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. 8. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.