® August 2000 T UC T DUC ROD TE PRO at P E r T TITU ente OL E OBS LE SU BS upport C om/tsc sil.c al S SIB POS Technic ww.inter A R w ur FO IL or act o cont -INTERS Ultra 8 1-88 HI20203 8-Bit, 160 MSPS, High-Speed D/A Converter Features Description • Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 160MHz The HI20203 is an 8-bit, 160MHz ultra high speed D/A converter. The converter is based on an R2R switched current source architecture that includes an input data register with a complement feature and is Emitter Coupled Logic (ECL) compatible. • 8-Bit (HI20203) Resolution • Differential Linearity Error . . . . . . . . . . . . . . . . 0.5 LSB • Low Glitch Noise • Analog Multiplying Function The HI20203 is an 8-bit accurate D/A with a linearity error of 0.5 LSB. • Low Power Consumption . . . . . . . . . . . . . . . . . . 420mW For 10-bit resolution, please refer to the HI20201 data sheet. • Evaluation Board Available Part Number Information • Direct Replacement for the Sony CX20201-3, CX20202-3 PART NUMBER Applications HI20203JCB • Wireless Communications TEMP. RANGE ( oC) -20 to 75 PACKAGE 28 Ld SOIC PKG. NO. M28.3A-S • Signal Reconstruction • Direct Digital Synthesis • High Definition Video Systems • Digital Measurement Systems • Radar Pinout HI20203 (PDIP, SOIC) TOP VIEW (MSB) D7 1 28 AVSS D6 2 27 VREF D5 3 26 AVEE D4 4 25 NC D3 5 24 NC D2 6 23 NC D1 7 22 NC D0 8 21 NC NC 9 20 IOUT NC 10 19 NC NC 11 18 AVSS NC 12 17 DVSS CLK 13 16 COMPL CLK 14 15 DVEE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1 File Number 4096.2 HI20203 Typical Application Circuit HI20203 DIGITAL DATA (ECL) D7 D7 (MSB) (1) D6 D6 (2) D5 D5 (3) D4 D4 (4) D3 D3 (5) D2 D2 (6) D1 D1 (7) D0 D0 (8) . (28) AVSS 1.5kΩ 1kΩ (27) VREF 2kΩ (26) AVEE ~2.7V TL431CP -5.2V 0.047µF 1.0µF (9) (10) 75Ω COAX CABLE (11) (20) I OUT (12) D/A OUT (18, 19, 21-25) NC 82Ω 82Ω CLK CLK (13) (17) DVSS -1.3V CLK (14) (16) COMPL 131Ω (15) DVEE 131Ω -5.2V 1.0µF 3.6kΩ 0.047µF -5.2V Functional Block Diagram 4 LSBs CURRENT CELLS (LSB) D0 D1 R2R NETWORK D2 INPUT 8-BIT REGISTER BUFFER D3 D4 D5 UPPER 4-BIT ENCODER D6 15 (MSB) D7 15 SWITCHED CURRENT CELLS I OUT COMPL CLK CLK AVEE AVSS BIAS CURRENT GENERATOR CLOCK BUFFER DVEE DVSS 2 VREF HI20203 Absolute Maximum Ratings TA = 25oC Thermal Information Digital Supply Voltage DVEE to DVSS . . . . . . . . . . . . . . . . . . . -7.0V Analog Supply Voltage AV DD to AV SS . . . . . . . . . . . . . . . . . . -7.0V Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 to DVEE V Reference Input Voltage. . . . . . . . . . . . . . . . . . . . . . +0.3 to AVEE V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Thermal Resistance (Typical, Note 5) θJA ( oC/W) SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Supply Voltage AVEE , DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4.75V to -5.45V AVEE - DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to +0.05V Digital Input Voltage VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to -0.7V VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.9V to -1.6V Reference Input Voltage, VREE . . . . . . . VEE + 0.5V to VEE + 1.4V Load Resistance, R L . . . . . . . . . . . . . . . . . . . . . . . . . . . . Above 75Ω Output Voltage, VO(FS) . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V to 1.2V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications AV EE = -5.2V, DVEE = -5.2V, AGND = 0V, DGND = 0V, RL = ∞, VOUT = -1V, TA = 25oC HI20203JCB/JCP PARAMETER TEST CONDITION MIN TYP MAX UNITS 8 - - Bits SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL fS = 160MHz (End Point) - - ±0.5 LSB Differential Linearity Error, DNL fS = 160MHz - - ±0.50 LSB Offset Error, VOS (Adjustable to Zero) (Note 3) - 1.8 - LSB Full Scale Error, FSE (Adjustable to Zero) (Note 3) - - ±26 LSB - - 20 mA 160 - - MHz - 15 - pV/s Full Scale Output Current, IFS DYNAMIC CHARACTERISTICS Throughput Rate See Figure 11 Glitch Energy, GE R OUT = 75Ω REFERENCE INPUT Voltage Reference Input Range With respect to AVEE +0.5 - +1.4 V Reference Input Current V REF = -4.58V -0.1 -0.4 -3.0 µA Voltage Reference to Output Small Signal Bandwidth -3dB point 1VP-P Input - 14.0 - MHz Output Rise Time, tr R LOAD = 75Ω - 1.5 - ns Output Fall Time, tf R LOAD = 75Ω - 1.5 - ns -1.0 -0.89 DIGITAL INPUTS Input Logic High Voltage, VIH (Note 2) Input Logic Low Voltage, V IL (Note 2) -1.75 3 V -1.6 V HI20203 Electrical Specifications AV EE = -5.2V, DV EE = -5.2V, AGND = 0V, DGND = 0V, RL = ∞, VOUT = -1V, TA = 25oC (Continued) HI20203JCB/JCP PARAMETER TEST CONDITION MIN TYP MAX UNITS Input Logic Current, IIL , IIH (For D9 thru D6, COMPL) VIH = -0.89V, VIL = -1.75V (Note 2) 0.1 1.5 6.0 µA Input Logic Current, IIL , IIH (For D5 thru D0) VIH = -0.89V, VIL = -1.75V (Note 2) 0.1 0.75 3.0 µA TIMING CHARACTERISTICS Data Setup Time, tSU See Figure 11 5 - - ns Data Hold Time, tHLD See Figure 11 1 - - ns Propagation Delay Time, tPD See Figure 11 - 3.8 - ns Settling Time, tSET (to 1/2 LSB) See Figure 11 - 4.3 - ns -60 -75 -90 mA - 420 470 mW POWER SUPPLY CHARACTERISITICS IEE Power Dissipation 75Ω load NOTES: 2. Parameter guaranteed by design or characterization and not production tested. 3. Excludes error due to reference drift. 4. Electrical specifications guaranteed only under the stated operating conditions. Timing Diagram CLK CLK DATA tSU tHD N N+1 tD tD 0V 90% D/A OUT -1V N+1 N 50% 10% tr tf FIGURE 1. LADDER SETTLING TIME FULL POWER BANDWIDTH (LS) 4 HI20203 FULL SCALE OUTPUT VOLTAGE (V) -2.0 FULL SCALE OUTPUT VOLTAGE (RELATIVE VALUE) VO(FS) /(VO(FS) AT TA = 25oC) Typical Performance Curves TA = 25 oC, VEE = -5.2V LINEAR AREA RL = 10kΩ -1.0 RL = 75Ω 0 0.5 1.0 1.5 1.05 RL = 10kΩ 1.00 RL = 75Ω 0.95 -20 FIGURE 2. VO(FS) RATIO vs (V REF - VEE) 10.0 PHASE -90 -10 GLITCH ENERGY (pV/s) 0 PHASE (DEGREE) GAIN GAIN (dB) 20 40 60 80 FIGURE 3. FULL SCALE OUTPUT VOLTAGE vs AMBIENT TEMPERATURE 0 -180 -20 10K 0 AMBIENT TEMPERATURE (oC) VREF - VEE (V) fCLK = 100MHz 8.0 6.0 4.0 2.0 100K 1M 10M 100M MULTIPLYING INPUT SIGNAL FREQUENCY (Hz) -50 FIGURE 4. OUTPUT CHARACTERISTICS vs MULTIPLYING INPUT SIGNAL FREQUENCY 0 50 CASE TEMPERATURE (oC) 100 FIGURE 5. GLITCH ENERGY vs CASE TEMPERATURE (FULL SCALE - 1023mV) Pin Descriptions 28 PIN SOIC 1-8 11, 12, 19, 21-25 PIN NAME PIN DESCRIPTION D0 (LSB) - D7 (MSB) Digital Data Bit 0, the Least Significant Bit thru Digital Data Bit 7, the Most Significant Bit. NC No connect, not used. 13 CLK Negative Differential Clock Input. 14 CLK Positive Differential Clock Input Digital (ECL) Power Supply -4.75V to -7V. 15 DVEE 16 COMPL 17 DVSS Digital Ground. 18 AVSS Analog Ground. 20 IOUT Current Output Pin. 26 AVEE Analog Supply -4.75V to -7V. 27 VREF Input Reference Voltage used to set the output full scale range. Data Complement Pin. When set to a (ECL) logic High the input data is complemented in the input buffer. When cleared to a (ECL) logic Low the input data is not complemented. 5 HI20203 Pin Descriptions 28 PIN SOIC PIN NAME 28 AVSS PIN DESCRIPTION Analog Ground Detailed Description 01 1111 1111 to 10 0000 0000. But in the HI20203 the glitch is moved to the 00 0001 1111 to 11 1110 0000 transition. This is achieved by the split R2R/segmented current source architecture. This decreases the amount of current switching at any one time and makes the glitch practically constant over the entire output range. By making the glitch a constant size over the entire output range this effectively integrates this error out of the end application. The HI20203 is an 8-bit, current-output D/A converter. The converter has 10 data bits but yields 8-bit performance. Architecture The HI20203 is a combined R2R/segmented current source design. The 6 least significant bits of the converter are derived by a traditional R2R network to binary weight the 1mA current sources. The upper 4 most significant bits are implemented as segmented or thermometer encoded current sources. The encoder converts the incoming 4 bits to 15 control lines to enable the most significant current sources. The thermometer encoder will convert binary to individual control lines. See Table 1. In measuring the output glitch of the HI20203 the output is terminated into a 75Ω load. The glitch is measured at the major carry’s throughout the DACs output range. The glitch energy is calculated by measuring the area under the voltage-time curve. Figure 7 shows the area considered as glitch when changing the DAC output. Units are typically specified in picoVolt/seconds (pV/s). TABLE 1. THERMOMETER ENCODER MSB BIT 6 BIT 5 BIT 4 THERMOMETER CODE 1 = ON, 0 = OFF I15 - I0 0 0 0 0 000 0000 0000 0000 0 0 0 1 000 0000 0000 0001 0 0 1 0 000 0000 0000 0011 0 0 1 1 000 0000 0000 0111 0 1 0 0 000 0000 0000 1111 0 1 0 1 000 0000 0001 1111 0 1 1 0 000 0000 0011 1111 0 1 1 1 000 0000 0111 1111 1 0 0 0 000 0000 1111 1111 1 0 0 1 000 0001 1111 1111 1 0 1 0 000 0011 1111 1111 1 0 1 1 000 0111 1111 1111 1 1 0 0 000 1111 1111 1111 1 1 0 1 001 1111 1111 1111 1 1 1 0 011 1111 1111 1111 1 1 1 1 111 1111 1111 1111 HI20203 34MHz LOW PASS FILTER (20) IOUT SCOPE 50Ω 75Ω FIGURE 6. HI20203 GLITCH TEST CIRCUIT A (mV) GLITCH ENERGY = (a x t)/2 The architecture of the HI20203 is designed to minimize glitch while providing a manufacturable 10-bit design that does not require laser trimming to achieve good linearity. t (ns) Glitch FIGURE 7. GLITCH ENERGY Glitch is caused by the time skew between bits of the incoming digital data. Typically the switching time of digital inputs are asymmetrical meaning that the turn off time is faster than the turn on time (TTL designs). In an ECL system where the logic levels switch from one non-saturated level to another, the switching times can be considered close to symmetrical. This helps to reduce glitch in the D/A. Unequal delay paths through the device can also cause one current source to change before another. To minimize this the Intersil HI20203 employs an internal register, just prior to the current sources, that is updated on the clock edge. Lastly the worst case glitch usually happens at the major transition i.e., Setting Full Scale The Full Scale output voltage is set by the Voltage Reference pin (27). The output voltage performance will vary as shown in Figure 2. The output structure of the HI20203 can handle down to a 75Ω load effectively. To drive a 50Ω load Figure 8 is 6 HI20203 The temperature coefficient of the full scale output voltage and zero offset voltage depend on the load resistance connected to IOUT . The larger the load resistor the better (i.e., smaller) the temperature coefficient of the D/A. See Figure 3 in the performance curves section. suggested. Note the equivalent output load is ~75Ω. HI20203 39Ω 50Ω COAX CABLE Noise Reduction D/A OUT (20) IOUT Digital switching noise must be minimized to guarantee system specifications. Since 1 LSB corresponds to 1mV for 10-bit resolution, care must be taken in the layout of a circuit board. 100Ω (18, 19, 21-25) NC Separate ground planes should be used for DV SS and AVSS . They should be connected back at the power supply. Separate power planes should be used for DVEE and AV EE . They should be decoupled with a 1µF tantalum capacitor and a ceramic 0.047µF capacitor positioned as close to the body of the IC as possible. FIGURE 8. HI20203 DRIVING A 50Ω LOAD Variable Attenuator Capability The HI20203 can be used in a multiplying mode with a variable frequency input on the VREF pin. In order for the part to operate correctly a DC bias must be applied and the incoming AC signal should be coupled to the VREF pin. See Figure 13 for the application circuit. The user must first adjust the DC reference voltage. The incoming signal must be attenuated so as not to exceed the maximum (+1.4V) and minimum (+0.5V) reference input. The typical output Small Signal Bandwidth is 14MHz. Integral Linearity The Integral Linearity is measured using the End Point method. In the End Point method the gain is adjusted. A line is then established from the zero point to the end point or Full Scale of the converter. All codes along the transfer curve must fall within an error band of 1 LSB of the line. Figure 10 shows the linearity test circuit. Differential Linearity The Differential Linearity is the difference from the ideal step. To guarantee monotonicity a maximum of 1 LSB differential error is allowed. When more than 1 LSB is specified the converter is considered to be missing codes. Figure 10 shows the linearity test circuit. Clock Phase Relationship The HI20203 is designed to be operated at very high speed (i.e., 160MHz). The clock lines should be driven with ECL100K logic for full performance. Any external data drivers and clock drivers should be terminated with 50Ω to minimize reflections and ringing. Internal Data Register The HI20203 incorporates a data register as shown in the Functional Block Diagram. This register is updated on the rising edge of the CLK line. The state of the Complement bit (COMPL) will determine the data coding. See Table 2. TABLE 2. INPUT CODING TABLE OUTPUT CODE INPUT CODE COMPL = 1 COMPL = 0 00 0000 0000 0 -1 10 0000 0000 -0.5 -0.5 11 1111 1111 -1 0 Thermal Considerations 7 HI20203 Test Circuits and Waveforms a b a b a b a b a b a b a b a b I2 S11 a b -0.89V -1.75V S1 S2 S3 S4 S5 S6 S7 S8 -0.89V OR -1.75V a S14 I3 b a S15 I4 b -0.89V 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 a S20 b S16 a b I1 I6 5.2V 4.56V 1mA S19 a b V1 S17 a S12 13 b a S13 14 b a b a b 16 I5 15 S18 a b 5.2V -1.75V FIGURE 9. CURRENT CONSUMPTION, INPUT CURRENT AND OUTPUT RESISTANCE LINEARITY ERRORS ARE MEASURED AS FOLLOWS “1” S1 S2 “0” 0.89V S3 1.75V S4 S5 S6 8-BIT DATA S7 S8 1.3V 1 SHOT CLK 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 * 10K 5.2V S1 0 0 0 S2 0 0 0 S3 0 0 0 1 1 1 •••• •••• •••• •••• • • • •••• INTEGRAL LINEARITY ERROR D/A OUT V0 5.2V V0 V1 V2 V4 V8 V16 V32 V64 V128 • • • V255 S7 0 0 1 S8 0 1 0 1 1 D/A OUT V0 V1 V2 • • • V255 DIFFERENTIAL LINEARITY ERROR V1 - V0 V2 - V1 V4 - V3 V8 - V7 V16 - V15 V32 - V31 V64 - V63 V128 - V127 • • • Error at individual measurement points are calculated according to the following definition. (V255 - V0)/1023 = V0(FS) /255 ≡ 1 LSB. FIGURE 10. DIFFERENTIAL LINEARITY ERROR AND LINEARITY ERROR 8 HI20203 Test Circuits and Waveforms (Continued) B 1/ HD100151 6 1 82 D 82 Q Q 131 -5.2V CLKF 131 -5.2V TO PG -1.3V 50Ω 1 CLKF HD100116 1 470 DL 82 131 82 82 1 131 -1.3V 131 -5.2V A 10kΩ 28 MSB 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 OUT 20 10 LSB 19 11 18 12 17 13 CLK 16 14 CLK 15 -5.2V C 50Ω 39 100 TO SCOPE -5.2V 131 DL: Delay line Capacitors are 0.047µF ceramic chip capacitors unless otherwise specified. FIGURE 11. MAXIMUM CONVERSION RATE, RISE TIME, FALL TIME, PROPAGATION DELAY, SETUP TIME, HOLD TIME AND SETTLING TIME Measuring Settling Time Settling time is measured as follows. The relationship between V and V0(FS) as shown in the D/A output waveform in Figure 12 is expressed as V = V 0(FS) (1 - e-tτ). The settling time for respective accuracy of 10, 9 and 8-bit is specified as τ V = 0.9995 V 0(FS) V = 0.999 V0(FS) V = 0.999 V0(FS) which results in the following: tS = 7.60τ tS = 6.93τ tS = 6.24τ V for 10-bit, for 9-bit, and for 8-bit, Rise time (tr) and fall time (tf) are defined as the time interval to slew from 10% to 90% of full scale voltage (V0(FS)): t V = 0.1 V0(FS) V = 0.9 V0(FS) FIGURE 12. D/A OUTPUT WAVEFORM and calculated as tr = tf = 2.20τ. The settling time is obtained by combining these expressions: tS = 3.45tr tS = 3.15tr tS = 6.24tr V0(FS) = 1V for 10-bit, for 9-bit, and for 8-bit 9 HI20203 Test Circuits and Waveforms (Continued) Adjust so that the voltage at point B becomes -1V with no AC input. “1” 1 28 2 27 10kΩ 0.1µF OSC 0.047µ 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 CLK 13 16 CLK 14 15 51 A -5.2V B TO SCOPE A GND -5.2V FIGURE 13A. VEE -0.62V WAVEFORM AT POINT A VEE -0.31V FIGURE 13B. 1VP-P AT 1MHz -1V WAVEFORM AT POINT B FIGURE 13C. FIGURE 13. MULTIPLYING BANDWIDTH 10 D GND