HI1171 8-Bit, 40 MSPS, High Speed D/A Converter August 1997 Features Description • Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . 40MHz The HI1171 is an 8-bit, 40MHz, high speed D/A converter. The converter incorporates an 8-bit input data register with blanking capability, and current outputs. The HI1171 features low glitch outputs. The architecture is a current cell arrangement to provide low linearity errors. • Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit • Integral Linearity Error . . . . . . . . . . . . . . . . . . 0.25 LSB • Low Glitch Noise The HI1171 is available in an Industrial temperature range and is offered in a 24 lead (200 mil) SOIC plastic package. • Single Supply Operation . . . . . . . . . . . . . . . . . . . . . . +5V • Low Power Consumption (Max) . . . . . . . . . . . . . .80mW For dual version, please refer to the HI21427 Data Sheet. For triple version, please refer to the HI21428 Data Sheet. • Evaluation Board Available (HI1171-EV) • Direct Replacement for the HI21421JCB Ordering Information Applications PART NUMBER • Wireless Telecommunications TEMP. RANGE (oC) • Signal Reconstruction HI1171JCB -40 to 85 • Direct Digital Synthesis HI1171-EV 25 PACKAGE PKG. NO. 24 Ld SOIC M24.2-S Evaluation Board • Imaging • Presentation and Broadcast Video • Graphics Displays • Signal Generators Pinout Typical Application Circuit HI1171 (SOIC) TOP VIEW +5V +5V HI1171 0.1µF 1 24 DVDD D1 2 23 DVDD D7 D7 (MSB)(8) D2 3 22 AVDD D6 D6 (7) D3 4 21 IOUT2 D5 D5 (6) D4 5 20 IOUT1 D4 D4 (5) 19 AVDD D3 D3 (4) D2 D2 (3) D1 D1 (2) D0 D0 (LSB) (1) D5 6 D6 7 18 AVDD D7 8 17 VG BLNK 9 16 VREF DVSS 10 CLK (12) 15 IREF VB 11 14 AVSS CLK 12 13 DVSS 0.1µF DVDD (23, 24) (18, 19, 22) AVDD (LSB) D0 0.1µF VB (11) BLNK (9) DVSS (10, 13) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 1 (17) VG (16) VREF 0.1µF 1kΩ (20) IOUT1 D/A OUT 200Ω (15) IREF 3.3kΩ (21) IOUT2 (14) AVSS File Number 3662.2 HI1171 Functional Block Diagram (LSB) D0 D1 D2 D3 DECODER 8-BIT LATCH D4 6 MSBs CURRENT CELLS D5 D6 IOUT1 VG DECODER - (MSB) D7 CURRENT CELLS (FOR FULL SCALE) BLNK BIAS VOLTAGE GENERATOR VB CLK IOUT2 2 LSBs CURRENT CELLS CLOCK GENERATOR 2 + VREF IREF HI1171 Absolute Maximum Ratings Thermal Information Digital Supply Voltage DVDD to DVSS . . . . . . . . . . . . . . . . . . . +7.0V Analog Supply Voltage AVDD to AVSS . . . . . . . . . . . . . . . . . . +7.0V Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0mA to 15mA Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Maximum Junction Temperature, Plastic Package . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications AVDD = +4.75V to +5.25V, DVDD = +4.75 to +5.25V, VREF = +2.0V, fS = 40MHz, CLK Pulse Width = 12.5ns, TA = 25oC (Note 4) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - 8 - Bits -0.5 - 1.3 LSB SYSTEM PERFORMANCE Resolution, n Integral Linearity Error, INL fS = 40MHz (End Point) Differential Linearity Error, DNL fS = 40MHz - - ±0.25 LSB Offset Error, VOS (Note 2) - - 1 mV Full Scale Error, FSE (Adjustable to Zero) (Note 2) - - ±13 LSB Full Scale Output Current, IFS - 10 15 mA Full Scale Output Voltage, VFS 1.9 2.0 2.1 V Output Voltage Range, VFSR 0.5 2.0 2.1 V DYNAMIC CHARACTERISTICS Throughput Rate See Figure 7 40.0 - - MHz Glitch Energy, GE ROUT = 75Ω - 30 - pV-s Differential Gain, ∆AV (Note 3) - 1.2 - % Differential Phase, ∆φ (Note 3) - 0.5 - Degree 0.5 - 2.0 V (Note 3) 1.0 - - MΩ Input Logic High Voltage, VIH (Note 3) 3.0 - - V Input Logic Low Voltage, VIL (Note 3) - - 1.5 V Input Logic Current, IIL, IIH (Note 3) - - ±5.0 µA Digital Input Capacitance, CIN (Note 3) - 5.0 - pF Data Setup Time, tSU See Figure 1 5 - - ns Data Hold Time, tHLD See Figure 1 10 - - ns REFERENCE INPUT Voltage Reference Input Range Reference Input Resistance DIGITAL INPUTS TIMING CHARACTERISTICS 3 HI1171 Electrical Specifications AVDD = +4.75V to +5.25V, DVDD = +4.75 to +5.25V, VREF = +2.0V, fS = 40MHz, CLK Pulse Width = 12.5ns, TA = 25oC (Note 4) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Propagation Delay Time, tPD See Figure 9 - 10 - ns Settling Time, tSET (to 1/2 LSB) See Figure 1 - 10 15 ns CLK Pulse Width, tPW1, tPW2 See Figure 1 12.5 - - ns POWER SUPPLY CHARACTERISITICS IAVDD 14.3MHz, at Color Bar Data Input - 10.9 11.5 mA IDVDD 14.3MHz, at Color Bar Data Input - 4.2 4.8 mA Power Dissipation 200Ω load at 2VP-P Output - - 80 mW NOTES: 2. Excludes error due to external reference drift. 3. Parameter guaranteed by design or characterization and not production tested. 4. Electrical specifications guaranteed only under the stated operating conditions. Timing Diagram tPW1 tPW2 CLK tSU tSU tSU tHLD tHLD tHLD DATA tPD 100% D/AOUT 50% tPD tPD 0% FIGURE 1. 4 HI1171 200 2 GLITCH ENERGY (pV/s) OUTPUT FULL SCALE VOLTAGE (V) Typical Performance Curves 1 100 VDD = 5.0V, R = 200Ω 16R = 3.3kΩ, TA = 25oC 1 REFERENCE VOLTAGE (V) 2 100 OUTPUT RESISTANCE (Ω) OUTPUT FULL SCALE VOLTAGE (V) FIGURE 2. OUTPUT FULL SCALE VOLTAGE vs REFERENCE VOLTAGE 200 FIGURE 3. OUTPUT RESISTANCE vs GLITCH ENERGY 2.0 1.9 VDD = 5.0V, VREF = 2.0V R = 200Ω, 16R = 3.3kΩ TA = 25oC 0 -25 0 25 50 75 AMBIENT TEMPERATURE (oC) FIGURE 4. OUTPUT FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE Pin Descriptions 24 PIN SOIC PIN NAME 1-8 D0(LSB) thru D7(MSB) 9 BLNK Blanking Line, used to clear the internal data register to the zero condition when High, normal operation when Low. 10, 13 DVSS Digital Ground. 11 VB 12 CLK Data Clock Pin 100kHz to 40MHz. 14 AVSS Analog Ground. 15 IREF Current Reference, used to set the current range. Connect a resistor to AVSS that is 16 times greater than the resistor on IOUT1 . (See Typical Applications Circuit). 16 VREF Input Reference Voltage used to set the output full scale range. PIN DESCRIPTION Digital Data Bit 0, the Least Significant Bit thru Digital Data Bit 7, the Most Significant Bit. Voltage Bias, connect a 0.1µF capacitor to DVSS . 5 HI1171 Pin Descriptions (Continued) 24 PIN SOIC PIN NAME 17 VG 18, 19, 22 AVDD Analog Supply 4.75V to 7V. 20 IOUT1 Current Output Pin. 21 IOUT2 Current Output pin used for a virtual ground connection. Usually connected to AVSS. 23, 24 DVDD Digital Supply 4.75V to 7V. PIN DESCRIPTION Voltage Ground, connect a 0.1µF capacitor to AVDD . Detailed Description The HI1171 is an 8-bit, current out D/A converter. The DAC can convert at 40MHz and run on a single +5V supply. The architecture is an encoded, switched current cell arrangement. As the values of both ROUT and RREF increase, power consumption is decreased, but glitch energy and output settling time is increased. Clock Phase Relationship Voltage Output Mode The output current of the HI1171 can be converted into a voltage by connecting an external resistor to IOUT1 . To calculate the output resistor use the following equation: The internal latch is closed when the clock line is high. The latch can be cleared by the BLNK line. When BLNK is set (HIGH) the contents of the internal data latch will be cleared. When BLNK is low data is updated by the CLK. ROUT = VFS /IFS , Noise Reduction where VFS can range from +0.5V to +2.0V and IFS can range from 0mA to 15mA. To reduce power supply noise separate analog and digital power supplies should be used with 0.1µF ceramic capacitors placed as close to the body of the HI1171 as possible. The analog (AVSS) and digital (DVSS) ground returns should be connected together back at the power supply to ensure proper operation from power up. In setting the output current the IREF pin should have a resistor connected to it that is 16 times greater than the output resistor: RREF = 16 x ROUT Test Circuits (LSB) D0 1 20 8-BIT COUNTER WITH LATCH OSCILLOSCOPE 2 VG 8 VREF 9 16 0.1µF CLK 200Ω 0.1µF BLK VB AVDD 17 D7 CLK 40MHz SQUARE WAVE IO 11 15 1kΩ 2V IREF AVSS 12 3.3kΩ FIGURE 5. MAXIMUM CONVERSION SPEED TEST CIRCUIT 6 HI1171 Test Circuits (Continued) (LSB) D0 1 20 IO DVM 2 CONTROLLER AVDD VG 8 0.1µF BLK VREF 9 16 0.1µF 1kΩ 2V 11 VB CLK 40MHz SQUARE WAVE 200Ω 17 D7 IREF 15 AVSS 12 CLK 3.3kΩ FIGURE 6. DC CHARACTERISTICS TEST CIRCUIT (LSB) D0 1 20 IO OSCILLOSCOPE 2 AVDD VG 17 D7 8 0.1µF BLK FREQUENCY DEMULTIPLIER CLK 10MHz SQUARE WAVE VREF 9 16 0.1µF 11 VB 200Ω 15 1kΩ 2V IREF AVSS 12 CLK 3.3kΩ FIGURE 7. PROPAGATION DELAY TIME TEST CIRCUIT (LSB) D0 1 20 8-BIT COUNTER WITH LATCH 2 VG 8 VREF 9 CLK 1MHz SQUARE WAVE DELAY CONTROLLER 16 0.1µF CLK OSCILLOSCOPE 75Ω 0.1µF BLK VB AVDD 17 D7 DELAY CONTROLLER IO 11 15 1kΩ 2V IREF AVSS 12 1.2kΩ FIGURE 8. SET UP HOLD TIME AND GLITCH ENERGY TEST CIRCUIT 7 Sales Office Headquarters ASIA Intersil (china) Ltd. china mainland TEL : (86) 13723742298 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 8