ISL24006 ® March 9, 2006 14-Channel Programmable Switchable I2C TFT-LCD Reference Voltage Generator with Integrated 4-Channel Static Gamma Drivers Features The ISL24006 is a 14-channel programmable switchable reference voltage generator with four channels of static gamma drivers integrated, for a complete 18-channel total gamma solution for TFT-LCD displays. The 14-channel programmable switchable configuration allows switching between two gamma curves. • Fast switch time (< 1µs) The ISL24006 is divided into two banks of seven generators: one designed to cover the range from VREFL_L to VREFL_H; the remaining seven channels covering the range from VREFU_L to VREFU_H. Each bank has its own separate high and low reference inputs, with integrated buffers (four static gamma drivers) to drive the column driver internal DAC resistor string to within 0.2V from the top and bottom rails. An output MUX is used to switch between the two curves in less than 1µs. Switching is controlled using an external select pin. • I2C interface • 14-channel programmable switchable • 4-channel static • Programmable with 20mV resolution • Digital supply 3.3V to 5V • Supply current of 32mA (without load) • Rail-to-Rail capability • Pb-free plus anneal available (RoHS compliant) Applications • TFT-LCD drive circuits • Reference voltage generators Pinout 32 OUT7 33 OUT6 34 OUT5 37 OUT2 OUT_REFU_H 1 Ordering Information TAPE & REEL PACKAGE PKG. DWG. # ISL24006IRZ (See Note) ISL24006IRZ - 38-Pin QFN MDP0046 (Pb-Free) ISL24006IRZ-T7 (See Note) ISL24006IRZ 7” 38-Pin QFN MDP0046 (Pb-Free) ISL24006IRZ-T13 ISL24006IRZ (See Note) 13” 38-Pin QFN MDP0046 (Pb-Free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 31 OUT_REFU_L AVDD 2 30 GND STD_REG 3 29 BG A0 4 28 GND SDA 5 27 VREFL_L SCL 6 26 VREFL_H THERMAL PAD OSC 7 25 NC DVDD 8 24 NC BANK_SEL 9 23 VREFU_L NC 10 22 VREFU_H GND 11 21 AVDD OUT_REFL_L 12 1 OUT8 19 OUT9 18 OUT10 17 OUT11 16 OUT12 15 OUT14 13 20 OUT_REFL_H OUT13 14 PART MARKING 38 OUT1 ISL24006 is available in the 38-pin QFN package and is specified for operation over the -40°C to +85°C temperature range. 36 OUT3 ISL24006 (38-PIN QFN) TOP VIEW ISL24006 includes an I2C interface for programming the offset values. PART NUMBER FN6110.1 35 OUT4 Data Sheet CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2005, 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL24006 Absolute Maximum Ratings (TA = 25°C) Supply Voltage between AVDD and GND . . . . . . . . . . . . . . . . .+18V Supply Voltage between DVDD and GND lesser of VS or +7V (max) Maximum Continuous Output Current [VREFU_H, VREFU_L, VREFL_H, VREFL_L] . . . . . . . . . . . . . 60mA [OUT1 to OUT14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Total Sourcing/Sink [Upper/Lower] . . . . . . . . . . . . . . . . . . 180mA Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. The device outputs cannot withstand shortcircuit condition for extended periods of time. To avoid damage, do not exceed absolute maximum rating of 20mA/channel. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER AVDD = 15V, DVDD = 5V, VREFU_H = 14V, VREFU_L = 8.5V, VREFL_H = 6.5V, VREFL_L = 1V, RL = 1kΩ and CL = 10pF to 1/2 AVDD, TA = 25°C, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 30 38 mA 2.75 4 mA SUPPLY IAVDD Supply Current IDVDD Digital Supply Current No load ANALOG VOH OUT1 to OUT7 VREFU_H = 14V, AVDD = 15V 13.94 13.98 14.02 V VOL OUT1 to OUT7 VREFU_L = 8.5V, AVDD = 15V 8.47 8.51 8.55 V VOH OUT8 to OUT14 VREFL_H = 6.5V, AVDD = 15V 6.44 6.48 6.52 V VOL OUT8 to OUT14 VREFL_L = 1.0V, AVDD = 15V 0.96 1.00 1.04 V PSRR Power Supply Rejection Ratio AVDD is moved from 14V to 16V 42 50 VAC Accuracy -50 0 +50 mV IB Input Bias Current, VREF(U_H, U_L, L_H, L_L) VREF = 1/2 AVDD 2 50 nA REG Load Regulation IOUT = 5mA step 0.5 BG Band Gap 1.1 1.3 SR Slew Rate 8 15 V/µs tS Settling Time 1 µs ±1/2 LSB dB mV/mA 1.4 V DIGITAL VIH Logic 1 Input Voltage VIL Logic 0 Input Voltage FCLK Clock Frequency RSDIN SDIN Input Resistance tS tH DVDD20% 20%* DVDD V 400 kHz 1 GΩ Setup Time 40 ns Hold Time 40 ns 2 SCL, SDA, STD_REG V FN6110.1 March 9, 2006 ISL24006 Block Diagram VREFU_L OSC CONTROL C3 VREFU_H OUT REFU_H INT/EXT OSCILLATOR 0 DELAY 1 S/H C0 MUX OUT1 MUX OUT2 MUX OUT3 MUX OUT4 MUX OUT5 MUX OUT6 MUX OUT7 S/H C1 S/H S/H C2 S/H S/H S/H S/H S/H S/H B MUX S/H S/H BANKA HI DAC HI S/H S/H SCL SDA I2C INTERFACE OUT REFU_L OUT REFL_H MUX B S/H BANKA LO STD_REG DAC LO S/H A0 MUX OUT8 MUX OUT9 MUX OUT10 MUX OUT11 MUX OUT12 MUX OUT13 MUX OUT14 S/H S/H S/H AVDD S/H ANALOG POWER S/H S/H S/H DVDD DIGITAL POWER S/H S/H S/H BG REFERENCE GENERATOR S/H S/H OUT REFL_L VREFL_H 3 VREFL_L BANK_SEL FN6110.1 March 9, 2006 ISL24006 Pin Descriptions PIN NUMBER PIN NAME PIN TYPE PIN FUNCTION 1 OUT REFU_H Analog Output Analog output of VREFU_H 2, 21 AVDD Analog Power Power supply for analog circuit 3 STD_REG Logic Input Selects mode, high = standard, low = register 4 A0 Logic Input I2C device address input, bit 0; when LO, hex address = 74; when HI, hex address = 75 5 SDA Input/Output I2C data 6 SCL Logic Input I2C clock 7 OSC Input/Output 8 DVDD Digital Power Power supply for digital circuit 9 BANK_SEL Digital Signal Select one of two sets of gamma voltages 10, 24, 25 NC 28, 30, 11 GND GND Input clock reference Not connected Ground 12 OUT REFL_L Analog Output Analog output of VREFL_L 13, 14, 15, 16, 17, 18, 19 OUT8 - OUT14 Analog Output Analog output voltages in lower range 20 OUT REFL_H Analog Output 22 VREFU_H Reference High reference for upper seven output voltages 23 VREFU_L Reference Low reference for upper seven output voltages 26 VREFL_H Reference High reference for lower seven output voltages 27 VREFL_L Reference Low reference for lower seven output voltages 29 BG Analog Bypass Pin 31 OUT REFU_L Analog Output Analog output of VREFU_L 32, 33, 34, 35, 36, 37, 38 OUT1 - OUT7 Analog Output Analog output voltages in upper range Analog output of VREFL_H Decoupling capacitor for internal reference generator Typical Performance Curves JEDEC JESD51-7 - HIGH EFFECTIVE THERMAL CONDUCTIVITY (4-LAYER) TEST BOARD 4.5 JEDEC JESD51-3 (2- LAYER) TEST BOARD QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 1.2 POWER DISSIPATION (W) POWER DISSIPATION (W) 4 QFN38 30°C/W 3.5 3 3.33W 2.5 2 1.5 1 0.5 0 0 25 50 75 85 100 AMBIENT TEMPERATURE (°C) 125 150 FIGURE 1. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 4 1 0.8 QFN38 125°C/W 0.8W 0.6 0.4 0.2 0 0 25 50 75 85 100 AMBIENT TEMPERATURE (°C) 125 150 FIGURE 2. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN6110.1 March 9, 2006 STANDARD MODE (STD/REG=HIGH) WRITE MODE I2C DATA I2C SDA In = don't care Device Address Start A6 A5 A4 A3 A2 A1 A0 W A W A I2C SDA Out Control Byte C7 C6 C5 C4 C3 Data 1 A C2 C1 C0 A A D7 D6 D5 D4 D3 Data 2 A D2 D1 D0 A A D7 D6 D5 D4 D3 D2 D1 D0 A A Data 12 14 Data 3 A D7 D6 D5 D2 D1 A D0 A Stop A A 5 1 I2C CLK In 2 3 4 5 6 7 8 9 R A R A 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 6 7 8 9 STANDARD MODE (STD/REG=HIGH) READ MODE I2C DATA Device Address Start Data 1 Data 2 A Data 3 A Data 14 12 NA Stop NA I2C SDA In A6 A5 A4 A3 A2 A1 A0 I2C SDA Out 2 3 4 5 6 7 A A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D2 D1 D0 A 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 6 7 8 9 W A W A REGISTER MODE (STD/REG=LO) WRITE MODE I2C DATA Device Address Start I2C SDA In A6 A5 A4 A3 A2 A1 A0 I2C SDA Out Register Address X X X X R3 R2 R1 R0 A 1 I2C CLK In 2 3 4 5 6 7 8 9 W A W A DATA A A D7 D6 D5 D4 D3 D2 D1 D0 A 1 2 3 4 5 6 7 8 9 STOP A A A 1 2 3 4 5 6 7 8 9 R A R A REGISTER MODE (STD/REG=LO) READ MODE I2C DATA I2C SDA In Device Address Start A6 A5 A4 A3 A2 A1 A0 I2C SDA Out I2C CLK In Register Address X X X X R3 R2 R1 R0 A 1 2 3 4 5 6 7 8 9 Device Address A A A6 A5 A4 A3 A2 A1 A0 A 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 DATA STOP A NA A D7 D6 D5 D4 D3 D2 D1 D0 A 9 1 2 3 4 5 6 7 8 9 FN6110.1 March 9, 2006 FIGURE 3. I2C TIMING DIAGRAM 1 1 ISL24006 1 I2C CLK In A ISL24006 General Description Byte Format The ISL24006 provides a versatile method of providing the reference voltages that are used in setting the transfer characteristics of LCD display panels. The V/T (Voltage/Transmission) curve of the LCD panel requires that a correction is applied to make it linear. However, if the panel is to be used in more than one application, the final curve may differ for different applications. By using the ISL24006, the V/T curve can be changed to optimize its characteristics according to the required application of the display product. Every byte put along the SDA line must be eight bits long. The number of bytes that can be transmitted between a Start and Stop condition is unrestricted. Data is always transferred with the most significant bit (MSB) first. Each of the 14 reference voltage outputs can be set with a 8bit resolution. The first half of the output buffers, OUT1 to OUT7 can be operated from VREFU_L to VREFU_H. The second half OUT8 to OUT14 can swing from VREFL_L to VREFL_H. It is also possible to use the ISL24006 for applications other than LCDs where multiple voltage references are required that can be set to 8-bit accuracy. Digital Interface The ISL24006 uses a simple two-wire I2C interface to program all 14 outputs. The bus line SCLK is the clock signal line and bus SDA is the bi-directional data information signal line. The ISL24006 can support a clock rate up to 400kHz. An external pull up typically 1kΩ resistor is required for each bus line. Acknowledge Each byte is followed by an acknowledge bit. When a master device is sending data (WRITE) the master puts a resistive high level on the SDA line during the acknowledge clock pulse. The peripheral that acknowledges, which is the receiver, has to pull down the SDA line during the acknowledge pulse. When a master device is receiving data (READ) the slave puts a resistive high level on the SDA line during the acknowledge clock pulse. The master will acknowledge by pulling down the SDA line during the acknowledge pulse. Not Acknowledge A Not Acknowledge (NA) is when the receiver does not pull down the SDA line during the acknowledge pulse: SDA line remains in the HI or in a high impedance state. A Not Acknowledge is the master device's signal to the slave device to release the SDA line so the master device can generate a Stop signal on the same line. The NA indicates that data just received is the last byte of the data transfer. Start and Stop Condition Standard Mode A Start condition is a high to low transition on the serial data line (SDA) line while the serial clock line (SCLK) holds high. The Stop condition is a low to high transition on the SDA line while SCLK is high. The master device always generates Start and Stop conditions. The bus is considered to be busy after the Start condition and to be free at a certain time interval after the Stop condition. The two bus lines must be high when the buses are not in use. The I2C Timing Diagram 2 (Figure 2) shows the format. When pin #6 (STD_REG) is pulled high, the part operates in Standard Mode, which is more commonly used than the Register Mode. In the Standard Mode, the user can program all outputs in one data stream or transfer frame. Data Validity For the Standard Mode in a WRITE transfer, a master device sends data to program all the output buffers of the ISL24006. The input data byte (DATA 1) to the first channel (OUT1) is the third byte following the control byte. The second channel (OUT2) is programmed by the fourth byte (DATA 2), and so on. Each byte is followed by an acknowledge bit. The data on the SDA line must be stable (clearly defined as HI or LO) during the HI period of the clock signal. SDA transition can only change when the clock signal on the SCLK line is LO. g g Start, Stop and Timing Details of I2C Interface Start Condition Stop Condition Data Clocked in SDA DATA SCL CLOCK tS tH tS tH tR tF FIGURE 4. I2C TIMING DIAGRAM 2 6 FN6110.1 March 9, 2006 ISL24006 TABLE 1. STANDARD MODE WRITE TRANSFER S ISL24006 ADDRESS + W A CONTROL BYTE A DATA 1 S = Start condition CONTROL BYTE = multifunction control P = Stop condition DATA 1 = 8-bit input to DAC OUT1 A = Acknowledge bit DATA 2 = 8-bit input to DAC OUT2 A DATA 2 A ... DATA 14 A P DATA 14 = 8-bit input to DAC OUT14 For the Standard mode in a READ transfer, a master device accepts data from the ISL24006. The output data byte (DATA 1) of the first channel (OUT1) is the second byte of the transfer. OUT2 output data byte is the third byte of the transfer, and so forth and so on. The ISL24006 sends an acknowledge bit after every eighth bit to tell the master device that the ISL24006 is ready to send another byte. Consequently, the master must send a Not Acknowledge, (NA) at the end of the 14th data byte to tell ISL24006 to release the SDA bus. program a desired reference voltage. A "1" indicates a Read transmission; the master device will receive data from the ISL24006 to read the previous data the voltage reference was set or programmed. TABLE 2. Standard Mode READ Transfer TABLE 3. Control Byte S ISL24006 ADDRESS + R A DATA 1 A DATA 2 A ... S = Start condition A = Acknowledge P = Stop condition NA = Not Acknowledge DATA 14 Control Byte The multi-function control byte contains information that selects the memory bank (bankA, or bankB), and operation (output, read, or write). It also controls the OSC pin function (external or internal). C7 C6 C5 C4 C3 C2 C1 C0 X X X X 0 0 0 0 P DATA 1 = 8-bit input to DAC OUT1 C0 = "1" 3.5µs lagging C1 DATA 2 = 8-bit input to DAC OUT2 DATA 14 = 8-bit input to DAC OUT14 See Timing Diagram 1 (Figure 1) for detailed formats. Devices Address and W/R Bit Data transfers follow the format shown in Timing Diagram 1. After the Start condition, a first byte is sent which contains the Device Address and write/read bit. This address is a 7-bit long device address and only two device addresses hex (74) and hex (75) in binary, bin (111010) and bin (111011) are allowed for the ISL24006. The first 6 bits (A6 to A1, MSBs) of the device address have been factory programmed and are always 111010. Only the least significant bit (LSB) A0 is allowed to change the logic state. This LSB is controlled externally on the pin #4, A0. When pulled high to DVDD, the LSB of the device address is high and thus the address is hex (75) or in binary bin (1110101). When pulled low to GND, the LSB of the device address low and thus the address is hex (74) or in binary 1110100. Since the device address has to be unique in the I2C bus line, a maximum of two ISL24006 may be used on the same bus at one time. The ISL24006 monitors the bus continuously and waiting for the Start condition followed by the device address. When the device recognizes its device address, it will start to accept data. The eighth bit (W/R) following the device address indicates the data direction. A "0" is a Write transmission; a master device will send data to the ISL24006 to set or 7 = "0" bypass oscillator = "0" write data to bankA (default) = "1" write data to bankB C2 = "0" read data from bankA (default) = "1" read data from bankB C3 = "0" internal oscillator (default) = "1" external oscillator The second bit, C1, selects which bank to write to. A "0" selects bankA. A "1" selects bankB. C1 is a "don't care" on a read mode. The third bit, C2, selects which bank to read from. A "0" selects bankA. A "1" selects bankB. C2 is a "don't care" on a write mode. The fourth bit, C3, selects the function of the OSC pin. A "0" selects the internal oscillator. When the internal oscillator is selected, the OSC pin acts as an output pin. It generates a square wave with a frequency of typically 20kHz where multiple chips can be synchronized. A "1" selects an external oscillator. When the external oscillator is selected, the OSC pin acts an input pin. Multiple chips can be synchronized to an external oscillator. The external frequency or refresh rate can be synchronized up to 200kHz typically. The rest of the bits (C4-C7) in the control byte are "don't cares". FN6110.1 March 9, 2006 ISL24006 Data Byte Data Bytes are the input code data to the 8-bit DACs. Most significant bits are clocked in first. These data bytes determine the output voltages of the ISL24006. TABLE 4. b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 1 1 0 1 0 7 6 5 4 3 2 1 0 2 × (1) + 2 × (0) + 2 × (1) + 2 × (1) + 2 × (1) + 2 × (0) + 2 × (1) + 2 × (0) Ideal Transfer Function Example Given a typical voltage applied to VREFU_H and VREFU_L: V REF U_H = 14V V REF L_H = 6.5V V REF U_L = 8.5V V REF L_L = 1V 14V – 8.5V R = ----------------------------- = 21.5mV 256 6.5V – 1V R = -------------------------- = 21.5mV 256 TABLE 5. BINARY INPUT DECIMAL VOUT1 (V) VOUT14 (V) 00000000 0 8.5 1 00000001 1 8.521484 1.021484 00000011 3 8.564453 1.064453 00000111 7 8.650391 1.150391 00001111 15 8.822266 1.322266 00011111 31 9.166016 1.666016 00111111 63 9.853516 2.353516 01111111 127 11.22852 3.728516 11111111 255 13.97852 6.478516 For transient load application, the external clock mode should be used to ensure all functions are synchronized together. The positive edge of the external clock to the OSC pin should be timed to avoid the transient load effect. The Application Drawing shows the LCD H rate signal used, here the positive clock edge is timed to avoid the transient load of the column driver circuits. After power on, the chip will default with the internal oscillator mode. At this time, the OSC pin will be in a high impedance condition to prevent contention. Channel Outputs Each of the channel outputs has a rail-to-rail buffer. This enables all channels to have the capability to drive to within 50mV of the power rails (see Electrical Characteristics for details). When driving large capacitive loads, a series resistor should be placed in series with the output. (Usually between 5Ω and 50Ω). Each of the channels is updated on a continuous cycle. The time for the new data to appear at a specific output will depend on the exact timing relationship of the incoming data to this cycle. Clock Oscillator Power-On Sequencing The ISL24006 require an internal clock or external clock to refresh its outputs. The outputs are refreshed at the falling OSC clock edges. The output refreshed switches open at the rising edges of the OSC clock. The driving load shouldn't be changed at the rising edges of the OSC clock. Otherwise, it will generate a voltage error at the outputs. This clock may be input or output via the clock pin labelled OSC. The internal clock is provided by an internal oscillator running at approximately 21kHz and can be output to the OSC pin. In a two-chip system, if the driving loads are stable, one chip may be programmed to use the internal oscillator; then the OSC pin will output the clock from the internal oscillator. The second chip may have the OSC pin connected to this clock source. At power-on, make sure that AVDD ≥ DVDD - 0.5V to prevent the ESD diode between AVDD and DVDD from driving too much current. If DVDD comes on first, leave AVDD floating. Do not ground AVDD. 8 Power Dissipation With the 30mA maximum continues output drive capability for each channel, it is possible to exceed the 125°C absolute maximum junction temperature. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the part to remain in the safe operation. FN6110.1 March 9, 2006 ISL24006 The maximum power dissipation allowed in a package is determined according to: T JMAX – T AMAX P DMAX = -------------------------------------------Θ JA where: • TJMAX = Maximum junction temperature • TAMAX = Maximum ambient temperature • θJA = Thermal resistance of the package • PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by the IC is the total quiescent supply current times the total power supply voltage and plus the power in the IC due to the loads. P DMAX = A VDD × I AVDD + Σ [ ( A VDD – V OUT i ) × I LOAD i ] when sourcing, and: P DMAX = A VDD × I AVDD + Σ ( V OUT i × I LOAD i ) when sinking. Where: • i = 1 to total 14 • AVDD = Supply voltage • IAVDD = Quiescent current • VOUTi = Output voltage of the i channel • ILOADi = Load current of the i channel By setting the two PDMAX equations equal to each other, we can solve for the RLOADs to avoid the device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat. Power Supply Bypassing and Printed Circuit Board Layout Good printed circuit board layout is necessary for optimum performance. A low impedance and clean analog ground plane should be used for the ISL24006. The traces from the two ground pins to the ground plane must be very short. The thermal pad should be connected to the analog ground plane. Lead length should be as short as possible and all power supply pins must be well bypassed. A 0.1µF ceramic capacitor must be placed very close to the AVDD, VREFU_H, VREFU_L, VREFL_H, VREFL_L, and BG pins. A 4.7µF local bypass ceramic capacitor should be placed to the AVDD, VREFU_H, VREFU_L, VREFL_H, VREFL_L pins. 9 FN6110.1 March 9, 2006 ISL24006 Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN6110.1 March 9, 2006