INTERSIL ISL6595

ISL6595
®
Data Sheet
February 27, 2006
Digital Multiphase Controller
Features
The ISL6595 digital multiphase controller provides core
power for today’s high current microprocessors by driving up
to six synchronous-rectified buck-converter channels in
parallel. Interleaved timing of the channels results in a higher
ripple frequency, reducing input and output ripple. With up to
six phases, each capable of up to 2MHz operation, the
ISL6595 can be used to build DC/DC converters that provide
up to 200A with excellent efficiency, low ripple, and the
lowest component count.
• Multiphase power conversion
- 1- to 6-phase operation
The ISL6595 utilizes digital technology to implement all
control functions, providing the ultimate in flexibility and
stability. The ISL6595 incorporates an industry standard I2C
serial interface for control and monitoring. Through the serial
interface, the power supply designer can quickly optimize
designs and monitor parameters. The interface allows the
ISL6595 to provide digitized information for real time system
monitoring and control.
• Precision digital current sense calibration
The ISL6595 provides superior loadline accuracy through
internal calibration that measures and corrects current sense
error sources upon startup. The ISL6595 has programmable
current sense temperature compensation that allows the
designer to tailor the response for best loadline accuracy
over temperature. Superior loadline accuracy reduces
component count and solution cost.
To further reduce component count the ISL6595
incorporates patented Active Transient Response (ATR)
technology, allowing the fastest response to transient events
for reduced output capacitance.
The flexibility of the ISL6595 allows the power supply
designer to implement a wide range of solutions. When used
with industry standard power train components, the ISL6595
provides the highest performance with lowest component
count and cost.
PART
MARKING
TEMP
(°C)
PACKAGE
(Pb-free)
PKG.
DWG #
ISL6595DRZ-T ISL6595DRZ 0 to 85 48 Ld 7x7 QFN L48.7x7P
Tape and Reel
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
• 100kHz to 2MHz switching frequency
• Supports Intel® VR10.x and VR11.0 VID codes
• Supports AMD® 5-bit and 6-bit VID codes
• Internal high precision voltage reference
- ±10mV voltage setpoint accuracy
• Precise digital current balancing with programmable
offsets for thermal balancing
• Digitally programmable loadline and loop compensation
• Differential voltage sense
• Digital temperature sensor compensation
• Active Transient Response (ATR) enables meeting
transient requirements with reduced output capacitance
• I2C interface for monitoring, control and configuration
• Internal non-volatile memory (NVM) to store custom
configurations
• Extensive fault detection capability with two user
configurable output fault pins (FAULT1, FAULT2)
- Input undervoltage
- Output under/overvoltage
- High side short
- Per phase and total output current
- Multiple internal and external temperature limits
- NVM configuration
- Calibration range and time-out
• Configurable latched fault or autonomous recovery
shutdown
• Single +3.3V supply operation
Ordering Information
PART
NUMBER
(Note)
FN9192.0
• Pb-free plus anneal available (RoHS compliant)
48 Ld QFN plastic package
Applications
• Core power regulation for Intel® and AMD® microprocessors
• Intelligent point-of-load (POL) power regulation
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6595
Pinout
VDD25
SCL
SDA
SADDR
RESET_N
LL0
CAL_CUR_EN
CAL_CUR_SEN
PWM1
ISEN1+
ISEN1-
PWM2
ISL6595 (QFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
VID7
1
36
VDD
VID6
2
35
ISEN2+
VID5
3
34
ISEN2-
VID4
4
33
PWM3
VID3
5
32
ISEN3+
VID2
6
31
ISEN3-
VID1
7
30
PWM4
VID0
8
29
ISEN4+
VID_SEL
9
28
ISEN4-
10
27
PWM6/ATRLBB
OUTEN
11
26
ISEN6+
VDD
12
25
ISEN6-
2
13
14
15
16
17
18
19
20
21
22
23
24
FAULT1
FAULT2
VR_READY
GND
V12_SEN
VSENN
VSENP
TEMP_SEN
ISEN5-
ISEN5+
PWM5
VDD
LL1
EXPOSED PAD
GND
FN9192.0
February 27, 2006
ISL6595
Functional Block Diagram (Differential I-Sense Inputs)
Window
Comparator
(OVP/UVP)
VSENP
VSENN
RESET_N
PWM6
POR
ISEN6+
ISEN6-
PWM5
Voltage
ADC
ISEN5+
ISEN5ISEN4+
ISEN4ISEN3+
PWM4
Current
Sense
ISEN3ISEN2+
ISEN2-
Current
ADC
ISEN1+
Channel
Current
ISEN1TEMP_SEN
PWM
Driver
Current
Balance
PID/PWM
Controller
PWM3
PWM2
AVP
PWM1
Temp
Sense
V12_SEN
SCL
SDA
I2C
FAULT2
Internal Memory
Fault Handler
SADDR
FAULT1
OUTEN
VID7
VID6
VID5
CAL_CUR_EN
VID4
Digital Calibration Controller
VID3
VID2
CAL_CUR_SEN
Deglitch
State Machine
VID1
VID0
VID_SEL
VR_READY
LL1
LL0
FIGURE 1. BLOCK DIAGRAM FOR DIFFERENTIAL I-SENSE, PWM-ONLY OUTPUT
3
FN9192.0
February 27, 2006
ISL6595
Typical VRD Application
+12V
`
+5V
ISL6594A
1 UGATE
PHASE 8
2 BOOT
PVCC 7
3 PWM
4 GND
4.7µF
+3.3V
V12_SEN
VDD
ISL6595
From
µP
GND
Fault
Outputs
ISL6594A
1 UGATE
PHASE 8
PVCC 7
VCC 6
VID7
PWM1
VID6
ISEN1+
3 PWM
VID5
ISEN1-
4 GND
4.7µF
PWM2
VID3
ISEN2+
VID2
ISEN2-
LGATE 5
`
PHASE 8
VID1
PWM3
VID0
ISEN3+
2 BOOT
PVCC 7
VID_SEL
ISEN3-
3 PWM
VCC 6
LL1
PWM4
4 GND
4.7µF
LL0
ISEN4+
OUTEN
ISEN4-
VR_READY
FAULT1
FAULT2
Vout
ISL6594A
1 UGATE
PWM5
To µP
`
2 BOOT
VID4
VCC 6
LGATE 5
LGATE 5
RTN
`
ISL6594A
ISEN5+
1 UGATE
PHASE 8
ISEN5-
2 BOOT
PVCC 7
PWM6
3 PWM
ISEN6+
4 GND
4.7µF
VCC 6
LGATE 5
ISEN6SDA
I2C I/F
SCL
SADDR
TEMP_SEN
RTHERM
CAL_CUR_EN
CAL_CUR_SEN
VSENP
VSENN
FIGURE 2. 4-PHASE VRD DESIGN
4
FN9192.0
February 27, 2006
ISL6595
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . -0.50V to 4.25V
All Pins Except ISENx, VSENP,
VSENN and Ground . . . . . . . . . . . . . . . . . . . . . . . -0.50V to 4.25V
All ISENx, VSENP, VSENN Pins . . . . . . . . . . . . . . . . -0.50V to 3.0V
All Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50V to 0.50V
ESD (Per JEDEC JES22-A114-B, JESD22-C101A, JESD22-A115-A)
Human Body Model (100pF, 1.5kΩ) . . . . . . . . . . . . . . . . . . 3,000V
Charged Device Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1,000V
Vapor Phase (60s), TVAPOR . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15s), TIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
θJC (°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . .
31
3
Maximum Junction Temperature (Plastic Package) . . 0°C to 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . +3.0V to +3.60V
Operating Case Temperature. . . . . . . . . . . . . . . . . . . . 0°C to 125°C
Operating Ambient Temperature . . . . . . . . . . . . . . . . . . 0°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VDD = +3.3V, TC = +25°C, unless otherwise specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
100
140
mA
Input LOW Voltage
-0.3
-
0.5
V
Input HIGH Voltage
2.8
-
3.6
V
VDD SUPPLY
Nominal Supply Current
IVDD
RESET_N
Input Current, Input Voltage LOW
VIN = 0.0V
-75
-
-10
µA
Input Current, Input Voltage HIGH
VIN = 3.5V
-
-
-
µA
Input Low Voltage
-0.3
-
0.4
V
Input High Voltage (Note 4)
0.8
-
5.5
V
VID[7:0], OUTEN, LL0, LL1, VID_SEL (Note 3)
Input Current, Input Voltage Low
VIN = 0.0V
-
-20
-30
µA
Input Current, Input Voltage High
VIN = 3.5V
-
15
25
µA
OUTEN INPUT
Input Threshold
VT_VR_EN
0.8
0.85
0.9
V
Input Hysteresis
VH_VR_EN
-
100
-
mV
-
-
20
MHz
Input Bandwidth
SDA, SCL INPUTS
Input LOW Voltage
VIL_S
-0.3
-
0.8
V
Input HIGH Voltage
VIH_S
2.4
-
5.5
V
Input Current, Input Voltage Low
IIL_S
VIN = 0.0V
-10
-
10
µA
Input Current, Input Voltage High
IIH_S
VIN = 3.5V
-10
-
10
µA
-
-
0.4
V
Output LOW Voltage
5
FN9192.0
February 27, 2006
ISL6595
Electrical Specifications
VDD = +3.3V, TC = +25°C, unless otherwise specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-0.3
-
0.3
V
-
-
1.5
MHz
VSENP, VSENN INPUTS
VSENN Voltage (Note 5)
Bandwidth
VSENP
VSENP = 1.6V
-10
-
10
µA
VSENN
VSENN = 0V
-10
-
10
µA
-275
-
-10
µA
Input Resistance
-
100
-
Ω
Clamp Voltage
-
1.65
-
V
TA = 25°C
-
-
1.6
%
TA = 0°C to 85°C
-
-
2
%
TA = 25°C
-
-
2
%
TA = 0°C to 85°C
-
-
2.2
%
ISEN[6:1]+ INPUTS
Input Current Range
I-sense Amplifier Linearity Error
Current Conversion ADC Error
Single-Ended rDS(on) Mode Bias Voltage
Programmable from 25mV to 100mV
-18
-
18
mV
Differential rDS(on) Mode Bias Voltage
Programmable from 25mV to 100mV
-18
-
18
mV
-
-
-
0µA Setting
-2.5
-
2.5
µA
-12.5µA Setting
-16
-
9
µA
-25µA Setting
-30
-
20
µA
-37.5µA Setting
-45
-
30
µA
0.19
-
0.22
V
-
295
-
mV
-275
-
-10
µA
-
200
-
Ω
TA = 25°C
1.15
-
1.25
V
TA = 0°C to 85°C
1.14
-
1.26
V
TA = 25°C
0.95
-
1.05
V
TA = 0°C to 85°C
0.94
-
1.05
V
Input LOW Voltage
-0.3
-
0.1
V
Input HIGH Voltage
VDD0.1
-
3.6
V
Input Current, Input Voltage LOW
-800
-
-400
µA
Input Current, Input Voltage HIGH
400
-
800
µA
Tri-State Input Bias Voltage
1.5
-
1.8
V
ISEN[6:1]- DCR SENSE MODE
Bias Current Accuracy
Programmable from 0 to 37.5µA
CAL_CUR_SEN INPUT
Sensed Voltage
RSEN = 20mΩ, Ical = 10A
TEMP_SEN INPUT
Bias Voltage
Iin = -20µA
Input Current Range
Input Resistance
V12_SEN INPUT
Voltage Threshold (Turn On)
Voltage Threshold (Turn Off)
SADDR INPUT
6
FN9192.0
February 27, 2006
ISL6595
Electrical Specifications
VDD = +3.3V, TC = +25°C, unless otherwise specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PWM[6:1] OUTPUTS
Output LOW Voltage
VOL
Open drain output, ILOAD = +5mA
-
-
0.4
V
Output LOW Voltage
VOL
Open drain output, ILOAD = +16mA
-
0.5
-
V
Output LOW Voltage
VOL
ILOAD = +5mA
-
-
0.4
V
Output LOW Voltage
VOL
Open drain output, Iload = +16mA
-
0.5
-
V
Output HIGH Voltage
VOH
ILOAD = -5mA
2.4
-
-
V
Output Current in Hi-Z State
IOZ
VOUT = 1.65V
-10
-
10
µA
Output LOW Voltage
VOL
ILOAD = +500µA
-
-
0.4
V
Output HIGH Voltage
VOH
ILOAD = -1mA
2.8
-
-
V
Output Low Voltage
VOL
ILOAD = ±500µA
0
-
0.3
V
Output High Voltage
VOH
ILOAD = ±500µA
0.8
-
3.3
V
From 10 – 90%
-
-
150
ns
VID = 1.20V, TA = 25°C
-8
-
+8
mV
VID = 0.85V to 1.65V, TA = 0 to 85°C
-10
-
+10
mV
TA = 25°C
-
-
0.4
%
TA = 0 to 85°C
-
-
0.75
%
TA = 25°C
-
-
8.5
mV
TA = 0 to 85°C
-
-
9
mV
TA = 25°C
-5
-
5
%
TA = 0 to 85°C, VDD = 3.0V to 3.6V
-10
-
10
%
0.35
0.40
0.45
V
-50
-
50
mV
-
-
-
-10
-
10
°C
FAULT1, FAULT2 OUTPUTS
CAL_CUR_EN OUTPUT
VR_READY OUTPUT (Note 3)
Transition Edge Rate
SETPOINT ACCURACY
Setpoint Accuracy (Note 5)
VREF
Voltage Conversion Gain Error (Note 5)
Voltage Conversion ADC Error INL (Note 5)
GREF3
INLvadc
SWITCHING FREQUENCY, RANGE 100kHz TO 2MHz (Note 6)
Frequency Accuracy (Note 6)
FAULT MONITORS
VOUVP
OUVP Threshold Voltage
OOVP Threshold Accuracy (Note 7)
Programmable from 0.225V to 1.8V
Internal OTP Threshold Range
See PTAT shut_down in Table 9
Internal OTP Threshold Accuracy
IUVP Rising Threshold Voltage
VIUVP_LH
1.15
-
1.25
V
IUVP Falling Threshold Voltage
VIUVP_HL
0.95
-
1.05
V
NOTES:
3. An open input will float to the logic-1 state. This feature is not intended as a replacement for an external pull-up resistor when the input is driven
by an open-drain driver.
4. VIH(max) is guaranteed but not tested. Input current is typically less than 2mA at VIH = +4V. In applications requiring +5.5V tolerance, the device
must be driven by a source impedance greater than 1kΩ.
5. Guaranteed but not tested in production.
6. Setting is programmable.
7. Guaranteed by calibration during production test.
7
FN9192.0
February 27, 2006
ISL6595
Pin Description
PIN #
NAME
I/O
TYPE
DESCRIPTION
1
VID7
I
1.2V CMOS
Bit 7 of processor voltage identification word (MSB of 8-bit VID word).
2
VID6
I
1.2V CMOS
Bit 6 of processor voltage identification word.
3
VID5
I
1.2V CMOS
Bit 5 of processor voltage identification word.
4
VID4
I
1.2V CMOS
Bit 4 of processor voltage identification word.
5
VID3
I
1.2V CMOS
Bit 3 of processor voltage identification word.
6
VID2
I
1.2V CMOS
Bit 2 of processor voltage identification word.
7
VID1
I
1.2V CMOS
Bit 1 of processor voltage identification word.
8
VID0
I
1.2V CMOS
Bit 0 of processor voltage identification word (LSB of 8-bit VID word).
9
VID_SEL
I
1.2V CMOS
VID table selection input.
“1” Æ VR11 VID table selected
“0” Æ VR10 VID table selected
10
LL1
I
1.2V CMOS
Processor load line select input control signal (MSB). Selects regulator load line
resistance.
11
OUTEN
I
1.2V CMOS
Processor output enable input signal used to command the regulator output.
“1” Æ Regulator output voltage enabled
“0” Æ Regulator output voltage disabled
12
VDD
I
VDD
3.3V power supply connection; decoupling cap should be placed close to pin.
13
FAULT1
O
3.3V CMOS
Programmable fault indicator #1.
14
FAULT2
O
3.3V CMOS
Programmable fault indicator #2.
15
VR_READY
O
Open Drain
Digital Controller output signal to indicate the regulator output voltage is within the
specified range.
“1” Æ µP VCC within 10% of target regulation voltage
“0” Æ µP VCC outside 10% of target regulation voltage
16
GND
17
V12_SEN
I
Analog
12V voltage divider input. Used to guarantee valid input power supply before starting
up (undervoltage lockout).
18
VSENN
I
Analog
Negative voltage sense input.
19
VSENP
I
Analog
Positive voltage sense input.
20
TEMP_SEN
I
Analog
External thermistor temperature sense. Connected to ground through a negative TC
thermistor, with series and shunt resistance added to achieve desired range. See
External Temperature Sense section for more information.
21
ISEN5-
I
22
ISEN5+
I
Analog
Phase channel #5 ADC current sense (+) input.
23
PWM5
O
3.3V CMOS
Phase channel #5 PWM output.
24
VDD
I
VDD
3.3V power supply connection; decoupling cap should be placed close to pin.
25
ISEN6-
I
26
ISEN6+
I
Analog
Phase channel #6 ADC current sense (+) input.
27
PWM6/ATRLBB
O
3.3V CMOS
Phase channel #6 PWM output or optional external ATRL output.
28
ISEN4-
I
29
ISEN4+
I
Analog
Phase channel #4 ADC current sense (+) input.
30
PWM4
O
3.3V CMOS
Phase channel #4 PWM output.
31
ISEN3-
I
32
ISEN3+
I
Analog
Phase channel #3 ADC current sense (+) input.
33
PWM3
O
3.3V CMOS
Phase channel #3 PWM output.
Pin used in test mode only, tie to Ground for normal operation.
8
Phase channel #5 ADC current sense (-) input, tie to ground if the phase is unused.
Phase channel #6 ADC current sense (-) input, tie to ground if the phase is unused.
Phase channel #4 ADC current sense (-) input, tie to ground if the phase is unused.
Phase channel #3 ADC current sense (-) input, tie to ground if the phase is unused.
FN9192.0
February 27, 2006
ISL6595
Pin Description
PIN #
(Continued)
NAME
I/O
TYPE
DESCRIPTION
34
ISEN2-
I
Phase channel #2 ADC current sense (-) input, tie to ground if the phase is unused.
35
ISEN2+
I
Analog
Phase channel #2 ADC current sense (+) input.
36
VDD
I
VDD
3.3V power supply connection, decoupling cap should be placed close to pin.
37
PWM2
O
3.3V CMOS
Phase channel #2 PWM output.
38
ISEN1-
I
39
ISEN1+
I
Analog
Phase channel #1 ADC current sense (+) input.
40
PWM1
O
3.3V CMOS
Phase channel #1 PWM output.
41
CAL_CUR_SEN
I
Analog
Calibration current sense input. Measures the voltage across the calibration sense
resistor and adjusts CAL_CUR_EN via an op amp loop such that the voltage across the
resistor is 200mV.
42
CAL_CUR_EN
O
Analog
Calibration current enable output. Drives the calibration FET gate voltage to adjust its
rDS(on) such that voltage across the sense resistor is set at 200mV.
43
LL0
I
1.2V CMOS
Processor load line select input control signal (LSB). Selects regulator load line
resistance and loadline offset voltage.
44
RESET_N
I
3.3V CMOS
Active LOW asynchronous system reset to place ISL6595 into default state.
“1” Æ asynchronous reset disabled
“0” Æ asynchronous reset enabled
45
SADDR
I
3.3V CMOS
I2C address LSB select.
“1” Æ Address 1110001 selected
“0” Æ Address 1110000 selected
46
SDA
I
3.3V CMOS
I2C interface serial data line.
47
SCL
I
3.3V CMOS
I2C interface serial clock line.
48
VD25
I
Analog
Decoupling capacitor for 2.5V internally generated voltage, recommend
0.01µF, 0.1µF max.
Phase channel #1 ADC current sense (-) input, tie to ground if the phase is unused.
General Description
The ISL6595 is a digital multi-phase pulse width modulation
controller integrated circuit for use in 2- to 6-phase
synchronous buck converter CPU core supply power
switching regulators. The device is optimized for delivering
voltages from 0.5 to 1.6V at high current levels (120A+) with
programmable PWM switching frequencies between 100kHz
and 2MHz. The ISL6595 brings the benefit of digital control
to voltage regulators targeting Intel® VRD/VRM 10.x, 11.0
and similar applications.
The ISL6595 is designed to maximize value to the user by
providing features, monitoring and performance to minimize
the number of required off-chip components, work with a
variety of widely available standard components, and to
accommodate wider device tolerance mismatches than
competing analog controller solutions.
The ISL6595 provides both ease-of-use and flexibility to the
user. Major features include:
• Internal Voltage and Temperature Reference – An internal
factory trimmed ±0.5% voltage reference sets the VID
DAC, voltage ADC and current ADC range. In addition, a
proportional-to-absolute-temperature (PTAT) reference is
9
generated and digitized to serve as the controller
temperature sensor.
• Internal Oscillator – Provides a factory trimmed
156.25MHz ±10% clock reference. Fixed and
programmable dividers generate all the needed internal
clocks to configure the controller’s switching frequency
and number of active phases.
• Dedicated Voltage ADC – A high precision differential
input voltage ADC digitizes the differential remote sense
voltage. An integrated anti-alias filter and ripple frequency
null filter minimize the impact of high frequency noise on
the system.
• Multiplexed Current Sense ADC – The average currents
from each phase are sensed as a voltage across the low
side FET using the multiplexed current ADC. Each phase
is sampled at the middle of its cycle, with timing optimized
through a programmable delay line. The internal
temperature reference and external thermistor
temperature are also digitized using the multiplexed
current ADC. Gain and offset of the sensor and ADC are
compensated through either a one time factory calibration,
or through a power-up calibration each time the output
voltage is reset.
FN9192.0
February 27, 2006
ISL6595
• Digital Control Loop and AVP – An over-sampled digital
Proportional-Integral-Derivative (PID) compensator
provides flexible loop compensation with programmable
coefficients. A digital post-filter provides additional phase
lead and/or high frequency filtering to optimize the
transient response and ripple of the system. A high
accuracy Active Voltage Positioning (AVP) loadline is
computed using the calibrated current sense
measurements. The AVP bandwidth is also programmable
to allow it to be optimized for dynamic performance.
• Window comparators – Window comparators with fixed
thresholds for input undervoltage lockout (IUVP), output
undervoltage and overvoltage protection (OUVP and
OOVP). In addition a second OOVP comparator is
provided with a programmable threshold with respect to
the VID.
• Active Transient Response (ATR) – ATR comparators with
programmable thresholds are used to provide fast
response to dynamic load transients, minimizing spike
overshoot and droop undershoot.
• Configurable PWM Generators – 1-6 PWM waveforms are
digitally generated ensuring low jitter and high linearity.
PWM outputs are configurable as either single tri-valent
outputs or dual outputs with programmable non-overlap
delay. Phases can be fully overlapped, with programmable
duty cycle limiting.
• Integrated NVM - Digital configuration is stored in an
integrated NVM, allowing fully independent (stand-alone)
operation. NVM is fully accessible to user so that a
completely new parameter set can be written. Vendor and
user defined memory locations are provided, allowing
version control and part identification. NVM integrity is
checked every configuration cycle through a cyclic
redundancy check (CRC) comparison.
• Serial Interface – Intersil PowerCode software provides
easy access to all configuration, telemetry, and testability
features over a 2 wire I2C serial interface.
The Intersil PowerCode interface allows full accessibility to
regulator telemetry during system operation including:
• Internal Controller Temperature
• External (via optional thermistor) System Temperature
• Per Phase Current
• Total Output Current
• Output Voltage
• Input Voltage
• Configurable latched and unlatched individual fault status
• Microprocessor Leakage Current
• User defined memory space
Fault reporting and shutdown behavior are also fully
configurable. Two individual fault outputs are provided
(FAULT1, FAULT2), both of which can be masked
independently. The outputs can be configured as either
10
latched or unlatched, active high or active low polarity, and
CMOS or open drain outputs. The shutdown operation also
allows all faults to be individually masked and for the
shutdown operation to be either latched or unlatched.
Individual status registers allow fault reporting over the serial
bus to identify the specific fault event. Fault detection
includes the following:
• Input Undervoltage (IUVP)
• Output Overvoltage (OOVP)
• Output Undervoltage (OUVP)
• Per Phase Overcurrent
• Total Output Overcurrent (OCP)
• Two levels of Internal Temperature Protection
• Four levels of External Temperature Protection
• Configuration Failure
• Calibration Time-out Failure
Theory of Operation
Power Up and Initialization
The ISL6595 is designed to provide supply sequence
independence and graceful turn-on and turn-off operation. It
operates from a single +3.3V supply, while an on-chip low
drop-out (LDO) regulator generates an internal +2.5V
supply. Power-up controller configuration is initialized by
either an internal threshold based power-on reset, or by an
external reset pin (RESET_N). During controller
configuration, the contents of the NVM are read into the
controller’s registers. During configuration, all outputs are
three-stated, allowing board pull-up or pull-down resistors to
set the correct default level.
Once configuration is completed, the controller enters an
inactive state. Outputs assume their default values, which
may be low, high or three-state. During the inactive state, the
controller can communicate over the serial bus, report
configuration or inactive state faults. The controller will leave
the inactive state and begin soft-start once it has a valid VID,
VR_EN is asserted, and the 12V power input is valid. The
12V input is sensed through a resistive divider on the board,
and a fixed threshold comparator must be tripped if the input
undervoltage lockout is enabled. The sense circuit can be
easily modified to also sense an independent or sequenced
lower drive voltage typically used to optimize the efficiency of
the power stage low side FET.
Soft-Start and Calibration
Prior to entering an active regulating state, the ISL6595
performs a well-controlled, monotonic initial ramp or “softstart”. Soft-start is performed by actively regulating the load
voltage while digitally ramping the target voltage from 0 to
the voltage set. During this time, the optional power-up
system calibration can be performed. The calibration
FN9192.0
February 27, 2006
ISL6595
algorithm compensates for variations in low-side FET
rDS(on), parasitic inductance and resistance by regulating to
a low voltage level, putting a known current load through
each phase individually and compensating for the current
sense gain and offset error, as well as changes in
temperature. Alternatively, default compensation values can
be used, or the compensation values can be computed
during system test and stored in memory. The external
current load needed to perform calibration can be
implemented with a precision resistor and N-channel FET.
The voltage across the resistor is sensed and the N-channel
FET gate voltage is adjusted through an internal op amp
loop to provide the desired precision current. The calibration
current level and the voltage level at which the calibration is
performed are both programmable.
After the soft-start ramp is completed, the regulator enters
the active regulation state and the VR_READY pin
transitions from “0” to “1”, indicating that the microprocessor
voltage is within ±10% of the target value.
VCC (500mV/DIV)
Timing is provided by an on-chip, factory trimmed,
temperature compensated oscillator.
The ISL6595 operates with a fixed switching frequency (i.e.
the switching frequency is fixed independent of load) that is
configurable between 100kHz and 2MHz. A programmable
divider is used to generate the switching frequency, where
the frequency is given by:
Fsw = 156.25MHz/(2 x div_sel x Nph)
where Fsw is the switching frequency, 156.25MHz is the
nominal frequency of the timing reference oscillator, div_sel
is the programmable divider ratio between 6 and 127, and
Nph is the number of phases between 1 and 6.
Output Voltage Sensing and Voltage ADC
VR_READY
(2V/DIV)
4.0ms/DIV
FIGURE 3. SOFT-START/CALIBRATION SEQUENCE (3-PHASE)
Shutdown
The ISL6595 also performs a controlled shutdown response
to minimize any voltage undershoot. The shutdown state can
be entered from the soft-start or active regulation states
either through user intervention (de-asserting VR_EN or all
one’s VID), or through a detected fault such as overtemperature or output overvoltage. During shutdown, the
PWM width is reduced at a steady programmable rate, and
then the power stage is three-stated once the pulse width
reaches 0.
After shutdown is complete, the controller re-enters the
inactive state after a fixed delay. This delay minimizes the
duty cycle associated with autonomous restarts if the fault
that caused the shutdown disappears once the output is
disabled. Alternatively, the fault can be configured so that it
11
Switching Frequency
Switching frequencies of less than 300kHz and greater than
1.5MHz are supported only for some number of phases
used.
CAL_CUR_EN
(2V/DIV)
CAL_CUR_SEN
(100mV/DIV)
is latched and clearing requires user intervention such as
toggling VR_EN, toggling RESET_N, or cycling power. If this
method is used, the user should ensure adequate delay is
provided to complete the shutdown prior to the start of a new
start-up. The delay may be as short as 2ms, although longer
delays are recommended to minimize the duty cycle in case
there is a fault which causes the start-up and shutdown cycle
to be repeated indefinitely.
The ISL6595 is built around a high performance digital
feedback control loop that senses the differential voltage at
the load. This is used to generate the appropriate pulse
width modulated (PWM) waveforms to drive the power
stages and regulate the load voltage.
The differential sense voltage is digitized with a high speed,
high precision analog-to-digital converter (ADC). The onchip factory trimmed temperature compensated bandgap
voltage reference ensures the ADC accuracy is well within
the regulator setpoint accuracy requirements. The ADC is
sampled synchronously so that there are 2 ADC samples
per phase per switching cycle, at a frequency given by:
Fs = 156.25MHz/div_sel
The ADC also includes a post-filter which provides a null at
Fsw * (Nph/2), which is the ripple frequency. This ripple null
filter works in conjunction with an internal analog anti-alias
filter. The anti-alias filter is a single pole, 2MHz low pass
filter. The corner frequency can be lowered by adding series
resistors in the board.
Current Sensing and Current ADC
The ISL6595 provides for precise current monitoring in each
power stage, allowing for industry-leading loadline accuracy
for active voltage positioning (AVP). The current in each
power stage is sensed through one of three methods
supported by the ISL6595. These are single-ended rDS(on)
FN9192.0
February 27, 2006
ISL6595
sense of the low-side FET, differential rDS(on) sense of the
low-side FET, or differential DCR sense of the buck inductor.
The sensed current is digitized using a multiplexed current
ADC.
For low-side rDS(on) current sense applications, the ISENx+
pin is held at virtual ground with a programmable offset from
25 to 100mV. An external sense resistor is connected to the
drain of the low side FET to monitor the current in this
device. The current sourced from the input is then given by:
ISEN = (Voffset – VrDS(on))/RSEN1. Input current is digitized
with the ADC with an effective ADC range of 0 – 275µA in
4.3µA steps.
For DCR current sense applications, a resistor in series with
a capacitor is placed across the inductor for each phase. In
this configuration, the resistor is tied to the FET side of the
inductor while the capacitor is tied to the load side of the
inductor. If the RC values are chosen such that the RC time
constant matches the L/DCR time constant, the resultant
voltage appearing across the capacitor will equal the voltage
across the inductor series resistance and thus represent the
current flowing through the inductor. In this application, a
sense resistor is then placed from the ISENx+ pin to the load
side of the capacitor while the ISENx- pin in placed on the
FET side of the capacitor. The current sourced from the input
is then given by: ISEN = (Voffset – Vdcr)/RSEN. Input
current is digitized with the ADC with an effective ADC range
of 0 – 275µA in 4.3µA steps.
Differential rDS(on) Current Sense
The positive current sense inputs (ISEN1+ to ISEN6+) are
held at a virtual ground with a programmable offset from
25mV to 100mV, in 25mV steps. The negative current sense
inputs (ISEN1- to ISEN6-) should be tied to the ground plane
local to the low side FET being sensed to eliminate the
effects of ground differences between the FET and the
ISL6595. The large voltage swing at the drain of the low side
FET is eliminated by using a series resistor, converting the
signal to a current equal to:
be either programmed as a default value, or it can be
determined by running the calibration routine either one time
at system test or every time the system starts up. Calibration
is performed by providing a known current load while the
regulator is on and correcting the gain and offset of the
current measurement. This requires the use of a precision
external current source consisting of a dedicated calibration
FET and sense resistor. The ISL6595 senses the voltage
across the resistor and provides a variable voltage to drive
the gate of the calibration FET, varying its rDS(on) such that
the current through the FET and resistor are under closed
loop control. The calibration current and voltage level at
which calibration occurs are programmable, and the
calibration routine can be bypassed if the default values are
to be used. The rDS(on) value is compensated for
temperature drift using either the on-chip temperature sense
or an external thermistor that can be placed close to the
power stage.
Differential DCR Current Sense
For DCR current sense applications, a resistor in series with
a capacitor is placed across the inductor for each phase. In
this configuration, the resistor is tied to the FET side of the
inductor while the capacitor is tied to the load side of the
inductor. If the RC values are chosen such that the RC time
constant matches the L/DCR time constant, the resultant
voltage appearing across the capacitor will equal the voltage
across the inductor series resistance and thus represent the
current flowing through the inductor. In this application, a
sense resistor is then placed from the ISENX+ pin to the
load side of the capacitor while the ISENX- pin in placed on
the FET side of the capacitor. The current sourced from the
input is then given by: ISEN = (Voffset – Vdcr)/RSEN. Input
current is digitized with the ADC with an effective ADC range
of 0 – 275µA in 4.3µA steps.
External Temperature Sense
VIN
PWM
Isense = (Voffset – Vds)/Rsense
where Isense is the current sourced by the sense input,
Voffset is the programmable offset, Vds is the voltage across
the low side FET, and Rsense is an external resistor whose
value is chosen to scale the input depending on the
expected rDS(on).
The input current is mirrored and multiplexed, then digitized
by the 6-bit current ADC with an effective input range of 0 to
275µA in 4.3µA steps. The ADC samples the current in each
phase once per switching cycle, and the sampling instant
can be varied using a programmable delay, such that
sampling in the middle of the ON-cycle can be guaranteed.
The current in the power stage can then be inferred from the
current ADC measurement if the drain-source resistance
(rDS(on)) of the FET is known. The rDS(on) of each FET can
12
VOUT
ISL6594
ISL6595
ISEN-
ISEN+
PWM
ADC
FIGURE 4. DIFFERENTIAL DCR SENSE
When configured to sense temperature from an external
thermistor, the temperature sense input, TEMP_SEN, is set
at virtual ground with a fixed offset of 300mV. An external
negative TC thermistor is tied to ground, generating the input
FN9192.0
February 27, 2006
ISL6595
Kfd1 and Kfd2 are the coefficients of a second order all
pole low pass post-filter
current for the measurement. A series and shunt resistor
network should be used to scale the resultant current to the
proper range. The current range is the same as the current
sense inputs, from 0 to 275µA in 4.3µA steps.
Kmod is a programmable maximum duty cycle scaling
term
The ADC measurements are converted to temperature using
a programmable 4-segment piece-wise linear table while the
internal proportional-to-absolute temperature (PTAT)
reference is digitized directly, using a linear curve fit. Both
internal and external temperature measurements are
multiplexed through the current ADC at a low frequency,
providing run-time internal and external temperature
information to perform temperature compensation, reporting,
alerts, and shutdown.
The control loop operates at the same frequency as the
voltage ADC, which is synchronous to the switching
frequency and given by:
Digital Control Loop and PWM Generation
Fs = 2 * Nph * Fsw = 156.25MHz/div_sel
The digital control loop uses a proportional, integral, and
derivative (PID) compensator to drive the digitized sense
voltage to the desired target. An additional second
derivative gain term and a 2nd order post-filter provide
additional high order zeros and poles to further refine the
wideband characteristics of the loop. All loop parameters
are programmable over a wide range of values, allowing
loop bandwidths of 10-300kHz to be attained depending on
the number and type of power stages used.
The compensator digital output is converted to a pulse width
using a digital counter based pulse width modulator. The
pulse width modulator uses 2 successive samples to
modulate the leading edge and then the trailing edge of a
pulse. The modulator provides for monotonic edge
placements with a resolution of 100ps. The next 2 samples
are then used to modulate the next phase in the firing
sequence. The pulse width modulator is capable of setting a
maximum duty cycle limit, overlapping adjacent phases, a
minimum pulse width of 13ns, and also producing zero pulse
width with minimal glitching.
Nph is the number of phases and div_sel is the divider
ratio setting the switching frequency
Vin is the power stage input voltage, typically 12V
Q is the ADC step size, 3.125mV
The effective transfer function of the compensator is given
by:

 V 
 Ki

1 + K fd1 + K fd2
Kmod

 in 
H( z ) = 
+ K p + K d (1 − z −1) + K d2 (1 − z −1)2 
 1 − z −1
 1 + K fd1z −1 + K fd2z −2  Nph ⋅ div _ sel  Q 
where:
Ki, Kp, Kd, and Kd2 are the integral, proportional,
derivative, and second derivative gain terms
Voltage Identification Codes
The target voltage is provided by external parallel 8-bit
voltage identification (VID) inputs. The ISL6595 is fully
compliant with VRD/VRM 11.0 deglitching and dynamic VID
stepping requirements.
TABLE 1. Intel® VR10 VID TABLE (WITH 6.25mV EXTENSION, Note 8)
VIDHI
(HEX)
VIDLO
(HEX)
VOLTAGE
(V)
VIDHI (HEX)
VIDLO (HEX)
VOLTAGE
(V)
VIDHI (HEX)
VIDLO (HEX)
VOLTAGE
(V)
2
B
1.6
5
4
1.33125
0
1
1.0875
2
A
1.59375
5
7
1.325
0
0
1.08125
2
D
1.5875
5
6
1.31875
0
3
1.075
2
C
1.58125
5
9
1.3125
0
2
1.06875
2
F
1.575
5
8
1.30625
0
5
1.0625
2
E
1.56875
5
B
1.3
0
4
1.05625
3
1
1.5625
5
A
1.29375
0
7
1.05
3
0
1.55625
5
D
1.2875
0
6
1.04375
3
3
1.55
5
C
1.28125
0
9
1.0375
3
2
1.54375
5
F
1.275
0
8
1.03125
3
5
1.5375
5
E
1.26875
0
B
1.025
3
4
1.53125
6
1
1.2625
0
A
1.01875
3
7
1.525
6
0
1.25625
0
D
1.0125
3
6
1.51875
6
3
1.25
0
C
1.00625
13
FN9192.0
February 27, 2006
ISL6595
TABLE 1. Intel® VR10 VID TABLE (WITH 6.25mV EXTENSION, Note 8) (Continued)
VIDHI
(HEX)
VIDLO
(HEX)
VOLTAGE
(V)
VIDHI (HEX)
VIDLO (HEX)
VOLTAGE
(V)
VIDHI (HEX)
VIDLO (HEX)
VOLTAGE
(V)
3
9
1.5125
6
2
1.24375
0
F
1.0
3
8
1.50625
6
5
1.2375
0
E
0.99375
3
B
1.5
6
4
1.23125
1
1
0.9875
3
A
1.49375
6
7
1.225
1
0
0.98125
3
D
1.4875
6
6
1.21875
1
3
0.975
3
C
1.48125
6
9
1.2125
1
2
0.96875
3
F
1.475
6
8
1.20625
1
5
0.9625
3
E
1.46875
6
B
1.2
1
4
0.95625
4
1
1.4625
6
A
1.19375
1
7
0.95
4
0
1.45625
6
D
1.1875
1
6
0.94375
4
3
1.45
6
C
1.18125
1
9
0.9375
4
2
1.44375
6
F
1.175
1
8
0.93125
4
5
1.4375
6
E
1.16875
1
B
0.925
4
4
1.43125
7
1
1.1625
1
A
0.91875
4
7
1.425
7
0
1.15625
1
D
0.9125
4
6
1.41875
7
3
1.15
1
C
0.90625
4
9
1.4125
7
2
1.14375
1
F
0.9
4
8
1.40625
7
5
1.1375
1
E
0.89375
4
B
1.4
7
4
1.13125
2
1
0.8875
4
A
1.39375
7
7
1.125
2
0
0.88125
4
D
1.3875
7
6
1.11875
2
3
0.875
4
C
1.38125
7
9
1.1125
2
2
0.86875
4
F
1.375
7
8
1.10625
2
5
0.8625
4
E
1.36875
7
B
1.1
2
4
0.85625
5
1
1.3625
7
A
1.09375
2
7
0.85
5
0
1.35625
7
D
OFF
2
6
0.84375
5
3
1.35
7
C
OFF
2
9
0.8375
5
2
1.34375
7
F
OFF
2
8
0.83125
5
5
1.3375
7
E
OFF
NOTE:
8. VIDHI = (VID4, VID3, VID2), VIDLO = (VID1, VID0, VID5, VID6.25).
14
FN9192.0
February 27, 2006
ISL6595
TABLE 2. Intel® VR10 VID TABLE (8-BIT, Note 9)
TABLE 2. Intel® VR10 VID TABLE (8-BIT, Note 9) (Continued)
VIDHI
(HEX)
VIDLO
(HEX)
VOLTAGE
(V)
VIDHI
(HEX)
VIDLO
(HEX)
VOLTAGE
(V)
VIDHI
(HEX)
VIDLO
(HEX)
VOLTAGE
(V)
VIDHI
(HEX)
VIDLO
(HEX)
VOLTAGE
(V)
0
0
OFF
3
0
1.31250
2
7
1.36875
5
7
1.06875
0
1
OFF
3
1
1.30625
2
8
1.36250
5
8
1.06250
0
2
1.60000
3
2
1.30000
2
9
1.35625
5
9
1.05625
0
3
1.59375
3
3
1.29375
2
A
1.35000
5
A
1.05000
0
4
1.58750
3
4
1.28750
2
B
1.34375
5
B
1.04375
0
5
1.58125
3
5
1.28125
2
C
1.33750
5
C
1.03750
0
6
1.57500
3
6
1.27500
2
D
1.33125
5
D
1.03125
0
7
1.56875
3
7
1.26875
2
E
1.32500
5
E
1.02500
0
8
1.56250
3
8
1.26250
2
F
1.31875
5
F
1.01875
0
9
1.55625
3
9
1.25625
6
0
1.01250
9
0
0.71250
0
A
1.55000
3
A
1.25000
6
1
1.00625
9
1
0.70625
0
B
1.54375
3
B
1.24375
6
2
1.00000
9
2
0.70000
0
C
1.53750
3
C
1.23750
6
3
0.99375
9
3
0.69375
0
D
1.53125
3
D
1.23125
6
4
0.98750
9
4
0.68750
0
E
1.52500
3
E
1.22500
6
5
0.98125
9
5
0.68125
0
F
1.51875
3
F
1.21875
6
6
0.97500
9
6
0.67500
1
0
1.51250
4
0
1.21250
6
7
0.96875
9
7
0.66875
1
1
1.50625
4
1
1.20625
6
8
0.96250
9
8
0.66250
1
2
1.50000
4
2
1.20000
6
9
0.95625
9
9
0.65625
1
3
1.49375
4
3
1.19375
6
A
0.95000
9
A
0.65000
1
4
1.48750
4
4
1.18750
6
B
0.94375
9
B
0.64375
1
5
1.48125
4
5
1.18125
6
C
0.93750
9
C
0.63750
1
6
1.47500
4
6
1.17500
6
D
0.93125
9
D
0.63125
1
7
1.46875
4
7
1.16875
6
E
0.92500
9
E
0.62500
1
8
1.46250
4
8
1.16250
6
F
0.91875
9
F
0.61875
1
9
1.45625
4
9
1.15625
7
0
0.91250
A
0
0.61250
1
A
1.45000
4
A
1.15000
7
1
0.90625
A
1
0.60625
1
B
1.44375
4
B
1.14375
7
2
0.90000
A
2
0.60000
1
C
1.43750
4
C
1.13750
7
3
0.89375
A
3
0.59375
1
D
1.43125
4
D
1.13125
7
4
0.88750
A
4
0.58750
1
E
1.42500
4
E
1.12500
7
5
0.88125
A
5
0.58125
1
F
1.41875
4
F
1.11875
7
6
0.87500
A
6
0.57500
2
0
1.41250
5
0
1.11250
7
7
0.86875
A
7
0.56875
2
1
1.40625
5
1
1.10625
7
8
0.86250
A
8
0.56250
2
2
1.40000
5
2
1.10000
7
9
0.85625
A
9
0.55625
2
3
1.39375
5
3
1.09375
7
A
0.85000
A
A
0.55000
2
4
1.38750
5
4
1.08750
7
B
0.84375
A
B
0.54375
2
5
1.38125
5
5
1.08125
7
C
0.83750
A
C
0.53750
2
6
1.37500
5
6
1.07500
7
D
0.83125
A
D
0.53125
15
FN9192.0
February 27, 2006
ISL6595
TABLE 2. Intel® VR10 VID TABLE (8-BIT, Note 9) (Continued)
TABLE 2. Intel® VR10 VID TABLE (8-BIT, Note 9) (Continued)
VIDHI
(HEX)
VIDLO
(HEX)
VOLTAGE
(V)
VIDHI
(HEX)
VIDLO
(HEX)
VOLTAGE
(V)
VIDHI
(HEX)
VIDLO
(HEX)
VOLTAGE
(V)
VIDHI
(HEX)
VIDLO
(HEX)
VOLTAGE
(V)
7
E
0.82500
A
E
0.52500
D
5
0.28125
F
5
0.08125
7
F
0.81875
A
F
0.51875
D
6
0.27500
F
6
0.07500
8
0
0.81250
B
0
0.51250
D
7
0.26875
F
7
0.06875
8
1
0.80625
B
1
0.50625
D
8
0.26250
F
8
0.06250
8
2
0.80000
B
2
0.50000
D
9
0.25625
F
9
0.05625
8
3
0.79375
B
3
0.49375
D
A
0.25000
F
A
0.05000
8
4
0.78750
B
4
0.48750
D
B
0.24375
F
B
0.04375
8
5
0.78125
B
5
0.48125
D
C
0.23750
F
C
0.03750
8
6
0.77500
B
6
0.47500
D
D
0.23125
F
D
0.03125
8
7
0.76875
B
7
0.46875
D
E
0.22500
F
E
OFF
8
8
0.76250
B
8
0.46250
D
F
0.21875
F
F
OFF
8
9
0.75625
B
9
0.45625
8
A
0.75000
B
A
0.45000
8
B
0.74375
B
B
0.44375
8
C
0.73750
B
C
0.43750
Active Voltage Positioning (AVP)
8
D
0.73125
B
D
0.43125
8
E
0.72500
B
E
0.42500
8
F
0.71875
B
F
0.41875
The ISL6595 allows selection of both the AVP loadline slope
and the VID setpoint offset. The loadline slope is selectable
from 0 to 4mΩ, and the setpoint offset is selectable from 0 to
50mV in 1.56mV steps.
C
0
0.41250
E
0
0.21250
C
1
0.40625
E
1
0.20625
C
2
0.40000
E
2
0.20000
C
3
0.39375
E
3
0.19375
C
4
0.38750
E
4
0.18750
C
5
0.38125
E
5
0.18125
C
6
0.37500
E
6
0.17500
C
7
0.36875
E
7
0.16875
C
8
0.36250
E
8
0.16250
C
9
0.35625
E
9
0.15625
C
A
0.35000
E
A
0.15000
C
B
0.34375
E
B
0.14375
C
C
0.33750
E
C
0.13750
C
D
0.33125
E
D
0.13125
C
E
0.32500
E
E
0.12500
Active Transient Response (ATR)
C
F
0.31875
E
F
0.11875
D
0
0.31250
F
0
0.11250
D
1
0.30625
F
1
0.10625
D
2
0.30000
F
2
0.10000
D
3
0.29375
F
3
0.09375
D
4
0.28750
F
4
0.08750
Active Transient Response (ATR) is supported through loadline tracking comparators with programmable thresholds.
Both internal- and external-loop ATR are supported.
Internal-loop ATR engages multiple phases to maximize
output current slew rate and minimize spike and droop due
to large transient events. Three independent window
comparators allows for variation in the number of phases
that sink or source. If the transient is slight, only one phase
16
NOTE:
9. VID_SEL=1, VIDHI = (VID7, VID6, VID5, VID4), VIDLO = (VID3,
VID2, VID1, VID0)
The total current is computed by adding the current
measured from each phase, then filtering with a single pole
programmable filter to set the AVP bandwidth.
Current Balancing/Thermal Balancing
The ISL6595 also uses the channel current measurements
to perform current balancing. To minimize thermal gradient
effects, each channel adaptively adjusts its current to match
the average channel current.
The current balance function can also be used to induce a
thermal gradient if, for example, some channels have
greater cooling capability due to better proximity to airflow.
The ISL6595 allows the user to independently force an offset
current to each channel, creating a current gradient. This
causes the current balance to force the channels with
greater cooling capability to supply a higher percentage of
the total current, creating a net thermal equilibrium amongst
all channels.
FN9192.0
February 27, 2006
ISL6595
will respond. If the transient is severe, up to three phases
respond. This avoids a dramatic sinking or sourcing event,
which can cause oscillation. The ISL6595 controller itself
uses hysteretic control algorithms after the transient event to
ensure that the power stages return to normal operation
smoothly with minimal ringing. External-loop ATR
(overshoot only) provides an output to engage an additional
low latency low side stage capable of quickly discharging the
load. This consists of a small low-side FET with a very fast
gate driver. Internal- and external-loop ATR can be used
independently or in conjunction to optimize transient
performance.
Output Configurations
The ISL6595 provides 6 configurable outputs that are used
to drive up to 6 phase power stages. The PWM6 output may
also be configured to provide the external loop ATRL output
to drive a low side overshoot control FET.
For driving external MOSFETs, tri-valent FET drivers must
be used. The driver input circuit has two thresholds (upper
and lower) along with a bias network such that its input is
centered between the two thresholds when the ISL6595
output driver is three-stated. This allows three values to be
defined for the signal, depending whether the output is high,
low, or high impedance. If the input signal is high, the gate
driver turns the high-side switch on. If the input signal is low,
the gate driver turns the low-side switch on. If the input
signal is three-state, the driver does not turn either high-side
or low-side switches on and the power stage is high
impedance or three-stated. Intersil’s ISL6594A/B and
ISL6596 FET drivers are optimized to operate with the
ISL6595.
The output drive signals are generated using a 3.3V trivalent driver. All outputs are tri-stated during reset,
configuration, and inactive state. This allows the user to set
the appropriate level to tri-state the power stage, using
external pull-up or pull-down resistors.
Output Firing Sequence
The PWM output and current sense (ISEN) pins of the
ISL6595 have been assigned such that they can be placed
sequentially for PC board layouts (i.e. phase 2 next to 1,
phase 3 next to 2, etc...). The output phases are set in a
pre-wired firing order to facilitate layout of high phase count
systems. For high phase count systems, the VRD layout in
the motherboard will likely require the power components to
be laid out across two sides of the processor. The firing
sequence shown in the table below ensures that for a highly
distributed power array, the maximum spatial distribution can
be obtained between sequential phases.
17
TABLE 3. OUTPUT FIRING SEQUENCE AND NUMBER OF
PHASES
#P
FIRING SEQUENCE
2
1Æ2Æ1Æ2Æ1Æ2Æ1Æ2Æ1Æ2Æ1Æ2…
3
1Æ2Æ3Æ1Æ2Æ3Æ1Æ2Æ3Æ1Æ2Æ3…
4
1Æ4Æ2Æ3Æ1Æ4Æ2Æ3Æ1Æ4Æ2Æ3…
5
1Æ4Æ2Æ5Æ3Æ1Æ4Æ2Æ5Æ3Æ1Æ4…
6
1Æ4Æ2Æ5Æ3Æ6Æ1Æ4Æ2Æ5Æ3Æ6…
Fault Detection and Fault Handling
The ISL6595 provides a very flexible fault detection reporting
and handling mechanism. Fault detection capability
includes:
• Input Undervoltage Protection (IUVP)
• Output Overvoltage Protection (OOVP)
• Output Undervoltage Protection (OUVP)
• Per Phase Overcurrent Protection (OCP)
• Total Output Overcurrent
• Two levels of Internal Temperature Protection
• Four levels of External Temperature Protection
• Configuration Failure
• Calibration Time-out Failure
All individual faults are latched and reported over the serial
interface. Two configurable fault outputs are provided
(FAULT1, FAULT2). Each output allows independent
masking of all faults, allowing a subset of faults to be
reported over that pin. The outputs can also be configured
as either latched or unlatched, active high or active low
polarity, and CMOS or open drain outputs.
Typical usage of the configurable fault pins would be as a
crowbar signal to drive an external crowbar device,
temperature alert to notify the system a thermal shutdown is
imminent, or as an interrupt to cause a micro-controller to
poll the fault registers.
Shutdown operation also allows a subset of faults to be
individually masked. Additionally, the shutdown recovery
can be either autonomous or latched. For autonomous
recovery, the faults are not latched, so if the fault condition is
eliminated when the controller returns to an inactive state, it
will wait for a programmable time period, and then attempt a
new soft start. If the fault condition reoccurs, the controller
will recommence the shutdown sequence, continuing this
cycle indefinitely until the fault conditions is eliminated. The
programmable delay ensures a sufficiently low duty cycle to
prevent the regulator components from being damaged from
power cycling, assuming the fault condition itself is not
immediately destructive.
FN9192.0
February 27, 2006
ISL6595
For latched shutdown, user intervention to clear the latched
fault is required before a new soft-start can be attempted.
User intervention must come in the form of VR_EN toggle,
RESET_N toggle, or controller power cycle.
Calibration Failure: Calibration failure is detected as the
inability to achieve a regulation target in the given timeframe. These failures typically indicate a component is
damaged or missing.
In addition to fault reporting, there are additional fault
handling capabilities specific to each fault type that attempts
to provide more graceful fault handling than a shutdown, but
more active than simply reporting. The specific fault
detection capability and alternate fault handling capability is
as follows:
I2C Interface
IUVP: The V12_SEN input continuously senses the +12V
supply through a nominally TBD:1 resistive divider. A
comparator with a programmable threshold is used to
indicate an undervoltage condition. IUVP can be used to
independently provide either an undervoltage lockout prior to
soft-start, or to both provide a lockout and force a shutdown
during active regulation.
OOVP/OUVP: Programmable comparators continuously
monitor the VSEN inputs to detect an output overvoltage or
undervoltage condition. The OOVP voltage threshold is set
relative to VID while OUVP uses a fixed threshold. OOVP is
enabled during soft start and active regulation, while OUVP
is enabled only during active regulation.
OCP: The OCP (overcurrent protection) continuously
monitors all channel currents to determine whether any of
the currents are greater than a programmable threshold.
Two mechanisms work independently to control overcurrent
conditions. A cycle-by-cycle current limit operates by
disabling a channel for one cycle when its current exceeds
the threshold. A second mechanism monitors the average
current for an overcurrent condition. A programmable
threshold sets a current limit at which a steeper loadline is
implemented, quickly reducing the output voltage downward
as the current increases. Both of these mechanisms allow
hiccup mode overcurrent protection, where the controller
continues to try to provide a regulated output voltage while in
overcurrent. Alternatively, a threshold can be set where the
overcurrent condition will cause the controller to initiate
shutdown.
Over-Temperature Alert/Shutdown: Both the internal and
external temperature monitors are able to provide fault
telemetry in order to shut down the VR in an overtemperature condition. Two programmable thresholds are
available for temperature faults. Crossing of the first
threshold can be used to only generate a fault report.
Crossing the second threshold can be used to cause a
shutdown to occur.
CRC Failure: The integrity of loading the configuration from
the NVM to the controller’s registers is checked through a
cyclic redundancy code (CRC) check of the data contents. A
CRC failure prevents the controller from leaving the inactive
state.
18
All operating parameters in the ISL6595 are configurable via
the I2C interface. Status can also be read back via the same
interface. The ISL6595 operates as a slave at a standard
speed of 100kHz.
Three transactions are supported on the I2C interface: 1) Set
current address, 2) Write register, 3) Read register from
current address.
All transactions start with a control byte sent from the I2C
master device. The control byte begins with a Start condition,
followed by 7-bits of slave address. The last bit sent by the
master is the R/W bit and is 0 for a write. If any slaves on the
I2C bus recognize their address, they will Acknowledge by
pulling the serial data line low for the last clock cycle in the
control byte. If no slaves exist at that address or are not
ready to communicate, the data line will be 1, indicating a
Not Acknowledge condition. The ISL6595 address on the
I2C bus is 1110_000 or 1110_001, with the LSB set by the
input pin SADDR.
To write a register in the ISL6595, the master sends a control
byte with the R/W bit set to 0, indicating a write. If it receives
an Acknowledge from the ISL6595 it sends a byte
representing the address MSB. The ISL6595 will respond
with an Acknowledge. The master then sends a byte
representing the address LSB. The ISL6595 will respond
with an Acknowledge. The master then sends a byte
representing the data MS-byte to be written at the current
address. The ISL6595 will respond with an Acknowledge.
The master then sends a byte representing the data LS -byte
to be written at the current address. The ISL6595 will
respond with an Acknowledge. The master then issues a
Stop condition, indicating to the ISL6595 that the current
transaction is complete.
To set the current 16-bit address in the ISL6595, the master
sends a control byte with the R/W bit set to 0, indicating a
write. If it receives an Acknowledge from the ISL6595 it
sends a byte representing the address MS-byte. The
ISL6595 will respond with an Acknowledge. The master then
sends a byte representing the address LS-byte. The
ISL6595 will respond with an Acknowledge. The master then
issues a Stop condition, indicating to the ISL6595 that the
current transaction is complete. Any read commands issued
to the ISL6595 will return data from this address.
To read a register from the ISL6595, the master first sets the
address to read from. It then sends a control byte with the
R/W bit set to 1, indicating a read. If it receives an
Acknowledge from the ISL6595 it send 8 clocks but does not
drive the serial data line. The ISL6595 will respond with the
MS-byte at the current address. The master will respond with
FN9192.0
February 27, 2006
ISL6595
an Acknowledge to indicate to the ISL6595 that the
transaction is not yet complete. The master again sends 8
clocks but does not drive the serial data line. The ISL6595
will respond with the LS-byte at the current address. The
master will respond with a Not Acknowledge to indicate to
the ISL6595 that the transaction is complete. The ISL6595
will stop driving the serial data line. The master then issues a
Stop condition to indicate that the transaction is complete.
If the ISL6595 has started an internal operation in response
to a transaction on the I2C bus (register read/write, flash
write, flash page erase) but the operation has not completed
before the last Acknowledge slot in the I2C bus protocol, the
ISL6595 will add wait states by stretching the low portion of
the last clock cycle. This also occurs in response to
read/write requests to addresses that do not support
physical memory in the ISL6595. In this case, the ISL6595
will add wait states until an internal watchdog timer expires,
and the I2C bus is guaranteed to be released.
I2C Read and Write Protocol
Data write
S
sla ve _a d d r + W
A
re g_a d dr M S B
A
re g_a d dr LS B
A
re g_d a ta M S B
A
re g_a d dr M S B
A
re g_a d dr LS B
A
P
re g_a d dr M S B
A
re g_a d dr LS B
N
P
A
re g_d a ta LS B
A
P
S et c urrent addres s
S
sla ve _a d d r + W
Read from c urrent addres s
S
sla ve _a d dr + R
A
Driven by m as ter
Driven by s lave
Key Registers
Table 4 provides brief descriptions of several key configuration (R/W – read/write) and status (RO – read only) registers available
on the ISL6595 Digital Multiphase Controller.
TABLE 4. KEY REGISTERS
RANGE
REGISTER
DESCRIPTION
FORMAT
MIN
MAX
RESOLUTION
isum_avg[18:0]
VR load current. Averaged sum of all channel current data
over a user programmable averaging window
(default = 16ms).
RO
0.00A
524.288A
1mA
vavp_avg_mon[9:0]
AVP output voltage. Averaged VAVP monitored value ADC
voltage.
RO
0.0mV
3,196.875mV
3.125mV
kavp [9:0]
AVP loadline slope. Nominal value of load line slope
resistance.
R/W
0.0Ω
3.902mΩ
0.003815mΩ
load_line_offset [4:0]
AVP loadline VID offset. VID set-point load-line offset
tolerance voltage.
R/W
0.0V
48.4375mV
1.5625mV
isum_max [7:0]
Overcurrent limit. Max load current threshold for over
current shutdown.
R/W
0.0A
+204.0A
0.800A
ptat_mon[5:0]
PTAT Temperature. Averaged PTAT calibration
temperature output.
RO
0°C
157.5°C
2.5°C
ptat_alert_ref[5:0]
PTAT alert temperature. PTAT sensor alert temperature
reference.
R/W
0°C
157.5°C
2.5°C
ptat_shutdown_ref[5:0]
PTAT shutdown temperature. PTAT sensor shutdown
temperature reference.
R/W
0°C
157.5°C
2.5°C
temp_mon[5:0]
Thermistor temperature. Averaged Thermistor monitor
temperature output.
RO
0°C
157.5°C
2.5°C
therm_alert_ref[5:0]
Thermistor alert temperature. Thermistor sensor alert
temperature reference.
R/W
0°C
157.5°C
2.5°C
R/W
0°C
157.5°C
2.5°C
therm_shutdown_ref[5:0] Thermistor shutdown temperature. Thermistor sensor
shutdown temperature reference.
19
FN9192.0
February 27, 2006
ISL6595
TABLE 4. KEY REGISTERS (Continued)
RANGE
REGISTER
DESCRIPTION
FORMAT
MIN
MAX
RESOLUTION
oovp_limit [5:0]
Output overvoltage protect threshold. Tracking VID over
voltage threshold.
R/W
0.0mV
787.5mV
12.5mV
fault1_mask[12:0]
fault2_mask[12:0]
FAULT1, FAULT2 pin output masks. Inputs are enabled
for reporting when set to logic 1. If multiple inputs are
selected, output is “OR” of selected input signals.
15 = Current ADC over range
14 = Load current monitor
13 = Average total current fault
12 = NVM fault
11 = Internal bus fault
10 = IUVP
9 = OUVP
8 = OOVP
7 = VR_HOT alert
6 = VR_FAN alert
5 = External (thermistor) temp alert
4 = External (thermistor) temp shutdown
3 = Internal (PTAT) temp alert
2 = Internal (PTAT) temp shutdown
1 = MHz controller fault
0 = Calibration fault
shutdown_mask[10:0]
Shutdown control mask. Inputs are enabled for shutdown
when set to logic 1. If multiple inputs are selected, output is
“OR” of selected input signals.
11= Averal total current fault
10 = Total current fault during active regulation
9 = Total current fault during soft-start
8 = Individual phase current fault during active regulation
7 = Individual phase current fault during soft-start
6 = Current ADC over range fault
5 = IUVP
4 = OUVP
3 = OOVP
2 = Thermistor temp shutdown
1 = PTAT temp shutdown 0 = Calibration fault
0 = Calibration fault
R/W
ch_mask[6:1]
Channel mask. Selects number of active phases. Phases
must be selected in sequential order.
R/W
000011 = 2-phase operation
000111 = 3-phase operation
001111 = 4-phase operation
011111 = 5-phase operation
111111 = 6-phase operation
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
20
FN9192.0
February 27, 2006
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L48.7x7P
21
ISL6595
FN9192.0
February 27, 2006