INTERSIL EL5397A

ES
EW D
®
NOT
R
EL5397A
I GNS
N
FOR6
D
E
30
ND
MMESEE EL5
Data Sheet
EC O
Triple 200MHz Fixed Gain Amplifier with
Enable
The EL5397A is a triple channel, fixed gain amplifier with a
bandwidth of 200MHz, making these amplifiers ideal for
today’s high speed video and monitor applications. The
EL5397A features internal gain setting resistors and can be
configured in a gain of +1, -1 or +2. The same bandwidth is
seen in both gain-of-1 and gain-of-2 applications.
With a supply current of just 4mA per amplifier and the ability
to run from a single supply voltage from 5V to 10V, these
amplifiers are also ideal for hand held, portable or battery
powered equipment.
The EL5397A also incorporates an enable and disable
function to reduce the supply current to 100µA typical per
amplifier. Allowing the CE pin to float or applying a low logic
level will enable the amplifier.
For applications where board space is critical, the EL5397A
is offered in the 16 Ld QSOP package, as well as a 16 Ld
SO (0.150"). The EL5397A is specified for operation over the
full industrial temperature range of -40°C to +85°C.
Pinout
November 8, 2006
FN7197.1
Features
• Gain selectable (+1, -1, +2)
• 200MHz -3dB bandwidth (AV = 1, 2)
• 4mA supply current (per amplifier)
• Single and dual supply operation, from 5V to 10V or ±2.5V
to ±5V
• Fast enable/disable
• Available in 16 Ld QSOP package
• Single (EL5197) available
• 400MHz, 9mA products available (EL5196 and EL5396)
Applications
• Battery-powered equipment
• Hand-held, portable devices
• Video amplifiers
• Cable drivers
• RGB amplifiers
• Test equipment
EL5397A
[16 LD SO (0.150"), 16 LD QSOP]
TOP VIEW
INA+
1
CEA
2
16 INA-
• Instrumentation
• Current to voltage converters
Ordering Information
PART
MARKING
TAPE
&
REEL
EL5397ACS
EL5397ACS
-
16 Ld SO
(0.150")
MDP0027
EL5397ACS-T7
EL5397ACS
7”
16 Ld SO
(0.150")
MDP0027
13”
16 Ld SO
(0.150")
MDP0027
15 OUTA
+
14 VS+
PART NUMBER
PACKAGE
PKG.
DWG. #
VS-
3
CEB
4
INB+
5
12 INB-
NC
6
11 NC
EL5397ACS-T13 EL5397ACS
CEC
7
10 OUTC
EL5397ACU
5397ACU
-
16 Ld QSOP MDP0040
INC+
8
9
EL5397ACU-T7
5397ACU
7”
16 Ld QSOP MDP0040
EL5397ACU-T13 5397ACU
13”
16 Ld QSOP MDP0040
+
13 OUTB
-
+
-
1
INC-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2006. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
EL5397A
Absolute Maximum Ratings (TA = +25°C)
Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V to VS+ +0.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . . . 11V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 50mA
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, RL = 150Ω, TA = +25°C unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Bandwidth
AV = +1
200
MHz
AV = +2
200
MHz
AV = -1
200
MHz
20
MHz
2100
V/µs
BW1
0.1dB Bandwidth
SR
Slew Rate
VO = -2.5V to +2.5V, AV = +2
tS
0.1% Settling Time
VOUT = -2.5V to +2.5V, AV = -1
12
ns
CS
Channel Separation
f = 5MHz
67
dB
eN
Input Voltage Noise
4.8
nV/√Hz
iN-
IN- Input Current Noise
17
pA/√Hz
iN+
IN+ Input Current Noise
50
pA/√Hz
dG
Differential Gain Error (Note 1)
AV = +2
0.03
%
dP
Differential Phase Error (Note 1)
AV = +2
0.04
°
1800
DC PERFORMANCE
VOS
Offset Voltage
TCVOS
Input Offset Voltage Temperature
Coefficient
Measured from TMIN to TMAX
AE
Gain Error
VO = -3V to +3V
RF, RG
Internal RF and RG
-10
1
10
5
-2
320
400
mV
µV/°C
2
%
480
Ω
INPUT CHARACTERISTICS
CMIR
Common Mode Input Range
±3V
±3.3V
V
+IIN
+ Input Current
-80
1
80
µA
-IIN
- Input Current
-50
1
50
µA
RIN
Input Resistance
45
kΩ
CIN
Input Capacitance
0.5
pF
OUTPUT CHARACTERISTICS
VO
RL = 150Ω to GND
±3.4V
±3.7V
V
RL = 1kΩ to GND
±3.8V
±4.0V
V
Output Current
RL = 10Ω to GND
95
120
mA
ISON
Supply Current - Enabled
No load, VIN = 0V
3
4
5
mA
ISOFF
Supply Current - Disabled
No load, VIN = 0V
100
150
µA
IOUT
Output Voltage Swing
SUPPLY
2
FN7197.1
November 8, 2006
EL5397A
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, RL = 150Ω, TA = +25°C unless otherwise specified. (Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
75
PSRR
Power Supply Rejection Ratio
DC, VS = ±4.75V to ±5.25V
55
-IPSR
- Input Current Power Supply
Rejection
DC, VS = ±4.75V to ±5.25V
-2
MAX
UNIT
dB
2
µA/V
ENABLE
tEN
Enable Time (Note 2)
40
ns
tDIS
Disable Time (Note 2)
600
ns
IIHCE
CE Pin Input High Current
CE = VS+
0.8
6
µA
IILCE
CE Pin Input Low Current
CE = VS-
0
-0.1
µA
VIHCE
CE Input High Voltage for Powerdown
VILCE
CE Input Low Voltage for Power-up
VS+ -1
V
VS+ - 3
V
NOTES:
1. Standard NTSC test, AC signal amplitude = 286mVP-P, f = 3.58MHz
2. Measured from the application of CE logic until the output voltage is at the 50% point between initial and final values
3
FN7197.1
November 8, 2006
EL5397A
Typical Performance Curves
Frequency Response (Phase), All Gains
Frequency Response (Gain)
90
6
AV=2
0
2
-2
AV=1
Phase (°)
Normalized Magnitude (dB)
AV=-1
-6
-90
-180
-270
-10
-14
1M
RL=150Ω
10M
100M
-360
1M
1G
RL=150Ω
10M
Frequency (Hz)
Frequency Response for Various CL
1G
Group Delay vs Frequency
14
3.5
AV=2
RL=150Ω
AV=2
3
10
2.5
22pF added
6
Delay (ns)
Normalized Magnitude (dB)
100M
Frequency (Hz)
10pF added
2
2
1.5
AV=1
1
0pF added
-2
0.5
-6
1M
10M
100M
0
1M
1G
RL=150Ω
10M
Frequency (Hz)
1G
Frequency (Hz)
Frequency Response for Various Common-Mode Input
Voltages
Transimpedance (ROL) vs Frequency
6
10M
3V
0
Phase
-3V
2
1M
0V
-2
-6
-10
100k
-180
10k
ROL
-270
1k
AV=2
RL=150Ω
-14
1M
Phase (°)
-90
Magnitude (Ω)
Normalized Magnitude (dB)
100M
-360
10M
100M
Frequency (Hz)
4
1G
100
1k
10k
100k
1M
10M
100M
1G
Frequency (Hz)
FN7197.1
November 8, 2006
EL5397A
Typical Performance Curves
(Continued)
PSRR and CMRR vs Frequency
-3dB Bandwidth vs Supply Voltage
20
250
RL=150Ω
PSRR/CMRR (dB)
-20
-3dB Bandwidth (MHz)
PSRR+
0
PSRR-
-40
CMRR
200
AV=2
150
AV=-1
AV=1
-60
-80
10k
100
100k
1M
10M
100M
1G
5
6
7
Frequency (Hz)
9
10
Total Supply Voltage (V)
Peaking vs Supply Voltage
-3dB Bandwidth vs Temperature
5
300
250
4
-3dB Bandwidth (MHz)
AV=-1
AV=1
Peaking (dB)
8
3
AV=2
2
1
200
150
100
50
RL=150Ω
0
5
6
7
8
9
0
-40
10
RL=150Ω
10
Total Supply Voltage (V)
110
60
160
Ambient Temperature (°C)
Peaking vs Temperature
Voltage and Current Noise vs Frequency
1
1k
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)
Peaking (dB)
0.8
0.6
0.4
i n+
100
in10
en
0.2
0
-40
RL=150Ω
10
60
Ambient Temperature (°C)
5
110
160
1
100
1k
10k
100k
1M
10M
Frequency (Hz)
FN7197.1
November 8, 2006
EL5397A
Typical Performance Curves
(Continued)
Supply Current vs Supply Voltage
100
10
10
8
Supply Current (mA)
Output Impedance (Ω)
Closed Loop Output Impedance vs Frequency
1
0.1
6
4
2
0.01
0.001
0
100
10k
1k
1M
100k
10M
100M
1G
0
2
4
Frequency (Hz)
2nd and 3rd Harmonic Distortion vs Frequency
10
12
25
AV=+2
VOUT=2VP-P
RL=100Ω
-40
2nd Order
Distortion
-50
AV=+2
RL=150Ω
20
Input Power Intercept (dBm)
-30
Harmonic Distortion (dBc)
8
Two-Tone 3rd Order Input Referred Intermodulation Intercept
(IIP3)
-20
-60
3rd Order
Distortion
-70
-80
15
10
5
0
-5
-90
1
10
AV=+2
RL=100Ω
-10
10
100
100
Frequency (MHz)
Frequency (MHz)
Differential Gain/Phase vs DC Input Voltage at 3.58MHz
Differential Gain/Phase vs DC Input Voltage at 3.58MHz
0.03
0.04
AV=2
0.02
dP
AV=1
0.03
dP
0.02
0
dG (%) or dP (°)
0.01
dG (%) or dP (°)
6
Supply Voltage (V)
dG
-0.01
-0.02
0.01
-0.01
-0.03
-0.02
-0.04
-0.03
-0.05
dG
0
-0.04
-1
-0.5
0
DC Input Voltage
6
0.5
1
-1
-0.5
0
0.5
1
DC Input Voltage
FN7197.1
November 8, 2006
EL5397A
Typical Performance Curves
(Continued)
Output Voltage Swing vs Frequency
THD<0.1%
Output Voltage Swing vs Frequency
THD<1%
10
10
RL=500Ω
8
Output Voltage Swing (VPP)
Output Voltage Swing (VPP)
8
RL=150Ω
6
4
2
RL=500Ω
6
RL=150Ω
4
2
AV=2
0
AV=2
0
1
10
100
1
10
Frequency (MHz)
100
Frequency (MHz)
Small Signal Step Response
Large Signal Step Response
VS=±5V
RL=150Ω
AV=2
VS=±5V
RL=150Ω
AV=2
200mV/div
1V/div
10ns/div
10ns/div
Settling Time vs Settling Accuracy
Transimpedance (RoI) vs Temperature
25
625
AV=2
RL=150Ω
VSTEP=5VP-P output
600
15
RoI (kΩ)
Settling Time (ns)
20
10
575
550
5
0
0.01
0.1
Settling Accuracy (%)
7
1
525
-40
10
60
110
160
Die Temperature (°C)
FN7197.1
November 8, 2006
EL5397A
Typical Performance Curves
(Continued)
Frequency Response (Phase)
8 Ld SO (0.150") Package
Frequency Response (Gain)
8 Ld SO (0.150") Package
6
90
AV=2
0
AV=1
-2
Phase (°)
Normalized Magnitude (dB)
AV=-1
2
-6
-10
-90
-180
-270
-14
1M
RL=150Ω
10M
100M
-360
1M
1G
RL=150Ω
10M
Frequency (Hz)
PSRR and CMRR vs Temperature
1G
ICMR and IPSR vs Temperature
90
2
80
PSRR
1.5
ICMR/IPSR (µA/V)
70
PSRR/CMRR (dB)
100M
Frequency (Hz)
60
50
CMRR
40
30
ICMR+
1
IPSR
0.5
ICMR-
0
20
10
-40
10
60
110
-0.5
-40
160
10
Die Temperature (°C)
60
110
160
Die Temperature (°C)
Offset Voltage vs Temperature
Input Current vs Temperature
60
2
40
Input Current (µA)
VOS (mV)
1
0
20
IB0
IB+
-20
-1
-40
-2
-40
10
60
Die Temperature (°C)
8
110
160
-60
-40
10
60
110
160
Die Temperature (°C)
FN7197.1
November 8, 2006
EL5397A
Typical Performance Curves
(Continued)
Positive Input Resistance vs Temperature
Supply Current vs Temperature
60
5
50
Supply Current (mA)
4
RIN+ (kΩ)
40
30
20
3
2
1
10
0
-40
10
60
110
0
-40
160
60
10
Die Temperature (°C)
110
160
Die Temperature (°C)
Positive Output Swing vs Temperature for Various Loads
Negative Output Swing vs Temperature for Various Loads
4.2
-3.5
4.1
150Ω
-3.6
4
-3.7
3.9
-3.8
VOUT (V)
VOUT (V)
1kΩ
3.8
3.7
150Ω
-3.9
-4
1kΩ
3.6
-4.1
3.5
-40
60
10
110
-4.2
-40
160
60
10
Die Temperature (°C)
110
160
Die Temperature (°C)
Output Current vs Temperature
Slew Rate vs Temperature
130
4000
Sink
Slew Rate (V/µS)
IOUT (mA)
125
Source
120
3500
3000
AV=2
RL=150Ω
115
-40
10
60
110
Die Temperature (°C)
Typical Performance Curves
9
160
2500
-40
10
60
110
160
Die Temperature (°C)
(Continued)
FN7197.1
November 8, 2006
EL5397A
Enable Response
Disable Response
500mV/div
500mV/div
5V/div
5V/div
20ns/div
400ns/div
Package Power Dissipation vs Ambient Temperature
JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board
Package Power Dissipation vs Ambient Temperature
JEDEC JESD51-7 High Effective Thermal Conductivity Test Board
1
1.4
Power Dissipation (W)
Power Dissipation (W)
)
/W
°C
”
50
.1
633mW
Q
SO
P1
15
6
8°
C/
W
0.5
0.4
0.3
1.250W
”)
50
.1
(0
/W
°C
80
(0
0
11
0.7
0.6
1.2
16
909mW
0.8
16
SO
SO
0.9
1
0.8
893mW
Q
11
2
0.6
SO
P1
6
°C
/W
0.4
0.2
0.2
0.1
0
-50 -40
-25
0
25
50
75 85
Ambient Temperature (°C)
10
100
125
0
-50 -40
-25
0
25
50
75 85
100
125
Ambient Temperature (°C)
FN7197.1
November 8, 2006
EL5397A
Pin Descriptions
16 LD SO
(0.150")
16 LD QSOP
PIN NAME
1
1
INA+
FUNCTION
EQUIVALENT CIRCUIT
Non-inverting input, channel A
RG
IN+
IN-
RF
Circuit 1
2
2
CEA
Chip enable, channel A
CE
Circuit 2
3
3
VS-
Negative supply
4
4
CEB
Chip enable, channel B
(See circuit 2)
5
5
INB+
Non-inverting input, channel B
(See circuit 1)
6, 11
6, 11
NC
7
7
CEC
Chip enable, channel C
(See circuit 2)
8
8
INC+
Non-inverting input, channel C
(See circuit 1)
9
9
INC-
Inverting input, channel C
(See circuit 1)
10
10
OUTC
Not connected
Output, channel C
OUT
RF
Circuit 3
12
12
INB-
13
13
OUTB
14
14
VS+
15
15
OUTA
16
16
INA-
11
Inverting input, channel B
(See circuit 1)
Output, channel B
(See circuit 3)
Positive supply
Output, channel A
(See circuit 3)
Inverting input, channel A
(See circuit 1)
FN7197.1
November 8, 2006
EL5397A
Applications Information
Product Description
The EL5397A is a triple channel fixed gain amplifier that
offers a wide -3dB bandwidth of 200MHz and a low supply
current of 4mA. The EL5397A works with supply voltages
ranging from a single 5V to 10V and they are also capable of
swinging to within 1V of either supply on the output. This
combination of high bandwidth and low power, together with
aggressive pricing make the EL5397A the ideal choice for
many low-power/high-bandwidth applications such as
portable, handheld, or battery-powered equipment.
For varying bandwidth and higher gains, consider the
EL5191 with 1GHz on a 9mA supply current or the EL5193
with 300MHz on a 4mA supply current. Versions include
single, dual, and triple amp packages with 5 Ld SOT-23,
16 Ld QSOP, and 8 Ld or 16 Ld SO outlines.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance. Low
impedance ground plane construction is essential. Surface
mount components are recommended, but if leaded
components are used, lead lengths should be as short as
possible. The power supply pins must be well bypassed to
reduce the risk of oscillation. The combination of a 4.7µF
tantalum capacitor in parallel with a 0.01µF capacitor has
been shown to work well when placed at each supply pin.
Disable/Power-Down
The EL5397A amplifier can be disabled placing its output in
a high impedance state. When disabled, the amplifier supply
current is reduced to < 150µA. The EL5397A is disabled
when its CE pin is pulled up to within 1V of the positive
supply. Similarly, the amplifier is enabled by floating or
pulling its CE pin to at least 3V below the positive supply. For
±5V supply, this means that an EL5397A amplifier will be
enabled when CE is 2V or less, and disabled when CE is
above 4V. Although the logic levels are not standard TTL,
this choice of logic voltages allows the EL5397A to be
enabled by tying CE to ground, even in 5V single supply
applications. The CE pin can be driven from CMOS outputs.
Gain Setting
temperature and process, external resistor should not be
used to adjust the gain settings.
400
400
IN-
IN+
+
FIGURE 1. AV = +2
400
400
IN-
IN+
+
FIGURE 2. AV = -1
400
IN-
IN+
400
+
FIGURE 3. AV = +1
Supply Voltage Range and Single-Supply
Operation
The EL5397A has been designed to operate with supply
voltages having a span of greater than or equal to 5V and
less than 11V. In practical terms, this means that the
EL5397A will operate on dual supplies ranging from ±2.5V to
±5V. With single-supply, the EL5397A will operate from 5V to
10V.
As supply voltages continue to decrease, it becomes
necessary to provide input and output voltage ranges that
can get as close as possible to the supply voltages. The
EL5397A has an input range which extends to within 2V of
either supply. So, for example, on ±5V supplies, the
EL5397A has an input range which spans ±3V. The output
range of the EL5397A is also quite large, extending to within
1V of the supply rail. On a ±5V supply, the output is therefore
capable of swinging from -4V to +4V. Single-supply output
range is larger because of the increased negative swing due
to the external pull-down resistor to ground. Figure 4 shows
The EL5397A is built with internal feedback and gain
resistors. The internal feedback resistors have equal value;
as a result, the amplifier can be configured into gain of +1,
-1, and +2 without any external resistors. Figure 1 shows the
amplifier in gain of +2 configuration. The gain error is ±2%
maximum. Figure 2 shows the amplifier in gain of -1
configuration. For gain of +1, IN+ and IN- should be
connected together as shown in Figure 3. This configuration
avoids the effects of any parasitic capacitance on the IN- pin.
Since the internal feedback and gain resistors change with
12
FN7197.1
November 8, 2006
EL5397A
an AC-coupled, gain of +2, +5V single supply circuit
configuration.
400
+5
Current Limiting
The EL5397A has no internal current-limiting circuitry. If the
output is shorted, it is possible to exceed the Absolute
Maximum Rating for output current or power dissipation,
potentially resulting in the destruction of the device.
Power Dissipation
400
+
+5
0.1µF
VOUT
1k
0.1µF
VIN
1k
FIGURE 4.
With the high output drive capability of the EL5397A, it is
possible to exceed the +125°C Absolute Maximum junction
temperature under certain very high load current conditions.
Generally speaking when RL falls below about 25Ω, it is
important to calculate the maximum junction temperature
(TJMAX) for the application to determine if power supply
voltages, load conditions, or package type need to be
modified for the EL5397A to remain in the safe operating
area. These parameters are calculated as follows:
T JMAX = T MAX + ( θ JA × n × PD MAX )
Video Performance
For good video performance, an amplifier is required to
maintain the same output impedance and the same
frequency response as DC levels are changed at the output.
This is especially difficult when driving a standard video load
of 150Ω, because of the change in output current with DC
level. Previously, good differential gain could only be
achieved by running high idle currents through the output
transistors (to reduce variations in output impedance.)
These currents were typically comparable to the entire 4mA
supply current of each EL5397A amplifier. Special circuitry
has been incorporated in the EL5397A to reduce the
variation of output impedance with current output. This
results in dG and dP specifications of 0.03% and 0.04°, while
driving 150Ω at a gain of 2.
Video performance has also been measured with a 500Ω
load at a gain of +1. Under these conditions, the EL5397A
has dG and dP specifications of 0.03% and 0.04°,
respectively.
where:
TMAX = Maximum ambient temperature
θJA = Thermal resistance of the package
n = Number of amplifiers in the package
PDMAX = Maximum power dissipation of each amplifier in
the package
PDMAX for each amplifier can be calculated as follows:
V OUTMAX
PD MAX = ( 2 × V S × I SMAX ) + ( V S - V OUTMAX ) × ---------------------------R
L
where:
VS = Supply voltage
ISMAX = Maximum supply current
Output Drive Capability
VOUTMAX = Maximum output voltage (required)
In spite of its low 4mA of supply current, the EL5397A is
capable of providing a minimum of ±95mA of output current.
With a minimum of ±95mA of output drive.
RL = Load resistance
Driving Cables and Capacitive Loads
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, the back-termination series resistor will
decouple the EL5397A from the cable and allow extensive
capacitive drive. However, other applications may have high
capacitive loads without a back-termination resistor. In these
applications, a small series resistor (usually between 5Ω and
50Ω) can be placed in series with the output to eliminate
most peaking.
13
FN7197.1
November 8, 2006
EL5397A
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
SO-8
SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
N
8
14
16
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
14
FN7197.1
November 8, 2006
EL5397A
Quarter Size Outline Plastic Packages Family (QSOP)
MDP0040
A
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
D
(N/2)+1
N
E
SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
PIN #1
I.D. MARK
E1
1
(N/2)
A
0.068
0.068
0.068
Max.
-
A1
0.006
0.006
0.006
±0.002
-
A2
0.056
0.056
0.056
±0.004
-
b
0.010
0.010
0.010
±0.002
-
c
0.008
0.008
0.008
±0.001
-
D
0.193
0.341
0.390
±0.004
1, 3
E
0.236
0.236
0.236
±0.008
-
E1
0.154
0.154
0.154
±0.004
2, 3
e
0.025
0.025
0.025
Basic
-
L
0.025
0.025
0.025
±0.009
-
L1
0.041
0.041
0.041
Basic
-
N
16
24
28
Reference
-
B
0.010
C A B
e
H
C
SEATING
PLANE
0.007
0.004 C
b
C A B
Rev. E 3/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
L1
A
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
c
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SEE DETAIL "X"
0.010
A2
GAUGE
PLANE
L
A1
4°±4°
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
15
FN7197.1
November 8, 2006