EL5106, EL5306 ® Data Sheet September 21, 2010 FN7357.6 350MHz Fixed Gain Amplifiers with Enable Features The EL5106 and EL5306 are fixed gain amplifiers with a bandwidth of 350MHz. This makes these amplifiers ideal for today’s high speed video and monitor applications. They feature internal gain setting resistors and can be configured in a gain of +1, -1 or +2. • Pb-free available (RoHS compliant) With a supply current of just 1.5mA and the ability to run from a single supply voltage from 5V to 12V, these amplifiers are also ideal for handheld, portable or battery powered equipment. • Fast enable/disable The EL5106 and EL5306 also incorporate an enable and disable function to reduce the supply current to 25µA typical per amplifier. Allowing the CE pin to float or applying a low logic level will enable the amplifier. • 450MHz, 3.5mA product available (EL5108 and EL5308) The EL5106 is offered in the 6 Ld SOT-23 and the industry-standard 8 Ld SOIC packages and the EL5306 is available in the 16 Ld SOIC and 16 Ld QSOP packages. All operate over the industrial temperature range of -40°C to +85°C. • Handheld, portable devices • Gain selectable (+1, -1, +2) • 350MHz -3dB BW (AV = 2) • 1.5mA supply current per amplifier • Single and dual supply operation, from 5V to 12V • Available in SOT-23 packages Applications • Battery powered equipment • Video amplifiers • Cable drivers • RGB amplifiers Ordering Information PART NUMBER PART MARKING PACKAGE PKG. DWG. # EL5106IWZ-T7* (Note 1) BAFA (Note 2) 6 Ld SOT-23 (Pb-free) P6.064A EL5106IWZ-T7A* (Note 1) BAFA (Note 2) 6 Ld SOT-23 (Pb-free) P6.064A EL5106IS 5106IS 8 Ld SOIC (150 mil) M8.15E EL5106ISZ (Note 1) 5106ISZ 8 Ld SOIC (150 mil) (Pb-free) M8.15E EL5106ISZ-T7* (Note 1) 5106ISZ 8 Ld SOIC (150 mil) (Pb-free) M8.15E EL5106ISZ-T13* (Note 1) 5106ISZ 8 Ld SOIC (150 mil) (Pb-free) M8.15E EL5306ISZ (Note 1) EL5306ISZ 16 Ld SOIC (150 mil) (Pb-free) M8.15E EL5306ISZ-T7* (Note 1) EL5306ISZ 16 Ld SOIC (150 mil) (Pb-free) M8.15E EL5306ISZ-T13* (Note 1) EL5306ISZ 16 Ld SOIC (150 mil) (Pb-free) M8.15E EL5306IUZ (Note 1) 5306IUZ 16 Ld QSOP (150 mil) (Pb-free) MDP0040 EL5306IUZ-T7* (Note 1) 5306IUZ 16 Ld QSOP (150 mil) (Pb-free) MDP0040 EL5306IUZ-T13* (Note 1) 5306IUZ 16 Ld QSOP (150 mil) (Pb-free) MDP0040 *Please refer to TB347 for details on reel specifications. NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. The part marking is located on the bottom of the part. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002-2005, 2007, 2010. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. EL5106, EL5306 Pinouts EL5306 (16 LD SOIC, QSOP) TOP VIEW EL5106 (8 LD SOIC) TOP VIEW NC 1 IN- 2 + IN+ 3 VS- 4 8 CE INA+ 1 7 VS+ CEA 2 6 OUT VS- 3 5 NC CEB 4 16 INA+ 14 VS+ + - INB+ 5 EL5106 (6 LD SOT-23) TOP VIEW OUT 1 VS- 2 6 VS+ INC+ 8 13 OUTB 12 INB- NC 6 CEC 7 15 OUTA 11 NC + - 10 OUTC 9 INC- 5 CE + - IN+ 3 4 IN- 2 FN7357.6 September 21, 2010 EL5106, EL5306 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . 13.2V Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V to VS+ +0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 50mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RL = 150Ω, TA = +25°C Unless Otherwise Specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE BW -3dB Bandwidth AV = +1 250 MHz AV = -1 380 MHz AV = +2 350 MHz 20 MHz 4500 V/µs 16 ns 2.8 nV/√Hz 6 pA/√Hz BW1 0.1dB Bandwidth SR Slew Rate VO = -2.5V to +2.5V, AV = +2 tS 0.1% Settling Time VOUT = -2.5V to +2.5V, AV = 2 eN Input Voltage Noise iN+ IN+ Input Current Noise dG Differential Gain Error (Note 3) AV = +2 0.02 % dP Differential Phase Error (Note 3) AV = +2 0.04 ° 3000 DC PERFORMANCE VOS Offset Voltage TCVOS Input Offset Voltage Temperature Coefficient Measured from TMIN to TMAX 5 AE Gain Error VO = -3V to +3V, RL = 150Ω 1 RF, RG Internal RF and RG -10 1 10 mV µV/°C 2.5 % 325 Ω ±3.3 V INPUT CHARACTERISTICS CMIR Common Mode Input Range +IIN + Input Current RIN Input Resistance CIN Input Capacitance ±3 1.5 at IN+ 7 µA 2 MΩ 1 pF OUTPUT CHARACTERISTICS VO RL = 150Ω to GND ±3.4 ±3.6 V RL = 1kΩ to GND ±3.7 ±3.85 V Output Current RL = 10Ω to GND 60 100 mA ISON Supply Current - Enabled (per amplifier) No load, VIN = 0V 1.35 1.5 1.82 mA ISOFF Supply Current - Disabled (per amplifier) No load, VIN = 0V 12 25 µA PSRR Power Supply Rejection Ratio 75 IOUT Output Voltage Swing SUPPLY 3 DC, VS = ±4.75V to ±5.25V dB FN7357.6 September 21, 2010 EL5106, EL5306 Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RL = 150Ω, TA = +25°C Unless Otherwise Specified. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT ENABLE tEN Enable Time 280 ns tDIS Disable Time 400 ns IIHCE CE Pin Input High Current CE = VS+ 1 5 25 µA IILCE CE Pin Input Low Current CE = VS- +1 0 -1 µA VIHCE CE Input High Voltage for Power-down VILCE CE Input Low Voltage for Enable VS+ -1 V VS+ -3 V NOTE: 3. Standard NTSC test, AC signal amplitude = 286mVP-P, f = 3.58MHz Pin Descriptions EL5106 (SO8) EL5106 (SOT23-6) 1, 5 2 4 EL5306 (SO16, QSOP16) PIN NAME 6, 11 NC Not connected 9, 12, 16 ININC-, INB-, INA- Inverting input FUNCTION EQUIVALENT CIRCUIT RG IN+ IN- RF CIRCUIT 1 Non-inverting input IN+ INA+, INB+, INC+ 3 3 1, 5, 8 4 2 3 VS- 6 1 10, 13, 15 OUT OUTC, OUTB, OUTA (Reference Circuit 1) Negative supply Output OUT RF CIRCUIT 2 7 6 14 VS+ Positive supply 8 5 2, 4, 7 CE, CEA, CEB, CEC Chip enable VS+ CE VSCIRCUIT 3 4 FN7357.6 September 21, 2010 EL5106, EL5306 Typical Performance Curves 11 VS = ±5V RL = 150Ω 3 9 1 GAIN (dB) NORMALIZED GAIN (dB) 5 AV = -1 -1 AV = 2 AV = 1 -3 -5 100k 1M 10M 100M AV = +2 VS = ±5V RL = 150Ω CL = 10pF CL = 6.8pF 7 CL = 2.2pF 5 CL = 0pF 3 1 100k 1G 1M FREQUENCY (Hz) AV = -1 RL = 150Ω AV = -1 1.2 350 AV = 1, 2 BW (MHz) DELAY TIME (ns) 450 RL = 150Ω 0.8 AV = 2 250 AV = 1 0.4 0 1 10 100 150 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 1k FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 3. GROUP DELAY vs FREQUENCY FIGURE 4. BANDWIDTH vs SUPPLY VOLTAGE 0 RL = 150Ω -10 0.8 AV = -1 0.6 AV = 2 0.4 AV = 1 0.2 -20 PSRR (dB) 1 PEAKING (dB) 1G 100M FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS CL FIGURE 1. FREQUENCY RESPONSE 1.6 10M FREQUENCY (Hz) -30 PSRR+ PSRR- -40 -50 -60 -70 0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 VS (V) FIGURE 5. PEAKING vs SUPPLY VOLTAGE 5 -80 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 6. POWER SUPPLY REJECTION RATIO vs FREQUENCY FN7357.6 September 21, 2010 EL5106, EL5306 Typical Performance Curves (Continued) 1.60 100 1.55 IS (mA) IMPEDANCE (Ω) 1.50 10 1 IS- 1.45 IS+ 1.40 1.35 1.30 1.25 0.1 10k 100k 1M 1.20 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 100M 10M VS (V) FREQUENCY (Hz) FIGURE 7. OUTPUT IMPEDANCE vs FREQUENCY 0 -10 VS = ±5V AV = 2 RL = 150Ω VOP-P = 2V M=100ns -30 -40 HD3 -50 CH1 2.00V/DIV -60 HD2 -70 CH2 1.00V/DIV -80 -90 0M 10M 20M 30M 40M 50M 60M FREQUENCY (Hz) FIGURE 9. HARMONIC DISTORTION vs FREQUENCY FIGURE 10. ENABLED RESPONSE 1.0 M=100ns CH1 2.00V/DIV CH2 1.00V/DIV JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 909mW 0.9 POWER DISSIPATION (W) DISTORTION (dB) -20 FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE (PER AMPLIFIER) SO16 (0.150”) θJA = +110°C/W 0.8 0.7 625mW 0.6 633mW SO8 θJA = +160°C/W 0.5 0.4 391mW 0.3 0.1 0 QSOP16 θJA = +158°C/W SOT23-6 θJA = +256°C/W 0.2 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 11. DISABLED RESPONSE 6 FIGURE 12. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN7357.6 September 21, 2010 EL5106, EL5306 Typical Performance Curves (Continued) POWER DISSIPATION (W) 1.4 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.250W 1.2 SO16 (0.150”) θJA = +80°C/W 1.0 909mW 0.8 893mW SO8 θJA = +110°C/W 0.6 435mW 0.4 0.2 0.1 0 SOT23-6 θJA = +230°C/W 0 25 50 QSOP16 θJA = +112°C/W 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 13. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Applications Information Product Description The EL5106 and EL5306 are fixed gain amplifier that offers a wide -3dB bandwidth of 350MHz and a low supply current of 1.5mA. They work with supply voltages ranging from a single 5V to 12V and they are also capable of swinging to within 1.2V of either supply on the output. These combinations of high bandwidth and low power make the EL5106 and EL5306 the ideal choice for many low-power/high-bandwidth applications such as portable, handheld, or battery-powered equipment. For varying bandwidth and higher gains, consider the EL5191 with 1GHz on a 9mA supply current or the EL5162 with 300MHz on a 4mA supply current. Versions include single, dual, and triple amp packages with 5 Ld SOT-23, 16 Ld QSOP, and 8 Ld SOIC or 16 Ld SOIC outlines. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Low impedance ground plane construction is essential. Surface mount components are recommended, but if leaded components are used, lead lengths should be as short as possible. The power supply pins must be well bypassed to reduce the risk of oscillation. The combination of a 4.7µF tantalum capacitor in parallel with a 0.01µF capacitor has been shown to work well when placed at each supply pin. the positive supply. For ±5V supply, this means that the amplifier will be enabled when CE is 2V or less, and disabled when CE is above 4V. Although the logic levels are not standard TTL, this choice of logic voltages allow the EL5106 and EL5306 to be enabled by tying CE to ground, even in 5V single supply applications. The CE pin can be driven from CMOS outputs. Gain Setting The EL5106 and EL5306 are built with internal feedback and gain resistors. The internal feedback resistors have equal value; as a result, the amplifier can be configured into gain of +1, -1, and +2 without any external resistors. Figure 14 shows the amplifier in gain of +2 configuration. The gain error is ±2% maximum. Figure 15 shows the amplifier in gain of -1 configuration. For gain of +1, IN+ and IN- should be connected together as shown in Figure 16. This configuration avoids the effects of any parasitic capacitance on the IN- pin. Since the internal feedback and gain resistors change with temperature and process, external resistor should not be used to adjust the gain settings. 325Ω 325Ω IN- IN+ + FIGURE 14. AV = +2 Disable/Power-Down The EL5106 and EL5306 amplifiers can be disabled placing their output in a high impedance state. When disabled, the amplifier supply current is reduced to <25µA. The EL5106 and EL5306 are disabled when its CE pin is pulled up to within 1V of the positive supply. Similarly, the amplifier is enabled by floating or pulling the CE pin to at least 3V below 7 FN7357.6 September 21, 2010 EL5106, EL5306 325Ω 325Ω 325Ω IN- +5 IN+ + 325Ω FIGURE 15. AV = -1 +5 0.1µF + VOUT 1k 325Ω 0.1µF IN- 325Ω - VIN 1k + IN+ FIGURE 17. FIGURE 16. AV = +1 Supply Voltage Range and Single-Supply Operation The EL5106 and EL5306 have been designed to operate with supply voltages having a span of greater than or equal to 5V and less than 11V. In practical terms, this means that the EL5106 and EL5306 will operate on dual supplies ranging from ±2.5V to ±5V. With single-supply, the EL5106 and EL5306 will operate from 5V to 10V. As supply voltages continue to decrease, it becomes necessary to provide input and output voltage ranges that can get as close as possible to the supply voltages. The EL5106 and EL5306 have an input range which extends to within 2V of either supply. So, for example, on ±5V supplies, the EL5106 and EL5306 have an input range which spans ±3V. The output range is also quite large, extending to within 1V of the supply rail. On a ±5V supply, the output is therefore capable of swinging from -4V to +4V. Single-supply output range is larger because of the increased negative swing due to the external pull-down resistor to ground. Figure 16 shows an AC-coupled, gain of +2, +5V single supply circuit configuration. 8 Video Performance For good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as DC levels are changed at the output. This is especially difficult when driving a standard video load of 150Ω, because of the change in output current with DC level. Previously, good differential gain could only be achieved by running high idle currents through the output transistors (to reduce variations in output impedance). Special circuitries have been incorporated in the EL5106 and EL5306 to reduce the variation of output impedance with current output. This results in dG and dP specifications of 0.02% and 0.04°, while driving 150Ω at a gain of 2. Output Drive Capability In spite of its low 1.5mA of supply current per amplifier, the EL5106 and EL5306 are capable of providing a maximum of ±125mA of output current. Driving Cables and Capacitive Loads When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, the back-termination series resistor will decouple the EL5106 and EL5306 from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. In these applications, a small series resistor (usually between 5Ω and 50Ω) can be placed in series with the output to eliminate most peaking. FN7357.6 September 21, 2010 EL5106, EL5306 Current Limiting where: The EL5106 and EL5306 have no internal current-limiting circuitry. If the output is shorted, it is possible to exceed the Absolute Maximum Rating for output current or power dissipation, potentially resulting in the destruction of the device. Power Dissipation With the high output drive capability of the EL5106 and EL5306, it is possible to exceed the +125°C Absolute Maximum junction temperature under certain very high load current conditions. Generally speaking when RL falls below about 25Ω, it is important to calculate the maximum junction temperature (TJMAX) for the application to determine if power supply voltages, load conditions, or package type need to be modified for the EL5106 and EL5306 to remain in the safe operating area. These parameters are calculated as shown in Equation 1: T JMAX = T MAX + ( θ JA × n × PD MAX ) (EQ. 1) TMAX = Maximum ambient temperature θJA = Thermal resistance of the package n = Number of amplifiers in the package PDMAX = Maximum power dissipation of each amplifier in the package PDMAX for each amplifier can be calculated as shown in Equation 2: V OUTMAX PD MAX = ( 2 × V S × I SMAX ) + ( V S - V OUTMAX ) × ---------------------------R L (EQ. 2) where: VS = Supply voltage ISMAX = Maximum bias supply current VOUTMAX = Maximum output voltage (required) RL = Load resistance Revision History DATE REVISION CHANGE 6/4/09 FN7357.6 Removed obsolete, leaded devices EL5106IW-T7, EL5106IW-T7A; EL5106IS-T7, EL5106IST13; EL5306IS, EL5306IS-T7, EL5306IS-T13; EL5306IU, EL5306IU-T7, EL5306IU-T13 Corrected Figure references in “Gain Setting” on page 7 (Fig 14 callout was referencing Fig 13; Fig 15 callout was referencing Fig 14; Fig 16 callout was referencing Fig 15) . Updated pin descriptions to match pin names of EL5306. Applied Intersil Standards: Updated Pb-free bullet in Features, Updated ordering information by removing tape and reel column and adding standard reference note and updating note to match lead finish, updated caution statement to legal's suggested verbiage. Changed date and Rev'd to 6. Updated POD MDP0038 toP6.064A - P6.064A replaces 6 Ld SOT-23 (same dimensions, just MDP0038 had both 5 & 6 Ld SOT23s w/dimensions listed in table) Updated POD MDP0027 to M8.15E - M8.15E replaces MDP0027 8 Ld SOIC (same dimensions, just MDP0027 had 8, 14, 16, 20, 24, 28 Ld SOICS with dimensions listed in table) P1, added Note 2 "The part marking is located on the bottom of the part" for SOT-23 package 9 FN7357.6 September 21, 2010 EL5106, EL5306 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (0.60) (1.27) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN 10 FN7357.6 September 21, 2010 EL5106, EL5306 Package Outline Drawing P6.064A 6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE Rev 0, 2/10 1.90 0-3° 0.95 D 0.08-0.20 A 5 6 4 PIN 1 INDEX AREA 2.80 3 1.60 3 0.15 C D 2x 1 (0.60) 3 2 0.20 C 2x 0.40 ±0.05 B 5 SEE DETAIL X 3 0.20 M C A-B D TOP VIEW 2.90 5 END VIEW 10° TYP (2 PLCS) 0.15 C A-B 2x H 1.14 ±0.15 C SIDE VIEW 0.10 C 0.05-0.15 1.45 MAX SEATING PLANE DETAIL "X" (0.25) GAUGE PLANE 0.45±0.1 4 (0.60) (1.20) NOTES: (2.40) (0.95) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 3. Dimension is exclusive of mold flash, protrusions or gate burrs. 4. Foot length is measured at reference to guage plane. 5. This dimension is measured at Datum “H”. 6. Package conforms to JEDEC MO-178AA. (1.90) TYPICAL RECOMMENDED LAND PATTERN 11 FN7357.6 September 21, 2010 EL5106, EL5306 Quarter Size Outline Plastic Packages Family (QSOP) MDP0040 A QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY D (N/2)+1 N INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES E PIN #1 I.D. MARK E1 1 (N/2) B 0.010 C A B e H C SEATING PLANE 0.007 0.004 C b C A B A 0.068 0.068 0.068 Max. - A1 0.006 0.006 0.006 ±0.002 - A2 0.056 0.056 0.056 ±0.004 - b 0.010 0.010 0.010 ±0.002 - c 0.008 0.008 0.008 ±0.001 - D 0.193 0.341 0.390 ±0.004 1, 3 E 0.236 0.236 0.236 ±0.008 - E1 0.154 0.154 0.154 ±0.004 2, 3 e 0.025 0.025 0.025 Basic - L 0.025 0.025 0.025 ±0.009 - L1 0.041 0.041 0.041 Basic - N 16 24 28 Reference Rev. F 2/07 NOTES: L1 A 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. c SEE DETAIL "X" 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 0.010 A2 GAUGE PLANE L A1 4°±4° DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN7357.6 September 21, 2010