CDP1822C/3 High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM March 1997 Features Description • For Applications in Aerospace, Military, and Critical Industrial Equipment The CDP1822C/3 is a 256 word by 4-bit random access memory designed for use in memory systems where high speed, low operating current, and simplicity in use are desirable. The CDP1822 features high speed and excellent noise immunity. It has separate data inputs and outputs and utilizes a single power supply of 4V to 6.5V. • Interfaces Directly with CDP1802 Microprocessor • Very Low Operating Current - At VDD = 5V and Cycle Time = 1µs . . . . . . 4mA (Typ) • Static CMOS Silicon-On-Sapphire Circuitry - CD4000 Series Compatible • Industry Standard Pinout • Two Chip Select Inputs - Simple Memory Expansion • Memory Retention for Standby. . . . . . . . . . . . . 2V (Min) Battery Voltage • Single Power Supply Operation . . . . . . . . . . 4V to 6.5V • High Noise Immunity 30% of VDD. . . . . . . . . 4V to 6.5V • Output Disable for Common I/O Systems • Three-State Data Output for Bus Oriented Systems Two Chip Select inputs simplify system expansion. An output Disable control provides Wire-OR-capability and is also useful in common Input/Output systems. The Output Disable input allows this RAM to be used in common data Input/Output systems by forcing the output into a high impedance state during a write operation independent of the Chip Select input condition. The output assumes a high impedance state when the Output Disable is at high level or when the chip is deselected by CS1 and/or CS2. The high noise immunity of the CMOS technology is preserved in this design. For TTL interfacing at 5V operation, excellent system noise margin is preserved by using an external pull-up resistor at each input. • Separate Data Inputs and Outputs • Latch-Up-Free Transient Radiation Tolerance Ordering Information PACKAGE SBDIP TEMP. RANGE -55oC to +125oC PART NUMBER CDP1822CD3 PKG. NO. D22.4A Pinout CDP1822C/3 (SBDIP) TOP VIEW OPERATIONAL MODES INPUTS CHIP SELECT 1 (CS1) CHIP SELECT 2 (CS2) A3 1 22 VDD A2 2 21 A4 A1 3 20 R/W A0 4 19 CS1 Read 0 1 0 1 Read A5 5 18 O. D. Write 0 1 0 0 Data In A6 6 17 CS2 Write 0 1 1 0 A7 7 16 DO4 High Impedance VSS 8 15 DI4 Standby 1 X X X DI1 9 14 DO3 High Impedance DO1 10 13 DI3 Standby X 0 X X DI2 11 12 DO2 High Impedance Output Disable X X 1 X High Impedance MODE OUTPUT READ/ DISABLE WRITE (OD) (R/W) OUTPUT Logic 1 = High, Logic 0 = Low, X = Don’t Care CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 6-19 File Number 2981.1 CDP1822C/3 Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1822C/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) SBDIP Package . . . . . . . . . . . . . . . . . . 80 21 Maximum Storage Temperature Range (TSTG) . . .-65oC to +150oC Maximum Lead Temperature (During Soldering) . . . . . . . . . +265oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150oC Recommended Operating Conditions At TA = Full Package Temperature Range.For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: LIMITS PARAMETER DC Operating Voltage Range Input Voltage Range MIN MAX UNITS 4 6.5 V VSS VDD V Static Electrical Specifications CONDITIONS LIMITS -55oC, +25oC +125oC SYMBOL VO (V) VIN (V) VDD (V) MIN MAX MIN MAX UNITS Quiescent Device Current (Note 1) IDD - 0, 5 5 - 390 - 1000 µA Output Low (Sink) Current (Note 1) IOL 0.4 0, 5 5 2.6 - 1.6 - mA Output High (Source) Current (Note 1) IOH 4.6 0, 5 5 - -1.2 - -0.8 mA Output Voltage Low-Level VOL - 0, 5 5 - 0.1 - 0.5 V Output Voltage High-Level VOH - 0, 5 5 VDD - 0.1 - VDD - 0.5 - V Input Low Voltage VIL 0.5, 4.5 - 5 - 0.3 VDD - 0.3 VDD V Input High Voltage VIH 0.5, 4.5 - 5 0.7 VDD - 0.7 VDD - V Input Leakage Current (Note 1) IIN - 0, 5 5 - ±3.2 - ±10 µA Operating Current (Note 1) IDD1 - 0, 5 5 - 6.5 - 10 mA Three-State Output Leakage Current IOUT 0, 5 0, 5 5 - ±3.2 - ± 19 µA Input Capacitance CIN - - - - 7.5 - 7.5 pF COUT - - - - 7.5 - 7.5 pF PARAMETER Output Capacitance NOTE: 1. Limits designate 100% testing, all other limits are designer’s parameters under given test conditions and do not represent 100% testing. 6-20 CDP1822C/3 Read Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF LIMITS +25oC, -55oC +125oC SYMBOL VDD (V) MIN MAX MIN MAX UNITS Read Cycle (Note 1) tRC 5 370 - 500 - ns Access from Address (Note 1) tADA 5 - 370 - 500 ns Output Valid from Chip Select 1 (Note 1) tDOA1 5 - 370 - 500 ns Output Valid from Chip Select 2 (Note 1) tDOA2 5 - 370 - 500 ns Output Active from Output Disable (Note 1) tDOA3 5 - 170 - 225 ns Output Hold from Chip Select 1 tDOH1 5 10 - 20 - ns Output Hold from Chip Select 2 tDOH2 5 10 - 20 - ns Output Hold from Output Disable tDOH3 5 10 - 20 - ns PARAMETER NOTE: 1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing VDD tRC CHIP SELECT 2 OUTPUT DISABLE tDOA1 (NOTE 1) tDOA2 (NOTE 1) tDOA3 (NOTE 1) READ ADDRESS DECODER DATA IN CHIP SELECT 1 tDOH1 tDOH2 VSS WRITE ADDRESS DECODER tDOH3 READ/ WRITE DATA OUT HIGH IMPEDANCE DATA OUT VALID HIGH IMPEDANCE VDD NOTE: Minimum timing for valid data output. Longer times will initiate an earlier but invalid output. FIGURE 1. READ CYCLE WAVEFORMS AND TIMING DIAGRAM 6-21 FIGURE 2. MEMORY CELL CONFIGURATION DATA OUT tADA A0 - A7 CDP1822C/3 Write Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF LIMITS +25oC, -55oC +125oC SYMBOL VDD (V) MIN MAX MIN MAX UNITS Write Cycle (Note 1) tWC 5 400 - 560 - ns Address Setup (Note 1) tAS 5 160 - 225 - ns Address Hold (Note 1) tAH 5 40 - 55 - ns tWRW 5 200 - 280 - ns Data in Setup (Note 1) tDIS 5 200 - 280 - ns Data in Hold (Note 1) tDIH 5 40 - 55 - ns Chip Select 1 Setup tCSS1 5 200 - 280 - ns Chip Select 2 Setup tCSS2 5 200 - 280 - ns Output Disable Setup tODS 5 140 - 225 - ns PARAMETER Write Pulse Width (Note 1) NOTE: 1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing tWC tAH A0 - A7 tCSSI tCSIH CHIP-SELECT 1 CHIP-SELECT 2 tCSS2 OUTPUT DISABLE tCS2H (NOTE 1) tODS tDIS tDIH DATA IN STABLE DI1 - DI4 tWRW READ/WRITE tAS DON’T CARE NOTE 1 NOTE: 1. tODS is required for common I/O operation only; for separate I/O operations, output disable is don’t care. FIGURE 3. WRITE CYCLE TIMING WAVEFORMS 6-22 CDP1822C/3 Data Retention Specifications TEST CONDITIONS LIMITS +25oC, -55oC +125oC SYMBOL VDR (V) VDD (V) MIN MAX MIN MAX UNITS Minimum Data Retention Voltage (Note 1) VDR - - - 2 - 2.5 V Data Retention Quiescent Current (Note 1) IDD 2 - - 70 - 380 µA tCDR - 5 450 - 650 - ns - 10 5 5 450 - 650 - ns PARAMETER Chip Deselect to Data Retention Time Recovery to Normal Operation Time tRC NOTE: 1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing. DATA RETENTION MODE VDD 0.95 VDD tCDR VDR tF CS2 0.95 VDD tRC tR VIH VIH VIL VIL FIGURE 4. LOW VDD DATA RETENTION TIMING WAVEFORMS R A3 1 22 VDD A2 2 21 A4 A1 3 20 01 A0 4 19 A9 A5 5 18 A11 A6 6 17 A10 A7 7 16 8 15 A8 VDD 2kΩ A8 9 14 10 13 11 12 TEMPERATURE DURATION VDD D 125oC 160 Hrs 7V 0 1.6 2.2 5.0 6.8 7.2 10.0µs VDD 01 0 R VDD A8 2kΩ R A8 2kΩ R VDD VDD 0 A0 VDD VDD 2kΩ R = 2kΩ ±20% PACKAGE A1 0 FIGURE 5. DYNAMIC/OPERATING BURN-IN CIRCUIT AND TIMING DIAGRAM All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 6-23