INTERSIL CDP1857

CDP1857C
4-Bit Bus Buffer/Separator
March 1997
Features
Description
• Provides Easy Connection of I/O to CDP1800-Series
Microprocessor Data Bus
The CDP1857C is a 4-bit CMOS non-inverting bus separator
designed for use in CDP1800-series microprocessor systems. It can
be controlled directly by a 1800-series microprocessor without the
use of additional components.
• Non-Inverting Fully Buffered Data Transfer
Ordering Information
PART
NUMBER
TEMP. RANGE
CDP1857CE
-40oC to +85oC
PDIP
E16.3
CDP1857CD
-40oC to +85oC
SBDIP
D16.3
PACKAGE
PKG. NO.
TABLE 1. CDP1857 FUNCTION FOR I/O BUS SEPARATOR
OPERATION
DATA BUS OUT
DB0-DB3
DATA OUT
DO0-DO3
CS
MRD
0
X
High Impedance
High Impedance
1
0
High Impedance
Data Bus
1
1
Data In
High Impedance
Pinout
The CDP1857 is designed for use as a bus buffer or separator
between the 1800-series microprocessor data bus and I/O devices.
It provides a chip-select (CS) input signal which, when high (1),
enables the bus-separator three-state output drivers. The direction
of data flow, when enabled, is controlled by the MRD input signal.
In the CDP1857, when MRD = 1, it enables the three-state bus drivers
(DB0-DB3) and transfers data from the DATA-IN lines onto the data
bus. When MRD = 0, it disables the three-state bus drivers (DB0DB3) and enables the three-state data output drivers (DO0-DO3),
thus, transferring data from the data bus to the DATA-OUT terminals.
The CDP1857 can be used as a bidirectional bus buffer by connecting
the corresponding DI and DO terminals (Figure 1). The MRD output
signal from the 1800-series microprocessor has the correct polarity to
control the CDP1857 when it is used as I/O bus buffer/separator.
Therefore, the 1800-series microprocessor MRD signal can be
connected directly to the MRD input of CDP1857. See Function Table
1 for use of the CDP1857 as an I/O bus buffer/separator.
The CDP1857C is supplied in 16-lead hermetic, dual-in-line ceramic
packages (D suffix), and in 16-lead plastic packages (E suffix).
Functional Diagram For CDP1857
16 LEAD DIP
TOP VIEW
DI0
1
14
DI0 1
DI1 2
DO0 3
16 VDD
DO0
15 CS
14 DB0
2
DI1
DO1 4
13
13 DB1
DO2 5
12 DB2
DO3 6
11 DB3
DI2 7
10 MRD
VSS 8
9 DI3
DB0
3
DO1
DB1
4
7
DI2
DO2
DI3
DO3
12
DB2
5
9
11
DB3
6
15
10
MRD
CS
16 = VDD
8 = VSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
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File Number
1192.2
CDP1857C
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (VDD)
(All Voltages Referenced to VSS Terminal) . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Thermal Resistance (Typical)
θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
85
N/A
SBDIP Package . . . . . . . . . . . . . . . . . .
85
22
Device Dissipation Per Output Transistor
TA = Full Package Temperature Range
(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range (TA)
Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC
Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC
Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC
Lead Temperature (During Soldering). . . . . . . . . . . . . . . . . . +265oC
At distance 1/16 ±1/32 In. (1.59 ± 0.79mm)
from case for 10s max
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
At TA = -40oC to +85oC, Except as Noted:
Static Electrical Specifications
CONDITIONS
PARAMETER
SYMBOL
VO
(V)
VIN
(V)
VDD
(V)
MIN
(NOTE 1)
TYP
MAX
UNITS
Quiescent Device Current
IDD
-
0, 5
5
-
5
50
µA
Output Low Drive (Sink) Current
IOL
0.4
0, 5
5
1.6
3.2
-
mA
Output High Drive (Source) Current
IOH
4.6
0, 5
5
-1.15
-2.3
-
mA
Output Voltage Low-Level (Note 3)
VOL
-
0, 5
5
-
0
0.1
V
Output Voltage High-Level (Note 3)
VOH
-
0, 5
5
4.9
5
-
V
Input Low Voltage
VIL
0.5, 4.5
-
5
-
-
1.5
V
Input High Voltage
VIH
0.5, 4.5
-
5
3.5
-
-
V
Input Leakage Current
IIN
Any Input
0, 5
5
-
-
1
µA
Operating Current (Note 2)
IDD1
0, 5
0, 5
5
-
50
100
µA
Input Capacitance
CIN
-
-
-
-
5
7.5
pF
NOTES:
1. Typical values are for TA =+25oC and nominal voltage.
2. Operating current measured in a CDP1802 system at 3.2MHz with outputs floating.
3. IOL = IOH = 1µA.
Dynamic Electrical Specifications
At TA = -40oC to +85oC, VDD = 5V ±5%, V IH = 0.7 VDD, VIL = 0.3 VDD, tR, tF = 20ns, CL = 100pF
SYMBOL
VDD
(V)
(NOTE 1)
TYP
MAX
UNITS
MRD or CS to DO
tED
5
150
225
ns
MRD or CS to DB
tEB
5
150
225
ns
DI to DB
tIB
5
100
150
ns
DB to DO
tBO
5
100
150
ns
PARAMETER
Propagation Delay Time:
NOTE:
1. Typical values are for TA = 25oC and nominal voltages.
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CDP1857C
Recommended Operating Conditions
At TA = Full Package Temperature Range.For maximum reliability, operating conditions
should be selected so that operation is always within the following ranges:
PARAMETER
Supply-Voltage Range
Recommended Input Voltage Range
MIN
MAX
UNITS
4
6.5
V
VSS
VDD
V
Timing Diagrams
CS
CS
MRD
MRD
DI
DI
tEB
tED
tEB
90%
DB
tED
90%
DB
10%
10%
FIGURE 1A. ENABLE TO DB TIME
FIGURE 1B. ENABLE TO DO TIME
CS
CS
MRD
MRD
DI
DI
tIB
DB
tIB
tBO
VALID DATA
VALID DATA
DB
FIGURE 1C. DI TO DB TIME
tBO
FIGURE 1D. DB TO DO TIME
FIGURE 1. TIMING DIAGRAMS FOR CDP1857C
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CDP1857C
Typical Applications
CDP1857
DO0-DO3
BUS
BUS
DB0-DB3
DI0-DI3
MRD
DIRECTION
CONTROL
CS
ENABLE BUS-TO-BUS
DATA TRANSFER
FIGURE 2. CDP1857 BIDIRECTIONAL BUS BUFFER OPERATION
MRD
CDP1800
SERIES
CPU
MWR
N0, N1
OR N2
DATA
BUS
CS
CDP1857
DO0-DO3
DB0-DB3
(4)
(4)
DATA BUS (8)
DI0-0I3
(8)
MRD
(4)
I/O
(8)
(4)
MRD
(4)
CDP1857
DI0-DI3
DB0-DB3
(4)
DO0-DO3
CS
FIGURE 3. CDP1857 BUS SEPARATOR OPERATION
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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