TI 74ACT16640DL

54ACT16640, 74ACT16640
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS173A - JULY 1990 - REVISED APRIL 1996
D
D
D
D
D
D
D
54ACT16640 . . . WD PACKAGE
74ACT16640 . . . DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus  Family
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture Optimizes
PCB Layout
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
EPIC  (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
125°C
Packaged in Plastic 300-mil Shrink
Small-Outline (DL) Packages Using 25-mil
Center-to-Center Pin Spacings and 380-mil
Fine-Pitch Ceramic Flat (WD) Packages
Using 25-mil Center-to-Center Spacings
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
description
The ’ACT16640 are inverting 16-bit transceivers
designed for asynchronous communication
between data buses.
These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. They allow
data transmission from the A bus to the B bus or
from the B bus to the A bus, depending on the logic
level at the direction-control (1DIR and 2DIR)
inputs. The output-enable (1OE and 2OE) inputs
can be used to disable the device so that the
buses are effectively isolated.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
The 74ACT16640 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16640 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT16640 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each section)
INPUTS
OPERATION
OE
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
54ACT16640, 74ACT16640
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS173A - JULY 1990 - REVISED APRIL 1996
logic symbol†
1OE
1DIR
48
G3
1
3 EN1 [BA]
3 EN2 [AB]
25
2OE
2DIR
1A1
G6
24
6 EN4 [BA]
6 EN5 [AB]
47
1
1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
3
44
5
43
6
41
8
40
9
38
11
37
12
36
13
4
2A3
2A4
2A5
2A6
2A7
2A8
1B1
2
46
1
1
2A2
2
1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
5
35
14
33
16
32
17
30
19
29
20
27
22
26
23
2B2
2B3
2B4
2B5
2B6
2B7
2B8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1OE
1DIR
1A1
48
2OE
1
2DIR
47
2
1B1
2A1
25
24
36
To Seven Other Channels
To Seven Other Channels
2
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13
• DALLAS, TEXAS 75265
2B1
54ACT16640, 74ACT16640
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS173A - JULY 1990 - REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.2 W
Storage temperature range,Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16640
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
IOL
∆t/∆v
Low-level output current
High-level input voltage
74ACT16640
MIN
2
2
0.8
Input transition rise or fall rate
0
TA
Operating free-air temperature
–55
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
UNIT
V
V
0.8
V
VCC
VCC
V
–24
–24
mA
24
24
mA
VCC
VCC
0
0
V
10
0
10
ns/V
125
–40
85
°C
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
54ACT16640, 74ACT16640
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS173A - JULY 1990 - REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
4.5 V
IOH = –50
50 µA
VOH
24 mA
IOH = –24
IOH = –75 mA†
II
IOZ‡
A or B ports
ICC
VO = VCC or GND
VI = VCC or GND,
Control inputs
MIN
IO = 0
VI = VCC or GND
VO = VCC or GND
MAX
74ACT16640
MIN
4.4
4.4
5.5 V
5.4
5.4
5.4
4.5 V
3.94
3.8
3.8
5.5 V
4.94
4.8
4.8
3.85
3.85
0.1
0.1
MAX
UNIT
V
0.1
5.5 V
0.1
0.1
0.1
4.5 V
0.36
0.44
0.44
5.5 V
0.36
0.44
0.44
1.65
1.65
±1
±1
µA
5.5 V
One input at 3.4 V,
Other inputs at VCC or GND
∆ICC§
Ci
IOL = 75 mA†
VI = VCC or GND
54ACT16640
4.4
4.5 V
IOL = 24 mA
Control inputs
TA = 25°C
TYP
MAX
5.5 V
IOL = 50 µA
VOL
MIN
V
5.5 V
±1
5.5 V
±0.5
±5
±5
µA
5.5 V
8
80
80
µA
5.5 V
0.9
1
1
mA
5V
4.5
pF
Cio
A or B ports
5V
16
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
pF
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPZH
tPZL
OE
A or B
tPHZ
tPLZ
OE
A or B
MIN
TA = 25°C
TYP
MAX
54ACT16640
MIN
74ACT16640
MAX
MIN
MAX
2.2
6
8.3
2.2
9.1
2.2
9.1
4.1
7.6
9.3
4.1
10.5
4.1
10.5
2.7
6.9
8.9
2.7
9.8
2.7
9.8
3.5
8.2
10.4
3.5
11.5
3.5
11.5
6.1
9.4
11.4
6.1
12.5
6.1
12.5
5.5
8.7
10.3
5.5
11
5.5
11
UNIT
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
d
Power dissipation capacitance per transceiver
TEST CONDITIONS
Outputs enabled
Outputs disabled
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CL = 50 pF,
pF
f = 1 MHz
TYP
52
9
UNIT
pF
54ACT16640, 74ACT16640
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS173A - JULY 1990 - REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × VCC
500 Ω
From Output
Under Test
S1
Open
GND
500 Ω
CL = 50 pF
(see Note A)
Output
Control
(low-level
enabling)
LOAD CIRCUIT
3V
Input
1.5 V
1.5 V
0V
tPHL
tPLH
VOH
Output
50% VCC
50% VCC
VOL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
1.5 V
1.5 V
3V
0V
tPZL
Output
Waveform 2
S1 at GND
(see Note B)
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright  1998, Texas Instruments Incorporated