Application Note 1969 ISL70001SRH, ISL70001SEH SPICE Average Model Abstract This application note describes how to use the SPICE model for the ISL70001SRH, ISL70001SEH Radiation Hardened and SEE Hardened 6A Synchronous Buck Regulator. This SPICE model was developed to help system designers evaluate the operation of this IC prior or in conjunction with prototyping a system design. This model accurately simulates typical performance characteristics at room temperature (+25°C) such as loop analysis, transient analysis and start-up. Functionality has been tested on CADENCE ORCAD 16.3. Other SPICE simulators may be used, however, the model may require translation. Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 License Statement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Project Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Power Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Inductor Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 VOUT Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Simulation Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 List of Figures FIGURE 1. FIGURE 2. FIGURE 3. FIGURE 4. Basic Noninverting Gain Configuration in Orcad Spice for AC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Simulated Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Simulated 3A Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Simulated Loop Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 November 25, 2015 AN1969.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1969 Introduction The Licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the Licensee’s company. The Licensee may modify the macro-model to suit his/her specific applications, and the Licensee may make copies of this macro-model for use within their company only. The ISL70001SRH, ISL70001SEH are radiation hardened and SEE hardened high efficiency monolithic synchronous buck regulators with integrated MOSFETs, which operate over an input voltage range of 3.0V to 5.5V. Utilizing peak current-mode control with integrated compensation and a switching frequency of 1MHz, this Point-of-Load (POL) provides excellent dynamic response in a small form factor. High integration and class leading radiation tolerance makes the ISL70001SRH, ISL70001SEH the ideal POL solution for many space applications. This macro-model is provided “AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.” In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice. Reference Documents • ISL70001SEH, ISL70001SRH Datasheet • SMD 5962-09225 Project Files License Statement The zip file: isl70001srh-pspice-average-model.zip contains the project file ISL70001SRH.opj to be used in an ORCAD simulator. The project file has the model definition file (.lib), symbol file (.olb) and the schematic page as shown in Figure 1. Three simulation profiles are included in the project to simulate startup, loop analysis and transient response. Figures 2 through 4 show the results of the three preset simulation profiles. The information in this SPICE model is protected under the United States copyright laws. Intersil Corporation hereby grants users of this macro-model hereto referred to as “Licensee”, a nonexclusive, nontransferable license to use this model as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. LOUT ISL70001SRH_AVG + U1 PVIN CIN1 22u CIN2 150u CIN3 150u CIN4 150u RCIN1 97M RCIN2 39.5m RCIN3 39.5m RCIN4 39.5m 0 0 0 0 CIN5 1u 3.3Vdc V2 0 CIN6 1u 0 D1 D1N5822 0 FB CAVDD 1u 0 OUT R4 10 VOUT V1 1Vac 0Vdc CSNUB 1n VOUT2 COUT1 150u COUT2 150u COUT3 150u RCOUT1 39.5m RCOUT2 39.5m RCOUT3 39.5m 0 0 0 COUT4 4.32u RLOAD 1.5 0 GND 0 VOUT VOUT R5 1k CFB 4700p 0 0 R1 9.09k EN R2 2.49k - L_1V = 1u R3 5.62 AVDD U2 IN LX SS CSS 100n CEN 0.01u LOUT LOUT 0 R6 665 0 0 PBLOCK = 3 I1 1 R7 1 0 FIGURE 1. BASIC NONINVERTING GAIN CONFIGURATION IN ORCAD SPICE FOR AC ANALYSIS Submit Document Feedback 2 AN1969.0 November 25, 2015 Application Note 1969 Power Blocks The model has a parameter named PBLOCK, which is equivalent to the number of LX nodes connected on the ISL70001SRH in a given application. By double clicking the text you can modify the number of blocks to match the prototype board. Inductor Value The average model is based on a mathematical representation of the ISL70001SRH. The value of the inductor is needed for the model to accurately simulate the regulator. The model has an added pin LOUT, which is connected to a current source I1 and resistor R7. These create a voltage that is fed into the pin and into the inductor U2. U2 translates the voltage into inductance by the equation L_1V = 1µ, for every volt on LOUT the inductor value is 1µH. To change the inductor value to say for example 500nH, one must change R7 to 0.5Ω. VOUT Value The output voltage must also be known for the average model to work correctly. The VOUT pin is added to read the output voltage and feed into the internal equations within the ISL70001SRH model. For proper simulation of the model VOUT must be connected to the output voltage of the ISL70001SRH application schematic. Simulation Performance Curves 1.6V 5.0A 1.2V 2.5A SEL>> 0A 0.8V I(R8) 1.55V 0.4V 1.50V 0V 0s 2ms V(VOUT) 4ms 6ms 8ms 10ms 1.45V 0s V(EN) 0.4ms 0.6ms 0.8ms 1.0ms Time FIGURE 2. SIMULATED START-UP 180d P h a s e 0.2ms V(VOUT) Time G a i n FIGURE 3. SIMULATED 3A TRANSIENT RESPONSE 100 100d 50 0d 0 -50 -100d -180d >> -100 1.0Hz 1 10Hz Loop_Phase 2 100Hz 1.0KHz Loop_Gain 10KHz 100KHz 1.0MHz 10MHz 100MHz Frequency FIGURE 4. SIMULATED LOOP RESPONSE Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the document is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 3 AN1969.0 November 25, 2015