TM TCM38C17 Quad Combo Interface to HC55181 and HC5503 Application Note March 2000 AN9852.1 Author: Ziad Asghar (Texas Instruments) Introduction channel of the SLIC appears at the transmit channel, deteriorating voice quality. This would result in the person hearing his own voice back through the handset. To reduce this effect, a transhybrid balance circuit is used between the combo and the SLIC. The transhybrid balance circuitry given below provides some degree of isolation, but for better performance, the transhybrid must include op amps. The TCM38C17 is a four-channel PCM combo. The term combo implies a CODEC and filters. This means that in addition to the ADC and DAC, the antialiasing filter and the smoothing filters are also on the chip. The TCM38C17 complies with CCITT/(D3/D4) G.711 and G.714 Channel Bank Specifications. [1] Figure 1 shows the block diagram of a single TCM38C17 channel. TCM38C17 Interface to the HC5503 SLIC This section gives details on interfacing the TCM38C17 with HC5503 SLIC. The test setup consists of: The TCM38C17 uses sigma-delta converter technology and provides the option of selecting A-Law or µ-Law companding. It has a single PCM I/O for a simplified PCM interface. Each channel can interface a full-duplex, 4-line voice telephone circuit with a time-division-multiplexed system. The crosstalk between channels is less than -100dB, which means that the TCM38C17 saves board space without any crosstalk. The TCM38C17 provides 8VP-P full-signal differential receiver output. • HC5503 SLIC Evaluation Board • TCM38C17 Test Board • Bread board to implement the transhybrid circuitry Figure 2 shows the test setup to measure how much of the signal appears at test point 3 when a signal is applied at test point 2. These parts typically are used in line card applications. The major components on a line card include a combo, SLIC, microcontroller, voltage regulators, and transient voltage suppressors. The SLIC, in addition to other things, converts the analog signal from two-wire to four-wire and vice-versa. In this process, some of the signal applied at the receive ANGLINANGLIN+ ANTIALIAS FILTER + The transhybrid circuitry given does not use on op amp. Instead, it consists only of resistors and capacitors. The amplifier forms the input stage of the TCM38C17. Some of the specifications of this amplifier are given in Table A-1 in the Appendix. DIGITAL FILTER Σ∆ ADC COMPRESSOR OUTPUT REGISTER CLOCK BUFFER GSX PCMOUT MCLK (2.048MHz) FRAME CONTROL FS GSR PWRO+ OUTPUT AMPLIFIER PWRO- INVERTING AMPLIFIER SWITCHEDCAPACITOR SMOOTHING FILTER DIGITAL FILTER Σ∆ DAC EXPANDER INPUT REGISTER PCMIN FIGURE 1. BLOCK DIAGRAM OF A TCM38C17 CHANNEL 4-1 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 Application Note 9852 Figure 3 shows the interface between one channel of the TCM38C17 and the Intersil HC5503 SLIC. 2 1 SLIC EVALUATION BOARD VRX TRANSHYBRID CIRCUITRY VTX 0.47µF 200kΩ TX -31.7 1200 0.012 -38.4 1600 0.010 -40 2000 0.009 -40.9 2400 0.009 -40.9 2800 0.008 -41.9 3200 0.008 -41.9 3600 0.008 -41.9 GSR TCM38C17 PWRO150kΩ 0.026 TCM38C17 TEST BOARD ANLGIN- R1 HC5503 400 -37.1 PWRO+ 150kΩ TRANSHYBRID LOSS (dB) 0.014 0.47µF R2 24.9kΩ TEST POINT 3 (VAC) 800 FIGURE 2. TEST SETUP 0.47µF FREQUENCY (Hz) PWRO+ 3 RX TABLE 1. TRANSHYBRID LOSS CALCULATION FOR HC5503 GSX ANLGIN- Without the transhybrid circuitry, the signal that is fed into the receive pin of the SLIC appears at the transmit pin. To check the whole loop, a 1kHz, 1VRMS signal was applied at the receive pin of the SLIC and the transhybrid circuit was removed. The signal appears at the transmit pin, which is connected to the analog input of the TCM38C17; using digital loop back, the analog output at the PWRO+ pin was observed. This configuration is shown in Figure 4. ANLGIN+ AREF 1 2 100nF PCMIN FIGURE 3. QCOMBO INTERFACE TO THE INTERSIL 5503 SLIC The transhybrid circuit works due to the inversion of the signal from the receive port to the transmit port. The voltage at RX is negative of the TX, so if the currents at the two ports are the same, then the input signal could be removed from the output signal. The resistors R1 and R2 can be changed to adjust the gain, which is given by the following equation: R1 + R2 A = -----------------------------R1 4 R 2 + ------- 4 (EQ. 1) The input and output gain adjustment are discussed in detail in PCM CODEC/Filter Combo Family: Device Design-In and Application Data.[2] Figure 3 shows the TCM38C17’s output used in the single-ended configuration. The analog input gain can be fixed simply by using the feedback loop through GSX. The AREF pin provides a reference voltage of 2.375V that is connected to ANLGIN+ for bias. Using the configuration in Figure 3, the transhybrid loss was calculated, using the formula: transhybrid loss = 20 x log (VO/1VRMS), where VO is the voltage at test point 3. The data was gathered by measuring the output at different frequencies in the voice band range. A 1VRMS signal was applied at test point 2. The results are given in Table 1. 4-2 SLIC EVALUATION BOARD VRX VTX PWRO+ TCM38C17 TEST BOARD ANLGINPCMOUT FIGURE 4. TEST SETUP WITHOUT TRANSHYBRID CIRCUIT The scope plot for the setup in Figure 4 at test point 2 is given in Figure 5. To make a comparison, the input signal scope plot and its FFT are provided in the Appendix in Figure A-1. Also in the Appendix (in Figure A-2), is the signal at the PWRO+ pin and its FFT, with a 1VRMS signal at the analog input with unity gain setting, and with PCMIN connected to PCMOUT. So Figure A-2 gives the output signal using digital loopback. The Appendix also provides a description on how to read the scope plots. To test the whole system with the transhybrid balance included, the following configuration was also tested. Application Note 9852 . 0.47µF ∆: 41.2dB @: -50.4dB RX 0.47µF C2 PK-PK 1.16V M2 MAX -6.0dB M2 MIN -82.2dB PWRO+ R1 GSR TCM38C17 R2 100kΩ PWRO- HC5518 GSX 100kΩ 0.47µF ANLGINANLGIN+ 44.2kΩ TX AREF 100nF CH2 500mV M 500µs CH2 1.96V FIGURE 8. QCOMBO INTERFACE TO THE HC5503 SLIC FIGURE 5. SCOPE PLOT FOR THE CONFIGURATION IN FIGURE 4 TELEPHONE TABLE 2. TRANSHYBRID LOSS CALCULATION FOR HC5518 VRX SLIC EVALUATION BOARD VTX 1 The same tests done for the HC5503 SLIC were carried out for the HC5518 SLIC. The results, given in Table 2, are based on a test setup similar to that given in Figure 2. TRANSHYBRID CIRCUITRY MIC 2 PCMIN PWRO+ TCM38C17 TEST BOARD FREQUENCY (Hz) TEST POINT 3 (VAC) TRANSHYBRID LOSS (dB) 400 0.017 -35.4 ANLGINPCMOUT 800 0.010 -40 1200 0.012 -38.4 1600 0.016 -35.9 2000 0.02 -34 2400 0.023 -32.8 2800 0.026 -31.7 3200 0.029 -30.8 3600 0.031 -30.2 SPEAKER FIGURE 6. TEST SETUP FOR THE COMPLETE SYSTEM In this case, a 1VRMS signal was applied to the microphone of the telephone (test point 2) and the output was observed at the speaker (test point 1); so the signal goes from the SLIC to the TCM38C17 and back through the transhybrid circuit. Figure 7 gives the scope plot showing the voltage at test point 1. ∆: 34.4dB @: -14.4dB Using the HC5518 in the configuration shown in Figure 4, the voltage at test point 2 is as follows: C2 PK-PK 720mV CH2 2.00V M 1.00ms CH2 M2 MAX 5.2dB ∆: 42.6dB @: -47.6dB M2 MIN -70.2dB M2 MAX 7.2dB M2 MIN -70.2dB -8.52V FIGURE 7. SCOPE PLOT FOR THE CONFIGURATION IN FIGURE 6 CH2 TCM38C17 Interface to the HC5518 SLIC FAMILY Figure 8 gives the interface between one channel of the TCM38C17 and the Intersil HC5503 SLIC. 4-3 2.00V M 500µs CH2 2.20V FIGURE 9. SCOPE PLOT FOR THE CONFIGURATION IN FIGURE 4, VOLTAGE AT TEST POINT 2 For the complete system test using the HC5518, the results are given in Figure 10. Application Note 9852 Figure 12 shows a diagram of a PCM-30 frame. E1 systems are used in countries not listed in the previous paragraph. ∆: 21.8dB @: -23.2dB M2 MAX -23.0dB All networks tied to the PSTN (public switched telephone network) operate synchronously at the given rate. At a digital end office, where the digital data is converted to analog, this clock is used to generate a frame synchronization pulse train. The frame sync information is used to assign a channel to its time slot within the frame. Up to 24 channels may be separated from the bit stream, based on their bit positions relative to the frame sync in a T1 system (32 in an E1 system). M2 MIN -90.2dB CH1 200mV M 500µs CH1 Upon receiving a frame sync, an individual combo will send its eight bits of data at 1.544MHz or 2.048MHz (depending on the system) and then wait through the remaining channels until its turn arrives again. While it waits, it samples the analog signal and converts it to digital data, which waits in the output buffer until the next frame sync. -12mV FIGURE 10. SCOPE PLOT FOR THE CONFIGURATION IN FIGURE 6, VOLTAGE AT TEST POINT 2 TIMING ISSUES Combos are designed to be interfaced to digital PCM telephone networks, which can be of two types. A T1 system operates at a 1.544MHz clock rate and allows for timedivision-multiplexing of 24 voiceband channels. The time intervals for a T1 signal are shown in Figure 11. T1 systems are used in the US, Canada, Japan and in parts of some other countries. T1 and E1 frames are 125µs in time duration. The TCM38C17 is more suited to an E1 system. It does not allow dynamic time slot assignment. The device has four separate FS pins for the four channels. The FS signal for the four channels has to be provided according to the timing given in Figure 13. The TCM38C17 can extract or insert any four channels, which meet the timing requirements, from/to the T1 or E1 bit stream. The four channels are labeled 0, 1, 2, 3 inside the TCM38C17, regardless of the corresponding channel numbers in the T1 or E1 frame. On the other hand, an E1 system operates at a 2.048MHz clock rate. An E1 system multiplexes 30 voiceband channels. An E1 frame consists of 32 eight-bit bytes, thirty bytes (channels) of these are used for voice transmission. Figure 12 shows a diagram of a PCM-30 frame. E1 systems are used in countries not listed in the previous paragraph. It is clear from the figure that FS signals for the channels have to be separated by 31.25µs. The MCLK for the TCM38C17 is fixed at 2.048MHz. For a 125µs frame, there are 256 complete cycles of the MCLK. Eight complete cycles of the MCLK are needed to shift the digital data in and out. Hence we have 32 time slots. The 31.25µs gap between the FS signals has 64 MCLK cycles implying 8 time slots. First, due to the limit on the MCLK, the TCM38C17 can be used for an E1 system. Second, the 31.25µs requirements implies that one TCM38C17 can use four time slots in an E1 frame. This means that an optimum solution would be to have eight TCM38C17s on one board, and that would cover the whole E1 frame. This is illustrated in Figure 14. All networks tied to the PSTN (public switched telephone network) operate synchronously at the given rate. At a digital end office, where the digital data is converted to analog, this clock is used to generate a frame synchronization pulse train. The frame sync information is used to assign a channel to its time slot within the frame. Up to 24 channels may be separated from the bit stream, based on their bit positions. On the other hand, an E1 system operates at a 2.048MHz clock rate. An E1 system multiplexes 30 voiceband channels. An E1 frame consists of 32 eight-bit bytes, thirty bytes (channels) of these are used for voice transmission. 193 BITS/FRAME 192 BITS ENCODED VOICE (24 8-BIT CHANNELS) CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH23 CH24 24 CHANNELS/FRAME X 8 BITS/CHANNEL + SYNC BIT = 193 BITS/FRAME 8000 FRAMES/SECOND X 193 BITS/FRAME = 1.544MBPS SYNCHRONIZATION BIT 8-BIT TIME SLOT FIGURE 11. A T1 PCM FRAME 4-4 Application Note 9852 256 BITS/FRAME 120 BITS ENCODED VOICE (15 8-BIT CHANNELS) CH1 CH2 CH3 120 BITS ENCODED VOICE (15 8-BIT CHANNELS) CH15 FRAMING BYTE CH16 CH30 SIGNALLING BYTE 8-BIT TIME SLOT 30 CHANNELS/FRAME X 8 BITS/CHANNEL + 2 OVERHEAD BYTES = 240 + 16 BITS = 256 BITS/FRAME 8000 FRAMES/SECOND X 256 BITS/FRAME = 2.048 MBP FIGURE 12. AN E1 FRAME 125µs 256 MCLK 0FS 31.25µs 1FS 31.25µs 2FS 31.25µs 3FS 31.25µs CHANNEL 0 DATA IN/OUT CHANNEL 1 DATA IN/OUT CHANNEL 2 DATA IN/OUT CHANNEL 3 DATA IN/OUT PCM IN/OUT 0FS 1FS 2FS 3FS 8 CLOCKS 64 CLOCKS 31.25µs 2.048MHz MCLK FIGURE 13. FRAME SYNC TIMING 4-5 Application Note 9852 TCM38C17 MICROCONTROLLER TCM38C17 TCM38C17 TIME SLOTS: 1, 9, 17, 25 TIME SLOTS: 2, 10, 18, 26 TIME SLOTS: 3, 11, 19, 27 4 SLICs 4 SLICs 4 SLICs TIME SLOTS: 4, 12, 20, 28 TCM38C17 TRANSIENT VOLTAGE SUPPRESSOR 4 SLICs TIME SLOTS: 5, 13, 21, 29 TCM38C17 4 SLICs TIME SLOTS: 6, 14, 22, 30 TCM38C17 VOLTAGE REGULATORS 4 SLICs TIME SLOTS: 7, 15, 23, 31 TCM38C17 4 SLICs TIME SLOTS: 8, 16, 24, 32 TCM38C17 4 SLICs FIGURE 14. BLOCK DIAGRAM OF A CARD FOR E1 APPLICATIONS Summary References The TCM38C17 is very well suited for line-card applications and can interface with various different types of SLICs. This report gives a brief description of how to interface the TCM38C17 with two different SLICs. It also provides frequency domain plots to give an estimate of the signal compared with the noise. The noise floor can be lowered further with better board design. The noise figures are greater than would be expected because of a microcontroller of the TCM38C17 test board. Active components can also be used in the design of the transhybrid balance to improve its performance further. [1] CCITT ITU-T G.711, G.712, G.714 Recommendations. [2] PCM CODEC/Filter Combo Family: Device Design-In and Application Data, Texas Instruments Incorporated, 1996 (SLWA006). [3] Wireless and Telecommunications Products Data Book, Texas Instruments Incorporated, 1996 (SLWD001). [4] Understanding Telephone Electronics, Stephen J. Bigelow, SAMS Publishing. [5] TCM4207A and TCM29C13 Telephone Line Card Application Report, Texas Instruments Incorporated. [6] LSSGR Technical Reference TR-TSY-000064, Section 7, Bell Communications Research. [7] AN9736 Application Note, Intersil Corporation, “Operation of the HC5503EVAL Evaluation Board”, AnswerFAX Doc. No. 99736. [8] AN9813 Application Note, Intersil Corporation, “HC5518XEVAL Evaluation Board User’s Guide”, AnswerFAX Doc. No. 99813. About the Author Ziad Asghar, (MSEE), of Texas Instruments, Inc., Data Communications Group, is an Applications/Systems Engineer working on Wireline Communications Systems. 4-6 Application Note 9852 Appendix Performance Data TABLE A-1. TCM38C17 INPUT AMPLIFIER SPECIFICATIONS TX AMPLIFIER PARAMETER MIN TYP Input Current at ANLGIN+ and ANLGINInput Offset Voltage at ANLGIN+ and ANLGIN- MAX UNIT +100 nA +5 mV CMRR at ANLGIN+ and ANLGIN- 55 dB Open-Loop Voltage Amplification at ANLGIN+ and ANLGIN- 60 dB Open-Loop Unity-gain Bandwidth at ANLGIN+ and ANLGINInput Resistance at ANLGIN+ and ANLGIN- 900 kHz 1- MΩ DISTANCE BETWEEN THE 2 HORIZONTAL CURSOR BARS, ESTIMATE OF DYNAMIC RANGE ∆: 57.2dB @: -56.8dB M2 MAX 0dB M2 MIN -82.0dB MAXIMUM POINT ON THE FET PLOT MINIMUM POINT ON THE FET PLOT ACTUAL VOLTAGE CH1 500mV 20.0dB M 500µs CH1 FFT OF THE VOLTAGE ABOVE SCALE (PER DIV.) FOR THE SIGNAL 0V 500Hz SCALE (PER DIV.) FOR FFT FIGURE A-1. 1VRMS ANALOG INPUT FROM SIGNAL GENERATOR ∆: 46.0dB @: -44.2dB C2 PK-PK 3.80V M2 MAX 2.0dB M2 MIN -76.2dB CH2 1.00V M 500µs CH2 1.96V FIGURE A-2. SIGNAL AT PWRO+ PIN, USING DIGITAL LOOPBACK WITH 1VRMS SIGNAL AT THE ANALOG INPUT WITH UNITY GAIN All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 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