TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 D D D D D D D D D D Meet CCITT/(D3/D4) Channel Bank Recommendations for Input Signals Greater than – 55 dBm0 Programmable Transmit and Receive Gain Control With Pin-Selectable Gain/Attenuation Levels Includes Differential Output on the TCM37C14A Precision Switched-Capacitor Filters and Converters Improved Version TCM29C13A Series COMBOs (CODEC and Filters) Low Power CMOS – Operating Mode . . . 70 mW Typical – Power-Down Mode . . . 7 mW Typical Internal Sample-and-Hold and Autozero Functions Precision Internal Voltage References TCM37C14A Features Pin-Selectable µ-Law or A-Law Companding and Pin-Selectable Master Clock Rate (1.536 MHz, 1.544 MHz, and 2.048 MHz Available) TCM37C15A is 2.048 MHz A-Law Only description TCM37C15A . . . DW OR N PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 VBB PWRO+ RIN RS1 RS2 GSR GS1 GS0 PCMIN FSR 20 19 18 17 16 15 14 13 12 11 VCC GSX TS1 TS2 ANLGIN AGND PCMOUT FSX MCLK DGND TCM37C14A . . . DW PACKAGE (TOP VIEW) VBB PWRO+ PWRO – RIN RS1 RS2 GSR GS1 GS0 CLKSEL PCMIN FSR 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC GSX TS1 TS2 ANLGIN AGND TSX PCMOUT FSX ASEL MCLK DGND The TCM37C14A and TCM37C15A PCM combo with programmable gain control devices are single-chip PCM combos (pulse-code-modulated CODECs with voice-band filtering). They are designed to perform transmit encoding (A/D conversion) and receive decoding (D/A conversion), as well as the transmit and receive filtering functions required to meet CCITT/(D3/D4) G.711 and G.714 specifications in a PCM system. Each device provides all the functions required to interface a full-duplex, 4-line voice telephone circuit with a TDM (time-division-multiplexed) system, and also perform the encoding and decoding of call progress tones. The TCM37C14A and TCM37C15A are based on the proven TI TCM29C13A core, and have the added feature of programmable transmit and receive gain. Primary applications include line interface for digital transmission and switching of T1/E1 carrier (PABX [private branch automatic exchange] and central office telephone systems), subscriber line concentrators, digital encryption systems, and digital signal processing. They are intended to be used at the analog termination of a PCM line or trunk to the POTS (plain old telephone system) local-loop line. The TCM37C15A is available in 20-pin DW SOIC (small-outline IC) or 20-pin N PDIP (plastic dual-in-line package) packages, and the TCM37C14A is available in a 24-pin DW SOIC package and includes differential output. All are characterized for operation from – 40°C to 85°C. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 AVAILABLE OPTIONS PACKAGE TA –40°C to 85°C 20 PIN SMALL OUTLINE (DW) 24 PIN PLASTIC DIP (N) TCM37C15AIDW SMALL OUTLINE (DW) TCM37C15AIN TCM37C14AIDW functional block diagram Transmit Section TS1 TS2 ANLGIN GSX 22 21 Auto Zero Gain Set Transmit Third-Order Antialias Low-Pass Filter (Analog) 20 23 Transmit Sixth-Order Low-Pass Filter (Switched Cap) Fc = 3400 Hz Transmit Third-Order High-Pass Filter (Switched Cap) Fc = 200 Hz 17 Sample and Hold ADC Output Register 18 16 Analog to Digital Control Logic Receive Section RIN GSR RS1 RS2 PWRO + PWRO –† 4 7 5 6 14 Buffer 2 Digital-toAnalog Control Logic Digital-toAnalog Converter 3 24 1 13 19 VBB DGND AGND † TCM37C14A only NOTE A: Terminal numbers shown are for the TCM37C14A. 2 FSX MCLK 10 CLKSEL† 15 ASEL† 9 GS0 8 GS1 Control Logic Filter VCC TSX† Control Section Reference Gain Set PCMOUT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12 FSR Input Register 11 PCMIN TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 Terminal Functions TERMINAL NAME I/O NO. DESCRIPTION ’37C15A ’37C14A AGND 15 19 ANLGIN 16 Analog ground return for all internal voice circuits. AGND is connected internally to DGND. 20 I Analog input to transmit operational amplifier. ASEL 15 I Selection between A-law and µ-law operation. When ASEL is connected to VBB, A-law is selected. When ASEL is connected to VCC or ground, µ-law is selected. CLKSEL 10 I Clock frequency selection. CLKSEL must be connected to VBB, VCC, or ground to select the master clock frequency. When CLKSEL is tied to VBB, MCLK is 2.048 MHz. When it is tied to ground, MCLK is at 1.544 MHz. When it is tied to VCC, MCLK is 1.536 MHz. Digital ground for all internal logic circuits. DGND is internally connected to AGND. DGND 11 13 FSR 10 12 I Frame-synchronization clock input/time-slot enable for receive channel. The receive channel enters the standby state when FSR is held low for 300 ms. FSX 13 16 I Frame-synchronization clock input/time-slot enable for transmit. The transmit channel enters the standby state when FSX is held low for 300 ms. GS0 8 9 I Input for first bit of the programmable gain control circuitry. GS0 works in combination with GS1 to simultaneously control transmit and receive gain, and controls power-down instruction. (See Table 1 and 2 for control logic information.) GS1 7 8 I Input for second bit of the programmable gain control circuitry. GS1 works in combination with GS0 to simultaneously control transmit and receive gain, and controls power-down instruction. (See Table 1 and 2 for control logic information.) GSR 6 7 I Input to gain-setting network of the output power amplifier. Gain is set by external resistors with three levels of programmable gain or attenuation control. (See Figure 6 and Figure 7 for recommended configuration.) GSX 19 23 O Output terminal of internal uncommitted operational amplifier. Internally, GSX is the voice signal input to the transmit filter. MCLK 12 14 I Master clock (input). For the TCM37C14A, the master clock frequency can be either 2.048 MHz, 1.544 MHz, or 1.536 MHz, and is selected by CLKSEL. MCLK for the TCM37C15A is 2.048 MHz. PCMIN 9 11 I Receive PCM input. PCM data is clocked in on PCMIN on eight consecutive negative transitions of the receive data clock (MCLK). PCMOUT 14 17 O Transmit PCM output. PCM data is clocked out on PCMOUT on eight consecutive positive transitions of the transmit data clock (MCLK). PWRO + 2 2 O Noninverting output of power amplifier. PWRO+ can drive transformer hybrids or high-impedance loads directly in a differential or a single-ended configuration. 3 O Inverting output of power amplifier. PWRO – is functionally identical with and complementary to PWRO +. I Input to receive section amplifiers. (See Figure 6 and Figure 7 for recommended circuitry.) PWRO – RIN 3 4 RS1 4 5 Terminal for first gain-control resistor of the receive section. RS1 is selected through closure of the first gain control switch. (See Figure 6 and Figure 7 for recommended circuitry.) RS2 5 6 Terminal for second gain control resistor of the receive section. RS2 is selected through closure of the second gain control switch. (See Figure 6 and Figure 7 for recommended configuration.) TS1 18 22 Terminal for gain-control resistor on input of transmit section. TS1 is selected through closure of the first gain-control switch. (See Figure 6 and Figure 7 for recommended configuration.) TS2 17 21 Terminal for gain-control resistor on input of transmit section. TS2 is selected through closure of the second gain-control switch. (See Figure 6 and Figure 7 for recommended configuration.) TSX VBB VCC 18 O Transmit channel time-slot strobe for the transmit channel (active low). TSX is an open drain output and can be used as an enable signal for a 3-state output buffer. 1 1 Negative supply voltage. Input is – 5 V ± 5%. 20 24 Positive supply voltage. Input is 5 V ± 5%. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Supply voltage, VBB (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 7 V Voltage range at any analog input, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3 V to VBB – 0.3 V Continuous total power dissipation at (or below) 25°C free-air temperature . . . . . . . . . . . . . . . . . . . 1300 mW Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . . 260°C JEDEC Latch up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 250 mA or ± 10 V † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltage values are with respect to GND. recommended operating conditions (see Note 2) Supply voltage, VCC (see Notes 2 and 3) Supply voltage, VBB MIN NOM MAX UNIT 4.75 5 5.25 V – 4.75 –5 – 5.25 V DGND voltage with respect to AGND 0 High-level input voltage, VIH V 2.2 Low-level input voltage, VIL V 0.8 At GSX/GSR Load resistance, resistance RL At PWRO + and/or PWRO – kΩ 300 Ω At GSX/GSR Load capacitance, capacitance CL 50 At PWRO + and/or PWRO – Operating free-air temperature, TA V 10 100 –40 85 pF °C NOTES: 2. To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device power-up sequence paragraphs later in this document should be followed. 3. Voltages at analog inputs and outputs, VCC and VBB terminals, are with respect to the AGND terminal. All other voltages are referenced to the DGND terminal unless otherwise noted. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (outputs not loaded) (unless otherwise noted) supply current PARAMETER 0°C to 85°C TEST CONDITIONS MIN TYP Operating ICC Supply S l currentt from f VCC Supply S l currentt from f VBB Power dissipation MIN TYP MAX 7 10 8 11 FSX, FSR at VIL (after 300 ms) 0.5 1.3 1 1.7 Power down GS0, GS1 = VIL (after 300 ms) 0.5 1.2 1 1.7 –7 –9 –9 – 11.5 Standby FSX, FSR at VIL (after 300 ms) – 0.6 –1 – 0.8 – 1.2 Power down GS0, GS1 = VIL (after 300 ms) – 0.3 – 0.9 – 0.4 – 1.2 70 100 80 110 Operating PD MAX Standby Operating IBB – 40°C to 0°C Standby FSX, FSR at VIL (after 300 ms) 9 13 10 17 Power down GS0, GS1 = VIL (after 300 ms) 7 12 10 17 TYP† MAX UNIT mA mA mW digital interface PARAMETER TEST CONDITIONS VOH VOL High-level output voltage at PCMOUT IIH IIL High-level input current, any digital input Ci Input capacitance Low-level output voltage at PCMOUT, TSX IOH = – 9.6 mA IOL = 3.2 mA MIN 2.4 V VI = 2.2 V to VCC VI = 0 to 0.8 V Low-level input current, any digital input Co Output capacitance † All typical values are at VBB = – 5 V, VCC = 5 V, and TA = 25°C. UNIT 0.5 V 12 µA 12 µA 5 pF 5 pF transmit amplifier input PARAMETER TEST CONDITIONS Input current at ANLGIN Input offset voltage at ANLGIN VI = – 2.17 V to 2.17 V VI = – 2.17 V to 2.17 V Common-mode rejection at ANLGIN VI = – 2.17 V to 2.17 V MIN TYP† ±100 ± 25 UNIT nA mV 55 dB Open-loop voltage amplification at GSX 5000 Open-loop unity-gain bandwidth at GSX 1 Input resistance at ANLGIN † All typical values are at VBB = – 5 V, VCC = 5 V, and TA = 25°C. MAX MHz 10 MΩ receive filter output‡ PARAMETER MIN Output offset voltage PWRO +, PWRO – (single ended), Relative to AGND Output resistance at PWRO +, PWRO – † All typical values are at VBB = – 5 V, VCC = 5 V, and TA = 25°C. ‡ PWRO – on TCM37C14A only POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP† MAX UNIT 80 mV 1 Ω 5 TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (outputs not loaded) (unless otherwise noted) (continued) gain and dynamic range, VCC = 5 V, VBB = – 5 V, TA = 25°C (see Notes 4, 5, and 6) (unless otherwise noted) PARAMETER TYP MAX UNIT Encoder milliwatt response (transmit gain tolerance) Signal input = 1.064 Vrms for µ-law, Signal input = 1.068 Vrms for A-law TEST CONDITIONS ± 0.04 ± 0.2 dBm0 Encoder milliwatt response variation with temperature and supplies TA = – 40°C – 85°C, supplies = ± 5% ± 0.08 Digital milliwatt response (receive gain tolerance) relative to zerotransmission level point Signal input per CCITT G.711, output signal = 1 kHz ± 0.04 Digital milliwatt response variation with temperature and supplies TA = – 40°C – 85°C, supplies = ± 5% ± 0.08 µ-law Zero transmission level point, point transmit channel (0 dBm0) Zero-transmission-level A-law µ-law A-law µ-law Zero transmission level point, Zero-transmission-level point receive channel (0 dBm0) A-law µ-law A-law MIN dB ± 0.2 dBm0 dB 2.76 RL = 600 Ω 2.79 dBm 1 RL = 900 Ω 1.03 5.76 RL = 600 Ω 5.79 dBm 4 RL = 900 Ω 4.03 NOTES: 4. Unless otherwise noted, the analog input is a 0-dBm0, 1020-Hz sine wave, where 0 dBm0 is defined as the zero-reference point of the channel under test with unity gain set on the amplifier. This corresponds to an analog signal input of 1.064 Vrms, or an output of 1.503 Vrms. 5. The input amplifier is set for unity gain, noninverting. The digital input is a PCM bit stream generated by passing a 0-dBm0, 1020-Hz sine wave through an ideal encoder. 6. Receive output is measured single ended with the output amplifier in the unity-gain configuration. All output levels are (sin x)/x corrected. gain tracking, reference level = – 10 dBm0 PARAMETER TEST CONDITIONS Transmit gain tracking error, sinusoidal input Receive gain tracking error, sinusoidal input MIN MAX 3 > input level ≥ – 40 dBm0 ± 0.25 – 40 > input level ≥ – 50dBm0 ± 0.5 – 50 > input level ≥ – 55 dBm0 ± 1.2 3 > input level ≥ – 40 dBm0 ± 0.25 – 40 > input level ≥ – 50 dBm0 ± 0.5 – 50 > input level ≥ – 55 dBm0 ± 1.2 UNIT dB dB noise PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT Transmit noise, C-message weighted ANLGIN = AGND 1 7 dBrnC0 Transmit noise, psophometrically weighted ANLGIN = AGND – 82 – 80 dBm0p Receive noise, C-message-weighted quiet code at PWRO + PCMIN = 11111111 (µ-law), PCMIN = 11010101 (A-law) 2 5 dBrnC0 Receive noise, psophometrically weighted † All typical values are at VBB = – 5 V, VCC = 5 V, and TA = 25°C. 6 PCM = lowest positive decode level POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 – 81 dBm0p TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (outputs not loaded) (unless otherwise noted) (continued) power supply rejection and crosstalk attenuation PARAMETER TEST CONDITIONS 0 < f < 30 kHz VCC supply voltage rejection ratio, ratio transmit channel 30 < f < 50 kHz 0 < f < 30 kHz ratio transmit channel VBB supply voltage rejection ratio, 30 < f < 50 kHz VCC supplyy voltage ratio,, receive channel g rejection j (single ended) y voltage g rejection j VBB supply ratio,, receive channel (single ended) 0 < f < 30 kHz 30 < f < 50 kHz 0 < f < 30 kHz 30 < f < 50 kHz MIN TYP† Idle channel, supply signal = 200 mVpp, mVpp f measured at PCMOUT – 40 Idle channel, supplyy signal = 200 mVpp,, g f measured at PCMOUT Idle channel, – 35 Idle channel, supplyy signal = 200 mVpp,, g narrow-band, f measured at PWRO+ – 40 Idle channel, supplyy signal g = 200 mVpp,, narrow-band, f measured at PWRO+ – 40 MAX UNIT dB – 45 dB – 55 dB – 45 dB – 45 Crosstalk attenuation, transmit-to-receive at PWRO + (single ended) ANLGIN = 0 dBm0, f = 1.02 kHz, unity gain, PCMIN = lowest decode level 75 dB Crosstalk attenuation, receive-to-transmit at PWRO + (single ended) PCMIN = 0 dBm0, f = 1.02 kHz 75 dB † All typical values are at VBB = – 5 V, VCC = 5 V, and TA = 25°C. distortion PARAMETER TEST CONDITIONS Transmit signal to distortion ratio, sinusoidal input (CCITT G.712 – Method 2) Receive signal to distortion ratio, sinusoidal input (CCITT G.712 – Method 2) MIN 0 > ANLGIN ≥ – 30 dBm0 36 – 30 > ANLGIN ≥ – 40 dBm0 30 – 40 > ANLGIN ≥ – 45 dBm0 25 0 > ANLGIN ≥ – 30 dBm0 36 – 30 > ANLGIN ≥ – 40 dBm0 30 – 40 > ANLGIN ≥ – 45 dBm0 25 MAX UNIT dB dB Transmit single-frequency distortion products Input signal = 0 dBm0 – 46 dBm0 Receive single-frequency distortion products Input signal = 0 dBm0 – 46 dBm0 CCITT G.712 (7.1) – 35 CCITT G.712 (7.2) – 49 CCITT G.712 (6.1) – 25 CCITT G.712 (9) – 40 Intermodulation distortion, end-to-end Spurious out-of-band signals, end-to-end POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 dBm0 7 TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (outputs not loaded) (unless otherwise noted) (continued) transmit filter transfer function (see Figure 1) PARAMETER Transmit absolute delay time to PCMOUT Transmit differential envelope delay y time relative to transmit absolute delay time Receive absolute delay time to PWRO + Receive differential envelope delay y time relative to transmit absolute delay time TEST CONDITIONS MIN fMCLK = 2.048 MHz, Input to ANLGIN is 1.02 kHz at 0 dBm0 245 f = 500 Hz to 600 Hz 170 f = 600 Hz to 1000 Hz 95 f = 1000 Hz to 2600 Hz 45 f = 2600 Hz to 2800 Hz 105 fMCLK = 2.048 MHz, Digital input is digital milliwatt codes f = 500 Hz to 600 Hz 190 MAX UNIT µs µs µs 45 f = 600 Hz to 1000 Hz 35 f = 1000 Hz to 2600 Hz 85 f = 2600 Hz to 2800 Hz Gain (voltage ( g amplification)) relative to gain g at 1.02 kHz TYP† µs 110 Input amplifier set for unity gain, Noninverting maximum gain out ut, output Input In ut signal at ANLGIN is 0 dBm0 16.67 Hz – 30 50 Hz – 25 60 Hz – 23 200 Hz – 1.8 – 0.125 300 Hz to 3 kHz – 0.15 0.15 3.3 kHz – 0.35 0.15 3.4 kHz –1 – 0.1 4 kHz dB – 14 † All typical values are at VBB = – 5 V, VCC = 5 V, and TA = 25°C. receive filter transfer function (see Figure 2) PARAMETER TEST CONDITIONS MIN Below 20 Hz 0.15 200 Hz Input signal at PCMIN is 0 dBm0 UNIT 0.15 20 Hz Gain (voltage amplification) relative to gain at 1 1.02 02 kHz MAX – 0.5 0.15 300 Hz to 3 kHz – 0.15 0.15 3.3 kHz – 0.35 0.15 3.4 kHz –1 – 0.1 4 kHz – 14 4.6 kHz and above – 30 dB timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) clock timing (see Figure 3) MIN NOM MAX 488 UNIT tc(MCLK) tr Clock period, MCLK (2.048 MHz systems) Rise time, MCLK 5 30 ns tf tw(MCLK) Fall time, MCLK 5 30 ns Pulse duration, MCLK (see Note 7) 220 Clock duty cycle [tw(CLK)/tc(CLK)], MCLK 45% NOTE 7: FSX CLK and FSR CLK must be phase-locked with MCLK. 8 POST OFFICE BOX 655303 ns • DALLAS, TEXAS 75265 ns 50% 55% TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) transmit timing (see Figure 3) MIN Delay time (frame sync), FSX high or low before MCLK ↓ td(FSX) MAX UNIT 100 tc(MCLK) –100 ns receive timing (see Figure 4) MIN td(FSR) tsu(PCMIN) Delay time (frame sync), FSR high or low before MCLK ↓ th(PCMIN) Hold time after PCMIN ↓ MAX UNIT 100 tc(MCLK) –100 50 Setup time, PCMIN high before MCLK ↓ 60 ns ns ns switching characteristics over recommended ranges of operating conditions (see Figures 3 and 4) TEST CONDITIONS MIN MAX UNIT tpd1 Propagation delay time, MCLK ↑ to bit 1 data valid at PCMOUT (data enable time on time slot entry) (see Note 8) PARAMETER CL = 0 pF to 100 pF 0 145 ns tpd2 Propagation delay time, MCLK ↑ bit n to bit n data valid at PCMOUT (data valid time) CL = 0 pF to 100 pF 0 145 ns tpd3 Propagation delay time, MCLK ↓ low bit 8 to bit 8 Hi-Z at PCMOUT (data float time on time slot exit) (see Note 8) CL = 0 pF 60 215 ns tpd4 Propagation delay time, MCLK ↑ bit 1 to TSX active (low) (time slot enable time) CL = 0 pF to 100 pF 0 145 ns tpd5 Propagation delay time, MCLK ↓ to bit 8 to TSX inactive (high) (timeslot disable time) (see Note 8) CL = 0 pF 60 190 ns NOTE 8: Timing parameters tpd1, tpd3, and tpd5 are referenced to the high-impedance state. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 0.15 dB 300 Hz 0 0.15 dB 3000 Hz 0 – 0.125 dB 200 Hz – 0.15 dB 3000 Hz – 0.15 dB 300 Hz –1 AV – Gain Relative to Gain at 1 kHz – dB Typical Filter Transfer Function – 0.10 dB 3400 Hz – 0.35 dB 3300 Hz –1dB 3400 Hz –1 –1.8 dB 200 Hz 0 0 – 10 – 10 – 14 dB 4000 Hz – 20 – 30 – 20 – 23 dB 60 Hz Typical Filter Transfer Function – 25 dB 50 Hz – 30 dB 16.67 Hz – 32 dB 4600 Hz – 30 – 40 – 40 – 50 – 50 – 60 10 50 100 1k f – Frequency – Hz NOTE A: Gain (voltage amplification) is defined as gain relative to gain at 1 kHz in dB. Figure 1. Transmit Filter Transfer Characteristics 10 0.15 dB 3300 Hz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 – 60 10 k Expanded Scale PARAMETER MEASUREMENT INFORMATION TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 PARAMETER MEASUREMENT INFORMATION 0.15 dB 3000 HZ 0.15 dB 300 Hz 0.15 dB 3300 HZ 0 – 0.15 dB 200 Hz – 0.15 dB 3000 Hz – 0.15 dB 300 Hz – 0.10 dB 3400 Hz – 0.35 dB 3300 Hz –1 0 Expanded Scale 0.15 dB 200 Hz –1 AV – Gain Relative to Gain at 1 kHz – dB –1dB 3400 Hz 0 0 – 10 – 10 – 14 dB 4000 Hz – 20 – 20 – 30 dB 4800 Hz Typical Filter Transfer Function – 30 – 30 – 40 – 40 – 50 – 50 – 60 50 100 1k – 60 10 k f – Frequency – Hz NOTE A: Gain (voltage amplification) is defined as gain relative to gain at 1 kHz in dB. Figure 2. Receive Filter Transfer Characteristics POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 PARAMETER MEASUREMENT INFORMATION Time Slot 1 MCLK 1 2 3 4 tr td(FSX) td(FSX) 6 tw(MCLK) FSX tpd1 5 7 8 tf tc(MCLK) tpd2 Bit 1† PCMOUT Bit 2 tpd3 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 tpd4 Bit 8‡ tpd5 TSX † Bit 1 = MSB = most significant bit (sign bit) and is clocked in first on PCMIN or clocked out first on PCMOUT. ‡ Bit 8 = LSB = least significant bit and is clocked in last on PCMIN or is clocked out last on PCMOUT. NOTE A: Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V when the high level is indicated and 0.8 V when the low level is indicated. Figure 3. Transmit Timing Time Slot 1 MCLK 1 td(FSR) 2 td(FSR) 3 tr 4 5 tf 6 7 8 tw(MCLK) tc(MCLK) FSR tsu(PCMIN) th(PCMIN) PCMIN Bit 1† Valid Bit 2 Valid Bit 3 Valid Bit 4 Valid Bit 5 Valid Bit 6 Valid Bit 7 Valid Bit 8‡ Valid † Bit 1 = MSB = most significant bit (sign bit) and is clocked in first on PCMIN or clocked out first on PCMOUT. ‡ Bit 8 = LSB = least significant bit and is clocked in last on PCMIN or is clocked out last on PCMOUT. NOTE A: Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V when the high level is indicated and 0.8 V when the low level is indicated. Figure 4. Receive Timing 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 PRINCIPLES OF OPERATION system reliability and design considerations The TCM37C14A and TCM37C15A system reliability and design considerations are described in the following paragraphs. latch-up Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device if supply current to the device is not limited. Even though the devices are heavily protected against latch-up, it is still possible to cause latch-up under certain conditions in which excess current is forced into or out of one or more terminals. Latch-up can occur when the positive supply voltage drops momentarily below ground, when the negative supply voltage rises momentarily above ground, or, possibly, if a signal is applied to a terminal after power has been applied but before the ground is connected. This can happen if the device is hot inserted into a card with the power applied, or if the device is mounted on a card that has an edge connector, and the card is hot inserted into a system with the power on. To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased Schottky diode with a forward voltage drop of less than or equal to 0.4 V (1N5711 or equivalent) between each power supply and GND (see Figure 5). If it is possible that a TCM37C14A- or TCM37C15A-equipped card with an edge connector could be hot inserted into a powered-up system, it is also important to ensure that the ground edge-connector traces are longer than the power and signal traces, so that the card ground is always the first to make contact. VCC DGND VBB Figure 5. Latch-Up Protection Diode Connection POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 PRINCIPLES OF OPERATION system reliability and design considerations (continued) device power-up sequence Latch-up also can occur if a signal source is connected without the device being properly grounded. A signal applied to one terminal could then find a ground through another signal terminal on the device. To ensure proper operation of the device and as a safeguard against this sort of latch-up, it is recommended that the following power-up sequence always be used: 1. Ensure that no signals are applied to the device before the power-up sequence is complete. 2. Connect GND. 3. Apply VBB (most negative voltage). 4. Apply VCC (most positive voltage). 5. Force a power down condition in the device. 6. Connect the master clock. 7. Release the power-down condition. 8. Apply FSX and/or FSR synchronization pulses. 9. Apply signal inputs. When powering down the device, this procedure should be followed in the reverse order. internal sequencing On the transmit channel, digital outputs PCMOUT and TSX† are held in the high-impedance state for approximately four frames (500 µs) after power up or application of VBB or VCC. After this delay, PCMOUT and TSX† are functional and occur in the proper timeslot. The analog circuits on the transmit side require approximately 60 ms to reach their equilibrium value due to the autozero circuit settling time. Thus, valid digital information, such as for on/off hook detection, is available almost immediately, while analog information is available after some delay. To further enhance system reliability, the PCMOUT and TSX† terminals are placed in a high-impedance state approximately 20 µs after an interruption of MCLK. This interruption could possibly occur with some kind of fault condition elsewhere in the system. † TCM37C14A only miscellaneous functions Miscellaneous functions of the TCM37C14A and TCM37C15A are described in the following paragraphs. gain/attenuation control On-chip logic is included on the TCM37C14A and TCM37C15A to control the channel gain or attenuation and power-down functions with minimum terminal allocation. The operational amplifiers in the receive and transmit sections can be configured to either attenuate or amplify the signal depending on how external resistors are connected to the device. Two control input terminals (GS0 and GS1) select one of three levels of gain or attenuation in the transmit and receive path as well as power-down. Note that the gain for both the transmit and receive sides are set together and that the device enters the power-down mode when both GS0 and GS1 are held low. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 PRINCIPLES OF OPERATION miscellaneous functions (continued) gain adjustment If gain is used on the receive side, the input PCM data levels must be properly limited to prevent saturation of the output amplifier. Refer to the gain and dynamic range table in the electrical characteristics section. The gain of the transmit and receive amplifiers is set by external resistors connected to the device as shown in Figure 6 and can be adjusted using internal switching elements as shown in Table 1. PWRO+ Analog Output RSF RSIN _ RIN + RSA S0 RSB RS1 S1 RS2 AGND From Buffer GSR GSX Receive Gain Control Circuitry (Gain Configuration) RTF RTIN Analog Input _ ANLGIN + RTA S0 TS1 RTB S1 TS2 AGND Transmit Gain Control Circuitry (Gain Configuration) Figure 6. Gain Control Circuitry Table 1. Logic Table for Programmable Gain Control CONTROL TERMINALS GS0 GS1 Low Low TRANSFER FUNCTION (GAIN) INTERNAL SWITCH POSITION RS1 RS2 TS1 TS2 RECEIVE TRANSMIT Power Down Low Hi Open Open Open Open – RSF/RSIN – RTF/RTIN Hi Low Closed Open Closed Open – RSF/RSIN || RSA – RTF/RTIN || RTA Hi Hi Open Closed Open Closed – RSF/RSIN || RSB – RTF/RTIN || RTB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 PRINCIPLES OF OPERATION miscellaneous functions (continued) attenuation adjust The attenuation of the transmit and receive amplifiers is set by external resistors connected to the device as shown in Figure 7 and can be adjusted using internal switching elements as shown in Table 2. Analog Output PWRO+ _ RSB + RSA RSF S0 AGND RS1 S1 RS2 RSIN RIN From Buffer GSR Receive Gain Control Circuitry (Attenuation Configuration) GSX _ RTB + RTA AGND S0 RTF TS1 S1 TS2 RTIN Analog Input ANLGIN Transmit Gain Control Circuitry (Attenuation Configuration) Figure 7. Attenuation Control Circuitry Table 2. Logic Table for Programmable Attenuation Control CONTROL TERMINALS 16 GS0 GS1 Low Low Low TRANSFER FUNCTION (ATTENUATION) INTERNAL SWITCH POSITION RS1 RS2 TS1 Hi Open Open Open Hi Low Closed Open Hi Hi Open Closed TS2 RECEIVE TRANSMIT Power Down Open – RSF/RSIN – RTF/RTIN Closed Open – RSF || RSB/RSIN – RTF || RTB/RTIN OPEN Closed – RSF || RSA/RSIN – RTF || RTA/RTIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 PRINCIPLES OF OPERATION miscellaneous functions (continued) power-down and standby operations To minimize power consumption, a power-down mode and three standby modes are provided. For power down, low signals are applied to terminals GS0 and GS1. In the power-down mode, the average power consumption is reduced to approximately 7 mW. The three standby modes give the options of placing the entire device on standby, placing only the transmit channel on standby, or placing only the receive channel on standby. To place the entire device on standby, both FSX and FSR are held low. For transmit-only operation, FSX is high and FSR is held low. For receive-only operation, FSR is high and FSX is low (see Table 3 for power-down and standby procedures). Table 3. Power-Down and Standby Procedures DEVICE STATUS TYPICAL POWER CONSUMPTION PROCEDURE DIGITAL OUTPUT STATUS Power down GS0 and GS1 are low. 7 mW TSX and PCMOUT are in the high-impedance state. Entire device on standby FSX and FSR are low. 9 mW TSX and PCMOUT are in the high-impedance state. Only transmit on standby FSX is low, FSR is high. 50 mW TSX and PCMOUT are placed in the high-impedance state within 300 ms. Only receive on standby FSR is low, FSX is high. 30 mW fixed-data-rate timing Fixed-data-rate timing uses master clock MCLK, frame synchronizer clocks FSX and FSR, and output TSX (TCM37C14A only). An 8-kHz clock signal should be applied to the FSX and FSR inputs to set the sampling frequency. Data is transmitted on PCMOUT on the first eight positive transitions of MCLK following the rising edge of FSX. Data is received on PCMIN on the first eight falling edges of MCLK following FSR. A D/A conversion is performed on the received digital word and the resulting analog sample voltage is held on an internal sample-and-hold capacitor until transferred to the receive filter. The TCM37C14A operates with MCLK frequencies of 1.536 MHz, 1.544 MHz, or 2.048 MHz, while the TCM37C15A operates at 2.048 MHz. precision voltage references Voltage references that determine the gain and dynamic range characteristics of the device are generated internally and require no external components to operate. A difference in subsurface charge density between two suitably implanted MOS devices is used to derive a temperature- and bias-stable reference voltage. These references are calibrated during the manufacturing process. Separate references are supplied to the transmit and receive sections, and each is calibrated independently. Each reference value is then further trimmed by the gain-setting operational amplifiers to a final precision value. Manufacturing tolerances of typically ± 0.04 dB in absolute gain for each half channel can be achieved, providing a significant margin to compensate for error in other board components. conversion laws The TCM37C14A provides pin-selectable µ-law or A-law operation as specified by the CCITT G.711 recommendation. A-law operation is selected when the ASEL terminal is connected to VBB and µ-law operation is selected when the ASEL terminal is connected to VCC or to GND. The TCM37C15A provides A-law operation only. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 PRINCIPLES OF OPERATION transmit operation The transmit operation is described in the following paragraphs. transmit filter The input section provides gain adjustment in the passband by means of an on-chip uncommitted operational amplifier. The load impedance to ground (AGND) at the amplifier output must be greater than 10 kΩ in parallel with less than 50 pF. A low-pass antialiasing section is included on the device. This section provides 35-dB attenuation at the sampling frequency. No external components are required to provide the necessary antialiasing function for the switched capacitor section of the transmit filter. The band-pass section provides passband flatness and stopband attenuation that fulfills the AT&T D3/D4 channel bank transmission specification and CCITT recommendation G.712. Device specifications meet or exceed digital class-5 central office switching systems requirements for input signals greater than –55 dBm0. A high-pass section configuration was chosen to reject low-frequency noise from 50- and 60-Hz power lines, 17-Hz European electric railroads, ringing frequencies and their harmonics, and other low-frequency noise. Even with the high rejection at these frequencies, the sharpness of the band edge gives low attenuation at 200 Hz. This feature allows the use of low-cost transformer hybrids without external components to be used in systems. encoding The encoder internally samples the output of the transmit filter and holds each sample on an internal sample-and-hold capacitor. The encoder performs an A/D conversion on a switched-capacitor array. Digital data representing the sample is then transmitted on the first eight data clocks bits of the next frame. The autozero circuit corrects for dc offset on the input signal to the encoder, using the sign-bit-averaging technique. The sign bit from the encoder output is long-term averaged and subtracted from the input to the encoder, removing all dc offset from the encoder input waveform. receive operation The receive operation is described in the following paragraphs. decoding The serial PCM word is received at the PCMIN terminal on the first eight data clock bits of the frame. D/A conversion is performed and the corresponding analog sample is held on an internal sample-and-hold capacitor. The sample voltage is then transferred to the receive filter. receive filter The receive filter provides passband flatness and stopband rejection that fulfills both the AT&T D3/D4 specification and CCITT recommendation G.712. The filter contains the required compensation for the (sin x)/x response of such decoders. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 PRINCIPLES OF OPERATION transmit operation (continued) receive output power amplifiers A balanced-output amplifier is provided to allow maximum flexibility in output configuration. Either of the two outputs can drive single-ended loads (i.e. referenced to AGND). Alternatively, the differential output can directly drive a bridged load. The output stage is capable of driving resistive loads as low as 300 Ω to a single-ended level of 12 dBm, or as low as 600 Ω in the differential mode to a level of 15 dBm. Transmission levels are specified relative to the receive channel output under digital milliwatt conditions (i.e. when the digital input at PCMIN is the 8-code sequence specified in CCITT recommendation G.711). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 APPLICATION INFORMATION Figure 8 shows a typical application of the TCM37C15A in the attenuation configuration. Resistor values have been chosen to provide gains of 0 dB, – 2.5 dB, and – 7 dB in the transmit direction using the formulas in Table 2 (gain is controlled by GS0 and GS1). In the receive direction, gain has been configured for unity at all three settings of GS0 and GS1. High-tolerance resistors are recommended for the gain-setting networks to ensure consistant and accurate gain. Resistor values should be selected such that all equivalent feedback and input resistors values are 10 kΩ or greater. For example: RSIN || RSA || RTB ≥ 10 kΩ and RTIN || RTA || RTB ≥ 10 kΩ in gain configuration (see Figure 6 and Table 1), and RSF || RSA || RSB ≥ 10 kΩ and RTF || RTA || RTB ≥ 10 kΩ in attenuation configuration (see Figure 7 and Table 2). Connect 0.1 µF bypass capacitors across the VCC and AGND device terminals and across the VBB and AGND device terminals to reduce noise. For best results, these capacitors should be physically located as close to the device terminals as possible. Although the TCM37C14A and TCM37C15A devices are heavily protected against latch-up, 0.4-V Schottky diodes D1 and D2 should be used for applications in environments that could expose the board to hot-swapping — a common cause of latch-up (see the latch-up paragraph earlier in this document). 2 Voice Out RSF 13.0 K 4 3 5 RSIN 13.0 K 6 GSX PWRO + 19 RTB 10.5 K RS1 TS1 RIN RS2 TS2 GSR 18 RTA 39.2 K 17 RTF 13.1 K TCM37C15A ANLGIN Voice In 16 RTIN 13.1 K 9 10 Data In 8 kHz Frame Sync 8 Gain-Set Inputs { 7 PCMOUT PCMIN FSR GS0 FSX MCLK Data In 8 kHz Frame Sync 2.048 MHz Master Clock GS1 VCC 20 AGND DGND 15 0.1 µF D1 5V 14 13 12 1N5711 11 VBB 1 0.1 µF D2 1N5711 –5V Figure 8. Typical TCM37C15A Application 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PIN SHOWN PINS ** 0.050 (1,27) 16 20 24 28 A MAX 0.410 (10,41) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.500 (12,70) 0.600 (15,24) 0.700 (17,78) DIM 0.020 (0,51) 0.014 (0,35) 16 0.010 (0,25) M 9 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.293 (7,45) Gage Plane 0.010 (0,25) 1 8 0°– 8° A 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) 0.004 (0,10) 4040000 / B 03/95 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 TCM37C14A, TCM37C15A PCM COMBO WITH PROGRAMMABLE GAIN CONTROL SLWS018B – JUNE 1996 – REVISED MAY 1998 MECHANICAL DATA N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 16 PIN SHOWN PINS ** 14 16 18 20 A MAX 0.775 (19,69) 0.775 (19,69) 0.920 (23.37) 0.975 (24,77) A MIN 0.745 (18,92) 0.745 (18,92) 0.850 (21.59) 0.940 (23,88) DIM A 16 9 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) MAX 0.035 (0,89) MAX 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 0°– 15° 0.010 (0,25) NOM 14/18 PIN ONLY 4040049/C 08/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. 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