CD4086BMS CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate December 1992 Features Pinout • Medium Speed Operation - tPHL = 90ns; tPLH = 140ns (Typ.) at 10V CD4086BMS TOP VIEW • High Voltage Type (20V Rating) A 1 • INHIBIT and ENABLE Inputs B 2 J = INH + ENABLE + AB + CD + EF + GH 3 • Buffered Outputs • 100% Tested for Quiescent Current at 20V NC 4 • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V 14 VDD 13 D 12 C 11 ENABLE/EXP E 5 10 INHIBIT/EXP F 6 9 H VSS 7 8 G NC = NO CONNECTION • Standardized Symmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Functional Diagram 10 INHIBIT/EXP Description CD4086BMS contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/EXP input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/EXP is tied to VSS and ENABLE/EXP to VDD. See Figure 2 and its associated explanation for applications where a capability greater than 4-wide is required. The CD4076B is supplied in these 14 lead outline packages: Braze Seal DIP H4H Frit Seal DIP H1B Ceramic Flatpack H4F A B C D 1 2 12 13 3 J E F G H 5 6 8 9 11 ENABLE/EXP LOGIC 1 ≡ HIGH LOGIC 0 ≡ LOW VDD = 14 VSS = 7 NC = 4 J = INH + ENABLE + AB + CD + EF + GH CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-1055 File Number 3328 Specifications CD4086BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current Input Leakage Input Leakage SYMBOL IDD IIL IIH CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 2 µA 2 +125 C - 200 µA VDD = 18V, VIN = VDD or GND 3 -55oC - 2 µA VIN = VDD or GND 1 +25oC -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA - 50 mV VIN = VDD or GND VDD = 20 VDD = 18V o Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Functional F VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-1056 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4086BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay DATA SYMBOL TPHL1 TPLH1 Propagation Delay INHIBIT TPHL2 Transition Time VDD = 5V, VIN = VDD or GND 9 10, 11 Propagation Delay DATA Propagation Delay INHIBIT CONDITIONS (NOTES 1, 2) GROUP A SUBGROUPS TEMPERATURE VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 TPLH2 VDD = 5V, VIN = VDD or GND 9 10, 11 TTHL TTLH VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 450 ns - 608 ns - 620 ns - 837 ns - 300 ns - 405 ns - 500 ns - 675 ns - 200 ns - 270 ns NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage VOL VDD = 5V, No Load 1, 2 1, 2 1, 2 1, 2 TEMPERATURE -55oC, +25oC MIN MAX UNITS µA - 1 +125oC - 30 µA -55oC, +25oC - 2 µA +125oC - 60 µA - 2 µA +125oC - 120 µA +25oC, +125oC, - 50 mV -55oC, +25oC -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) IOL10 IOL15 IOH5A IOH5B IOH10 VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V 1, 2 1, 2 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 7-1057 1, 2 +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -2.6 mA Specifications CD4086BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) SYMBOL IOH15 CONDITIONS VDD =15V, VOUT = 13.5V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +125oC - -2.4 mA o -55 C - -4.2 mA Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC 7 - V Propagation Delay DATA TPHL1 VDD = 10V 1, 2, 3 +25oC - 180 ns VDD = 15V 1, 2, 3 +25oC - 120 ns o - 250 ns o Propagation Delay DATA TPLH1 Propagation Delay INHIBIT TPHL2 Propagation Delay INHIBIT TPLH2 Transition Time Input Capacitance VDD = 10V TTHL1 TTLH1 CIN 1, 2, 3 +25 C VDD = 15V 1, 2, 3 +25 C - 180 ns VDD = 10V 1, 2, 3 +25oC - 120 ns VDD = 15V 1, 2, 3 +25oC - 80 ns VDD = 10V 1, 2, 3 +25oC - 200 ns VDD = 15V 1, 2, 3 +25oC - 140 ns o VDD = 10V 1, 2, 3 +25 C - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns 1, 2 +25oC - 7.5 pF Any Input NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 20V, VIN = VDD or GND TEMPERATURE MIN MAX UNITS 1, 4 +25 - 7.5 µA oC N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V N Threshold Voltage Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V P Threshold Voltage Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns Functional F VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-1 IDD ± 0.2µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) 7-1058 Specifications CD4086BMS TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group B IDD, IOL5, IOH5A 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group A Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 3, 4 1, 2, 5 - 13 14 Static Burn-In 2 Note 1 3, 4 7 1, 2, 5, 6, 8 - 14 Dynamic BurnIn Note 1 4 7 14 3, 4 7 1, 2, 5, 6, 8 - 14 Irradiation Note 2 9V ± -0.5V 50kHz 25kHz 3 1, 2, 5, 6, 8, 9, 12, 13 10, 11 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 7-1059 CD4086BMS VDD p p p p p p p n * A 1 n * B 2 p p n * C n 12 n * D n 13 p p n n VDD p n p p p n n * E 5 * F n n n 3 J n 6 p VSS p TERM 14 = VDD TERM 7 = VSS n VDD VSS * G 8 n * H 9 ENABLE/EXP 11 * INHIBIT/EXP * ALL INPUTS PROTECTED BY * 10 VSS CMOS PROTECTION NETWORK FIGURE 1. SCHEMATIC DIAGRAM INHIBIT/EXP1 VSS INHIBIT/EXP2 VSS A1 B1 C1 D1 A2 B2 C2 D2 J1 J2 E1 F1 E2 F2 G1 H1 G2 H2 ENABLE/EXP2 VDD ENABLE/EXP1 J2 = A1 B1 + C1 D1 + E1 FE + G1 H1 + A2 B2 + C2 D2 + E2 F2 + G2 H2 FIGURE 2. TWO CD4086BMS’S CONNECTED AS AN 8-WIDE 2-INPUT A-O-I GATE Figure 2 above shows two CD4086’s utilized to obtain 8-wide 2-input A-O-I function. The output (J1) of one CD4086 is fed directly to the ENABLE/EXP2 line of the second CD4086. In a similar fashion, any NAND gate output can be fed directly into the ENABLE/EXP input to obtain a 5-wide A-O-I function. In addition, and AND gate output can be fed directly into the INHIBIT/EXP input with the same result. 7-1060 CD4086BMS Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC 6 CURRENT PEAK 10V 10 5 VI 14 10 4 VO 3 CURRENT PEAK 5V 5 15 VDD 7 11 ID VSS 2 VDD OUTPUT VOLTAGE (VO) - V VDD DRAINCURRENT (ID) - mA 15 OUTPUT VOLTAGE (VO) - V AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 15V MIN MAX VDD VDD 10 VI 10 14 VO 5 11 1 7 ID VSS VDD 0 0 5 10 0 15 5 10 15 INPUT VOLTAGE (VI) - V INPUT VOLTAGE (VI) - V FIGURE 4. MINIMUM AND MAXIMUM VOLTAGE TRANSFER CHARACTERISTICS 30 OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 5. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA ) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -15 -20 -25 -15V GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) AMBIENT TEMPERATURE (TA) = +25oC 0 -10 -10V 15.0 FIGURE 6. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS -30 FIGURE 7. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC 0 TRANSITION TIME (tTHL, tTLH) (ns) OUTPUT LOW (SINK) CURRENT (IOL) (mA) FIGURE 3. TYPICAL VOLTAGE AND CURRENT TRANSFER CHARACTERISTICS 200 150 SUPPLY VOLTAGE (VDD) = 5V 100 10V 15V 50 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 8. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE 7-1061 CD4086BMS Typical Performance Characteristics (Continued) 10 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC 4 0 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V SUPPLY VOLTAGE (VDD) = 15V -5 103 10V 10V 102 -10V 5V 101 CL = 50pF CL = 15pF -15V -15 100 10-1 100 101 102 103 104 FREQUENCY (f) (kHz) 300 AMBIENT TEMPERATURE (TA) = +25oC 250 SUPPLY VOLTAGE (VDD) = 5V FIGURE 10. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME (tPLH) (ns) HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME (tPHL) - ns FIGURE 9. TYPICAL POWER DISSIPATION vs FREQUENCY 200 150 10V 100 50 15V 0 500 300 200 10V 100 15V 0 FIGURE 11. TYPICAL DATA OR ENABLE HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME vs LOAD CAPACITANCE PROPAGATION DELAY TIME (tPHL, tPLH) (ns) SUPPLY VOLTAGE (VDD) = 5V 400 20 40 60 80 100 LOAD CAPACITANCE (CL) - pF 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 12. TYPICAL DATA OR ENABLE LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME vs LOAD CAPACITANCE AMBIENT TEMPERATURE (TA) = +25oC LOAD CAPACITANCE (CL) = 50pF 1250 1000 tPLH 750 500 tPHL 250 0 2.5 -10 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) POWER DISSIPATION (PD) (µW) 105 5 7.5 10 12.5 15 17.5 20 SUPPLY VOLTAGE (VDD) (V) FIGURE 13. TYPICAL DATA OR ENABLE PROPAGATION DELAY TIME vs SUPPLY VOLTAGE 7-1062 CD4086BMS Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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