Application Note AN-1043 Stabilize the Buck Converter with Transconductance Amplifier By Michael (Chongming) Qiao, Parviz Parto and Reza Amirani 1. Introduction..................................................................................... 1 2. Loop Gain of System ...................................................................... 2 3. Typical Procedure of Compensator Design .................................................... 2 4. Type II (PI) Compensator Design ................................................... 3 4.1 Introduction to PI Compensator.................................................... 3 4.2) Design Example of PI Compensator ........................................... 4 5. Type III (PID) Compensator............................................................ 5 5.1) Introduction to Type III Compensators ........................................ 5 5.2) Type III (PID) Compensator Design Method A............................ 6 5.3) Design Example of PID Compensator Method A ........................ 7 5.4) Type III (PID) Compensation Design Method B .......................... 8 5.5) Design Example of IRU3037 with Ceramic Capacitor and PID Compensator Method B...................................................... 10 6. Conclusion.................................................................................... 10 Synchronous DC-DC buck converters have high efficiency, and International Rectifier has developed a series of PWM voltage mode controllers for synch buck converters, including single and multi-phase controllers such as IRU3037, IRU3038, IRU3046 and IRU3055. One feature of these controllers is that transconductance amplifiers are employed as voltage feedback error amplifiers. APPLICATION NOTE AN-1043 Stabilize the Buck Converter with Transconductance Amplifier Michael (Chongming) Qiao, Parviz Parto and Reza Amirani, International Rectifier Synchronous buck converters have received great attention in low power, low voltage DC-DC converter applications in recent years due to their high efficiency. International Rectifier Inc. has developed a series of PWM voltage mode controllers for synchronous buck converters, including single phase and multi-phase controllers such as IRU3037, IRU3038, IRU3046, IRU3055, etc. One feature of these controllers is that transconductance amplifiers are employed as voltage feedback Error Amplifiers. Theoretically, a transconductance amplifier is an equivalent voltage controlled current source. It multiplies the difference of input voltage with a certain gain and generates a current into the output node. It features high output impedance and it is stable by most of the output compensation components. The output short circuit protection and internal compensation is not required. This results in a smaller die size and simple design. In this application note, how to stabilize the buck converter with transconductance Error amplifier is discussed. The goal of the design is to provide a loop gain function with a high bandwidth (high zero-crossover frequency) and adequate phase margin. As a result, fast load response and good steady state output can be achieved. 1. Introduction to Synchronous Buck Converter with Transconductance Amplifier L Q1 and ESR is the Equivalent Series Resistance of output capacitor. There are three sections. One is synchronous buck converter including output inductor and capacitor. The controller such as IRU3037 provides the basic function block such as PWM generator and transconductance amplifier. The resistor and capacitor with the transconductance amplifier, function as a compensator to stabilize the system. From control system point of view, the three blocks are shown in Figure 2. G(s) Compensator VREF Buck Converter 1 VOSC D(s) GP (s) VOUT Figure 2 - The control diagram for the synchronous buck converter with transconductance amplifier. The transfer function of the PWM generator is basically 1/VOSC , where VOSC is the peak to peak voltage of oscillator listed in the datasheet. The transfer function of the buck converter can be simplified as follows: 1+ESR3COUT3s GP(s)= RL PWM Generator (R L 1+s3 Output Inductor LOAD 3VIN ) +ESR3COUT +s 23L3COUT ---(1) ESR + Output Capacitor V IN Q2 R LOAD V OUT COUT For simplification, we can combine the transfer function of PWM generator and buck converter. This results in power stage of buck converter and is expressed as: Buck Converter V REF gm Rf1 Rc1 PWM generator Compensator with Transconductance Amplifier G(s) = GP(s)3 Cc2 Cc1 Rf2 Figure 1 - Simplified diagram for synchronous buck converter with transconductance amplifier. The simplified diagram for synchronous buck converter with transconductance amplifier is shown in Figure 1, where RL is the inherent resistance of output inductor Rev. 1.1 10/07/02 The (s) indicates that the transfer function varies as a function of frequency. 1 VOSC ---(2) Basically, the transfer function of the power stage is a second order system and the Bode plot is shown in Figure 3. The resonance of the output LC filter introduces a double pole and -40dB Gain Slope (see Figure 3). The resonance frequency of the LC filter is expressed as follows: FPO = www.irf.com 1 23p3 L3COUT ---(3) 1 APPLICATION NOTES AN-1043 The ESR of the output capacitor and capacitance introduces one zero for the system. The zero is given as: FZO = 1 23p3ESR3COUT Power Stage ---(4) -40dB Where FZO is a character parameter and dependent on the characteristic of what capacitor is chosen. Typically, for an electrolytic capacitor, the F ZO is in a few KHz range. f -20dB FPO VIN VOSC Magnitude FZO -20dB Desired Loop Gain Fo -40dB f f 0 Phase -20dB -90 -180 Fpo 0 Fzo Figure 4 - Bode plot of desired loop gain function. f 3. Typical Procedure of Compensator Design In order to realize the desired loop gain with high enough zero-cross over frequency and proper phase margin, a compensator has to be designed. A typical procedure is as follows: Phase -90 -180 Figure 3 - The Bode plot of buck converter power stage. 2. Loop Gain of System The loop gain of system is defined as the product of transfer function along the closed control loop. From Figure 2, the loop gain is defined as: H(s) = D(s)3 1 3GP(s) = D(s)3G(s) VOSC Step 1 - Collect system parameters such as input voltage, output voltage, etc. and determine switching frequency. Step 2 - Determine the power stage poles and zeros. Step 3 - Determine the zero crossover frequency and compensation type. The compensation type is determined by the location of zero crossover frequency and characteristics of output capacitor as shown in Table 1. ---(5) The Bode plots of desired loop gain and power stage is shown in Figure 4, where FO is the zero crossover frequency defined as the frequency when loop gain equals unity. Typically, FO can be chosen to be 1/10~1/5 of the switching frequency. F O determines how fast the dynamic load response is. The higher FO is, the faster dynamic response will be. The slope rate of loop gain around FO should be –20dB in order to get a stable system. The phase margin is shown in Figure 4. Typically, 458 or more phase margin is desired for a stable system. 2 Phase Margin Compensator Location of Zero Typical Type Crossover Frequency Output (FO) Capacitor Type II (PI) FPO < FZO < FO < fS/2 Electrolytic, Tantalum Type III (PID) FPO < FO < FZO < fS/2 Tantalum, Method A Ceramic Type III (PID) FPO < FO < fS/2 < FZO Ceramic Method B www.irf.com Table 1 - The compensation type and location of zero crossover frequency. Rev. 1.1 10/07/02 APPLICATION NOTE Step 4 - Determine the desired location of zeros and poles for the selected compensator. Step 5 - Calculate the real parameters-resistor and capacitors for the selected compensator. Choose the resistors and capacitors from standard catalog such that they are as close to the calculated value as possible. A PI compensator can be used as shown in Figure 5. Overall, the Bode plots of power stage, desired loop gain and PI compensator are displayed in Figure 6. A PI compensator has one zero at: FZ1 = 4. Type II (PI) Compensator Design 1 2p3RC13CC1 VOUT VREF Rf2 = VOUT Rf1 + Rf2 Rf1 VOUT = VREF Rc1 VREF ---(7) The output voltage can be directly connected to the feedback pin of the Error amplifier. This is shown as: Ve gm ---(6) Resistors Rf1 and Rf2 are used to determine the output voltage. The output voltage is determined as: 4.1) Introduction to PI Compensator Rf2 AN-1043 The resistor RC1 determines the zero crossover frequency. It can be calculated as: Cc1 RC1 = Figure 5 - PI Compensator configuration. 2p3FO3L3VOSC Rf1 + Rf2 3 ESR3VIN3gm Rf2 When the above equation is combined with equation (7), it results to: -40dB RC1 = Power Stage 2p3FO3L3VOSC VOUT 3 ESR3VIN3gm VREF ---(8) Set the zero of PI compensator to 75% of FPO: Fpo fs/2 Fzo Desired Loop Gain FZ1 = -20dB 1 = 0.753FPO 2p3RC13CC1 ---(9) The compensator capacitor Cc1 can be calculated as: -20dB -20dB PI Compensator CC1 = Fo L3COUT 1 = 0.753RC1 0.7532p3FPO3RC1 ---(10) In practice, one more capacitor is sometimes added in parallel with the RC network as shown in Figure 7. VOUT Rf1 Fz1 Figure 6 - Bode plot of the buck converter power stage, desired loop gain and PI compensator. In many applications, an electrolytic capacitor is chosen as the output capacitor due to its low cost. For electrolytic capacitor, the zero caused by ESR (FZO) is a few KHz. If the switching frequency is a few hundred KHz, the zero crossover frequency FO is chosen to be 1/10 of switching frequency and FO is located at: Rf2 Ve gm Rc1 Cc2 VREF Cc1 Figure 7 - PI compensator with one additional pole. FPO < FZO < FO < fS/2 Rev. 1.1 10/07/02 www.irf.com 3 APPLICATION NOTES AN-1043 This additional capacitor gives a second pole as: FP2 = 1 CC13CC2 2p3RC13 CC1 + CC2 Step 1 - Collect system parameters such as input voltage, output voltage, etc. and determine switching frequency. ---(11) Set this pole to one half of switching frequency, which results in the capacitor Cc2. FP2 = CC2 = fS 2 1 1 p3RC13fS CC1 1 ≅ p3RC13fS ---(12) 4.2) Design Example of PI Compensator Take IRU3037 controlled buck converter as an example. The schematic is shown in Figure 8. Input Voltage Output Voltage Output Current Switching Frequency Output Inductor Output Capacitor Peak to Peak Oscillator Ramp Voltage Reference Voltage Transconductance Gain 5V 3.3V 10A 200KHz 3.3mH 2200mF with 18mV ESR VOSC = 1.25V VREF = 1.25V gm=0.6mA/V or 600mmho Table 2 - The parameters of IRU3037 controlled buck converter in Figure 8. 5V D1 1N4148 L1 1uH C2 2x 10TPB100ML, 100uF, 55mV D2 1N4148 C3 1uF C4 1uF Vcc C5 0.1uF Vc Q1 IRF7457 HDrv U1 SS C8 0.1uF L2 3.3uH IRU3037 Q2 IRF7460 LDrv Comp 3.3V @ 10A C7 2200uF ESR 18mV Rf1 Cc1 4.7nF Cc2 68pF C1 47uF Fb 1.65K, 1% Gnd Rc1 27K Rf2 1K, 1% Figure 8 - Application of IRU3037 with PI compensator. 4 www.irf.com Rev. 1.1 10/07/02 APPLICATION NOTE Step 2 - Determine the power stage poles and zeros. The pole caused by the output inductor and output capacitor is calculated as: FPO = FPO = 1 2p3 L3COUT 1 2p3 3.3mH32200mF AN-1043 (Optional) Second capacitor CC2 can be calculated using equation (12): 1 1 CC2 = p3RC13fS = p327K3200K ≅ 59pF Select CC2 = 68pF ≅ 1.87KHz The zero caused by ESR of the output capacitor is calculated as: FZO 1 = 2p3ESR3COUT FZO 1 = ≅ 4KHz 2p318mV32200mF Calculate resistors Rf1 and Rf2. Select resistor Rf2 to be a reasonable value. For example, from low noise point of view, select Rf2=1K, 1%. Rf1 = 3.3-1.25 VO-V REF 3Rf2 = 31K = 1.64K 1.25 VREF Select Rf1 = 1.64K, 1% 5. Type III (PID) Compensator Step 3 - Determine the zero crossover frequency and compensation type. Select desired zero-crossover frequency: fS fS ~ 5 10 Select FO=20KHz FO [ fS Because we have FPO<FZO<FO< , a PI Compensator 2 is chosen. 5.1) Introduction The PI compensation is based on the output capacitor having enough ESR to ensure stability. If the output capacitor is a ceramic capacitor, the zero caused by ESR will be much larger than the desired zero cross over frequency, the type III (PID) compensation is considered as shown in Figure 9. The Bode plot of the PID compensation network is shown in Figure 10. VOUT Step 4 - Determine the desired location of zeros and poles for the selected compensator. Select: FZ1 = 0.753FPO = 0.7531.87KHz ≅ 1.4KHz Rf3 Rc1 fS = 100KHz 2 gm Step 5 - Calculate the real parameters-resistor and capacitors for the selected compensator. Calculate RC1 from equation (8): RC1 = 2p3FO3L3VOSC VO 3 ESR3VIN3g m VREF RC1 = 2p320KHz33.3mH31.25 3 3.3 18mV35V30.6310-3 1.25 Zc Cc2 Rf1 Cf3 If additional capacitor is chosen: FP2 = Zf Cc1 Ve Rf2 VREF Figure 9 - PID compensation network. PID Compensator -20dB -20dB RC1 ≅ 25.3K Select RC1 = 27K Calculate CC1 By: Fz1 1 L3COUT CC1 = = 0.7532p3FPO3RC1 0.753RC1 CC1 = Fz2 Fp2 Fp3 = fs/2 Figure 10 - Bode plot of PID compensator. 3.3mH32200mF ≅ 4.2nF 0.75327K Select CC1 = 4.7nF Rev. 1.1 10/07/02 www.irf.com 5 APPLICATION NOTES AN-1043 The transfer function of the PID compensator is given as: Ve 1-gm3ZC = ---(13) VOUT 1+gm3Zf+Zf/Rf2 Set first zero of PID at 75% of the resonant pole caused by output inductor and capacitor: The error amplifier gain is independent of the transconductance under the following condition: Zf gm3Zf >> 1+ and gm3ZC >> 1 Rf2 So we have: Set second zero of PID at exact resonant pole caused by output inductor and capacitor: Ve ≅ VOUT ZC Zf FZ2 = FPO s s 1+ 1+ ( 2p3F )( 2p3F ) 3 s s +C ) (1+ 2p3F )(1+ 2p3F ) 1 s3Rf13(CC1 Z1 Z2 P2 P3 C2 ---(20) ---(21) Set second pole of PID at the zero caused by output capacitor ESR: FP2 = FZO By replacing the ZC and Zf according to Figure 9, the transfer function can be expressed as: D(s)= FZ1 = 75%3FPO ---(22) Set the third pole of PID at one half of switching frequency: FP3 = fS/2 ---(23) The Bode plot of power stage and proposed PID compensator is shown in Figure 11. ---(14) The compensator has two zeros and three poles. FZ1 = 1 2p3RC13CC1 FZ2 = 1 2p3Cf33(Rf1+Rf3) FP3 = -20dB 1 2p3Rf33Cf3 1 2p3RC13 CC13CC2 CC1+CC2 Loop Gain ---(17) -20dB Fo ---(18) The type III compensator is usually designed by selection of location of F Z1, FZ2, F P2 and FP3 in order to get the desired zero crossover frequency and enough phase margin. If gm3ZC> 1, equation (13) will change its polarity and a 180 degree phase shift will be introduced. The system will become unstable. Therefore, a careful selection of ZC has to be made. It is verified that the following restriction has to be followed: 2 RC1 >> g m (mandatory); 1 Rf1 ?? Rf2 ?? Rf3 > g m (desirable) ---(19) Where Rf1 ?? Rf2 ?? Rf3 are the parallel resistance of Rf1, Rf2 and Rf3. 5.2) Type III (PID) Compensator Design Method A If the zero caused by ESR is less than half of the switching frequency, that is FPO<FO<FZO<fS/2, then the following design method can be used. 6 Fzo Fpo ---(16) FP1 = 0 FP2 = -40dB Power Stage ---(15) -40dB PID Compensator -20dB -20dB Fz1 Fz2 Fp2 Fp3 = fs/2 Figure 11 - The Bode plot of the buck converter power stage, the desired loop gain and PID compensator (method A). The zero crossover frequency FO is determined by the following equation: Cf3 = www.irf.com VOSC 32p3FO3L3COUT VIN3RC1 ---(24) Rev. 1.1 10/07/02 APPLICATION NOTE AN-1043 5V D1 1N4148 L1 1uH C2 2x 10TPB100ML, 100uF, 55mV D2 1N4148 C3 1uF C4 1uF Vcc C5 0.1uF Vc Q1 IRF7457 HDrv U1 SS C8 0.1uF C1 47uF Tantalum L2 Q2 IRF7460 LDrv C7 Poscap, 2x 6TPC150M 150uF, ESR 40mV Each Rf1 Comp Fb 11.7K, 1% Gnd Cf3 2.2nF Rf2 7.15K, 1% Rc1 Cc1 4.7nF 3.3V @ 10A 3.3uH IRU3037 Rf3 2.74K 10K Cc2 150pF Figure 12 - An example of IRU3037 controlled buck converter with PID compensation method A. 5.3) Design Example of PID Compensator Method A Step 1 - Collect system parameters in Figure 12 such as input voltage, output voltage, etc. and determine the switching frequency. Comparing with section 4.2, only the output capacitor is changed. The output capacitor is 23150mF with 40mV each. The total ESR is: Step 3 - Determine the zero crossover frequency and compensation type. Select desired zero-crossover frequency. FO [ fS fS ~ 5 10 If we select FO=30KHz and we have FPO<FZO<FO<fS/2, the PI compensator in section 4.2 can be chosen. ESR = 40mV/2 = 20mV Total capacitor is: Suppose FO=15KHz and FPO<FO<FZO<fS/2, then a PID compensator with method A is chosen. COUT = 23150mF = 300mF Step 2 - Determine the power stage poles and zeros. FPO = FPO = Step 4 - Determine the desired location of zeros and poles for the selected compensator. Select: 1 2p3 2p3 L3COUT 1 3.3mH3300mF FZ1 = 0.753FPO = 3.75KHz ≅ 5KHz FZ2 = FPO = 5KHz FP2 = FZO = 26.5KHz Zero caused by ESR: FZO = 1 1 2p3ESR3COUT = 2p320mV323150mF FP3 = fS 200KHz = = 100KHz 2 2 FZO ≅ 26.5KHz Rev. 1.1 10/07/02 www.irf.com 7 APPLICATION NOTES AN-1043 Step 5 - Calculate the real parameters-resistor and capacitors for the selected compensator. 2 Select RC1 so that RC1 >> g m 2 2 = ≅ 3.3K gm 0.6mA / V Select RC1 = 10K 5.4) Type III (PID) Compensation Design Method B If a ceramic capacitor is chosen, the zero caused by ESR of capacitor is in the order of the switching frequency such as FZO>fS/2. The compensator method A will not be very suitable. The compensation calculation can be based on the lead lag compensation (method B). The Bode plot of power stage, loop gain, PID compensator method B and phase are shown in Figure 13. Calculate CC1 and CC2 by setting FZ1=0.753FPO and FP3=fS/2: 1 1 CC1 = = = 4.2nF 2p3FZ13RC1 2p33.75KHz310K Select CC1 = 4.7nF Power Stage 1 1 = = 159pF 2p3FP33RC1 2p3100KHz310K Select CC2 = 150pF > 30pF(reasonable capacitor) CC2 ≅ Fpo Fzo -40dB -20dB Calculate capacitor Cf3 by using equation (24): Loop Gain Cf3 = VOSC 32p3FO3L3COUT VIN3RC1 Cf3 = 1.2532p315KHz33.3mH3300mF ≅ 2.3nF 5V310K -20dB Fo Select Cf3=2.2nF -40dB Calculate Rf3 and Rf1 by setting FP2=FZO and FZ2=FPO: Rf3 = 1 1 = = 2.73K 2p3Cf33FP2 2p32.2nF326.5KHz PID Compensator Select Rf3 = 2.74K Rf1 = -20dB -20dB 1 - Rf3 2p3Cf33FZ2 Fz1 1 Rf1 = - 2.74K = 11.7K 2p32.2nF35KHz Phase of PID Compensator Select Rf1 = 11.7K Fz2 Fp2 Fp3 = fs/2 Phase Boost Calculate Rf2: Rf2 = VREF 3 Rf1 VOUT - VREF Rf2 = 1.25 311.7K = 7.13K 3.3 - 1.25 Figure 13 - Bode plot of buck converter with PID compensator method B. In the bold outline area of Figure 13, the PID compensator can be seen as lead-lag compensation. It is known that the lead-lag compensation can give a maximum phase boost at frequency. Select Rf2 = 7.15K, 1% Check: Rf1 ?? Rf2 ?? Rf3 = 11.7K ?? 7.15K ?? 2.74K Rf1 ?? Rf2 ?? Rf3 ≅ 1.7K > 1/gm = 1.6K F= FP23FZ2 ---(25) If Rf1 ?? Rf2 ?? Rf3<1/gm, then iteration may be required by going back and selecting a larger RC1. 8 www.irf.com Rev. 1.1 10/07/02 APPLICATION NOTE The maximum phase gain will be generated, that is: ( ) FP2 - FZ2 uMAX = Sin-1 FP2 + FZ2 The second zero of PID compensator can be calculated by: 1 - SinuMAX FZ2 = FO3 ---(29) 1 + SinuMAX ---(26) One of the design strategies is that we can set the maximum phase boost occurring at zero-cross over frequency, that is: FO = FP23FZ2 ---(27) Suppose uMARGIN is the desired phase margin and 60° is typical value. Parameter f is the phase of power stage at zero crossover frequency. The required phase boost from PID compensator is set by: uMAX = uMARGIN - f AN-1043 The second pole of compensator is given by: 1 + SinuMAX 1 - SinuMAX FP2 = FO3 ---(30) The other zeroes and poles of compensator can be set by: Select FZ1 by FZ1<FZ2 and FZ1<FPO ---(31) FP3 = FS/2 ---(32) The zero crossover frequency is determined by the following: ---(28) Because f ≅ 0 and uMAX ≅ uMARGIN. Cf3 = 2p3FO3L3COUT VOSC 3 RC1 VIN ---(33) 5V D1 1N4148 L1 1uH C2 2x 10TPB100ML, 100uF, 55mV D2 1N4148 C3 1uF C4 1uF Vcc C8 0.1uF C5 0.1uF Vc HDrv U1 SS C1 47uF Tantalum Q1 IRF7457 L2 3.3V @ 10A 3.3uH IRU3037 LDrv Q2 IRF7460 C7 10x 22uF ESR, 10mV Each Rf1 Comp Fb 27.4K Gnd Cc1 3.3nF Rc1 Rf2 16.7K, 1% Cf3 1nF Rf3 2.15K 20K Cc2 82pF Figure 14 - Example of IRU3037 controlled buck converter with ceramic capacitors and PID compensator method B. Rev. 1.1 10/07/02 www.irf.com 9 APPLICATION NOTES AN-1043 5.5) Design Example of IRU3037 with Ceramic Capacitor and PID Compensator Method B Step 1 - Collect system parameters in Figure 14 and determine switching frequency. Comparing with section 4.2 output capacitor is 10 ceramic cap with 22mF, 10mV ESR. Total capacitance is: ESR = 10mV/10 = 1mV Step 2 - Determine the power stage poles and zeros. FPO = 1 2p3 3.3mH3220mF Calculate: Select CC1 = 3.3nF 1 1 CC2 = 2p3FP33RC1 = 2p3100KHz320K ≅ 80pF ≅ 5.9Hz FZO = 1 2p3ESR3COUT FZO = 1 ≅ 723KHz 2p31mV3220mF Select CC2 = 82pF Calculate Cf3 based on location of zero crossover frequency: Step 3 - Determine the zero crossover frequency and compensation type. Select zero crossover frequency as: FO = Select RC1 = 20K Calculate: L3COUT 1 2p3 RC1 >> 2/gm = 2/0.6mmho ≅ 3.3K 1 1 CC1 = 2p3FZ13RC1 = 2p32.68KHz320K ≅ 3nF COUT = 10322mF = 220mF FPO = Step 5 - Calculate the real parameters-resistor and capacitors of compensator. Select RC1: fS 200KHz = = 20KHz 10 10 Cf3 = 2p3FO3L3COUT VOSC 3 RC1 VIN Cf3 = 2p320K33.3mH3220mF 1.25V 3 ≅ 1.14nF 20K 5V Select Cf3 = 1nF Because FPO< FO< fS/2 << FZO, we select the PID compensation based on lead lag (method B). Calculate: 1 1 = 2p31nF374KHz ≅ 2.15K 2p3Cf33FP2 Rf3 = Step 4 - Determine the desired location of zeros and poles for PID compensator. The desired phase margin is: uMAX ≅ uMARGIN = 608 Select Rf3 = 2.15K Calculate: Rf1 = Then: 1 - Rf3 2p3Cf33FZ2 FZ2 = FO3 1 - SinuMAX ≅ 5.36KHz 1 + SinuMAX 1 Rf1 = 2p31nF35.36KHz - 2.15K ≅ 27.5K FP2 = FO3 1 + SinuMAX ≅ 74KHz 1 - SinuMAX Select Rf1 = 27.4K, 1% Select FZ1<FZ2 and FZ1<FPO Select FZ1 = 0.53FZ2 = 0.535.36KHz ≅ 2.68KHz For DC regulation, calculate: Rf2 = Select FP3 = fS/2 = 100KHz VREF 1.25 3Rf1 = 327.4K ≅ 16.7K VO-V REF 3.3-1.25 Select Rf2 = 16.7K, 1% Check: Rf1 ?? Rf2 ?? Rf3 = 27.5K ?? 16.7 ?? 2.15K ≅ 1.8K Rf1 ?? Rf2 ?? Rf3 > 1/gm = 1.6K 10 www.irf.com Rev. 1.1 10/07/02 APPLICATION NOTE Conclusion The control loop design based on transconductance amplifier is proposed for buck converter. For most of buck converter with electrolytic capacitor and low performance tantalum capacitors, a simple type II (PI) compensator can be employed. For ceramic output capacitors, a type III or PID compensator is usually required. Although IRU3037 controlled circuits are taken as an example in this application note, the proposed design method also applies to other IC applications such as IRU3046 or IRU3055 controlled multi-phase buck converters. AN-1043 References [1] D. Maksimovic, R. Erickson, “Advances in Averaged Switch Modeling and Simulation” 2.4MB slides from 3 hour tutorial seminar presented at the IEEE Power Electronics Specialists Conference, June 1999, Charleston, South Carolina. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 02/01 Rev. 1.1 10/07/02 www.irf.com 11